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Dissertations / Theses on the topic 'Logical synthesis'

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Published: 30 May 2022

Last updated: 31 July 2025

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1

Yang, Ting. "Evaluating development projects : exploring a synthesis model of the logical framework approach and outcome mapping." Thesis, University of Sussex, 2018. http://sro.sussex.ac.uk/id/eprint/79800/.

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Under the current results-driven development agenda, sound evaluation, and a corresponding evaluation toolkit, need to be in place to examine whether and to what extent development interventions have achieved their targeted objectives and results, and to generate lessons for further development learning and improvement. My review of the literature shows that innovative and appropriate evaluation approaches are needed to address key challenges in evaluation such as the tension between learning and accountability objectives, the need to unpack the mechanisms linking outputs and outcomes or goal,

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2

Fornari, François-Xavier. "Optimisation du controle et implantation en circuits de programmes esterel." Paris, ENMP, 1995. http://www.theses.fr/1995ENMP0531.

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Cette these decrit l'application de techniques d'optimisation de circuits digitaux a l'optimisation du controle de programmes ecrits avec le langage synchrone esterel. Elle presente de plus une implantation de ces programmes en circuits. Le compilateur esterel v4 exprime le controle d'un programme esterel sous forme d'un jeu de registres et d'un systeme d'equations booleennes triees pilotant un ensemble d'actions. Sous certaines conditions, ce controle est considere comme un circuit digital. Il est alors ameliore en utilisant des methodes sophistiquees d'optimisations sequentielles presentes d

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3

Teslenko, Maxim. "All Around Logic Synthesis." Doctoral thesis, Stockholm : Mikroelektronik och informationsteknik, Kungliga Tekniska högskolan, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4700.

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4

Kozlowski, Tomasz. "Application of exclusive-OR logic in technology independent logic optimisation." Thesis, University of Bristol, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.296702.

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5

Färm, Petra. "Advanced algorithms for logic synthesis." Licentiate thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-1717.

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<p>In this thesis, new algorithms for logic synthesis areexplored. Our work is motivated by two observations: (1)Traditional logic synthesis applies literal count as theprimary quality metric during the technology independentoptimization phase. Thissimplistic metric often leads to badcircuit structures as it cannot foresee the impact of earlychoices on the final area, delay, power consumption, etc. (2)Although powerful, global Boolean optimization is not robustand corresponding algorithms cannot be used in practice withoutartificially restricting the application window. Othertechniques, such a

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6

Hadjinicolaou, M. G. "Synthesis of programmable logic arrays." Thesis, Brunel University, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.371168.

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7

Pearce, Maureen. "Logic synthesis for programmable devices." Thesis, University of Bristol, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.357911.

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8

Wang, Qi. "Logic synthesis for low power." Diss., The University of Arizona, 1998. http://hdl.handle.net/10150/288924.

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The dissertation addresses several problems in the power optimization and power-delay tradeoffs in digital CMOS circuits. The work is organized according to the three main sources of power dissipation: Power dissipation due to switching (P(sc)), standby or leakage power (P(leak)) and short circuit power (P(sc)). First we present new, efficient and provably correct algorithms for minimizing the switching power in combinational and sequential CMOS logic circuits. The techniques are based on the addition and removal of redundancies at the logic level. The basic technique developed for combination

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9

Berrada, Fathi Wafâa. "Influence des architectures "materiel" et "logiciel" de systemes de synthese d'image sur l'efficacite d'algorithmes de visualisation." Université Louis Pasteur (Strasbourg) (1971-2008), 1988. http://www.theses.fr/1988STR13185.

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Presentation sur le materiel existant, les logiciels de base disponibles, les normalisations operationnelles ainsi que les algorithmes diffuses actuellement. Il est montre comment ces trois parties interreagissent entre elles. Il est precise qu'elle parait etre l'architecture "materiel" et "logiciel" la plus adaptee a une exploitation avancee

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10

Димко, Єгор Павлович. "Моделі та методи оптимального керування індукційним дуплекс-процесом за умов невизначеності". Thesis, Національний технічний університет "Харківський політехнічний інститут", 2018. http://repository.kpi.kharkov.ua/handle/KhPI-Press/38635.

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Дисертація на здобуття наукового ступеня кандидата технічних наук за спеціальністю 05.13.03 – системи та процеси керування. – Національний технічний університет "Харківський політехнічний інститут", Харків, 2018. Дисертація присвячена вирішенню актуальної науково-практичної задачі – розробці методів оптимального управління в умовах невизначеності. Показана можливість побудови адекватної математичної моделі індукційного дуплекс-процесу плавки як об'єкта управління в умовах неможливості реалізації плану активного експерименту в виробничих умовах. На основі цього запропоновано для опису кінцевого

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11

Poulain, Thierry. "Contribution du génie logiciel pour la conception et l'évaluation d'applications de supervision." Valenciennes, 1994. https://ged.uphf.fr/nuxeo/site/esupversions/86faffad-3e4b-4990-b7c1-7a6b0cf7faac.

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A partir d'une démarche axée sur le génie logiciel, l'objectif de cette thèse est d'intégrer des fonctionnalités de prototypage, favorisant le cycle de développement d'applications de surveillance. Le mémoire est divisé en cinq chapitres. Dans le premier, sont abordés les systèmes de supervision. Puis, après avoir identifié un ensemble de problèmes ergonomiques résultant de leur utilisation et de leur conception, une démarche globale de conception et évaluation développée au LAIH est décrite. Une application de supervision nécessitant de nombreux développements informatiques, les principaux mo

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12

Färm, Petra. "Integrated Logic Synthesis Using Simulated Annealing." Doctoral thesis, KTH, Mikroelektronik och Informationsteknik, IMIT, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4257.

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A conventional logic synthesis flow is composed of three separate phases: technologyindependent optimization, technology mapping, and technology dependentoptimization. A fundamental problem with such a three-phased approach is thatthe global logic structure is decided during the first phase without any knowledge ofthe actual technology parameters considered during later phases. Although technologydependent optimization algorithms perform some limited logic restructuring,they cannot recover from fundamental mistakes made during the first phase, whichoften results in non-satisfiable solutions.We

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13

Kraan, H. C. "Proof planning for logic program synthesis." Thesis, University of Edinburgh, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.653555.

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The area of logic program synthesis is attracting increased interest. Most efforts have concentrated on applying techniques from functional program synthesis to logic program synthesis. This thesis investigates a new approach: Synthesizing logic programs automatically via middle-out reasoning in proof planning. [Bundy <I>et al </I>90a] suggested middle-out reasoning in proof planning. Middle-out reasoning uses variables to represent unknown details of a proof. Unification instantiates the variables in the subsequent planning, while proof planning provides the necessary search control. Middle-o

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14

Winterstein, Felix. "Separation logic for high-level synthesis." Thesis, Imperial College London, 2016. http://hdl.handle.net/10044/1/33371.

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High-level synthesis (HLS) promises a significant shortening of the digital hardware design cycle by raising the abstraction level of the design entry to high-level languages such as C/C++. However, applications using dynamic, pointer-based data structures remain difficult to implement well, yet such constructs are widely used in software. Automated optimisations that leverage the memory bandwidth of dedicated hardware implementations by distributing the application data over separate on-chip memories and parallelise the implementation are often ineffective in the presence of dynamic data stru

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15

Chua, Shin Cheng. "Design and synthesis of reversible logic." Thesis, Curtin University, 2016. http://hdl.handle.net/20.500.11937/1504.

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Energy lost during computation is an important issue for digital design. Today, all electronics devices suffer from energy lost due to the conventional logic system used. The amount of energy loss in the form of heat leads to immense challenges in nowadays circuit design. To overcome that, reversible logic has been invented. Since properties of reversible logic differ greatly than conventional logic, synthesis methods used for conventional logic cannot be used in reversible logic. In this dissertation, we proposed new synthesis algorithms and several circuit designs using reversible logic.

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16

Димко, Єгор Павлович. "Моделі та методи оптимального керування індукційним дуплекс-процесом за умов невизначеності". Thesis, НТУ "ХПІ", 2018. http://repository.kpi.kharkov.ua/handle/KhPI-Press/38290.

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Дисертація на здобуття наукового ступеня кандидата технічних наук за спеціальністю 05.13.03 – системи та процеси керування. – Національний технічний університет "Харківський політехнічний інститут", Харків, 2018. Дисертація присвячена вирішенню актуальної науково-практичної задачі – розробці методів оптимального управління в умовах невизначеності. Показана можливість побудови адекватної математичної моделі індукційного дуплекс-процесу плавки як об'єкта управління в умовах неможливості реалізації плану активного експерименту в виробничих умовах. На основі цього запропоновано для опису кінцевог

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17

Xu, Leeka. "Synthesis and optimisation of combinational logic using universal logic module networks." Thesis, Edinburgh Napier University, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295379.

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18

Krenz, René. "Graph dominators in logic synthesis and verification." Licentiate thesis, KTH, KTH, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4293.

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<p>This work focuses on the usage of dominators in circuit graphs in order to reduce the complexity of synthesis and verification tasks. One of the contributions of this thesis is a new algorithm for computing multiple-vertex dominators in circuit graphs. Previous algorithms, based on single-vertex dominators suffer from their rare appearance in many circuits. The presented approach searches efficiently for multiple-vertex dominators in circuit graphs. It finds dominator relations, where algorithms for computing single-vertex dominators fail. Another contribution of this thesis is the applicat

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19

Wang, Xiaojun. "An interactive, high-level logic synthesis system." Thesis, Staffordshire University, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.387386.

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20

Vasilko, Milan. "Design synthesis for dynamically reconfigurable logic systems." Thesis, Bournemouth University, 2000. http://eprints.bournemouth.ac.uk/291/.

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Dynamic reconfiguration of logic circuits has been a research problem for over four decades. While applications using logic reconfiguration in practical scenarios have been demonstrated, the design of these systems has proved to be a difficult process demanding the skills of an experienced reconfigurable logic design expert. This thesis proposes an automatic synthesis method which relieves designers of some of the difficulties associated with designing partially dynamically reconfigurable systems. A new design abstraction model for reconfigurable systems is proposed in order to support design

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21

Oreifej, Rashad. "SYNTHESIS OF SELF-RESETTING STAGE LOGIC PIPELINES." Master's thesis, University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3572.

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As designers began to pack multi-million transistors onto a single chip, their reliance on a global clocking signal to orchestrate the operations of the chip has started to face almost insurmountable difficulties. As a result, designers started to explore clockless circuits to avoid the global clocking problem. Recently, self-resetting circuits implemented in dynamic logic families have been proposed as viable clockless alternatives. While these circuits can produce excellent performances, they display serious limitations in terms of area cost and power consumption. A middle-of-the-road altern

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22

Marshall, I. "Hardware synthesis from an interval temporal logic." Thesis, University of East Anglia, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.361488.

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23

Padua, C. I. P. S. "A logic synthesis approach to silicon compilation." Thesis, University of Southampton, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.381234.

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24

Lu, Aiguo. "Logic synthesis for field programmable gate arrays." Thesis, University of Bristol, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295061.

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25

Nguena-Timo, Omer. "Synthesis for a weak real-time logic." Thesis, Bordeaux 1, 2009. http://www.theses.fr/2010BOR13931/document.

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Dans cette thèse, nous nous intéressons à la spécification et à la synthèse de contrôleurs des systèmes temps-réels. Les modèles pour ces systèmes sont des Event-recording Automata. Nous supposons que les contrôleurs observent tous les évènements se produisant dans le système et qu'ils peuvent interdirent uniquement des évènements contrôlables. Tous les évènements ne sont pas nécessairement contrôlables. Une première étude est faite sur la logique Event-recording Logic (ERL). Nous proposons des nouveaux algorithmes pour les problèmes de vérification et de satisfaisabilité. Ces algorithmes prés

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26

Liu, Tai-hung. "Logic synthesis for high-performance digital circuits /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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27

PALANISWAMY, ASHOK KUMAR. "SYNTHESIS AND TESTING OF THRESHOLD LOGIC CIRCUITS." OpenSIUC, 2014. https://opensiuc.lib.siu.edu/dissertations/963.

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Threshold logic gates gaining more importance in recent years due to the significant development in the switching devices. This renewed the interest in synthesis and testing of circuits with threshold logic gates. Two important synthesis considerations of threshold logic circuits are addressed namely, threshold logic function identification and reducing the total number of threshold logic gates required to represent the given boolean circuit description. A fast method to identify the given Boolean function as a threshold logic function with weight assignment is introduced. It characterizes the

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28

Lukac, Martin. "Quantum Inductive Learning and Quantum Logic Synthesis." PDXScholar, 2009. https://pdxscholar.library.pdx.edu/open_access_etds/2319.

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Since Quantum Computer is almost realizable on large scale and Quantum Technology is one of the main solutions to the Moore Limit, Quantum Logic Synthesis (QLS) has become a required theory and tool for designing Quantum Logic Circuits. However, despite its growth, there is no any unified aproach to QLS as Quantum Computing is still being discovered and novel applications are being identified. The intent of this study is to experimentally explore principles of Quantum Logic Synthesis and its applications to Inductive Machine Learning. Based on algorithmic approach, I first design a Genetic Alg

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29

Chowdhury, Adib Kabir. "Efficient methods for synthesis of multivalued logic." Thesis, Curtin University, 2014. http://hdl.handle.net/20.500.11937/335.

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Multi-Valued Logic (MVL) synthesis has economically revolutionized the method of designing logic functions. MVL has become an alternative to our universal binary logic. In this thesis, as a branch of emerging technology, MVL is considered for circuit simplification and size reduction. Reduced MVL circuits are obtained by efficient synthesis algorithms. Different approaches on synthesizing techniques are investigated. Synthesized circuits are demonstrated with dynamic and static performances over binary and existing MVL techniques.

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30

Matsuura, Satoshi. "Synthetic RNA-based logic computation in mammalian cells." Kyoto University, 2019. http://hdl.handle.net/2433/242426.

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31

Larese, Costanza. "The principle of analyticity of logic : a philosophical and formal Perspective." Doctoral thesis, Scuola Normale Superiore, 2019. http://hdl.handle.net/11384/86138.

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The subject of the present work is the principle of analyticity of logic. In order for the question ‘Is logic analytic?’ to make sense and before trying to ﬁnd an answer to this problem, it is obviously necessary to specify two preliminary issues, namely, the meaning of the term ‘analytic’ and the meaning of the term ‘logic’. The former issue is somehow justiﬁed and expected: after all, analyticity represents one of the philosophical concepts par excellence and, as such, it has been at the core of a lively debate throughout the history of the discipline. But, despite possible appearances to th

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32

Lämmermann, Sven. "Runtime Service Composition via Logic-Based Program Synthesis." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3371.

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33

Wist, Dominic. "Attacking complexity in logic synthesis of asynchronous circuits." Phd thesis, Universität Potsdam, 2011. http://opus.kobv.de/ubp/volltexte/2012/5970/.

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Most of the microelectronic circuits fabricated today are synchronous, i.e. they are driven by one or several clock signals. Synchronous circuit design faces several fundamental challenges such as high-speed clock distribution, integration of multiple cores operating at different clock rates, reduction of power consumption and dealing with voltage, temperature, manufacturing and runtime variations. Asynchronous or clockless design plays a key role in alleviating these challenges, however the design and test of asynchronous circuits is much more difficult in comparison to their synchronous coun

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34

Krenz-Bååth, René. "Dominator-based Algorithms in Logic Synthesis and Verification." Doctoral thesis, KTH, Elektronik- och datorsystem, ECS, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4579.

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Today's EDA (Electronic Design Automation) industry faces enormous challenges. Their primary cause is the tremendous increase of the complexity of modern digital designs. Graph algorithms are widely applied to solve various EDA problems. In particular, graph dominators, which provide information about the origin and the end of reconverging paths in a circuit graph, proved to be useful in various CAD (Computer Aided Design) applications such as equivalence checking, ATPG, technology mapping, and power optimization. This thesis provides a study on graph dominators in logic synthesis and verifica

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Krenz-Bååth, René. "Dominator-based algorithms in logic synthesis and verification /." Stockholm : Department of Electronic, Computer, and Software Systems, School of Information and Communication Technology, Royal Institute of Technology (KTH), 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4579.

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Zhuang, Nan. "Logic synthesis and technology mapping using genetic algorithms." Thesis, Imperial College London, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.286760.

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37

Lester, Nigel L. K. "Logic synthesis using Reed-Muller and SOP expressions." Thesis, University of Bristol, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295060.

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Saul, Jonathan. "Logic synthesis based on the Reed-Muller representation." Thesis, University of Bristol, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.357962.

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39

Cresswell, Stephen N. "Deductive synthesis of recursive plans in linear logic." Thesis, University of Edinburgh, 2001. http://hdl.handle.net/1842/1896.

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Conventionally, the problem of plan formation in Artificial Intelligence deals with the generation of plans in the form of a sequence of actions. This thesis describes an approach to extending the expressiveness of plans to include conditional branches and recursion. This allows problems to be solved at a higher level, such that a single plan in such a language is capable of solving a class of problems rather than a single problem instance. A plan of fixed size may solve arbitrarily large problem instances. To form such plans, we take a deductive planning approach, in which the formation of th

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Wang, Lingli. "Automated synthesis and optimization of multilevel logic circuits." Thesis, Edinburgh Napier University, 2000. http://researchrepository.napier.ac.uk/Output/4342.

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With the increased complexity of Very Large Scaled Integrated (VLSI) circuits, multilevel logic synthesis plays an even more important role due to its flexibility and compactness. The history of symbolic logic and some typical techniques for multilevel logic synthesis are reviewed. These methods include algorithmic approach; Rule-Based approach; Binary Decision Diagram (BDD) approach; Field Programmable Gate Array(FPGA) approach and several perturbation applications. One new kind of don't cares (DCs), called functional DCs has been proposed for multilevel logic synthesis. The conventional two-

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McKenzie, Lynn Mhairi. "Logic synthesis and optimisation using Reed-Muller expansions." Thesis, Edinburgh Napier University, 1995. http://researchrepository.napier.ac.uk/Output/4276.

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This thesis presents techniques and algorithms which may be employed to represent, generate and optimise particular categories of Exclusive-OR Sum- Of-Products (ESOP) forms. The work documented herein concentrates on two types of Reed-Muller (RM) expressions, namely, Fixed Polarity Reed-Muller (FPRM) expansions and KROnecker (KRO) expansions (a category of mixed polarity RM expansions). Initially, the theory of switching functions is comprehensively reviewed. This includes descriptions of various types of RM expansion and ESOP forms. The structure of Binary Decision Diagrams (BDDs) and Reed-Mu

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Sarabi, Andisheh. "Logic Synthesis with High Testability for Cellular Arrays." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4752.

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The new Field Programmable Gate Array (FPGA) technologies and their structures have opened up new approaches to logic design and synthesis. The main feature of an FPGA is an array of logic blocks surrounded by a programmable interconnection structure. Cellular FPGAs are a special class of FPGAs which are distinguished by their fine granularity and their emphasis on local cell interconnects. While these characteristics call for specialized synthesis tools, the availability of logic gates other than Boolean AND, OR and NOT in these architectures opens up new possibilities for synthesis. Among th

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Silva, Augusto Neutzling. "Syhthesis of thereshold logic based circuits." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/119435.

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Circuitos baseados em portas lógicas de limiar (threshold logic gates – TLG) vem sendo estudados como uma alternativa promissora em relação ao tradicional estilo lógico CMOS, baseado no operadores AND e OR, na construção de circuitos integrados digitais. TLGs são capazes de implementar funções Booleanas mais complexas em uma única porta lógica. Diversos novos dispositivos, candidatos a substituir o transistor MOS, não se comportam como chaves lógicas e são intrinsicamente mais adequados à implementação de TLGs. Exemplos desses dispositivos são os memristores, spintronica, diodos de tunelamento

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Nayeem, Noor Muhammed. "Synthesis and testing of reversible Toffoli circuits." Thesis, Lethbridge, Alta. : University of Lethbridge, Dept. of Mathematics and Computer Science, c2012, 2012. http://hdl.handle.net/10133/3309.

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Recently, researchers have been interested in reversible computing because of its ability to dissipate nearly zero heat and because of its applications in quantum computing and low power VLSI design. Synthesis and testing are two important areas of reversible logic. The thesis first presents an approach for the synthesis of reversible circuits from the exclusive- OR sum-of-products (ESOP) representation of functions, which makes better use of shared functionality among multiple outputs, resulting in up to 75% minimization of quantum cost compared to the previous approach. This thesis also inve

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Midde, Bharath Reddy. "Design, analysis, and synthesis of 16 bit arithmetic logic unit using reversible logic gate." Thesis, California State University, Long Beach, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10099864.

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<p> In the modern world, an Arithmetic Logic Unit (ALU) is one of the most crucial component of an embedded system and is used in many devices like calculators, cell phones, computers, and so on. An ALU is a multi-functional circuit that conditionally performs one of several possible functions on two operands A and B depending on control inputs. It is nevertheless the main performer of any computing device. This project proposes the design of programmable reversible logic gate structures, targeted for the ALU implementation and their use in the realization of an efficient reversible ALU. This

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46

Rao, Jinghai. "Semantic Web Service Composition via Logic-based Program Synthesis." Doctoral thesis, Norwegian University of Science and Technology, Department of Computer and Information Science, 2004. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-344.

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<p>The ability to efficient selection and integration of inter-organizational heterogeneous Web services at runtime becomes an important requirement to the Web service provision. In an Web service application, if no single existing Web service can satisfy the functionality required by the user, there should be a program or an agent to automated combine existing services together in order to fulfill the request.</p><p>The aim of this thesis is to consider the Web service composition problem from the viewpoint of logic-based program synthesis, and to propose an agent-based framework for supporti

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47

Dubrova, Elena Vladimirovna. "Boolean and multiple-valued functions in combinational logic synthesis." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp02/NQ34259.pdf.

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48

Ngom, Alioune. "Synthesis of multiple-valued logic functions by neural networks." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp03/NQ36787.pdf.

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49

El-Maleh, Aiman H. "Testability preservation of combinational and sequential logic synthesis transformations." Thesis, McGill University, 1995. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=29016.

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In order to reduce the test development cost and guarantee testable designs, it is essential to have synthesis transformations that are testability and test-set preserving. In this thesis, we study testability preservation of transformations that form the basis of existing state-of-the-art logic synthesis and optimization techniques.<br>We show that the concurrent decomposition and factorization transformations, except dual-extraction of multiplexor structures, preserve testablility and test-set under several testing constraints. Furthermore, we provide sufficient conditions for test-set prese

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50

Xu, Siyao M. Eng Massachusetts Institute of Technology. "Reversible logic synthesis with minimal usage of ancilla bits." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/100615.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 49-50).<br>Reversible logic has attracted much research interest over the last few decades, especially due to its application in quantum computing. In the construction of reversible gates from basic gates, ancilla bits are c

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