Relevant bibliographies by topics / Logic optimizations

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Logic optimizations'

Author: Grafiati
Published: 28 June 2021
Last updated: 29 July 2025

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Journal articles on the topic "Logic optimizations"

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Rus, Teodor, and Eric van Wyk. "Using Model Checking in a Parallelizing Compiler." Parallel Processing Letters 08, no. 04 (1998): 459–71. http://dx.doi.org/10.1142/s0129626498000468.

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In this paper we describe the usage of temporal logic model checking in a parallelizing compiler to analyze the structure of a source program and locate opportunities for optimization and parallelization. The source program is represented as a process graph in which the nodes are sequential processes and the edges are control and data dependence relationships between the computations at the nodes. By labeling the nodes and edges with descriptive atomic propositions and by specifying the conditions necessary for optimizations and parallelizations as temporal logic formulas, we can use a model c
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Kudva, P., Associate, A. Sullivan, and W. Dougherty. "Measurements for structural logic synthesis optimizations." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 6 (2003): 665–74. http://dx.doi.org/10.1109/tcad.2003.811456.

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Khurshid, Burhan, and Roohie Naaz. "Technology - Dependent Optimization of FIR Filters based on Carry - Save Multiplier and 4:2 Compressor unit." Electronics ETF 20, no. 2 (2017): 43. http://dx.doi.org/10.7251/els1620043k.

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This work presents an FPGA implementation of FIR filter based on 4:2 compressor and CSA multiplier unit. The hardware realizations presented in this pa per are based on the technology-dependent optimization of these individual units. The aim is to achieve an efficient mapping of these isolated units on Xilinx FPGAs. Conventional filter implementations consider only technology-independent optimizations and rely on Xilinx CAD tools to map the logic onto FPGA fabric. Very often this results in inefficient mapping. In this paper, we consider the traditional CSA-4:2 compressor based FIR filte rs an
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Gäher, Lennard, Michael Sammler, Simon Spies, et al. "Simuliris: a separation logic framework for verifying concurrent program optimizations." Proceedings of the ACM on Programming Languages 6, POPL (2022): 1–31. http://dx.doi.org/10.1145/3498689.

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Today’s compilers employ a variety of non-trivial optimizations to achieve good performance. One key trick compilers use to justify transformations of concurrent programs is to assume that the source program has no data races : if it does, they cause the program to have undefined behavior (UB) and give the compiler free rein. However, verifying correctness of optimizations that exploit this assumption is a non-trivial problem. In particular, prior work either has not proven that such optimizations preserve program termination (particularly non-obvious when considering optimizations that move i
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BÁRÁNY, VINCE, MICHAEL BENEDIKT, and BALDER TEN CATE. "SOME MODEL THEORY OF GUARDED NEGATION." Journal of Symbolic Logic 83, no. 04 (2018): 1307–44. http://dx.doi.org/10.1017/jsl.2018.64.

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AbstractThe Guarded Negation Fragment (GNFO) is a fragment of first-order logic that contains all positive existential formulas, can express the first-order translations of basic modal logic and of many description logics, along with many sentences that arise in databases. It has been shown that the syntax of GNFO is restrictive enough so that computational problems such as validity and satisfiability are still decidable. This suggests that, in spite of its expressive power, GNFO formulas are amenable to novel optimizations. In this article we study the model theory of GNFO formulas. Our resul
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Lacey, David, Neil D. Jones, Eric Van Wyk, and Carl Christian Frederiksen. "Proving correctness of compiler optimizations by temporal logic." ACM SIGPLAN Notices 37, no. 1 (2002): 283–94. http://dx.doi.org/10.1145/565816.503299.

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ZHOU, NENG-FA, TAISUKE SATO, and YI-DONG SHEN. "Linear tabling strategies and optimizations." Theory and Practice of Logic Programming 8, no. 01 (2007): 81–109. http://dx.doi.org/10.1017/s147106840700316x.

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AbstractRecently there has been a growing interest in research in tabling in the logic programming community because of its usefulness in a variety of application domains including program analysis, parsing, deductive databases, theorem proving, model checking, and logic-based probabilistic learning. The main idea of tabling is to memorize the answers to some subgoals and use the answers to resolve subsequent variant subgoals. Early resolution mechanisms proposed for tabling such as OLDT and SLG rely on suspension and resumption of subgoals to compute fixpoints. Recently, the iterative approac
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Zhou, Neng-Fa. "Global Optimizations in a Prolog Compiler for the Toam." Journal of Logic Programming 15, no. 4 (1993): 275–94. http://dx.doi.org/10.1016/s0743-1066(14)80001-0.

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Xu, Ziyang, Yebin Chon, Yian Su, et al. "PROMPT: A Fast and Extensible Memory Profiling Framework." Proceedings of the ACM on Programming Languages 8, OOPSLA1 (2024): 449–73. http://dx.doi.org/10.1145/3649827.

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Memory profiling captures programs’ dynamic memory behavior, assisting programmers in debugging, tuning, and enabling advanced compiler optimizations like speculation-based automatic parallelization. As each use case demands its unique program trace summary, various memory profiler types have been developed. Yet, designing practical memory profilers often requires extensive compiler expertise, adeptness in program optimization, and significant implementation effort. This often results in a void where aspirations for fast and robust profilers remain unfulfilled. To bridge this gap, this paper p
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Apoorva, Reddy Proddutoori. "Improvizing Power Optimizations Using Dynamic Cascode Voltage Switching Logic." Journal of Scientific and Engineering Research 6, no. 11 (2019): 311–14. https://doi.org/10.5281/zenodo.12798330.

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In this paper we display another choice the 13-decision demonstrate, based on a graph chart that can be utilized to maximize proficiency Make DCVS circuits yourself. We assess our compared to customary DCVS amalgamation strategies that utilize requested parallel choices graphs that illustrate that our approach will without a doubt succeed as well as or on the other hand superior compared to OBDD based methodologies. Within the journey for high-performance CMOS, dynamic cascode voltage switch (DCVS) circuits are rising as an vital modern range of ponder. consolidated circuits Potential benefits
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Dissertations / Theses on the topic "Logic optimizations"

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Crha, Adam. "Syntéza a optimalizace polymorfních obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2021. http://www.nusl.cz/ntk/nusl-444886.

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Tato práce se zabývá metodami logické syntézy a optimalizací pro polymorfní obvody. V práci jsou jak diskutovány existující metody pro konvenční obvody, tak i představeny nové metody, aplikovatelné na polymorfní elektroniku. Hlavním přínosem práce je představení nových metod optimalizace a logické syntézy pro polymorfní obvody. Přesto, že v minulých letech byly představeny metody pro návrh polymorfních obvodů, jsou tyto metody založené na evolučních technikách nebo nejsou dobře škálovatelné. Z toho vyplývá, že stále neexistuje stabilní metodika pro návrh složitějších polymorfních obvodů. Tato
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Xu, Qing. "Optimization techniques for distributed logic simulation." Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=96665.

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Gate level simulation is a necessary step to verify the correctness of a circuitdesign before fabrication. It is a very time-consuming application, especially in lightof current circuit sizes. Since circuits are continually growing in size and complexity,there is a need for more efficient simulation techniques to keep the circuit verificationtime acceptably small. The use of parallel or distributed simulation is such a technique.When executed on a network of workstations, distributed simulation is alsoa very cost-effective technique. This research focuses on optimization techniques forTime War
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Dadone, Paolo. "Design Optimization of Fuzzy Logic Systems." Diss., Virginia Tech, 2001. http://hdl.handle.net/10919/27893.

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Fuzzy logic systems are widely used for control, system identification, and pattern recognition problems. In order to maximize their performance, it is often necessary to undertake a design optimization process in which the adjustable parameters defining a particular fuzzy system are tuned to maximize a given performance criterion. Some data to approximate are commonly available and yield what is called the supervised learning problem. In this problem we typically wish to minimize the sum of the squares of errors in approximating the data. We first introduce fuzzy logic systems and the superv
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Lehar, Matthew A. 1977. "A branching fuzzy-logic classifier for building optimization." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/32512.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2005.<br>Includes bibliographical references (p. 109-110).<br>We present an input-output model that learns to emulate a complex building simulation of high dimensionality. Many multi-dimensional systems are dominated by the behavior of a small number of inputs over a limited range of input variation. Some also exhibit a tendency to respond relatively strongly to certain inputs over small ranges, and to other inputs over very large ranges of input variation. A branching linear discriminant can be used to is
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Alidina, Mazhar Murtaza. "Precomputation-based sequential logic optimization for low power." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/36454.

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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.<br>Includes bibliographical references (leaves 69-71).<br>by Mazhar Murtaza Alidina.<br>M.S.
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Sapiña, Sanchis Julia. "Rewriting Logic Techniques for Program Analysis and Optimization." Doctoral thesis, Universitat Politècnica de València, 2018. http://hdl.handle.net/10251/94044.

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Esta tesis propone una metodología de análisis dinámico que mejora el diagnóstico de programas erróneos escritos en el lenguaje Maude. La idea clave es combinar técnicas de verificación de aserciones en tiempo de ejecución con la fragmentación dinámica de trazas de ejecución para detectar automáticamente errores en tiempo de ejecución, al tiempo que se reduce el tamaño y la complejidad de las trazas a analizar. En el caso de violarse una aserción, se infiere automáticamente el criterio de fragmentación, lo que facilita al usuario identificar rápidamente la fuente del error. En primer lugar, l
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Wang, Lingli. "Automated synthesis and optimization of multilevel logic circuits." Thesis, Edinburgh Napier University, 2000. http://researchrepository.napier.ac.uk/Output/4342.

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With the increased complexity of Very Large Scaled Integrated (VLSI) circuits, multilevel logic synthesis plays an even more important role due to its flexibility and compactness. The history of symbolic logic and some typical techniques for multilevel logic synthesis are reviewed. These methods include algorithmic approach; Rule-Based approach; Binary Decision Diagram (BDD) approach; Field Programmable Gate Array(FPGA) approach and several perturbation applications. One new kind of don't cares (DCs), called functional DCs has been proposed for multilevel logic synthesis. The conventional two-
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Dosi, Shubham. "Optimization and Further Development of an Algorithm for Driver Intention Detection with Fuzzy Logic and Edit Distance." Master's thesis, Universitätsbibliothek Chemnitz, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-202567.

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Inspired by the idea of vision zero, there is a lot of work that needs to be done in the field of advance driver assistance systems to develop more safer systems. Driver intention detection with a prediction of upcoming behavior of the driver is one possible solution to reduce the fatalities in road traffic. Driver intention detection provides an early warning of the driver's behavior to an Advanced Driver Assistance Systems (ADAS) and at the same time reduces the risk of non-essential warnings. This will significantly reduce the problem of warning dilemma and the system will become more safer
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Feng, Yi. "Dynamic Fuzzy Logic Control of GeneticAlgorithm Probabilities." Thesis, Högskolan Dalarna, Datateknik, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:du-3286.

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Genetic algorithms are commonly used to solve combinatorial optimizationproblems. The implementation evolves using genetic operators (crossover, mutation,selection, etc.). Anyway, genetic algorithms like some other methods have parameters(population size, probabilities of crossover and mutation) which need to be tune orchosen.In this paper, our project is based on an existing hybrid genetic algorithmworking on the multiprocessor scheduling problem. We propose a hybrid Fuzzy-Genetic Algorithm (FLGA) approach to solve the multiprocessor scheduling problem.The algorithm consists in adding a fuzzy
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Sunki, Supriya. "Performance optimization in three-dimensional programmable logic arrays (PLAs)." [Tampa, Fla.] : University of South Florida, 2005. http://purl.fcla.edu/fcla/etd/SFE0001255.

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Books on the topic "Logic optimizations"

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Gulati, Kanupriya, ed. Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-7518-8.

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Khatri, Sunil P. Advanced techniques in logic synthesis, optimizations and applications. Springer, 2011.

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Kastner, Ryan. Synthesis techniques and optimizations for reconfigurable systems. Kluwer Academic Publishers, 2004.

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Sasao, Tsutomu, ed. Logic Synthesis and Optimization. Springer US, 1993. http://dx.doi.org/10.1007/978-1-4615-3154-8.

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McAloon, Kenneth. Optimization and computational logic. Wiley, 1996.

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Sasao, Tsutomu. Logic Synthesis and Optimization. Springer US, 1993.

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Hooker, John. Logic-Based Methods for Optimization. John Wiley & Sons, Inc., 2000. http://dx.doi.org/10.1002/9781118033036.

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Ames Research Center. Artificial Intelligence Research Branch., ed. Efficient dynamic optimization of logic programs. NASA Ames Research Center, Artificial Intelligence Research Branch, 1992.

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Ames Research Center. Artificial Intelligence Research Branch., ed. Efficient dynamic optimization of logic programs. NASA Ames Research Center, Artificial Intelligence Research Branch, 1992.

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Chandru, Vijay. Optimization methods for logical inference. Wiley, 1999.

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Book chapters on the topic "Logic optimizations"

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Schrijvers, Tom. "Analyses, Optimizations and Extensions of Constraint Handling Rules: Ph.D. Summary." In Logic Programming. Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11562931_44.

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Kozen, Dexter, and Maria-Cristina Patron. "Certification of Compiler Optimizations Using Kleene Algebra with Tests." In Computational Logic — CL 2000. Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-44957-4_38.

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Yang, Yu-Shen, Subarna Sinha, Andreas Veneris, Robert Brayton, and Duncan Smith. "Automated Logic Restructuring with aSPFDs." In Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7518-8_15.

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Krishnaswamy, Smita, Haoxing Ren, Nilesh Modi, and Ruchir Puri. "Logic Difference Optimization for Incremental Synthesis." In Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7518-8_12.

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Bernasconi, Anna, Valentina Ciriani, Gabriella Trucco, and Tiziano Villa. "Logic Synthesis by Signal-Driven Decomposition." In Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7518-8_2.

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Bollapalli, Kalyana C., Sunil P. Khatri, and Laszlo B. Kish. "Digital Logic Using Non-DC Signals." In Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7518-8_20.

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Kravets, Victor N., and Alan Mishchenko. "Sequential Logic Synthesis Using Symbolic Bi-decomposition." In Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7518-8_3.

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Brayton, Robert, Alan Mishchenko, and Satrajit Chatterjee. "Boolean Factoring and Decomposition of Logic Networks." In Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7518-8_4.

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Debray, Saumya K. "Compiler optimizations for low-level redundancy elimination: An application of meta-level prolog primitives." In Meta-Programming in Logic. Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/3-540-56282-6_8.

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Qian, Weikang, Marc D. Riedel, Kia Bazargan, and David J. Lilja. "Synthesizing Combinational Logic to Generate Probabilities: Theories and Algorithms." In Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7518-8_18.

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Conference papers on the topic "Logic optimizations"

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Arenas, Marcelo, Pablo Barceló, Diego Bustamante, Jose Caraball, and Bernardo Subercaseaux. "A Uniform Language to Explain Decision Trees." In 21st International Conference on Principles of Knowledge Representation and Reasoning {KR-2023}. International Joint Conferences on Artificial Intelligence Organization, 2024. http://dx.doi.org/10.24963/kr.2024/6.

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The formal XAI community has studied a plethora of interpretability queries aiming to understand the classifications made by decision trees. However, a more uniform understanding of what questions we can hope to answer about these models, traditionally deemed to be easily interpretable, has remained elusive. In an initial attempt to understand uniform languages for interpretability, Arenas et al. proposed FOIL, a logic for explaining black-box ML models, and showed that it can express a variety of interpretability queries. However, we show that FOIL is limited in two important senses: (i) it i
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Yu, Xuewen, Pengcheng Huang, Haiyan Chen, and Wei Chen. "Critical Path Optimization for Logic Netlists." In 2024 9th International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2024. https://doi.org/10.1109/icicm63644.2024.10814480.

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Kennings, Andrew. "Session details: Logic optimizations for physical synthesis." In ISPD '08: International Symposium on Physical Design. ACM, 2008. http://dx.doi.org/10.1145/3250830.

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Nakamura, Kennichi, and Hiroki Nakahara. "Optimizations of Ternary Generative Adversarial Networks." In 2022 IEEE 52nd International Symposium on Multiple-Valued Logic (ISMVL). IEEE, 2022. http://dx.doi.org/10.1109/ismvl52857.2022.00031.

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Ehliar, Andreas, and Dake Liu. "An ASIC perspective on FPGA optimizations." In 2009 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2009. http://dx.doi.org/10.1109/fpl.2009.5272311.

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Lacey, David, Neil D. Jones, Eric Van Wyk, and Carl Christian Frederiksen. "Proving correctness of compiler optimizations by temporal logic." In the 29th ACM SIGPLAN-SIGACT symposium. ACM Press, 2002. http://dx.doi.org/10.1145/503272.503299.

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Nguyen, Hong Diep, Bogdan Pasca, and Thomas B. Preußer. "FPGA-Specific Arithmetic Optimizations of Short-Latency Adders." In 2011 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2011. http://dx.doi.org/10.1109/fpl.2011.49.

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Veenstra, Kerry, Bruce Pedersen, Jay Schleicher, and Chiakang Sung. "Optimizations for a highly cost-efficient programmable logic architecture." In the 1998 ACM/SIGDA sixth international symposium. ACM Press, 1998. http://dx.doi.org/10.1145/275107.275115.

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Nobre, Ricardo. "Identifying sequences of optimizations for HW/SW compilation." In 2013 23rd International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2013. http://dx.doi.org/10.1109/fpl.2013.6645615.

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Zhu, Keren, Mingjie Liu, Hao Chen, Zheng Zhao, and David Z. Pan. "Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network." In MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD. ACM, 2020. http://dx.doi.org/10.1145/3380446.3430622.

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Reports on the topic "Logic optimizations"

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Smith, James F., Rhyne III, and II Robert D. Fuzzy Logic Resource Management and Coevolutionary Game-based Optimization. Defense Technical Information Center, 2001. http://dx.doi.org/10.21236/ada390559.

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Borgwardt, Stefan, and Veronika Thost. Temporal Query Answering in EL. Technische Universität Dresden, 2015. http://dx.doi.org/10.25368/2022.214.

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Context-aware systems use data about their environment for adaptation at runtime, e.g., for optimization of power consumption or user experience. Ontology-based data access (OBDA) can be used to support the interpretation of the usually large amounts of data. OBDA augments query answering in databases by dropping the closed-world assumption (i.e., the data is not assumed to be complete any more) and by including domain knowledge provided by an ontology. We focus on a recently proposed temporalized query language that allows to combine conjunctive queries with the operators of the well-known pr
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Lee, Eleanor, Brian Coffey, Andrew McNeil, and Thierry Nouidui. Automated Production of Optimization-Based Control Logics for Dynamic Façade Systems, with Experimental Application to Two-Zone External Venetian Blinds. Office of Scientific and Technical Information (OSTI), 2013. http://dx.doi.org/10.2172/1871301.

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Pasupuleti, Murali Krishna. Automated Smart Contracts: AI-powered Blockchain Technologies for Secure and Intelligent Decentralized Governance. National Education Services, 2025. https://doi.org/10.62311/nesx/rrv425.

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Abstract: Automated smart contracts represent a paradigm shift in decentralized governance by integrating artificial intelligence (AI) with blockchain technologies to enhance security, scalability, and adaptability. Traditional smart contracts, while enabling trustless and automated transactions, often lack the flexibility to adapt to dynamic regulatory frameworks, evolving economic conditions, and real-time security threats. AI-powered smart contracts leverage machine learning, reinforcement learning, and predictive analytics to optimize contract execution, detect fraudulent transactions, and
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