Journal articles: 'Linear integrated circuits'

1

Silva, M. M. "Linear integrated circuits." Proceedings of the IEEE 73, no. 8 (1985): 1340. http://dx.doi.org/10.1109/proc.1985.13290.

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BARNABY, H. J. "TOTAL DOSE EFFECTS IN LINEAR BIPOLAR INTEGRATED CIRCUITS." International Journal of High Speed Electronics and Systems 14, no. 02 (June 2004): 519–41. http://dx.doi.org/10.1142/s0129156404002491.

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Electronics systems that operate in space or strategic environments can be severely damaged by exposure to ionizing radiation. Space-based systems that utilize linear bipolar integrated circuits are particularly susceptible to radiation-induced damage because of the enhanced sensitivity of these circuits to the low rate of radiation exposure. The phenomenon of enhanced low-dose-rate sensitivity (ELDRS) demonstrates the need for a comprehensive understanding of the mechanisms of total dose effects in linear bipolar circuits. The majority of detailed bipolar total dose studies to date have focused on radiation effects mechanisms at either the process or transistor level. The goal of this text is to provide an overview of total dose mechanisms from the circuit perspective; in particular, the effects of transistor gain degradation on specific linear bipolar circuit parameters and the effects of circuit parameter degradation on select linear bipolar circuit applications.

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Rax, B. G., A. H. Johnston, and C. I. Lee. "Proton damage effects in linear integrated circuits." IEEE Transactions on Nuclear Science 45, no. 6 (1998): 2632–37. http://dx.doi.org/10.1109/23.736507.

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Rax, B. G., A. H. Johnston, and T. Miyahira. "Displacement damage in bipolar linear integrated circuits." IEEE Transactions on Nuclear Science 46, no. 6 (1999): 1660–65. http://dx.doi.org/10.1109/23.819135.

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Jantos, P., D. Grzechca, and J. Rutkowski. "Evolutionary algorithms for global parametric fault diagnosis in analogue integrated circuits." Bulletin of the Polish Academy of Sciences: Technical Sciences 60, no. 1 (March 1, 2012): 133–42. http://dx.doi.org/10.2478/v10175-012-0019-4.

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Evolutionary algorithms for global parametric fault diagnosis in analogue integrated circuitsAn evolutionary method for analogue integrated circuits diagnosis is presented in this paper. The method allows for global parametric faults localization at the prototype stage of life of an analogue integrated circuit. The presented method is based on the circuit under test response base and the advanced features classification. A classifier is built with the use of evolutionary algorithms, such as differential evolution and gene expression programming. As the proposed diagnosis method might be applied at the production phase there is a method for shortening the diagnosis time suggested. An evolutionary approach has been verified with the use of several exemplary circuits - an oscillator, a band-pass filter and two operational amplifiers. A comparison of the presented algorithm and two classical methods - the linear classifier and the nearest neighborhood method - proves that the heuristic approach allows for acquiring significantly better results.

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Abraitis, Vidas, and Žydrūnas Tamoševičius. "Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA." Solid State Phenomena 144 (September 2008): 214–19. http://dx.doi.org/10.4028/www.scientific.net/ssp.144.214.

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Transition delay testing of sequential circuits in a clocked environment is analyzed. There are presented two test pattern generator methods for built in self testing of the circuit implemented as Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) of Virtex family. Cellular automaton and Linear Feedback Shift Register (LFSR) structures are used for test sequence generation. The circuits are tested as the black boxes under Transition fault model. Experimental results of the test pattern generation methods are presented and analyzed. Results compared with exhaustive test of transition faults for ASICs and programmable integrated circuits with given configuration.

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Robinson, Megan C., Zoya Popović, and Gregor Lasser. "Linear broadband interference suppression circuit based on GaN monolithic microwave integrated circuits." IET Circuits, Devices & Systems 17, no. 4 (July 2023): 213–24. http://dx.doi.org/10.1049/cds2.12159.

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Vosper, J. V. "Book Review: Linear Integrated Circuits: Operation and Applications." International Journal of Electrical Engineering & Education 23, no. 2 (April 1986): 184. http://dx.doi.org/10.1177/002072098602300223.

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Jain, L. C. "Book Review: Operational Amplifiers and Linear Integrated Circuits:." International Journal of Electrical Engineering & Education 29, no. 2 (April 1992): 162. http://dx.doi.org/10.1177/002072099202900212.

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Buchner, Stephen, and Dale McMorrow. "Single-Event Transients in Bipolar Linear Integrated Circuits." IEEE Transactions on Nuclear Science 53, no. 6 (December 2006): 3079–102. http://dx.doi.org/10.1109/tns.2006.882497.

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Sun, Zhi, Weijia Wei, Mingyue Zhang, Wenjia Shi, Yeqing Zong, Yihua Chen, Xiaojing Yang, Bo Yu, Chao Tang, and Chunbo Lou. "Synthetic robust perfect adaptation achieved by negative feedback coupling with linear weak positive feedback." Nucleic Acids Research 50, no. 4 (February 15, 2022): 2377–86. http://dx.doi.org/10.1093/nar/gkac066.

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Abstract Unlike their natural counterparts, synthetic genetic circuits are usually fragile in the face of environmental perturbations and genetic mutations. Several theoretical robust genetic circuits have been designed, but their performance under real-world conditions has not yet been carefully evaluated. Here, we designed and synthesized a new robust perfect adaptation circuit composed of two-node negative feedback coupling with linear positive feedback on the buffer node. As a key feature, the linear positive feedback was fine-tuned to evaluate its necessity. We found that the desired function was robustly achieved when genetic parameters were varied by systematically perturbing all interacting parts within the topology, and the necessity of the completeness of the topological structures was evaluated by destroying key circuit features. Furthermore, different environmental perturbances were imposed onto the circuit by changing growth rates, carbon metabolic strategies and even chassis cells, and the designed perfect adaptation function was still achieved under all conditions. The successful design of a robust perfect adaptation circuit indicated that the top-down design strategy is capable of predictably guiding bottom-up engineering for robust genetic circuits. This robust adaptation circuit could be integrated as a motif into more complex circuits to robustly implement more sophisticated and critical biological functions.

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Johnston, A. H., and R. E. Plaag. "Models for Total Dose Degradation of Linear Integrated Circuits." IEEE Transactions on Nuclear Science 34, no. 6 (1987): 1474–80. http://dx.doi.org/10.1109/tns.1987.4337502.

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Zikumaru, Yushi. "NQR Spectrometer with a Two Integrated Circuits Radio Frequency Head." Zeitschrift für Naturforschung A 45, no. 3-4 (April 1, 1990): 591–94. http://dx.doi.org/10.1515/zna-1990-3-467.

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Abstract An NQR spectrometer has been constructed using two linear integrated circuits in its oscillator-detector. This is very simple and compact and works in range 3-65 MHz. The radio frequency voltage can be varied from 10 mVp-p to 15 V p-p by changing the supply-voltage of an integrated circuit μA 733. The utility of the spectrometer is demonstrated by recording 35Cl NQR spectra in p-C6H4Cl2 , NaClO3 , and KClO3 .

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Zhang, Xiao Feng, Fo Chang Xie, Guo Wei Yang, and Wei Zhang. "The Transceiver Circuit Design of Digital Ultrasonic System." Advanced Materials Research 834-836 (October 2013): 968–73. http://dx.doi.org/10.4028/www.scientific.net/amr.834-836.968.

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This paper introduces the design process of the digital ultrasonic transmission circuit: echo receiving circuit and the echo signal regulate circuit. Among them, outside 500 V DC - DC module for high voltage power input, use non-tuned type circuit design ultrasonic transmission circuit ; Select high voltage fast recovery diode FR107 design echo receiving limiter circuit; Using ultra-high speed, low noise, low distortion of the integrated operational amplifier MAX4104ESA design preamplifier circuits and the band-pass filter circuits; Using linear decibels, low noise, wide bandwidth, high gain accuracy amplifier AD603 design echo amplifying circuit. The experimental results indicate that the basic realization of the ultrasonic transceiver circuit and echo signal conditioning functions.

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Widemann, C., S. Stegemann, W. John, and W. Mathis. "Analytic investigations on the susceptibility of nonlinear analog circuits to substrate noise." Advances in Radio Science 11 (July 4, 2013): 171–75. http://dx.doi.org/10.5194/ars-11-171-2013.

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Abstract. This work deals with the conducted susceptibility of nonlinear analog circuits with respect to substrate noise. The substrate coupling mechanism is modeled by a passive three-terminal network that is obtained by means of the finite element method with a subsequently performed model order reduction. Applying this substrate model to the bulk terminal of MOS transistors in integrated analog circuits, it is possible to examine the influence of substrate noise on the circuit's functionality. By means of a block-oriented approach, analytic expressions for the output behavior of the circuits are found. The utilized multi-input Wiener model separates the linear dynamic from the nonlinear static circuit properties. Due to this separation the frequency response of both signals, i.e.,input signal and substrate noise, respectively, can be identified, and hence, the frequency range in which the circuit is most susceptible to substrate noise. Since the nonlinear static behavior of each MOS transistor depends on two signals, truncated multivariate Taylor series expansions of the nonlinear elements are performed on the basis of the EKV model description (Enz et al., 1995). The proposed modeling is illustrated by a simple example.

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Parandin, Fariborz, Saeed Olyaee, Reza Kamarian, and Mohamadreza Jomour. "Design and Simulation of Linear All-Optical Comparator Based on Square-Lattice Photonic Crystals." Photonics 9, no. 7 (June 29, 2022): 459. http://dx.doi.org/10.3390/photonics9070459.

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An optical comparator is an important logic circuit used in digital designs. Photonic crystals are among the platforms for implementing different kinds of gates and logic circuits, and they are structures with alternating refractive indices. In this paper, an optical comparator is designed and simulated based on a square lattice photonic crystal. In the design of this comparator, a small-sized structure is used. The simulation results show that in the proposed comparator, there is a high difference between logical values “0” and “1”, which are defined based on the optical power level. Due to the small size of this comparator and the adequate difference between logical values “0” and “1”, this structure suits photonic integrated circuits with high accuracy. The proposed structure footprint is 149.04 µm2, and the calculated rise time for this circuit is less than 0.4 ps.

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Singh, Jagmeet, Hugh Morison, Zhimu Guo, Bicky A. Marquez, Omid Esmaeeli, Paul R. Prucnal, Lukas Chrostowski, Sudip Shekhar, and Bhavin J. Shastri. "Neuromorphic photonic circuit modeling in Verilog-A." APL Photonics 7, no. 4 (April 1, 2022): 046103. http://dx.doi.org/10.1063/5.0079984.

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One of the significant challenges in neuromorphic photonic architectures is the lack of good tools to simulate large-scale photonic integrated circuits. It is crucial to perform simulations on a single platform to capture the circuit’s behavior in the presence of both optical and electrical components. Here, we adopted a Verilog-A based approach to model neuromorphic photonic circuits by considering both the electrical and optical properties. Verilog-A models for the primary optical devices, such as lasers, couplers, waveguides, phase shifters, and photodetectors, are discussed, along with studying the composite devices such as microring resonators. Model parameters for different optical devices are extracted and tuned by analyzing the measured data. The simulated and experimental results are also compared for validation of Verilog-A models. Finally, a single photonic neuron circuit is simulated by implementing input, weight, and non-linear activation function by using lasers, microring resonators, and modulator, respectively. Electro-optical rapid co-simulation would significantly improve the efficiency of optimizing the devices and provide an accurate simulation of the circuit performance.

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Dahl, Nicolai J., Pere L. Muntal, and Michael A. E. Andersen. "Systematic Design of a Pseudodifferential VCO Using Monomial Fitting." Elektronika ir Elektrotechnika 29, no. 5 (October 31, 2023): 36–43. http://dx.doi.org/10.5755/j02.eie.35279.

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Digital integrated electronics benefits from its higher abstraction level, allowing optimisation methods and automated workflows. However, analogue integrated circuit design is still predominantly done manually, leading to lengthy design cycles. This paper proposes a new systematic design approach for the sizing of analogue integrated circuits to address this issue. The method utilises a surrogate optimisation technique that approximates a simple monomial function based on few simulation results. These monomials are convex and can be optimised using a simple linear optimisation routine, resulting in a single global optimal solution. We show that monomial functions, in many cases, have an analytic relation to integrated circuits, making them well suited for the application. The method is demonstrated by designing a 14 MHz pseudodifferential voltage-controlled oscillator (VCO) with minimised current consumption and is manufactured in a 180 nm process. The measured total current matches the predicted and is lower than that for other similar state-of-the-art VCOs.

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Liu, Zhuang Jian, Yong Wei Zhang, Ji Zhou Song, Dae Hyeong Kim, Yong Gang Huang, and John Rogers. "Numerical Simulation of Stretchable and Foldable Silicon Integrated Circuits." Advanced Materials Research 74 (June 2009): 197–200. http://dx.doi.org/10.4028/www.scientific.net/amr.74.197.

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This paper presents numerical simulation strategies for stretchable silicon integrated circuits that use stiff thin film on elastomeric substrates. Detailed numerical simulation studies reveal the key underlying aspects of these systems. The results indicate, as an example, optimized mechanics and materials for circuits that exhibit maximum principal strains less than 0.2% even for applied strains of up to ~90%. Simple circuits, including CMOS inverters provide an example that validates these designs. The results suggest practical routes to high performance electronics with linear elastic responses to large strain deformations, suitable for diverse applications that are not readily addressed with conventional wafer-based technologies.

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Mukherjee, Parijat, G. Peter Fang, Rod Burt, and Peng Li. "Efficient Identification of Unstable Loops in Large Linear Analog Integrated Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 9 (September 2012): 1332–45. http://dx.doi.org/10.1109/tcad.2012.2194492.

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Johnston, A. H., G. M. Swift, and B. G. Rax. "Total dose effects in conventional bipolar transistors and linear integrated circuits." IEEE Transactions on Nuclear Science 41, no. 6 (December 1994): 2427–36. http://dx.doi.org/10.1109/23.340598.

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Johnston, A. H., B. G. Rax, and C. I. Lee. "Enhanced damage in linear bipolar integrated circuits at low dose rate." IEEE Transactions on Nuclear Science 42, no. 6 (1995): 1650–59. http://dx.doi.org/10.1109/23.488762.

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Lubecke, V. M., W. r. McGrath, Yu-Chong Tai, and D. B. Rutledge. "Microfabrication of linear translator tuning elements in submillimeter-wave integrated circuits." Journal of Microelectromechanical Systems 7, no. 4 (1998): 404–10. http://dx.doi.org/10.1109/84.735348.

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Johnston, A. H., and B. G. Rax. "Testing and Qualifying Linear Integrated Circuits for Radiation Degradation in Space." IEEE Transactions on Nuclear Science 53, no. 4 (August 2006): 1779–86. http://dx.doi.org/10.1109/tns.2006.878291.

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Savchenko, Andrey, A. Kulay, I. Strukov, K. Chubur, Sergey Grechanyy, and Konstantin Zolnikov. "A PHYSICAL MODEL FOR ESTIMATING THE INTENSITY OF SINGLE EVENTS WHEN EXPOSED TO INDIVIDUAL NUCLEAR PARTICLES." Modeling of systems and processes 12, no. 4 (January 23, 2020): 78–83. http://dx.doi.org/10.12737/2219-0767-2020-12-4-78-83.

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Neudeck, Philip G., David J. Spry, Liang Yu Chen, Carl W. Chang, Glenn M. Beheim, Robert S. Okojie, Laura J. Evans, et al. "Prolonged 500 °C Operation of 6H-SiC JFET Integrated Circuitry." Materials Science Forum 615-617 (March 2009): 929–32. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.929.

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This paper updates the long-term 500 °C electrical testing results from 6H-SiC junction field effect transistors (JFETs) and small integrated circuits that were introduced at ICSCRM-2007. Two packaged JFETs have now been operated in excess of 7000 hours at 500 °C with less than 10% degradation in linear I-V characteristics. Several simple digital and analog demonstration integrated circuits successfully operated for 2000-6500 hours at 500 °C before failure.

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BAUMGARTNER, C., and O. A. PALUSINSKI. "METHODOLOGY FOR FORMULATION OF CIRCUIT EQUATIONS FOR SPECTRAL ANALYSIS." Journal of Circuits, Systems and Computers 02, no. 02 (June 1992): 187–206. http://dx.doi.org/10.1142/s0218126692000131.

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While analog simulation of integrated circuits is a very powerful design tool, the maximum size of the investigated circuits is limited by the necessary CPU times. Using spectral technique with respect to Chebyshev polynomials and in conjunction with waveform relaxation was shown to considerably reduce the computational effort for transient simulation. After a brief introduction of this novel simulation technique, equation formulation will be described in detail. Also discussed is how the choice of circuit variables used for formulation affects theoretical and numerical properties of the method. Element “stamps” are given which can be used for the construction and solution of the linear equation system.

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KAMEDA, SEIJI, AKIRA HONDA, and TETSUYA YAGI. "REAL TIME IMAGE PROCESSING WITH AN ANALOG VISION CHIP SYSTEM." International Journal of Neural Systems 09, no. 05 (October 1999): 423–28. http://dx.doi.org/10.1142/s0129065799000423.

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A linear analog network model is proposed to characterize the function of the outer retinal circuit in terms of the standard regularization theory. Inspired by the function and the architecture of the model, a vision chip has been designed using analog CMOS Very Large Scale Integrated circuit technology. In the chip, sample/hold amplifier circuits are incorporated to compensate for statistic transistor mismatches. Accordingly, extremely low noise outputs were obtained from the chip. Using the chip and a zero-crossing detector, edges of given images were effectively extracted in indoor illumination.

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Shaw, Brian M. "Book Review: Op-Amps and Linear Integrated Circuits (3rd Edition): A. GAYAKWAD." International Journal of Electrical Engineering & Education 32, no. 2 (April 1995): 190–91. http://dx.doi.org/10.1177/002072099503200220.

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Johnston, Allan H., and B. G. Rax. "Failure Modes and Hardness Assurance for Linear Integrated Circuits in Space Applications." IEEE Transactions on Nuclear Science 57, no. 4 (August 2010): 1966–72. http://dx.doi.org/10.1109/tns.2010.2049583.

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Gorelick, J. L., R. Ladbury, and L. Ka. "The effects of neutron irradiation on gamma sensitivity of linear integrated circuits." IEEE Transactions on Nuclear Science 51, no. 6 (December 2004): 3679–85. http://dx.doi.org/10.1109/tns.2004.839245.

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Eranosyan, V. Ts. "Automated installation for measuring low-frequency noise parameters of linear integrated circuits." Measurement Techniques 30, no. 6 (June 1987): 570–72. http://dx.doi.org/10.1007/bf00866854.

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Wang, Han, Yi Cheng Zeng, and Zhi Jun Li. "Current Mode Maximum and Minimum Circuit." Applied Mechanics and Materials 577 (July 2014): 478–81. http://dx.doi.org/10.4028/www.scientific.net/amm.577.478.

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A new current mode circuit which can maintain the maximum output and minimum output at the same time is presented in this paper. The design technique is achieved by the combination of trans linear loop, winner take all (WTA) circuit and loser take all (LTA) circuit. Therefore, the proposed circuit can be more practical than conventional circuits and can be easily designed in 0.5 μm CMOS technology for CSMC. Analysis and simulations of WTA and LTA circuit have been shown to display the usability of the proposed circuit, where the input frequency range is around 10 MHz. The proposed circuit can also play a neuron role in artificial neural network (ANN) implemented in the form of an integrated circuit.

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Liu, Saifei, Richard F. Newland, Phillip J. Tully, Sigrid C. Tuble, and Robert A. Baker. "In Vitro Evaluation of Gaseous Microemboli Handling of Cardiopulmonary Bypass Circuits with and without Integrated Arterial Line Filters." Journal of ExtraCorporeal Technology 43, no. 3 (September 2011): 107–14. http://dx.doi.org/10.1051/ject/201143107.

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The delivery of gaseous microemboli (GME) by the cardiopulmonary bypass circuit should be minimized whenever possible. Innovations in components, such as the integration of arterial line filter (ALF) and ALFs with reduced priming volumes, have provided clinicians with circuit design options. However, before adopting these components clinically, their GME handling ability should be assessed. This study aims to compare the GME handling ability of different oxygenator/ALF combinations with our currently utilized combination. Five commercially available oxygenator/ALF combinations were evaluated in vitro: Terumo Capiox SX25RX and Dideco D734 (SX/ D734),Terumo Capiox RX25R and AF125 (RX/AF125),Terumo FX25R (FX), Sorin Synthesis with 102 μm reservoir filter (SYN102), and Sorin Synthesis with 40 μm reservoir filter (SYN40). GME handling was studied by introducing air into the venous return at 100 mL/min for 60 seconds under two flow/ pressure combinations : 3.5 L/min, 150 mmHg and 5 L/min, 200 mmHg. Emboli were measured at three positions in the circuit using the Emboli Detection and Classification (EDAC®) Quantifier and analyzed with the General Linear Model. All circuits significantly reduced GME. The SX/D734 and SYN40 circuits were most efficient in GME removal whilst the SYN102 handled embolic load (count and volume) least efficiently (p < .001). A greater number of emboli <70 μm were observed for the SYN102, FX and RX/AF125 circuits (p < .001). An increase in embolic load occurred with higher flow/pressure in all circuits (p < .001). The venous reservoir significantly influences embolic load delivered to the oxygenator (p < .001). The majority of introduced venous air was removed; however, significant variation existed in the ability of the different circuits to handle GME. Venous reservoir design influenced the overall GME handling ability. GME removal was less efficient at higher flow and pressure, and for smaller sized emboli. The clinical significance of reducing GME requires further investigation.

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Saleh, Alaa, Abdel Kader El Rafei, Mountakha Dieng, Tibault Reveyrand, Raphael Sommet, Jean-Michel Nebus, and Raymond Quere. "Compact RF non-linear electro thermal model of SiGe HBT for the design of broadband ADC's." International Journal of Microwave and Wireless Technologies 4, no. 6 (August 29, 2012): 569–78. http://dx.doi.org/10.1017/s1759078712000566.

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The design of high speed integrated circuits heavily relies on circuit simulation and requires compact transistor models. This paper presents a non-linear electro-thermal model of SiGe heterojunction-bipolar transistor (HBT). The non-linear model presented in this paper uses a hybrid π topology and it is extracted using IV and S-parameter measurements. The thermal sub-circuit is extracted using low-frequency S-parameter measurements. The model extraction procedure is described in detail. It is applied here to the modeling of npn SiGe HBTs. The proposed non-linear electro-thermal model is expected to be used for the design of high-speed electronic functions such as broadband analog digital converters in which both electrical and thermal aspects are engaged. The main focus and contribution of this paper stands in the fact that the proposed non-linear model covers wideband-frequency range (up to 65 GHz).

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Piqueira, José R. C., Maurízio Q. de Oliveira, and Luiz H. A. Monteiro. "Linear Approach for Synchronous State Stability in Fully Connected PLL Networks." Mathematical Problems in Engineering 2008 (2008): 1–13. http://dx.doi.org/10.1155/2008/364084.

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Synchronization is an essential feature for the use of digital systems in telecommunication networks, integrated circuits, and manufacturing automation. Formerly, master-slave (MS) architectures, with precise master clock generators sending signals to phase-locked loops (PLLs) working as slave oscillators, were considered the best solution. Nowadays, the development of wireless networks with dynamical connectivity and the increase of the size and the operation frequency of integrated circuits suggest that the distribution of clock signals could be more efficient if distributed solutions with fully connected oscillators are used. Here, fully connected networks with second-order PLLs as nodes are considered. In previous work, how the synchronous state frequency for this type of network depends on the node parameters and delays was studied and an expression for the long-term frequency was derived (Piqueira, 2006). Here, by taking the first term of the Taylor series expansion for the dynamical system description, it is shown that for a generic network withNnodes, the synchronous state is locally asymptotically stable.

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Zhao, San Ping. "A Pressure Sensor with Electrical Readout Based on IL Electrofluidic Circuit." Applied Mechanics and Materials 66-68 (July 2011): 1936–41. http://dx.doi.org/10.4028/www.scientific.net/amm.66-68.1936.

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This paper presents a novel pressure sensor based on IL electrofluidic circuit. The simple configuration makes the device capable of being seamlessly integrated to wide varieties of PDMS microfluidic devices. The experimental results demonstrate that IL-filled microfluidic channels can be utilized as electrical resistors to construct functional circuits, and an electrofluidic Wheatstone bridge circuit has been designed to construct the pressure sensor. In the pressure sensor performance characterization, the calibration results show that the gate voltage is linear proportional to the applied pressure with sensitivity of 8.45 mV/psi and the pressure as small as 2.5 psi can be easily detected.

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Zhou, Yang, Sitao Zhang, and Chongyi Chen. "Optimization and improvement of voltage mode band-gap reference circuit and current mode band-gap reference circuit based on comparative analysis method." Theoretical and Natural Science 25, no. 1 (December 20, 2023): 136–43. http://dx.doi.org/10.54254/2753-8818/25/20240946.

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Voltage mode band-gap reference source and current mode band-gap reference source is the basic unit of integrated circuit, which plays an important role in some circuit systems such as low-voltage linear regulator, power control chip and analog-to-digital/analog-to-digital converter. Band-gap reference circuit is divided into voltage mode band-gap reference circuit and current mode band-gap reference circuit, and their basic principles and optimization methods are different. The voltage mode bandgap reference voltage is generated by superimposing voltages with positive and negative temperature coefficients, thereby producing a low-temperature related factor. In contrast, the current mode bandgap reference generates a reference voltage by superimposing currents with positive and negative temperature coefficients, requiring appropriate resistance matching and compensation. This paper analyzes the basic principles of the above two band-gap reference circuits, analyzes the temperature characteristics and mismatch sources of them, compares the research results including the implementation mode, temperature characteristics, application range and optimization scheme of the two, and looks forward to the future development prospect of both types of circuits.

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Dimopoulos, K. Z., J. N. Avaritsiotis, and S. J. White. "Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits." Active and Passive Electronic Components 14, no. 4 (1992): 199–218. http://dx.doi.org/10.1155/1992/13545.

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A method for the electrical parameters analysis and modelling of lossy-coupled multilayer on-chip interconnection lines at high bit rates is presented in detail. It can be used by the VLSI designer to analyze on-chip interconnections with linear, as well as nonlinear/time varying terminators and to simulate the pulse propagation characteristics in high-speed integrated circuits. First the capacitance, inductance, conductance and resistance matrices per unit length for the given multiconductor geometry is computed. A multiple coupled line model consisting of uncoupled lossy transmission lines and linear dependent current and voltage sources if finally calculated according to the capacitance, inductance, conductance and resistance matrix values computed.

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Borys, Andrzej. "On Definition of Operator o for Weakly Nonlinear Circuits." International Journal of Electronics and Telecommunications 62, no. 3 (September 1, 2016): 253–59. http://dx.doi.org/10.1515/eletel-2016-0034.

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Abstract For the first time, operator o appeared in the literature on weakly nonlinear circuits in a Narayanan’s paper on modelling transistor nonlinear distortion with the use of Volterra series. Its definition was restricted only to the linear part of a nonlinear circuit description. Obviously, as we show here, Narayanan’s operator o had meaning of a linear convolution integral. The extended version of this operator, which was applied to the whole nonlinear circuit representation by the Volterra series, was introduced by Meyer and Stephens in their paper on modelling nonlinear distortion in variable-capacitance diodes. We show here that its definition as well as another definition communicated to the author of this paper are faulty. We draw here attention to these facts because the faults made by Meyer and Stephens were afterwards replicated in publications of Palumbo and his coworkers on harmonic distortion calculation in integrated CMOS amplifiers, and recently in a paper about distortion analysis of parametric amplifier by H. Shrimali and S. Chatterjee. These faults are also present in some class notes for students, which are available on WWW-pages.

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Deval, Y., H. Lapuyade, R. Fouillat, H. Barnaby, F. Darracq, R. Briand, D. Lewis, and R. D. Schrimpf. "Evaluation of a design methodology dedicated to dose-rate-hardened linear integrated circuits." IEEE Transactions on Nuclear Science 49, no. 3 (June 2002): 1468–73. http://dx.doi.org/10.1109/tns.2002.1039685.

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42

Weng, T., S. Stegemann, W. John, and W. Mathis. "An identification procedure of multi-input Wiener models for the distortion analysis of nonlinear circuits." Advances in Radio Science 11 (July 4, 2013): 165–70. http://dx.doi.org/10.5194/ars-11-165-2013.

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Abstract. In this contribution, a system identification procedure of a two-input Wiener model suitable for the analysis of the disturbance behavior of integrated nonlinear circuits is presented. The identified block model is comprised of two linear dynamic and one static nonlinear block, which are determined using an parameterized approach. In order to characterize the linear blocks, an correlation analysis using a white noise input in combination with a model reduction scheme is adopted. After having characterized the linear blocks, from the output spectrum under single tone excitation at each input a linear set of equations will be set up, whose solution gives the coefficients of the nonlinear block. By this data based black box approach, the distortion behavior of a nonlinear circuit under the influence of an interfering signal at an arbitrary input port can be determined. Such an interfering signal can be, for example, an electromagnetic interference signal which conductively couples into the port of consideration.

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McMORROW, DALE, JOSEPH S. MELINGER, and ALVIN R. KNUDSON. "SINGLE-EVENT EFFECTS IN III-V SEMICONDUCTOR ELECTRONICS." International Journal of High Speed Electronics and Systems 14, no. 02 (June 2004): 311–25. http://dx.doi.org/10.1142/s0129156404002375.

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Single-event effects are a serious concern for high-speed III-V semiconductor devices operating in radiation-intense environments. GaAs integrated circuits (ICs) based on field effect transistor technology exhibit single-event upset sensitivity to protons and very low linear energy transfer (LET) particles. The current understanding of single-event effects in III-V circuits and devices, and approaches for mitigating their impact, are discussed.

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Prakht, V. A., V. V. Goman, and A. S. Paramonov. "Design Optimization of Secondary Element of Single-Sided Linear Induction Motors Using a Genetic Algorithm." ENERGETIKA. Proceedings of CIS higher education institutions and power engineering associations 64, no. 6 (December 6, 2021): 505–16. http://dx.doi.org/10.21122/1029-7448-2021-64-6-505-516.

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The article focuses on the use of genetic algorithms for the design of linear induction motors. Comparison of genetic algorithm with classical methods in the context of electrical machines designing has been carried out. The results of solving an optimization problem for two designs are presented, viz. a laboratory linear induction electric motor based on a three-phase SL-5-100 inductor and a traction single-sided linear induction electric motor of an urban transport system. The optimality criterion included maximizing the power factor and efficiency, as well as the rigidity of the mechanical characteristic while ensuring a starting traction force of at least a set value. The results of optimization of such parameters of the secondary element as the width and thickness of the conductive strip as well as the thickness of the magnetic circuit are described. The relevance of the problem of optimizing the parameters of the secondary element with unchanged parameters of the inductor is due to the fact that the same inductor can be used to build various structures, while the secondary element is created for each specific application and integrated directly into the working body of the mechanism or is a driven product. To calculate the traction and energy characteristics of linear induction electric motors, an electromagnetic model based on detailed equivalent circuits was used, taking into account longitudinal and transverse edge effects and providing a calculation time for one set of parameters of about 1 s. In accordance with this model, the electric motor is reduced to a set of three detailed equivalent circuits: a magnetic circuit, primary and secondary electrical circuits. The result of the optimization of these electric motors was an increase in the efficiency by 1.6 and 1.4 %, respectively, an increase in the power factor by 0.9 and 0.2 %, and an increase in the rigidity of traction characteristics and starting traction force.

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Caselli, Michele, Marco Ronchi, and Andrea Boni. "Power Management Circuits for Low-Power RF Energy Harvesters." Journal of Low Power Electronics and Applications 10, no. 3 (September 19, 2020): 29. http://dx.doi.org/10.3390/jlpea10030029.

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The paper describes the design and implementation of power management circuits for RF energy harvesters suitable for integration in wireless sensor nodes. In particular, we report the power management circuits used to provide the voltage supply of an integrated temperature sensor with analog-to-digital converter. A DC-DC boost converter is used to transfer efficiently the energy harvested from a generic radio-frequency rectifier into a charge reservoir, whereas a linear regulator scales the voltage supply to a suitable value for a sensing and conversion circuit. Implemented in a 65 nm CMOS technology, the power management system achieves a measured overall efficiency of 20%, with an available power of 4.5 μW at the DC-DC converter input. The system can sustain a temperature measurement rate of one sample/s with an RF input power of −28 dBm, making it compatible with the power levels available in generic outdoor environments.

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Wang, San-Fu. "A 5 V-to-3.3 V CMOS Linear Regulator with Three-Output Temperature-Independent Reference Voltages." Journal of Sensors 2016 (2016): 1–7. http://dx.doi.org/10.1155/2016/1436371.

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This paper presents a 5 V-to-3.3 V linear regulator circuit, which uses 3.3 V CMOS transistors to replace the 5 V CMOS transistors. Thus, the complexity of the manufacturing semiconductor process can be improved. The proposed linear regulator is implemented by cascode architecture, which requires three different reference voltages as the bias voltages of its circuit. Thus, the three-output temperature-independent reference voltage circuit is proposed, which provides three accurate reference voltages simultaneously. The three-output temperature-independent reference voltages also can be used in other circuits of the chip. By using the proposed temperature-independent reference voltages, the proposed linear regulator can provide an accurate output voltage, and it is suitable for low cost, small size, and highly integrated system-on-chip (SoC) applications. Moreover, the proposed linear regulator uses the cascode technique, which improves both the gain performance and the isolation performance. Therefore, the proposed linear regulator has a good performance in reference voltage to output voltage isolation. The voltage variation of the linear regulator is less than 2.153% in the temperature range of −40°C–120°C, and the power supply rejection ratio (PSRR) is less than −42.8 dB at 60 Hz. The regulator can support 0~200 mA output current. The core area is less than 0.16 mm2.

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Liu, Lun Cai, Xiao Zong Huang, and Wen Gang Huang. "An Integrated Optical Sensor Receiver with the Sensitivity of 0.7 μA Fabricated with Standard CMOS Process." Applied Mechanics and Materials 251 (December 2012): 206–9. http://dx.doi.org/10.4028/www.scientific.net/amm.251.206.

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A fully integrated CMOS receiver front-end with digital output for optical signal processing system is presented. This circuit is composed of trans-impedance amplifier (TIA) for weak optical current detection, post-amplifier for both a linear and limiting amplification, control circuits and the digital output interface. Measured with photodiode which is driven by pulse voltage source, a sensitivity of 0.7μA was achieved. The current model methodology is employed to optimize the noise performance. The front-end consumes the current of 1.5mA with the power supply of 3.3V. The design was done in a low-cost standard CMOS process with 0.6μm featured size, taking area of 600μm×150μm excluding the bonding pads.

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Wu, Anquan, Bin Liang, Yaqing Chi, and Zhenyu Wu. "Investigation of Heavy-Ion Induced Single-Event Transient in 28 nm Bulk Inverter Chain." Symmetry 12, no. 4 (April 15, 2020): 624. http://dx.doi.org/10.3390/sym12040624.

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The reliability of integrated circuits under advanced process nodes is facing more severe challenges. Single-event transients (SET) are an important cause of soft errors in space applications. The SET caused by heavy ions in the 28 nm bulk silicon inverter chains was studied. A test chip with good symmetry layout design was fabricated based on the 28 nm process, and the chip was struck by using 5 kinds of heavy ions with different linear energy transfer (LET) values on heavy-ion accelerator. The research results show that in advanced technology, smaller sensitive volume makes SET cross-section measured at 28 nm smaller than 65 nm by an order of magnitude, the lower critical charge required to generate SET will increase the reliability threat of low-energy ions to the circuit, and high-energy ions are more likely to cause single-event multiple transient (SEMT), which cannot be ignored in practical circuits. The transients pulse width data can be used as a reference for SET modeling in complex circuits.

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Barajas, Enrique, Xavier Aragones, Diego Mateo, and Josep Altet. "Differential Temperature Sensors: Review of Applications in the Test and Characterization of Circuits, Usage and Design Methodology." Sensors 19, no. 21 (November 5, 2019): 4815. http://dx.doi.org/10.3390/s19214815.

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Differential temperature sensors can be placed in integrated circuits to extract a signature of the power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper first discusses the singularity that differential temperature sensors provide with respect to other sensor topologies, with circuit monitoring being their main application. The paper focuses on the monitoring of radio-frequency analog circuits. The strategies to extract the power signature of the monitored circuit are reviewed, and a list of application examples in the domain of test and characterization is provided. As a practical example, we elaborate the design methodology to conceive, step by step, a differential temperature sensor to monitor the aging degradation in a class-A linear power amplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how, for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamic range is required. A circuit solution for this objective is proposed, as well as recommendations for the dimensions and location of the devices that form the temperature sensor. The paper concludes with a description of a simple procedure to monitor time variability.

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Lertkonsarn, Samran, and Worawat Sa-ngiamvibool. "The development a fully-balanced current-tunable first-order low-pass filter with Caprio technique." EUREKA: Physics and Engineering, no. 5 (September 30, 2022): 99–106. http://dx.doi.org/10.21303/2461-4262.2022.002406.

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This paper presents the development and design of a fully-balanced current-tunable first-order low-pass filter with Caprio technique, which could include the design and implementation of a first-order low-pass filter circuits. The filter consists of six bipolar junction transistor (BJT) and a single capacitor. The filter construction uses a bipolar junction transistor (BJT) as the main device and a single capacitor. A fully-balanced current-tunable first-order low-pass filter with Caprio technique developed. The architecture of the circuit is quite simple and proportional, symmetrical with signs of difference. Circuits developed into integrated circuits act like basic circuits for frequency filter circuits, current modes with Caprio techniques, obtained by improving the first-order low-pass filter for signal differences with incoming impedances. Adjusting the parameters of the circuit with the caprio technique achieves the optimal parameter value for correcting the total harmonic distortion value. The results of testing the operation of the circuit, a fully-balanced current-tunable first-order low-pass filter with Caprio technique developed and designed using the PSpice program. The simulation results showed good results in line with predicted theoretical analysis. The sensitivity of the device to the center frequency (ω0) response is low and independent of variables, the angular frequency is linear with wide current adjustment throughout the sweeping range of a wide frequency range, with a wide range of over tree orders of magnitude. Therefore, fully-balanced current-tunable first-order low-pass filter developed is very suitable to apply various applications regarding low frequency signal filtration, for example in biomedical systems, for example.

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Journal articles on the topic 'Linear integrated circuits'

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