Journal articles: 'Lightweight architectures'

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Sahlabadi, Mahdi, Ravie Chandren Muniyandi, Zarina Shukur, and Faizan Qamar. "Lightweight Software Architecture Evaluation for Industry: A Comprehensive Review." Sensors 22, no. 3 (February 7, 2022): 1252. http://dx.doi.org/10.3390/s22031252.

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Processes for evaluating software architecture (SA) help to investigate problems and potential risks in SA. It is derived from many studies that proposed a plethora of systematic SA evaluation methods, while industrial practitioners currently refrain from applying them since they are heavyweight. Nowadays, heterogeneous software architectures are organized based on the new infrastructure. Hardware and associated software allow different systems, such as embedded, sensor-based, modern AI, and cloud-based systems, to cooperate efficiently. It brings more complexities to SA evaluation. Alternatively, lightweight architectural evaluation methods have been proposed to satisfy the practitioner’s concerns, but practitioners still do not adopt these methods. This study employs a systematic literature review with a text analysis of SA’s definitions to propose a comparison framework for SA. It identifies lightweight features and factors to improve the architectural evaluation methods among industrial practitioners. The features are determined based on the practitioner’s concerns by analyzing the architecture’s definitions from stakeholders and reviewing architectural evaluation methods. The lightweight factors are acquired by studying the five most commonly used lightweight methods and the Architecture-based Tradeoff Analysis Method (ATAM), the most well-known heavyweight method. Subsequently, the research addresses these features and factors.

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Prathiba, A., Suyash Vardhan Srivathshav, Ramkumar P. E., Rajkamal E., and Kanchana Bhaaskaran V. S. "Lightweight VLSI Architectures for Image Encryption Applications." International Journal of Information Security and Privacy 16, no. 1 (January 2022): 1–23. http://dx.doi.org/10.4018/ijisp.291700.

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Lightweight cryptography offers significant security service in constrained environments such as wireless sensor networks and Internet of Things. The focus of this article is to construct lightweight SPN block cipher architectures with substitution box based on finite fields. The paper also details the FPGA implementation of the lightweight symmetric block cipher algorithm of SPN type with combinational S-box. Restructuring of traditional look-up-table Substitution Box (S-Box) sub-structure with a combinational logic S-box is attempted. Elementary architectures namely the basic round architecture and reduced datawidth architecture incorporating look-up-table and combinational S-Box substructure are compared in terms of area and throughput. Proposed restructure mechanism occupies less FPGA resources with no comprise in the latency and also demonstrates performance efficiency and low power consumption in Xilinx FPGAs. Robustness of the proposed method against various statistical attacks has been analyzed through comparison with other existing encryption mechanisms.

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Shikalgar, Sajeeda, Rakesh K. Yadav, and Parikshit N. Mahalle. "Lightweight MobileNet Model for Image Tempering Detection." International Journal on Recent and Innovation Trends in Computing and Communication 11, no. 5 (May 17, 2023): 55–69. http://dx.doi.org/10.17762/ijritcc.v11i5.6524.

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In recent years, there has been a wide range of image manipulation identification challenges and an overview of image tampering detection and the relevance of applying deep learning models such as CNN and MobileNet for this purpose. The discussion then delves into the construction and setup of these models, which includes a block diagram as well as mathematical calculations for each layer. A literature study on Image tampering detection is also included in the discussion, comparing and contrasting various articles and their methodologies. The study then moves on to training and assessment datasets, such as the CASIA v2 dataset, and performance indicators like as accuracy and loss. Lastly, the performance characteristics of the MobileNet and CNN designs are compared. This work focuses on Image tampering detection using convolutional neural networks (CNNs) and the MobileNet architecture. We reviewed the MobileNet architecture's setup and block diagram, as well as its application to Image tampering detection. We also looked at significant literature on Image manipulation detection, such as major studies and their methodologies. Using the CASIA v2 dataset, we evaluated the performance of MobileNet and CNN architectures in terms of accuracy and loss. This paper offered an overview of the usage of deep learning and CNN architectures for image tampering detection and proved their accuracy in detecting manipulated images.

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Iqbal, Shahzaib, Syed S. Naqvi, Haroon A. Khan, Ahsan Saadat, and Tariq M. Khan. "G-Net Light: A Lightweight Modified Google Net for Retinal Vessel Segmentation." Photonics 9, no. 12 (November 30, 2022): 923. http://dx.doi.org/10.3390/photonics9120923.

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In recent years, convolutional neural network architectures have become increasingly complex to achieve improved performance on well-known benchmark datasets. In this research, we have introduced G-Net light, a lightweight modified GoogleNet with improved filter count per layer to reduce feature overlaps, hence reducing the complexity. Additionally, by limiting the amount of pooling layers in the proposed architecture, we have exploited the skip connections to minimize the spatial information loss. The suggested architecture is analysed using three publicly available datasets for retinal vessel segmentation, namely DRIVE, CHASE and STARE datasets. The proposed G-Net light achieves an average accuracy of 0.9686, 0.9726, 0.9730 and F1-score of 0.8202, 0.8048, 0.8178 on DRIVE, CHASE, and STARE datasets, respectively. The proposed G-Net light achieves state-of-the-art performance and outperforms other lightweight vessel segmentation architectures with fewer trainable number of parameters.

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Abbas, Yasir Amer, Ahmed Salah Hameed, Safa Hazim Alwan, and Maryam Adnan Fadel. "Efficient hardware implementation for lightweight mCrypton algorithm using FPGA." Indonesian Journal of Electrical Engineering and Computer Science 23, no. 3 (September 1, 2021): 1674. http://dx.doi.org/10.11591/ijeecs.v23.i3.pp1674-1680.

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<p>The lightweight cryptography is used for low available resources devices such as radio frequency identification (RFID) tags, internet of things (IoTs) and wireless sensor networks. In such case, the lightweight cryptographic algorithms should consider power consumption, design area, speed, and throughput. This paper presents a new architecture of mCrypton lightweight cryptographic algorithm which considers the above-mentioned conditions. Resource-shared structure is used to reduce the area of the new architecture. The proposed architecture is implemented using ISE Xilinx V14,5 and Spartan 3 FPGA platform. The simulation results introduced that the proposed design area is 375 of slices, up to 302 MHz operating frequency, a throughput of 646 Mbps, efficiency of 1.7 Mbps/slice and 0.089 Watt power consumption. Thus, the proposed architecture outperforms similar architectures in terms of area, speed, efficiency and throughput.</p>

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Bouwers, Eric, and Arie van Deursen. "A Lightweight Sanity Check for Implemented Architectures." IEEE Software 27, no. 4 (July 2010): 44–50. http://dx.doi.org/10.1109/ms.2010.60.

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Bogoi, Smaranda, and Andreea Udrea. "A Lightweight Deep Learning Approach for Liver Segmentation." Mathematics 11, no. 1 (December 26, 2022): 95. http://dx.doi.org/10.3390/math11010095.

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Liver segmentation is a prerequisite for various hepatic interventions and is a time-consuming manual task performed by radiology experts. Recently, various computationally expensive deep learning architectures tackled this aspect without considering the resource limitations of a real-life clinical setup. In this paper, we investigated the capabilities of a lightweight model, UNeXt, in comparison with the U-Net model. Moreover, we conduct a broad analysis at the micro and macro levels of these architectures by using two training loss functions: soft dice loss and unified focal loss, and by substituting the commonly used ReLU activation function, with the novel Funnel activation function. An automatic post-processing step that increases the overall performance of the models is also proposed. Model training and evaluation were performed on a public database—LiTS. The results show that the UNeXt model (Funnel activation, soft dice loss, post-processing step) achieved a 0.9902 dice similarity coefficient on the whole CT volumes in the test set, with 15× fewer parameters in nearly 4× less inference time, compared to its counterpart, U-Net. Thus, lightweight models can become the new standard in medical segmentation, and when implemented thoroughly can alleviate the computational burden while preserving the capabilities of a parameter-heavy architecture.

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Lai, Yilin. "Hardware Architectures of FPGA-based Accelerators for Convolutional Neural Networks." Highlights in Science, Engineering and Technology 62 (July 27, 2023): 54–60. http://dx.doi.org/10.54097/hset.v62i.10424.

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Convolutional Neural Networks (CNNs) have been widely used in Artificial Intelligence applications due to their unsupervised feature, which automatically identifies relevant features without human intervention. Outperforming power-hungry GPUs and inflexible ASICs in lightweight CNNs, FPGAs serve as a promising platform on balancing peak performance, energy efficiency and flexibility. In the last decade, several frameworks have been proposed to optimize the global performance of CNN on hardware platforms. This paper presents a survey on hardware architectures generated by various software frameworks designed for mapping CNN on FPGAs. Classic architectural cases of the streaming architecture and the single computation engine from traditional CNN-specific processors to end-to-end mapping using High Level Synthesis (HLS) tools which emerged in recent years are carefully analyzed in a sequential order. Moreover, adaptability of existing frameworks to upcoming challenges and future directions of FPGA-based CNN accelerators are identified, providing an in-depth evaluation on the topic of hardware architectures of FPGA-based CNN accelerators.

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Alsubhi, Khalid, Bander Alzahrani, Nikos Fotiou, Aiiad Albeshri, and Mohammed Alreshoodi. "Reliable Application Layer Routing Using Decentralized Identifiers." Future Internet 14, no. 11 (November 6, 2022): 322. http://dx.doi.org/10.3390/fi14110322.

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Modern internet of things (IoT) applications can benefit from advanced communication paradigms, including multicast and anycast. Next-generation internet architectures, such as information-centric networking (ICN), promise to support these paradigms, but at the same time they introduce new security challenges. This paper presents a solution that extends an ICN-like architecture based on software-defined networking (SDN) that supports those communication paradigms. Using the proposed solution, the underlying architecture is enhanced with a novel security mechanism that allows content “advertisements” only from authorized endpoints. This mechanism prevents “content pollution”, which is a significant security threat in ICN architectures. The proposed solution is lightweight, and it enables identity sharing as well as secured and controlled identity delegation.

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Popovic, Miroslav, Miodrag Djukic, Vladimir Marinkovic, and Nikola Vranic. "On task tree executor architectures based on intel parallel building blocks." Computer Science and Information Systems 10, no. 1 (2013): 369–92. http://dx.doi.org/10.2298/csis120519008p.

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Our aim was to optimize a SOA control system by evolving the architecture of the service component that transforms system models into task trees, which are then executed by the runtime library called the Task Tree Executor, TTE. In the paper we present the two novel TTE architectures that evolved from the previous TTE architecture and introduced finer grained parallelism. The novel architectures execute TTE tasks as more lightweight TBB tasks and Cilk strands rather than the OS threads, which was the case for the previous TTE architecture. The experimental evaluation based on time needed for TTE reliability estimation, by statistical usage tests, shows that these novel TTE architectures are providing the average relative speedup, RS, from 8x to 11x, over the original TTE, on a dual-core machine. Additional experiments made on eight-core machine showed that RS provided by TTE based on TBB scales perfectly, and goes up to 77x.

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Mhaouch, Ayoub, Wajdi Elhamzi, Abdessalem Ben Abdelali, and Mohamed Atri. "Optimized Piccolo Lightweight Block Cipher: Area Efficient Implementation." Traitement du Signal 39, no. 3 (June 30, 2022): 805–14. http://dx.doi.org/10.18280/ts.390305.

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Piccolo algorithm is one of the lightweight block ciphers designed specifically for low-resource devices which present physical constraints in terms of area, power, and memory. Various hardware architectures for Piccolo block cipher have been proposed in recent years with the aim of obtaining a more appropriate low-resource design for specific constrained applications. The latter must meet real-time processing constraints without affecting the need for hardware resources. Finding a good compromise between computation time and implementation resource consumption is a major consideration in the design process. In this paper, we suggest six serial hardware architectures for Piccolo lightweight algorithm with a 128 bits key length. Proposed architectures are compared to existing designs based on hardware resource occupancy, latency, and throughput. Also, we tested the security of the Piccolo algorithm, and the obtained results show the good robustness of the Piccolo block cipher against statistical attacks. Thus, we can use the Piccolo algorithm in lightweight applications that require a high level of privacy.

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Gao, Peng, Xiao Liu, Hong-Chuan Sang, Yu Wang, and Fei Wang. "Efficient and Lightweight Visual Tracking with Differentiable Neural Architecture Search." Electronics 12, no. 17 (August 27, 2023): 3623. http://dx.doi.org/10.3390/electronics12173623.

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Over the last decade, Siamese network architectures have emerged as dominating tracking paradigms, which have led to significant progress. These architectures are made up of a backbone network and a head network. The backbone network comprises two identical feature extraction sub-branches, one for the target template and one for the search candidate. The head network takes both the template and candidate features as inputs and produces a local similarity score for the target object in each location of the search candidate. Despite promising results that have been attained in visual tracking, challenges persist in developing efficient and lightweight models due to the inherent complexity of the task. Specifically, manually designed tracking models that rely heavily on the knowledge and experience of relevant experts are lacking. In addition, the existing tracking approaches achieve excellent performance at the cost of large numbers of parameters and vast amounts of computations. A novel Siamese tracking approach called TrackNAS based on neural architecture search is proposed to reduce the complexity of the neural architecture applied in visual tracking. First, according to the principle of the Siamese network, backbone and head network search spaces are constructed, constituting the search space for the network architecture. Next, under the given resource constraints, the network architecture that meets the tracking performance requirements is obtained by optimizing a hybrid search strategy that combines distributed and joint approaches. Then, an evolutionary method is used to lighten the network architecture obtained from the search phase to facilitate deployment to devices with resource constraints (FLOPs). Finally, to verify the performance of TrackNAS, comparison and ablation experiments are conducted using several large-scale visual tracking benchmark datasets, such as OTB100, VOT2018, UAV123, LaSOT, and GOT-10k. The results indicate that the proposed TrackNAS achieves competitive performance in terms of accuracy and robustness, and the number of network parameters and computation volume are far smaller than those of other advanced Siamese trackers, meeting the requirements for lightweight deployment to resource-constrained devices.

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Rudolph, Enrico, Christian Müller, Andreas Ehrlich, Sandra Gelbrich, and Lothar Kroll. "Development of a Variable Gridshell for Application in Mobile Architecture." Key Engineering Materials 809 (June 2019): 541–46. http://dx.doi.org/10.4028/www.scientific.net/kem.809.541.

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Within the research project a variable gridshell in lightweight design was developed that permit the building of free-formed mobile architectures. The construction consists of a large number of straight length-adjustable bars pin-jointed via so-called knots and enables extremely efficient and stable support structures with high potential for lightweight construction.

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Zanelli, Alessandra, Carol Monticelli, and Marijke Mollaert. "Sustainable innovation in minimal mass structures and lightweight architectures." Architectural Engineering and Design Management 17, no. 3-4 (June 15, 2021): 167–68. http://dx.doi.org/10.1080/17452007.2021.1938458.

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Lara-Nino, Carlos Andres, Arturo Diaz-Perez, and Miguel Morales-Sandoval. "Lightweight Hardware Architectures for the Present Cipher in FPGA." IEEE Transactions on Circuits and Systems I: Regular Papers 64, no. 9 (September 2017): 2544–55. http://dx.doi.org/10.1109/tcsi.2017.2686783.

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Skianis, Charalabos, Fabrizio Granelli, Periklis Chatzimisios, Christos Verikoukis, and Michael Devetsikiotis. "Lightweight Mobile and Wireless Systems: Technologies, Architectures, and Services." Journal of Computer Systems, Networks, and Communications 2010 (2010): 1–2. http://dx.doi.org/10.1155/2010/420806.

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Korona, Mateusz, Radosław Giermakowski, Mateusz Biernacki, and Mariusz Rawski. "Lightweight Strong PUF for Resource-Constrained Devices." Electronics 13, no. 2 (January 14, 2024): 351. http://dx.doi.org/10.3390/electronics13020351.

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Physical Unclonable Functions are security primitives that exploit the variation in integrated circuits’ manufacturing process, and, as a result, each instance processes applied stimuli differently. This feature can be used to provide a unique fingerprint of the electronic device, or as an interesting alternative to classic key storage methods. Due to their nature, they are often considered an element of the Internet of Things nodes. However, their application heavily depends on resource consumption. Lightweight architectures are proposed in the literature but are technology-dependent or still introduce significant hardware overhead. This paper presents a lightweight, Strong PUF based on ring oscillator architecture, which offers small hardware overhead and sufficient security levels for resource-constrained Internet of Things devices. The PUF design utilizes a Linear Feedback Shift Register-based scramble module to generate many challenge–response pairs from a small number of ring oscillators and a control module to manage the response generation process. The proposed PUF can be used as a Weak PUF for key generation or a Strong PUF for device authentication.

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Sangeeta, Sangeeta, Preeti Gulia, and Nasib Singh Gill. "Flow incorporated neural network based lightweight video compression architecture." Indonesian Journal of Electrical Engineering and Computer Science 26, no. 2 (May 1, 2022): 939. http://dx.doi.org/10.11591/ijeecs.v26.i2.pp939-946.

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The sudden surge in the video transmission over internet motivated the exploration of more promising and potent video compression architectures. Though the frame prediction based hand designed techniques are performing well and widely used but the recent deep learning based researches in this domain provided further directions of pure deep learning based next generation codecs. As the bandwidth over the internet is varying, adaptive bit rate representation is more suitable for video quality adjustment in tune with bandwidth variation. The proposed architecture comprises of end to end trainable video compression network consisting of majorly three modules namely-motion extension network, flow autoencoder and frame autoencoder. Frame autoencoder generates the individual compressed frames, flow autoencoder is used for optical flow based motion compensation chore and next frame is predicted by the motion extension network. The network is designed and evaluated in incremental manner. The analysis of the outcomes demonstrates the promising performance of the network quantitatively and qualitatively. Moreover, the results reveal that inclusion of optical flow based motion compensation network to the MotionNet architecture has enhanced the performance.

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Sathuluri, Akhil, Anand Vazhapilli Sureshbabu, Jintin Frank, Maximilian Amm, and Markus Zimmermann. "Computational Systems Design of Low-Cost Lightweight Robots." Robotics 12, no. 4 (June 25, 2023): 91. http://dx.doi.org/10.3390/robotics12040091.

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With the increased demand for customisation, developing task-specific robots for industrial and personal applications has become essential. Collaborative robots are often preferred over conventional industrial robots in human-centred production environments. However, fixed architecture robots lack the ability to adapt to changing user demands, while modular, reconfigurable robots provide a quick and affordable alternative. Standardised robot modules often derive their characteristics from conventional industrial robots, making them expensive and bulky and potentially limiting their wider adoption. To address this issue, the current work proposes a top-down multidisciplinary computational design strategy emphasising the low cost and lightweight attributes of modular robots within two consecutive optimisation problems. The first step employs an informed search strategy to explore the design space of robot modules to identify a low-cost robot architecture and controller. The second step employs dynamics-informed structural optimisation to reduce the robot’s net weight. The proposed methodology is demonstrated on a set of example requirements, illustrating that (1) the robot modules allow exploring non-intuitive robot architectures, (2) the structural mass of the resulting robot is 16 % lower compared to a robot designed using conventional aluminium tubes, and (3) the designed modules ensure the physical feasibility of the robots produced.

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Otto, Steve W. "Parallel Array Classes and Lightweight Sharing Mechanisms." Scientific Programming 2, no. 4 (1993): 203–16. http://dx.doi.org/10.1155/1993/393409.

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We discuss a set of parallel array classes, MetaMP, for distributed-memory architectures. The classes are implemented in C++ and interface to the PVM or Intel NX message-passing systems. An array class implements a partitioned array as a set of objects distributed across the nodes – a "collective" object. Object methods hide the low-level message-passing and implement meaningful array operations. These include transparent guard strips (or sharing regions) that support finite-difference stencils, reductions and multibroadcasts for support of pivoting and row operations, and interpolation/contraction operations for support of multigrid algorithms. The concept of guard strips is generalized to an object implementation of lightweight sharing mechanisms for finite element method (FEM) and particle-in-cell (PIC) algorithms. The sharing is accomplished through the mechanism of weak memory coherence and can be efficiently implemented. The price of the efficient implementation is memory usage and the need to explicitly specify the coherence operations. An intriguing feature of this programming model is that it maps well to both distributed-memory and shared-memory architectures.

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Ibrahem, Hatem, Ahmed Salem, and Hyun-Soo Kang. "RT-ViT: Real-Time Monocular Depth Estimation Using Lightweight Vision Transformers." Sensors 22, no. 10 (May 19, 2022): 3849. http://dx.doi.org/10.3390/s22103849.

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The latest research in computer vision highlighted the effectiveness of the vision transformers (ViT) in performing several computer vision tasks; they can efficiently understand and process the image globally unlike the convolution which processes the image locally. ViTs outperform the convolutional neural networks in terms of accuracy in many computer vision tasks but the speed of ViTs is still an issue, due to the excessive use of the transformer layers that include many fully connected layers. Therefore, we propose a real-time ViT-based monocular depth estimation (depth estimation from single RGB image) method with encoder-decoder architectures for indoor and outdoor scenes. This main architecture of the proposed method consists of a vision transformer encoder and a convolutional neural network decoder. We started by training the base vision transformer (ViT-b16) with 12 transformer layers then we reduced the transformer layers to six layers, namely ViT-s16 (the Small ViT) and four layers, namely ViT-t16 (the Tiny ViT) to obtain real-time processing. We also try four different configurations of the CNN decoder network. The proposed architectures can learn the task of depth estimation efficiently and can produce more accurate depth predictions than the fully convolutional-based methods taking advantage of the multi-head self-attention module. We train the proposed encoder-decoder architecture end-to-end on the challenging NYU-depthV2 and CITYSCAPES benchmarks then we evaluate the trained models on the validation and test sets of the same benchmarks showing that it outperforms many state-of-the-art methods on depth estimation while performing the task in real-time (∼20 fps). We also present a fast 3D reconstruction (∼17 fps) experiment based on the depth estimated from our method which is considered a real-world application of our method.

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Villarreal, Alexa, Raul Barbosa, Saptasree Bose, Bhupendra B. Srivastava, Victoria Padilla-Gainza, and Karen Lozano. "Color tunable aerogels/sponge-like structures developed from fine fiber membranes." Materials Advances 3, no. 6 (2022): 2716–25. http://dx.doi.org/10.1039/d1ma00946j.

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Navarro, Pedro J., Leanne Miller, Francisca Rosique, Carlos Fernández-Isla, and Alberto Gila-Navarro. "End-to-End Deep Neural Network Architectures for Speed and Steering Wheel Angle Prediction in Autonomous Driving." Electronics 10, no. 11 (May 25, 2021): 1266. http://dx.doi.org/10.3390/electronics10111266.

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The complex decision-making systems used for autonomous vehicles or advanced driver-assistance systems (ADAS) are being replaced by end-to-end (e2e) architectures based on deep-neural-networks (DNN). DNNs can learn complex driving actions from datasets containing thousands of images and data obtained from the vehicle perception system. This work presents the classification, design and implementation of six e2e architectures capable of generating the driving actions of speed and steering wheel angle directly on the vehicle control elements. The work details the design stages and optimization process of the convolutional networks to develop six e2e architectures. In the metric analysis the architectures have been tested with different data sources from the vehicle, such as images, XYZ accelerations and XYZ angular speeds. The best results were obtained with a mixed data e2e architecture that used front images from the vehicle and angular speeds to predict the speed and steering wheel angle with a mean error of 1.06%. An exhaustive optimization process of the convolutional blocks has demonstrated that it is possible to design lightweight e2e architectures with high performance more suitable for the final implementation in autonomous driving.

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Tang, Feng, Geng Sheng Rao, Qiang Chen, and Ping Zhang. "Open Robot Control Platform Based on LSOA." Applied Mechanics and Materials 341-342 (July 2013): 719–26. http://dx.doi.org/10.4028/www.scientific.net/amm.341-342.719.

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Aims to address the restrictions imposed by tranditional robot Control system development approach such as close structure, function immobility, lack of reconfiguration at run time, hard to guarantee. a lightweight service-oriented architectures (LSOA) for robot control system is proposed. The main features of this architecture include central control mode, message-based interaction and configuration system based on embedded database. This architecture provides good supports for runtime reconfiguration, and allows integrating different components with the aid of a configuration system. The experiment indicates that the LSOA approach can improve the flexibility, reconfiguration and agility of the system.

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Tappari, Sunitha, and K. Sridevi. "Review on lightweight hardware architectures for the crypt-analytics in FPGA." International Journal of Engineering & Technology 7, no. 3 (August 22, 2018): 1888. http://dx.doi.org/10.14419/ijet.v7i3.14138.

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Internet of Things (IoT) plays a vital role in the Wireless sensor networks (WSNs), which is used for many applications, such as military, health, and environmental. Security is the major concern and it is very difficult to achieve because of a different kind of attack in the network. In recent years, many authors have introduced different Hardware Architectures to solve these security problems. This paper has discussed about a review of various Hardware Architectures for the lightweight Crypt-analytics methods and the comparative learning of various Crypt-analytics and authentication systems carried out. The comparative study result showed that the lightweight algorithms have good per-formance compared to the conventional Crypt-analytics algorithm in terms of memory requirement, operations, and power consumption.

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Xie, Qi, and Yuanyuan Zhao. "Physical-Unclonable-Function-Based Lightweight Three-Factor Authentication for Multiserver Architectures." Mathematics 12, no. 1 (December 25, 2023): 79. http://dx.doi.org/10.3390/math12010079.

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To support more complex and robust online services, enterprise-class applications prefer to interconnect multiple servers as the pedestal to enhance the system’s interoperability. However, the multiserver architecture always struggles to reconcile the trade-off between convenience and security, leaving users exposed to a variety of network attack threats. Existing security authentication schemes based on the Chebyshev Chaotic Map for multiserver architectures cannot provide three-factor (including password, biometric feature, and smart card) security. Therefore, we propose a novel Physical-Unclonable-Function-based Lightweight Three-Factor Authentication (PUF-LTA) scheme, which can achieve three-factor security. The PUF-LTA scheme mainly includes two components: (1) PUF-assisted registration and (2) lightweight mutual authentication with one-time interaction. During the PUF-assisted registration process, to defend against side-channel attacks on smart cards, the login credentials of users are XORed with the unique identifier generated by the PUF so that the adversary cannot obtain these secret login credentials. During the lightweight mutual authentication process, we combine the Chebyshev polynomial map and symmetric encryption/decryption to negotiate the session key between users and servers, which only needs one interaction. The security performance of PUF-LTA is theoretically proved by leveraging the random oracle model. In contrast with relevant multiserver authentication schemes, PUF-LTA is more efficient and suitable for resource-constrained multiserver environments because it can ensure secure three-factor authentication and support flexible biometrics and password updates with less computation cost.

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Aivaliotis, Vassileios, Kyriaki Tsantikidou, and Nicolas Sklavos. "IoT-Based Multi-Sensor Healthcare Architectures and a Lightweight-Based Privacy Scheme." Sensors 22, no. 11 (June 3, 2022): 4269. http://dx.doi.org/10.3390/s22114269.

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Health 4.0 is a new promising addition to the healthcare industry that innovatively includes the Internet of Things (IoT) and its heterogeneous devices and sensors. The result is the creation of numerous smart health applications that can be more effective, reliable, scalable and cost-efficient while facilitating people with their everyday life and health conditions. Nevertheless, without proper guidance, the employment of IoT-based health systems can be complicated, especially with regard to security challenges such susceptible application displays. An appropriate comprehension of the structure and the security demands of IoT-based multi-sensor systems and healthcare infrastructures must first be achieved. Furthermore, new architectures that provide lightweight, easily implementable and efficient approaches must be introduced. In this paper, an overview of IoT integration within the healthcare domain as well as a methodical analysis of efficient smart health frameworks, which mainly employ multiple resource and energy-constrained devices and sensors, will be presented. An additional concern of this paper will be the security requirements of these key IoT components and especially of their wireless communications. As a solution, a lightweight-based security scheme, which utilizes the lightweight cryptographic primitive LEAIoT, will be introduced. The proposed hardware-based design displays exceptional results compared to the original CPU-based implementation, with a 99.9% increase in key generation speed and 96.2% increase in encryption/decryption speed. Finally, because of its lightweight and flexible implementation and high-speed keys’ setup, it can compete with other common hardware-based cryptography architectures, where it achieves lower hardware utilization up to 87.9% with the lowest frequency and average throughput.

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Yeo, Seon Ju, Min Jun Oh, and Pil J. Yoo. "Lightweight Materials: Structurally Controlled Cellular Architectures for High‐Performance Ultra‐Lightweight Materials (Adv. Mater. 34/2019)." Advanced Materials 31, no. 34 (August 2019): 1970245. http://dx.doi.org/10.1002/adma.201970245.

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Papa, Lorenzo, Gabriele Proietti Mattia, Paolo Russo, Irene Amerini, and Roberto Beraldi. "Lightweight and Energy-Aware Monocular Depth Estimation Models for IoT Embedded Devices: Challenges and Performances in Terrestrial and Underwater Scenarios." Sensors 23, no. 4 (February 16, 2023): 2223. http://dx.doi.org/10.3390/s23042223.

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The knowledge of environmental depth is essential in multiple robotics and computer vision tasks for both terrestrial and underwater scenarios. Moreover, the hardware on which this technology runs, generally IoT and embedded devices, are limited in terms of power consumption, and therefore, models with a low-energy footprint are required to be designed. Recent works aim at enabling depth perception using single RGB images on deep architectures, such as convolutional neural networks and vision transformers, which are generally unsuitable for real-time inferences on low-power embedded hardware. Moreover, such architectures are trained to estimate depth maps mainly on terrestrial scenarios due to the scarcity of underwater depth data. Purposely, we present two lightweight architectures based on optimized MobileNetV3 encoders and a specifically designed decoder to achieve fast inferences and accurate estimations over embedded devices, a feasibility study to predict depth maps over underwater scenarios, and an energy assessment to understand which is the effective energy consumption during the inference. Precisely, we propose the MobileNetV3S75 configuration to infer on the 32-bit ARM CPU and the MobileNetV3LMin for the 8-bit Edge TPU hardware. In underwater settings, the proposed design achieves comparable estimations with fast inference performances compared to state-of-the-art methods. Moreover, we statistically proved that the architecture of the models has an impact on the energy footprint in terms of Watts required by the device during the inference. Then, the proposed architectures would be considered to be a promising approach for real-time monocular depth estimation by offering the best trade-off between inference performances, estimation error and energy consumption, with the aim of improving the environment perception for underwater drones, lightweight robots and Internet of things.

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Zheng, Wenhan. "Comparison of transfer-learning for lightweight pre-trained model on image classification." Applied and Computational Engineering 53, no. 1 (March 28, 2024): 56–63. http://dx.doi.org/10.54254/2755-2721/53/20241244.

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This paper presents a comparative study of the performance of three convolutional neural network (CNN) architectures - EffcientNet-B0, ResNet-50, and AlexNet - for a given image classification task. The study provides a comprehensive investigation of the training process, hardware configurations, training time, and individual model performance. The investigation also assesses the models suitability for different applications. The findings can help both researchers and practitioners select the most suitable model for their specific needs and applications. The paper provides an analysis of each CNN architecture and discusses their strength and weaknesses. The results demonstrate that EffcientNet-B0 achieves the highest accuracy, but its training performance is not optimal. ResNet-50, on the other hand, exhibits high accuracy with efficient training using transfer learning. Finally, ALEXNET provides a baseline for comparison with traditional CNN designs. The paper also highlights the trade-offs involved in selecting a CNN architecture and highlights their relative advantages and disadvantages. The reader is provided with insights into which CNN architecture is most suitable for specific applications based on their requirements.

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Kitsos, Paris, Nicolas Sklavos, Maria Parousi, and Athanassios N. Skodras. "A comparative study of hardware architectures for lightweight block ciphers." Computers & Electrical Engineering 38, no. 1 (January 2012): 148–60. http://dx.doi.org/10.1016/j.compeleceng.2011.11.022.

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Yeo, Seon Ju, Min Jun Oh, and Pil J. Yoo. "Structurally Controlled Cellular Architectures for High‐Performance Ultra‐Lightweight Materials." Advanced Materials 31, no. 34 (November 21, 2018): 1803670. http://dx.doi.org/10.1002/adma.201803670.

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Singh, Pulkit, K. Abhimanyu Kumar Patro, Bibhudendra Acharya, and Rahul Kumar Chaurasiya. "Efficient hardware architectures of Lilliput lightweight algorithm for image encryption." International Journal of Ad Hoc and Ubiquitous Computing 41, no. 4 (2022): 205. http://dx.doi.org/10.1504/ijahuc.2022.126779.

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Yun, Heuijee, and Daejin Park. "Efficient Object Detection Based on Masking Semantic Segmentation Region for Lightweight Embedded Processors." Sensors 22, no. 22 (November 17, 2022): 8890. http://dx.doi.org/10.3390/s22228890.

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Because of the development of image processing using cameras and the subsequent development of artificial intelligence technology, various fields have begun to develop. However, it is difficult to implement an image processing algorithm that requires a lot of calculations on a light board. This paper proposes a method using real-time deep learning object recognition algorithms in lightweight embedded boards. We have developed an algorithm suitable for lightweight embedded boards by appropriately using two deep neural network architectures. The first architecture requires small computational volumes, although it provides low accuracy. The second architecture uses large computational volumes and provides high accuracy. The area is determined using the first architecture, which processes semantic segmentation with relatively little computation. After masking the area using the more accurate deep learning architecture, object detection is implemented with improved accuracy, as the image is filtered by segmentation and the cases that have not been recognized by various variables, such as differentiation from the background, are excluded. OpenCV (Open source Computer Vision) is used to process input images in Python, and images are processed using an efficient neural network (ENet) and You Only Look Once (YOLO). By running this algorithm, the average error can be reduced by approximately 2.4 times, allowing for more accurate object detection. In addition, object recognition can be performed in real time for lightweight embedded boards, as a rate of about 4 FPS (frames per second) is achieved.

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Khosa, Ikramullah, Abdur Rahman, Khurram Ali, Jahanzeb Akhtar, Ammar Armghan, Jehangir Arshad, and Melkamu Deressa Amentie. "Fault-Level Grading of Photovoltaic Cells Employing Lightweight Deep Learning Models." Computational Intelligence and Neuroscience 2023 (February 7, 2023): 1–16. http://dx.doi.org/10.1155/2023/2663150.

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The deployment of photovoltaic (PV) cells as a renewable energy resource has been boosted recently, which enhanced the need to develop an automatic and swift fault detection system for PV cells. Prior to isolation for repair or replacement, it is critical to judge the level of the fault that occurred in the PV cell. The aim of this research study is the fault-level grading of PV cells employing deep neural network models. The experiment is carried out using a publically available dataset of 2,624 electroluminescence images of PV cells, which are labeled with four distinct defect probabilities defined as the defect levels. The deep architectures of the classical artificial neural networks are developed while employing hand-crafted texture features extracted from the EL image data. Moreover, optimized architectures of the convolutional neural network are developed with a specific emphasis on lightweight models for real-time processing. The experiments are performed for two-way binary classification and multiclass classification. For the first binary categorization, the proposed CNN model outperformed the state-of-the-art solution with a margin of 1.3% in accuracy with a significant 50% less computational complexity. In the second binary classification task, the CPU-based proposed model outperformed the GPU-based solution with a margin of 0.9% accuracy with an 8× lighter architecture. Finally, the multiclass categorization of PV cells is performed and the state-of-the-art results with 83.5% accuracy are achieved. The proposed models offer a lightweight, efficient, and computationally cheaper CPU-based solution for the real-time fault-level categorization of PV cells.

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Bhingardive, Viraj, Goutam Prasanna Kar, and Suryasarathi Bose. "Lightweight, flexible and ultra-thin sandwich architectures for screening electromagnetic radiation." RSC Advances 6, no. 74 (2016): 70018–24. http://dx.doi.org/10.1039/c6ra14154d.

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A lightweight and flexible multilayered structure consisting of poly(vinylidene fluoride) and iron particles decorated carbon fiber mat was successfully fabricated for electromagnetic interference shielding application.

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Verma, Satya Bhushan, Brijesh Pandey, and Bineet Kumar Gupta. "Containerization and its Architectures: A Study." ADCAIJ: Advances in Distributed Computing and Artificial Intelligence Journal 11, no. 4 (June 5, 2023): 395–409. http://dx.doi.org/10.14201/adcaij.28351.

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Containerization is a technique for lightweight virtualization of programs in cloud computing, which leads to the widespread use of cloud computing. It has a positive impact on both the development and deployment of software. Containers can be divided into two groups based on their setup. The Application Container and the System Container are two types of containers. A container is a user-space that is contained within another container, while a system container is a user-space that is contained within another container. This study compares and contrasts several container architectures and their organization in micro-hosting environments for containers.

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Ibrahem, Hatem, Ahmed Salem, and Hyun-Soo Kang. "DTS-Net: Depth-to-Space Networks for Fast and Accurate Semantic Object Segmentation." Sensors 22, no. 1 (January 3, 2022): 337. http://dx.doi.org/10.3390/s22010337.

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We propose Depth-to-Space Net (DTS-Net), an effective technique for semantic segmentation using the efficient sub-pixel convolutional neural network. This technique is inspired by depth-to-space (DTS) image reconstruction, which was originally used for image and video super-resolution tasks, combined with a mask enhancement filtration technique based on multi-label classification, namely, Nearest Label Filtration. In the proposed technique, we employ depth-wise separable convolution-based architectures. We propose both a deep network, that is, DTS-Net, and a lightweight network, DTS-Net-Lite, for real-time semantic segmentation; these networks employ Xception and MobileNetV2 architectures as the feature extractors, respectively. In addition, we explore the joint semantic segmentation and depth estimation task and demonstrate that the proposed technique can efficiently perform both tasks simultaneously, outperforming state-of-art (SOTA) methods. We train and evaluate the performance of the proposed method on the PASCAL VOC2012, NYUV2, and CITYSCAPES benchmarks. Hence, we obtain high mean intersection over union (mIOU) and mean pixel accuracy (Pix.acc.) values using simple and lightweight convolutional neural network architectures of the developed networks. Notably, the proposed method outperforms SOTA methods that depend on encoder–decoder architectures, although our implementation and computations are far simpler.

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Cui, Liyuan, Guoqiang Zhong, Xiang Liu, and Hongwei Xu. "A Compact Object Detection Architecture with Transformer Enhancing." Journal of Physics: Conference Series 2278, no. 1 (May 1, 2022): 012034. http://dx.doi.org/10.1088/1742-6596/2278/1/012034.

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Abstract With the advancements in rising computer vision processing, Transformer has attracted increasing interesting in this field. However, it is limited because of its unprecedented storage, heavy reliance on data size and intolerable computational power consumption. While lightweight network is in other extreme, pursuing the compact architectures accompanied by performance loss. In this paper, we enhance an architecture as the backbone of object detection networks through combining right-size Transformer, i.e. Vision Transformer module. Specifically, based on GhostNet, a well-known lightweight neural network structure moreover, embed this Vision Transformer module at the end of GhostNet, and use the input data with slicing design to reduce the computational burden of the neural networks. Vision Transformer is taken to enhance the architecture as the backbone of object detection networks, and the well-known YOLOv5 as the baseline. We conduct multi-metric comparison experiments on two medium-scale object detection datasets with large, medium and small scale networks. Results show that without relying on ultra-large dataset and pre-trained models, the proposed Transformer module enhanced architecture achieves comparable or even higher mAP metrics with only half of the model size and floating-point computation of the baseline.

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An, Fubang, Lingli Wang, and Xuegong Zhou. "A High Performance Reconfigurable Hardware Architecture for Lightweight Convolutional Neural Network." Electronics 12, no. 13 (June 27, 2023): 2847. http://dx.doi.org/10.3390/electronics12132847.

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Since the lightweight convolutional neural network EfficientNet was proposed by Google in 2019, the series of models have quickly become very popular due to their superior performance with a small number of parameters. However, the existing convolutional neural network hardware accelerators for EfficientNet still have much room to improve the performance of the depthwise convolution, squeeze-and-excitation module and nonlinear activation functions. In this paper, we first design a reconfigurable register array and computational kernel to accelerate the depthwise convolution. Next, we propose a vector unit to implement the nonlinear activation functions and the scale operation. An exchangeable-sequence dual-computational kernel architecture is proposed to improve the performance and the utilization. In addition, the memory architectures are designed to complete the hardware accelerator for the above computing architecture. Finally, in order to evaluate the performance of the hardware accelerator, the accelerator is implemented based on Xilinx XCVU37P. The results show that the proposed accelerator can work at the main system clock frequency of 300 MHz with the DSP kernel at 600 MHz. The performance of EfficientNet-B3 in our architecture can reach 69.50 FPS and 255.22 GOPS. Compared with the latest EfficientNet-B3 accelerator, which uses the same FPGA development board, the accelerator proposed in this paper can achieve a 1.28-fold improvement of single-core performance and 1.38-fold improvement of performance of each DSP.

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Patel, Chirag, Dulari Bhatt, Urvashi Sharma, Radhika Patel, Sharnil Pandya, Kirit Modi, Nagaraj Cholli, et al. "DBGC: Dimension-Based Generic Convolution Block for Object Recognition." Sensors 22, no. 5 (February 24, 2022): 1780. http://dx.doi.org/10.3390/s22051780.

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The object recognition concept is being widely used a result of increasing CCTV surveillance and the need for automatic object or activity detection from images or video. Increases in the use of various sensor networks have also raised the need of lightweight process frameworks. Much research has been carried out in this area, but the research scope is colossal as it deals with open-ended problems such as being able to achieve high accuracy in little time using lightweight process frameworks. Convolution Neural Networks and their variants are widely used in various computer vision activities, but most of the architectures of CNN are application-specific. There is always a need for generic architectures with better performance. This paper introduces the Dimension-Based Generic Convolution Block (DBGC), which can be used with any CNN to make the architecture generic and provide a dimension-wise selection of various height, width, and depth kernels. This single unit which uses the separable convolution concept provides multiple combinations using various dimension-based kernels. This single unit can be used for height-based, width-based, or depth-based dimensions; the same unit can even be used for height and width, width and depth, and depth and height dimensions. It can also be used for combinations involving all three dimensions of height, width, and depth. The main novelty of DBGC lies in the dimension selector block included in the proposed architecture. Proposed unoptimized kernel dimensions reduce FLOPs by around one third and also reduce the accuracy by around one half; semi-optimized kernel dimensions yield almost the same or higher accuracy with half the FLOPs of the original architecture, while optimized kernel dimensions provide 5 to 6% higher accuracy with around a 10 M reduction in FLOPs.

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Bayat-Sarmadi, Siavash, Mehran Mozaffari Kermani, Reza Azarderakhsh, and Chiou-Yng Lee. "Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures." IEEE Transactions on Circuits and Systems II: Express Briefs 61, no. 2 (February 2014): 125–29. http://dx.doi.org/10.1109/tcsii.2013.2291075.

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Qu, Y. F., J. H. Ma, Y. Q. He, L. Zhang, F. C. Ren, and B. Li. "3D printing-directed flexible strain sensors of accordion-like architecture to achieve ultrastretchability with the assist of ultrasonic cavitation treatment." Journal of Physics: Conference Series 2085, no. 1 (November 1, 2021): 012042. http://dx.doi.org/10.1088/1742-6596/2085/1/012042.

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Abstract A new class of accordion-like cellular architecture with sinusoidal struts is designed to enhance the planar stretchability of cellular solids, aiming to fabricate flexible strain sensors with ultrastretchability. The combination manufacturing process of fused deposition modeling (FDM) 3D printing technique and ultrasonic cavitation-enabled treatment was introduced into the fabrication of flexible strain sensors made of thermoplastic polyurethane (TPU) substrate and carbon nanotubes (CNTs). A negative Poisson’s ratio (NPR) architecture made of TPU was firstly 3D-printed by FDM. The ultrasonic cavitation treatment was then conducted on the soft auxetic structure immersing in CNTs liquid, aiming to embed the CNTs into the surface layer of the flexible TPU substrate with NPR configurations. Instead of 3D printing the TPU matrix composite after hybridization inside the matrix material, the hybrid manufacturing procedure can ensure that the intrinsic excellent mechanical properties of TPU are not embrittled. Besides, the sinusoidal struts in accordion-like cellular architectures offer a design route to extend the material property chart to achieve ultrahigh stretchability in lightweight 3D printable flexible polymers for the applications that require combined stretchability, lightweight, and energy absorption such as soft robotics, stretchable electronics, and wearable protection shields.

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Mamatkulovich, Babakulov Bekzod. "LIGHTWEIGHT RESIDUAL LAYERS BASED CONVOLUTIONAL NEURAL NETWORKS FOR TRAFFIC SIGN RECOGNITION." European International Journal of Multidisciplinary Research and Management Studies 02, no. 05 (May 1, 2022): 88–94. http://dx.doi.org/10.55640/eijmrms-02-05-19.

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System for Traffic Sign Recognition and Classification is significantly important for especially traffic safety, traffic surveillance, artificial driver services and by all means, for self-driving cars. Traffic sign recognition plays an important role to tackle the traffic related obstacles. And, as traffic sign recognition is particularly applied to portable devices, lightweight models are essential aspect of the agenda. To overcome the mentioned problems, we propose lightweight convolutional neural networks with residual blocks based deep learning model for traffic recognition systems. We not only present the model efficiency but also show the several conducted experiments will well known deep CNN architectures over publicly available German traffic sign recognition benchmark. Our model showed 99.9 % accuracy by F-score, exceeding other models. At last, our model shows generally validity for traffic sign classification problem.

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Vamsi, Bandi, Debnath Bhattacharyya, Divya Midhunchakkravarthy, and Jung-yoon Kim. "Early Detection of Hemorrhagic Stroke Using a Lightweight Deep Learning Neural Network Model." Traitement du Signal 38, no. 6 (December 31, 2021): 1727–36. http://dx.doi.org/10.18280/ts.380616.

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In present days, the major disease affecting people all across the world is “Cerebrovascular Stroke”. Computed tomographic (CT) images play a crucial role in identifying hemorrhagic strokes. It also helps in understanding the impact of damage caused in the brain cells more accurately. The existing research work is implemented on the Graphical Processing Unit (GPU’s) for stroke segmentation using heavyweight convolutions that require more processing time for diagnosis and increases the model's cost. Deep learning techniques with VGG-16 architecture and Random Forest algorithm are implemented for detecting hemorrhagic stroke using brain CT images under segmentation. A two-step light-weighted convolution model is proposed by using the data collected from multiple- repositories to inscribe this constraint. In the first step, the input CT images are given to VGG-16 architecture and in step two, data frames are given to random forest for stroke segmentation with three levels of classes. In this paper, we explore various training time values in the detection of stroke that reduces when compared with existing heavyweight models. Experimental results have shown that when compared to other existing architectures, our hybrid model VGG-16 and random forest achieved increased results obtained are dice coefficient with 72.92 and accuracy with 97.81% which shows promising results.

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Pyrgas, Lampros, and Paris Kitsos. "Compact Hardware Architectures of Enocoro-128v2 Stream Cipher for Constrained Embedded Devices." Electronics 9, no. 9 (September 14, 2020): 1505. http://dx.doi.org/10.3390/electronics9091505.

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Lightweight cryptography is a vital and fast growing field in today’s world where billions of constrained devices interact with each other. In this paper, two novel compact architectures of the Enocoro-128v2 stream cipher are presented. The Enocoro-128v2 is part of the ISO/IEC 29192-3 standard. The first architecture has an 8-bit datapath while the second one has a 4-bit datapath. The proposed architectures were implemented on the BASYS3 board (Artix 7 XC7A35T) using the VERILOG hardware description language. The hardware implementation of the proposed 8-bit architecture runs at a 189 MHz clock and reaches a throughput equal to 302 Mbps, while at the same time, it utilizes only 254 Look-up Tables (LUTs) and 330 Flip-flops (FFs). Each round of computations requires 5 clock cycles. The 4-bit implementation has an operating frequency of 204 MHz and reaches a throughput equal to 181 Mbps, with each round requiring 9 clock cycles. The 4-bit implementation utilizes 249 LUTs and 343 FFs. To our knowledge, this is the first time that such implementations of the Enocoro-128v2 are presented. Both implementations utilize a very low number of resources (only 78 FPGA slices are required for the 8-bit architecture and only 83 for the 4-bit one) and the results demonstrate that they are sustainable for area constrained embedded devices.

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Liu, H. Clive, Anesia D. Auguste, James O. Hardin, Andrew Sharits, and J. Daniel Berrigan. "Additive-Manufactured Stochastic Polyimide Foams for Low Relative Permittivity, Lightweight Electronic Architectures." ACS Applied Materials & Interfaces 13, no. 23 (June 2, 2021): 27364–71. http://dx.doi.org/10.1021/acsami.1c02862.

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Mecca, Giansalvatore, Michele Santomauro, Donatello Santoro, and Enzo Veltri. "IoT Helper: A Lightweight and Extensible Framework for Fast-Prototyping IoT Architectures." Applied Sciences 11, no. 20 (October 17, 2021): 9670. http://dx.doi.org/10.3390/app11209670.

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Industry 4.0 is focused on the task of creating Smart Factories, which require the automation of traditional industrial processes and the fully connection and integration of different systems and devices. However, despite the wide availability of tools and technology, developing intelligent applications in the industry framework remains a complex and expensive task. This paper proposes a lightweight, extensible and scalable framework called IoT Helper to facilitate the adoption of IoT and IIoT solutions both in industry and domotics. The framework is designed to be highly flexible and declarative in nature, thus allowing for a wide range of configurations with minimal user efforts. To emphasize the practical applicability or our proposal, we present two real-life use cases where the framework was successfully adopted. We also investigate a crucial aspect of these applications, i.e., what level of scalability can be achieved with a lean generic framework based on inexpensive components such as ours. Comprehensive experimental results show the excellent cost-to-performance ratio of our solution. We consider this to be an important contribution because it paves the way for a more widespread adoption of IIoT-enabling technologies in industry.

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Janakiraman, Siva, K. Thenmozhi, John Bosco Balaguru Rayappan, and Rengarajan Amirtharajan. "Indicator-based lightweight steganography on 32-bit RISC architectures for IoT security." Multimedia Tools and Applications 78, no. 22 (July 20, 2019): 31485–513. http://dx.doi.org/10.1007/s11042-019-07960-z.

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Sun, Wanmei, Smit A. Shah, Joseph L. Lowery, Ju Hyun Oh, Jodie L. Lutkenhaus, and Micah J. Green. "Lightweight Kevlar‐Reinforced Graphene Oxide Architectures with High Strength for Energy Storage." Advanced Materials Interfaces 6, no. 21 (September 12, 2019): 1900786. http://dx.doi.org/10.1002/admi.201900786.

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Journal articles on the topic 'Lightweight architectures'

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