Relevant bibliographies by topics / Leakage Current Density

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Leakage Current Density'

Author: Grafiati
Published: 6 September 2023

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Journal articles on the topic "Leakage Current Density"

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Kawahara, Takamitsu, Naoki Hatta, Kuniaki Yagi, Hidetsugu Uchida, Motoki Kobayashi, Masayuki Abe, Hiroyuki Nagasawa, Bernd Zippelius, and Gerhard Pensl. "Correlation between Leakage Current and Stacking Fault Density of p-n Diodes Fabricated on 3C-SiC." Materials Science Forum 645-648 (April 2010): 339–42. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.339.

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The correlation between leakage current and stacking fault (SF) density in p-n diodes fabricated on 3C-SiC homo-epitaxial layer is investigated. The leakage current density at reverse bias strongly depends on the SF density; an increase of one order of magnitude in the SF density enhances the leakage current by five orders of magnitude at a reverse bias of 400 V. In order to obtain commercially suitable MOSFETs with 10-4Acm-2 at 600V, the SF density has to be reduced below 6×104 cm-2. Photoemission caused by hot electrons, which travel along a leakage path, can be observed at the crossing between a SF and the edge of p-well region; where the maximum electric field is induced. The mechanism of the leakage current is discussed in detail in a separate paper.
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Tamada, Minoru, Yuji Noguchi, and Masaru Miyayama. "Defects and Leakage Current in PbTiO3 Single Crystals." Key Engineering Materials 350 (October 2007): 77–80. http://dx.doi.org/10.4028/www.scientific.net/kem.350.77.

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Single crystals of PbTiO3 (PT) were grown by a self flux method, and effects of lattice defects on the leakage current properties were investigated. While PT crystals annealed in air at 700 oC showed a leakage current density of the order of 10-5 A/cm2, annealing under a high oxygen partial pressure of 35 MPa increased leakage current density to 10-4 A/cm2. The increase in leakage current by the oxidation treatment provides direct evidence that electron hole is a detrimental carrier for the leakage current property of PT at room temperature. The vacancies of Pb are suggested to act as an electron acceptor for generating electron holes.
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Kim, Hyung Chul, Moon Seob Han, Hyun June Park, Dong Uk Jang, Gyung Suk Kil, and Nirmal Kumar Nair. "Consideration of Uncertainty in Diagnosis for Railway Arrester." Key Engineering Materials 321-323 (October 2006): 1507–12. http://dx.doi.org/10.4028/www.scientific.net/kem.321-323.1507.

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This paper presents a method for diagnosis of railway arrester considering uncertainty. Arresters, a protective device that prevents damage due to transient voltages, deteriorate due to the absorption of moisture, repetitive operation during over-voltages and manufacturing defects. Various diagnostic techniques are available for monitoring deterioration of arresters. The technique based on the amplitude of leakage current measures the root mean square or peak values of leakage current components. After measuring the total leakage current, harmonics of leakage current components are analyzed by using a microprocessor based device. The level of leakage current is indicative of the arrester conditions. Harmonics of leakage current components occur due to nonlinear characteristics of railway arrester. Since leakage current contains uncertainty characteristics of power source, the probability density functions of leakage current components can be obtained for ZnO arrester. This paper presents a probabilistic approximation method for the harmonic currents analysis in diagnosis for railway arresters. Mean and variance of harmonic currents in railway system are obtained based on leakage current components. These statistical measures can be helpful to reduce the diagnostic error for railway arrester.
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Ishikawa, Tsuyoshi, T. Katsuno, Y. Watanabe, H. Fujiwara, and T. Endo. "Critical Density of Nanoscale Pits for Suppressing Variability in Leakage Current of a SiC Schottky Barrier Diode." Materials Science Forum 717-720 (May 2012): 371–74. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.371.

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We investigate the influence of SiC surface morphology on increase and variability in reverse leakage current of SiC Schottky barrier diodes using device simulation. It is found that etch pits with only a few tens of nm in depth has a large influence on leakage current and is also shown that leakage current is sensitive to both etch pit shape and density. From these results, we suggest the critical density of nanoscale pit, which is suppressing the variability of leakage current, at various drift layer thickness tdrift and doping concentration Ndrift.
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Hirokazu, Fujiwara, T. Katsuno, Tsuyoshi Ishikawa, H. Naruoka, Masaki Konishi, T. Endo, Y. Watanabe, et al. "Impact of Surface Morphology above Threading Dislocations on Leakage Current in 4H-SiC Diodes." Materials Science Forum 717-720 (May 2012): 911–16. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.911.

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The impact of threading dislocation density on the leakage current of reverse IV characteristics in 1.2 kV Schottky barrier diodes (SBDs), junction barrier Schottky diodes (JBSDs), and PN junction diodes (PNDs) was investigated. The leakage current density and threading dislocation density have different positive correlations in each type of diode. For example, the correlation in SBDs is strong, but weak in PNDs. The threading dislocations were found to be in the same location as the current leakage points in the SBDs, but not in the PNDs. Nano-scale inverted cone pits were observed at the Schottky junction interface in SBDs, and it was found that leakage current increases in these diodes due to the concentration of electric fields at the peaks of the pits. These nano-scale pits were also observed directly above threading dislocations. In addition, this study succeeded in reducing the leakage current variation of 200 A-class JBSDs and SBDs by eliminating the nano-scale pits above the threading dislocations. As a result, a theoretical straight-line waveform was achieved.
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Uno, Shigeyasu, Kazuaki Deguchi, Yoshinari Kamakura, and Kenji Taniguchi. "Trap Density Dependent Inelastic Tunneling in Stress-Induced Leakage Current." Japanese Journal of Applied Physics 41, Part 1, No. 4B (April 30, 2002): 2645–49. http://dx.doi.org/10.1143/jjap.41.2645.

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Kim, Hyojung, Jongwoo Park, Junehwan Kim, Nara Lee, Gaeun Lee, Soonkon Kim, Pyungho Choi, Dohyun Beak, Jangkun Song, and Byoungdeog Choi. "Leakage Current Analysis Method for Metal Insulator Semiconductor Capacitors Through Low-Frequency Noise Measurement." Journal of Nanoscience and Nanotechnology 21, no. 3 (March 1, 2021): 1966–70. http://dx.doi.org/10.1166/jnn.2021.18901.

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Use of thinner oxides to improve the operating speed of a complementary metal-oxidesemiconductor (CMOS) device causes serious gate leakage problems. Leakage current of the dielectric analysis method has I–V, C–V, and charge pumping, but the procedure is very complicated. In this premier work, we analyzed the leakage current of metal insulator semiconductor (MIS) capacitors with different initiators through low-frequency noise (LFN) measurement with simplicity and high sensitivity. The LFN measurement results show a correlation between power spectral density (SIG) and gate leakage current (IG). MIS capacitors of hafnium zirconium silicate (HZS, (HfZrO4)1-x (SiO2)x) were used for the experiments with varying SiO2 ratio (x = 0, 0.1, 0.2) of hafnium zirconium oxide (HZO, HfZrO4). As the SiO2 ratio increased, the leakage current decreased according to J–V measurement. Further, the C–V measurement confirmed that the oxide-trapped charge (Not) increased with increasing SiO2 ratio. Finally, the LFN measurement method revealed that the cause of leakage current reduction was trap density reduction of the insulator.
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Negara, I. Made Yulistya, I. G. N. Satriyadi Hernanda, Dimas Anton Asfani, Mira Kusuma Wardani, Bonifacius Kevin Yegar, and Reynaldi Syahril. "Effect of Seawater and Fly Ash Contaminants on Insulator Surfaces Made of Polymer Based on Finite Element Method." Energies 14, no. 24 (December 20, 2021): 8581. http://dx.doi.org/10.3390/en14248581.

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Polymer is an insulating substance that has become increasingly popular in recent years due to its benefits. Light density, superior dielectric and thermal properties, and water-resistant or hydrophobic properties are only a few of the benefits. The presence of impurities or pollutants on the insulator’s surface lowers its dielectric capacity, which can lead to current leakage. The influence of seawater and fly ash pollutants on the distribution of the electric field and the current density of the insulator was simulated in this study. The finite element method was used to execute the simulation (FEM). Polymer insulators are subjected to testing in order to gather current leakage statistics. The tested insulator is exposed to seawater pollution, which varies depending on the equivalent salt density deposit value (ESDD). The pollutant insulator for fly ash varies depending on the value of non-soluble deposit density (NSDD). The existence of a layer of pollutants increased the value of the electric field and the value of the surface current density, according to the findings. Both in simulation and testing, the ESDD value of seawater pollutants and the NSDD value of fly ash contaminants influenced the value of the leakage current that flowed. The greater the ESDD and NSDD values are, the bigger the leakage current will be.
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Geng, Kuiwei, Ditao Chen, Quanbin Zhou, and Hong Wang. "AlGaN/GaN MIS-HEMT with PECVD SiNx, SiON, SiO2 as Gate Dielectric and Passivation Layer." Electronics 7, no. 12 (December 10, 2018): 416. http://dx.doi.org/10.3390/electronics7120416.

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Three different insulator layers SiNx, SiON, and SiO2 were used as a gate dielectric and passivation layer in AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMT). The SiNx, SiON, and SiO2 were deposited by a plasma-enhanced chemical vapor deposition (PECVD) system. Great differences in the gate leakage current, breakdown voltage, interface traps, and current collapse were observed. The SiON MIS-HEMT exhibited the highest breakdown voltage and Ion/Ioff ratio. The SiNx MIS-HEMT performed well in current collapse but exhibited the highest gate leakage current density. The SiO2 MIS-HEMT possessed the lowest gate leakage current density but suffered from the early breakdown of the metal–insulator–semiconductor (MIS) diode. As for interface traps, the SiNx MIS-HEMT has the largest shallow trap density and the lowest deep trap density. The SiO2 MIS-HEMT has the largest deep trap density. The factors causing current collapse were confirmed by Photoluminescence (PL) spectra. Based on the direct current (DC) characteristics, SiNx and SiON both have advantages and disadvantages.
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Albertin, Katia F., M. A. Valle, and I. Pereyra. "Study Of MOS Capacitors With TiO2 And SiO2/TiO2 Gate Dielectric." Journal of Integrated Circuits and Systems 2, no. 2 (November 18, 2007): 89–93. http://dx.doi.org/10.29292/jics.v2i2.272.

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MOS capacitors with TiO2 and TiO2/SiO2 dielectric layer were fabricated and characterized. TiO2 films where physical characterized by Rutherford Backscattering, Fourier TransformInfrared Spectroscopy and Elipsometry measurements. Capacitance-voltage (1MHz) and current voltage measurements were utilized to obtain, the effective dielectric constant, effective oxide thickness (EOT), leakage current density and interface quality. The results show that the obtained TiO2 films present a dielectric constant of approximately 40, a good interface quality with silicon and a leakage current density, of 70 mA/cm2 for VG = 1V, acceptable for high performance logic circuits and low power circuits fabrication, indicating that this material is a viable substitute for current dielectric layers in order to prevent tunneling currents.
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Dissertations / Theses on the topic "Leakage Current Density"

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Kumar, Manish. "High density and high reliability thin film embedded capacitors on organic and silicon substrates." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26655.

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Thesis (M.S.)--Materials Science and Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Tummala Rao; Committee Member: Pulugurtha Raj; Committee Member: Wong C P. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Tewg, Jun-Yen. "Zirconium-doped tantalum oxide high-k gate dielectric films." Diss., Texas A&M University, 2004. http://hdl.handle.net/1969.1/1346.

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A new high-k dielectric material, i.e., zirconium-doped tantalum oxide (Zr-doped TaOx), in the form of a sputter-deposited thin film with a thickness range of 5-100 nm, has been studied. Important applications of this new dielectric material include the gate dielectric layer for the next generation metal-oxide-semiconductor field effect transistor (MOSFET). Due to the aggressive device scaling in ultra-large-scale integrated circuitry (ULSI), the ultra-thin conventional gate oxide (SiO2) is unacceptable for many practical reasons. By replacing the SiO2 layer with a high dielectric constant material (high-k), many of the problems can be solved. In this study, a novel high-k dielectric thin film, i.e., TaOx doped with Zr, was deposited and studied. The film’s electrical, chemical, and structural properties were investigated experimentally. The Zr dopant concentration and the thermal treatment condition were studied with respect to gas composition, pressure, temperature, and annealing time. Interface layer formation and properties were studied with or without an inserted thin tantalum nitride (TaNx) layer. The gate electrode material influence on the dielectric properties was also investigated. Four types of gate materials, i.e., aluminum (Al), molybdenum (Mo), molybdenum nitride (MoN), and tungsten nitride (WN), were used in this study. The films were analyzed with ESCA, XRD, SIMS, and TEM. Films were made into MOS capacitors and characterized using I-V and C-V curves. Many promising results were obtained using this kind of high-k film. It is potentially applicable to future MOS devices.
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Heideklang, René. "Data Fusion for Multi-Sensor Nondestructive Detection of Surface Cracks in Ferromagnetic Materials." Doctoral thesis, Humboldt-Universität zu Berlin, 2018. http://dx.doi.org/10.18452/19586.

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Ermüdungsrissbildung ist ein gefährliches und kostenintensives Phänomen, welches frühzeitig erkannt werden muss. Weil kleine Fehlstellen jedoch hohe Testempfindlichkeit erfordern, wird die Prüfzuverlässigkeit durch Falschanzeigen vermindert. Diese Arbeit macht sich deshalb die Diversität unterschiedlicher zerstörungsfreier Oberflächenprüfmethoden zu Nutze, um mittels Datenfusion die Zuverlässigkeit der Fehlererkennung zu erhöhen. Der erste Beitrag dieser Arbeit in neuartigen Ansätzen zur Fusion von Prüfbildern. Diese werden durch Oberflächenabtastung mittels Wirbelstromprüfung, thermischer Prüfung und magnetischer Streuflussprüfung gewonnen. Die Ergebnisse zeigen, dass schon einfache algebraische Fusionsregeln gute Ergebnisse liefern, sofern die Daten adäquat vorverarbeitet wurden. So übertrifft Datenfusion den besten Einzelsensor in der pixelbasierten Falscherkennungsrate um den Faktor sechs bei einer Nutentiefe von 10 μm. Weiterhin wird die Fusion im Bildtransformationsbereich untersucht. Jedoch werden die theoretischen Vorteile solcher richtungsempfindlichen Transformationen in der Praxis mit den vorliegenden Daten nicht erreicht. Nichtsdestotrotz wird der Vorteil der Fusion gegenüber Einzelsensorprüfung auch hier bestätigt. Darüber hinaus liefert diese Arbeit neuartige Techniken zur Fusion auch auf höheren Ebenen der Signalabstraktion. Ein Ansatz, der auf Kerndichtefunktionen beruht, wird eingeführt, um örtlich verteilte Detektionshypothesen zu integrieren. Er ermöglicht, die praktisch unvermeidbaren Registrierungsfehler explizit zu modellieren. Oberflächenunstetigkeiten von 30 μm Tiefe können zuverlässig durch Fusion gefunden werden, wogegen das beste Einzelverfahren erst Tiefen ab 40–50 μm erfolgreich auffindet. Das Experiment wird auf einem zweiten Prüfkörper bestätigt. Am Ende der Arbeit werden Richtlinien für den Einsatz von Datenfusion gegeben, und die Notwendigkeit einer Initiative zum Teilen von Messdaten wird betont, um zukünftige Forschung zu fördern.
Fatigue cracking is a dangerous and cost-intensive phenomenon that requires early detection. But at high test sensitivity, the abundance of false indications limits the reliability of conventional materials testing. This thesis exploits the diversity of physical principles that different nondestructive surface inspection methods offer, by applying data fusion techniques to increase the reliability of defect detection. The first main contribution are novel approaches for the fusion of NDT images. These surface scans are obtained from state-of-the-art inspection procedures in Eddy Current Testing, Thermal Testing and Magnetic Flux Leakage Testing. The implemented image fusion strategy demonstrates that simple algebraic fusion rules are sufficient for high performance, given adequate signal normalization. Data fusion reduces the rate of false positives is reduced by a factor of six over the best individual sensor at a 10 μm deep groove. Moreover, the utility of state-of-the-art image representations, like the Shearlet domain, are explored. However, the theoretical advantages of such directional transforms are not attained in practice with the given data. Nevertheless, the benefit of fusion over single-sensor inspection is confirmed a second time. Furthermore, this work proposes novel techniques for fusion at a high level of signal abstraction. A kernel-based approach is introduced to integrate spatially scattered detection hypotheses. This method explicitly deals with registration errors that are unavoidable in practice. Surface discontinuities as shallow as 30 μm are reliably found by fusion, whereas the best individual sensor requires depths of 40–50 μm for successful detection. The experiment is replicated on a similar second test specimen. Practical guidelines are given at the end of the thesis, and the need for a data sharing initiative is stressed to promote future research on this topic.
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"High Power Density, High Efficiency Single Phase Transformer-less Photovoltaic String Inverters." Doctoral diss., 2017. http://hdl.handle.net/2286/R.I.45041.

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abstract: Two major challenges in the transformer-less, single-phase PV string inverters are common mode leakage currents and double-line-frequency power decoupling. In the proposed doubly-grounded inverter topology with innovative active-power-decoupling approach, both of these issues are simultaneously addressed. The topology allows the PV negative terminal to be directly connected to the neutral, thereby eliminating the common-mode ground-currents. The decoupling capacitance requirement is minimized by a dynamically-variable dc-link with large voltage swing, allowing an all-film-capacitor implementation. Furthermore, the use of wide-bandgap devices enables the converter operation at higher switching frequency, resulting in smaller magnetic components. The operating principles, design and optimization, and control methods are explained in detail, and compared with other transformer-less, active-decoupling topologies. A 3 kVA, 100 kHz single-phase hardware prototype at 400 V dc nominal input and 240 V ac output has been developed using SiC MOSFETs with only 45 μF/1100 V dc-link capacitance. The proposed doubly-grounded topology is then extended for split-phase PV inverter application which results in significant reduction in both the peak and RMS values of the boost stage inductor current and allows for easy design of zero voltage transition. A topological enhancement involving T-type dc-ac stage is also developed which takes advantage of the three-level switching states with reduced voltage stress on the main switches, lower switching loss and almost halved inductor current ripple. In addition, this thesis also proposed two new schemes to improve the efficiency of conventional H-bridge inverter topology. The first scheme is to add an auxiliary zero-voltage-transition (ZVT) circuit to realize zero-voltage-switching (ZVS) for all the main switches and inherent zero-current-switching (ZCS) for the auxiliary switches. The advantages include the provision to implement zero state modulation schemes to decrease the inductor current THD, naturally adaptive auxiliary inductor current and elimination of need for large balancing capacitors. The second proposed scheme improves the system efficiency while still meeting a given THD requirement by implementing variable instantaneous switching frequency within a line frequency cycle. This scheme aims at minimizing the combined switching loss and inductor core loss by including different characteristics of the losses relative to the instantaneous switching frequency in the optimization process.
Dissertation/Thesis
Doctoral Dissertation Electrical Engineering 2017
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Thapliyal, Prashant. "High-K Dielectrics–Studies on (Ta2O5)1-x– (TiO2)x, (0 ≤ x ≤ 0.11), Thin Films." Thesis, 2021. https://etd.iisc.ac.in/handle/2005/5579.

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Recently the increasing demand for miniaturized electronic gadgets has raised the interest in searching the high dielectric constant (K) materials for memory elements. Among the investigated high dielectric constant metal oxides, complex perovskites, such as barium titanate, strontium titanate, etc. and their solid solutions; and binary oxides, such as tantalum pentoxide, titanium oxide, zirconium oxide, etc. and their solid solutions are prominent. Due to the toxicity and compatibility issues of many complex perovskite oxides with the current fabrication procedures, binary oxides have been a preferred choice to use as a gate dielectric in memory devices. Among the binary oxides, tantalum pentoxide (Ta2O5) was found to have high dielectric constant and good compatibility with the existing fabrication procedures of silicon devices and a potential to replace the silicon-based dielectrics, such as SiO2, SiOxNy, etc., in the memory devices. With the addition of TiO2, ZrO2, etc., the dielectric constant of bulk Ta2O5 was found to increase by manifold, and so the potential of miniaturization to improve in that proportion was envisaged. The present study was carried out to search the high dielectric constant and low leakage current thin films of Ta2O5 ¬– TiO2 compositions for memory devices. Thin films of different compositions of (Ta2O5)1−x–(TiO2)x (TTOx) were prepared using mosaic and ceramic targets and the structural, electrical, and optical properties of prepared films were investigated. TTOx thin films with compositions, x = 0, 0.03, 0.06, 0.08, and 0.11, were deposited onto the silicon and quartz substrates by direct current (DC) magnetron sputtering. The as-deposited thin film samples were annealed, in the ambient air, at 500, 600, 700 and 800 ˚C, for 1.5 h. The dielectric constant was found significantly depending on the composition and annealing temperature. Among the prepared compositions, at 1 MHz, the highest dielectric constant 71 was observed for x = 0.06, annealed at 700 ˚C. Using the measured optical transmittance, different optical parameters, viz., refractive index, extinction coefficient, and optical bandgap of the prepared films were obtained and found strongly dependent on the annealing temperature. The observed current–voltage (I–V) characteristics show the decreasing leakage current density with increasing annealing temperature. On annealing at 800 ˚C, the C–V and I–V characteristics of the deposited film compositions were found affected significantly due to the growing interfacial SiO2 layer at the film–substrate (Si) interface. The electrical properties and existing different current conduction mechanisms in different electric field regions were observed depending on the growing interfacial SiO2 layer with increasing annealing temperature. A comparative study of the TTOx films of the same composition prepared following two different routes: first, by the radio frequency (RF) sputtering of the ceramic target; and second, by DC sputtering of mosaic (Ta, Ti) metal target, in the presence of oxygen, was also carried out. The same post-deposition treatment was followed for both types of films deposited from two different routes. The structural, electrical, and optical properties with current conduction mechanisms, for the films prepared from the two different routes, were measured, compared and analyzed. The observations have been described in the present thesis.
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Book chapters on the topic "Leakage Current Density"

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Monazzah, Amir Mahdi Hosseini, Amir M. Rahmani, Antonio Miele, and Nikil Dutt. "Exploiting Memory Resilience for Emerging Technologies: An Energy-Aware Resilience Exemplar for STT-RAM Memories." In Dependable Embedded Systems, 505–26. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_21.

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AbstractDue to the consistent pressing quest of larger on-chip memories and caches of multicore and manycore architectures, Spin Transfer Torque Magnetic RAM (STT-MRAM or STT-RAM) has been proposed as a promising technology to replace classical SRAMs in near-future devices. Main advantages of STT-RAMs are a considerably higher transistor density and a negligible leakage power compared with SRAM technology. However, the drawback of this technology is the high probability of errors occurring especially in write operations. Such errors are asymmetric and transition-dependent, where 0 → 1 is the most critical one, and is high subjected to the amount and current (voltage) supplied to the memory during the write operation. As a consequence, STT-RAMs present an intrinsic trade-off between energy consumption vs. reliability that needs to be properly tuned w.r.t. the currently running application and its reliability requirement. This chapter proposes FlexRel, an energy-aware reliability improvement architectural scheme for STT-RAM cache memories. FlexRel considers a memory architecture provided with Error Correction Codes (ECCs) and a custom current regulator for the various cache ways and conducts a trade-off between reliability and energy consumption. FlexRel cache controller dynamically profiles the number of 0 → 1 transitions of each individual bit write operation in a cache block and based on that selects the most-suitable cache way and current level to guarantee the necessary error rate threshold (in terms of occurred write errors) while minimizing the energy consumption. We experimentally evaluated the efficiency of FlexRel against the most efficient uniform protection scheme from reliability, energy, area, and performance perspectives. Experimental simulations performed by using gem5 has demonstrated that while FlexRel satisfies the given error rate threshold, it delivers up to 13.2% energy saving. From the area footprint perspective, FlexRel delivers up to 7.9% cache ways’ area saving. Furthermore, the performance overhead of the FlexRel algorithm which changes the traffic patterns of the cache ways during the executions is 1.7%, on average.
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Malavena, Gerardo. "Modeling of GIDL–Assisted Erase in 3–D NAND Flash Memory Arrays and Its Employment in NOR Flash–Based Spiking Neural Networks." In Special Topics in Information Technology, 43–53. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-85918-3_4.

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AbstractSince the very first introduction of three-dimensional (3–D) vertical-channel (VC) NAND Flash memory arrays, gate-induced drain leakage (GIDL) current has been suggested as a solution to increase the string channel potential to trigger the erase operation. Thanks to that erase scheme, the memory array can be built directly on the top of a $$n^+$$ n + plate, without requiring any p-doped region to contact the string channel and therefore allowing to simplify the manufacturing process and increase the array integration density. For those reasons, the understanding of the physical phenomena occurring in the string when GIDL is triggered is important for the proper design of the cell structure and of the voltage waveforms adopted during erase. Even though a detailed comprehension of the GIDL phenomenology can be achieved by means of technology computer-aided design (TCAD) simulations, they are usually time and resource consuming, especially when realistic string structures with many word-lines (WLs) are considered. In this chapter, an analysis of the GIDL-assisted erase in 3–D VC nand memory arrays is presented. First, the evolution of the string potential and GIDL current during erase is investigated by means of TCAD simulations; then, a compact model able to reproduce both the string dynamics and the threshold voltage transients with reduced computational effort is presented. The developed compact model is proven to be a valuable tool for the optimization of the array performance during erase assisted by GIDL. Then, the idea of taking advantage of GIDL for the erase operation is exported to the context of spiking neural networks (SNNs) based on NOR Flash memory arrays, which require operational schemes that allow single-cell selectivity during both cell program and cell erase. To overcome the block erase typical of nor Flash memory arrays based on Fowler-Nordheim tunneling, a new erase scheme that triggers GIDL in the NOR Flash cell and exploits hot-hole injection (HHI) at its drain side to accomplish the erase operation is presented. Using that scheme, spike-timing dependent plasticity (STDP) is implemented in a mainstream NOR Flash array and array learning is successfully demonstrated in a prototype SNN. The achieved results represent an important step for the development of large-scale neuromorphic systems based on mature and reliable memory technologies.
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Li, Qiangqiang, Yanghui Zhang, Lili Shen, Ning Zhao, Tao Zhang, and Xiaoxia Sun. "The Effect of Leakage Current on the Performance of Proton-Conducting Solid Oxide Fuel Cells." In Advances in Energy Research and Development. IOS Press, 2022. http://dx.doi.org/10.3233/aerd220024.

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In this study, a numerical model is built to analyze the leakage current of a proton conductor solid oxide fuel cell. The transports of electron-hole and proton transfer in a mixed conductor electrolyte is described by the Nernst-Planck equation. The model is validated using experimental data. The leakage current, potential distribution, Faraday efficiency and energy efficiency are analyzed. When the output voltage of the fuel cell is greater than 0.5 V, the leakage current will cause the energy efficiency in a significant reduction. The lower the temperature, the lower the leakage current density. Lowering the temperature will improve the Faraday efficiency and energy efficiency of the fuel cell. Lower output voltage helps improve the Faraday efficiency.
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Zhou, Yingjian, and Wei Chen. "Analysis and Optimization of Low-Voltage and High-Current Matrix Current-Doubler Rectifiers Integrated Magnetic Components." In Advances in Transdisciplinary Engineering. IOS Press, 2022. http://dx.doi.org/10.3233/atde221039.

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All parties favour the half-bridge current-doubling rectifier circuit due to its advantages: small output current pulsation, low switching voltage stress, and high anti-unbalance ability. Further integration of the secondary inductor and the transformer further reduces the size of the converter and dramatically improves the power density. This paper carefully analyzes the existing magnetic integration schemes. Combined with the characteristics of low-voltage and high-current DC converters, the secondary winding in this paper adopts the form of one turn to further reduce the loss so as to adapt to the secondary output of high current. The way the integrated magnetics are matrixed. The secondary side has a higher DC flux offset, and the magnetic core material adopts a magnetic powder core with high saturation magnetic density, which is equivalent to a distributed air gap, which significantly reduces the additional winding loss caused by the air gap diffusion magnetic flux cutting the winding. The winding loss, termination loss, core loss, and distribution parameters of single and matrix integrated magnetic components were compared and analyzed. Focus on optimization analysis. At the same time, it focuses on the influence of matrix on the DC bias and DC loss of the current-doubling rectifier core. At the same time, the leakage inductance and winding loss of the integrated magnetic components are comprehensively considered, and a compromise design is carried out further to improve the power density of the integrated magnetic components.
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Preethi, Sapna R., and Mohammed Mujeer Ulla. "Low-Power Methodologies and Strategies in VLSI Circuits." In Advances in Computer and Electrical Engineering, 1–16. IGI Global, 2022. http://dx.doi.org/10.4018/978-1-6684-4974-5.ch001.

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Due to the fact that low-power gadgets are currently dominating the electronics sectors, researchers are studying their design. Power management is a crucial parameter for designing VLSI circuits since it is essential for estimating the performance of devices, especially those utilized in biomedical and IoT applications. To achieve greater performance, designing a low-power system on a IC is becoming increasingly challenging due to the reduction in size of chip, increases in chip density, and rise in device complexity. Furthermore, for the less than 90 nm node, due to its increasingly complicated design, the total power factor on a chip is turning into a significant difficulty. Leakage current also has a significant effect on how low-power VLSI devices manage their power. Leakage and dynamic power reduction are increasingly being prioritized in VLSI circuit design in order to improve the battery life of electronic portable devices. The many methodologies, tactics, and power management schemes that can be employed for the design of low-power circuit systems are discussed in this chapter.
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Stevic, Zoran, and Ilija Radovanovic. "Supercapacitors: The Innovation of Energy Storage." In Updates on Supercapacitors [Working Title]. IntechOpen, 2022. http://dx.doi.org/10.5772/intechopen.106705.

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In addition to the accelerated development of standard and novel types of rechargeable batteries, for electricity storage purposes, more and more attention has recently been paid to supercapacitors as a qualitatively new type of capacitor. A large number of teams and laboratories around the world are working on the development of supercapacitors, while their ever-improving performances enable wider use. The major challenges are to improve the parameters of supercapacitors, primarily energy density and operating voltage, as well as the miniaturization, optimization, energy efficiency, economy, and environmental acceptance. This chapter provides an overview of new techniques and technologies of supercapacitors that are changing the present and future of electricity storage, with special emphasis on self-powering sensor and transmitter systems. The latest achievements in the production, modeling, and characterization of supercapacitor elements (electrode materials, electrolytes, and supporting elements) whose parameters are optimized for long-term self-supply of low power consumers (low voltage, high energy density, and low leakage current, etc.) are considered.
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Kumar, Sunil, and Balwinder Raj. "Simulations and Modeling of TFET for Low Power Design." In Advances in Systems Analysis, Software Engineering, and High Performance Computing, 640–67. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-4666-8823-0.ch021.

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In Complementary Metal-Oxide-Semiconductor (CMOS) technology, scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past four decades. However, as the technology advancement on nanometer scale regime for the purpose of building ultra-high density integrated electronic computers and extending performance, CMOS devices are facing fundamental problems such as increased leakage currents, large process parameter variations, short channel effects, increase in manufacturing cost, etc. The new technology must be energy efficient, dense, and enable more device function per unit area and time. There are many novel nanoscale semiconductor devices, this book chapter introduces and summarizes progress in the development of the Tunnel Field-Effect Transistors (TFETs) for low power design. Tunnel FETs are interesting devices for ultra-low power applications due to their steep sub-threshold swing (SS) and very low OFF-current. Tunnel FETs avoid the limit 60mv/decade by using quantum-mechanical Band-to-Band Tunneling (BTBT).
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"Chapter 9 Effect of current leakage on electro-adhesion forces in rolling friction and magnetic flux density distribution on track surfaces of rolling-element bearings." In Tribology in Electrical Environments, 179–209. Elsevier, 2006. http://dx.doi.org/10.1016/s0167-8922(06)80022-2.

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Conference papers on the topic "Leakage Current Density"

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Uno, Shigeyasu, Kazuaki Deguchi, Yoshinari Kamakura, and Kenji Taniguchi. "Trap Density Dependent Inelastic Tunneling in Stress-Induced Leakage Current." In 2001 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2001. http://dx.doi.org/10.7567/ssdm.2001.c-9-1.

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Oleinik, G. M., V. V. Aleksandrov, A. V. Branitskii, I. N. Frolov, E. V. Grabovskii, E. I. Predkova, O. B. Reshetnjak, and S. I. Tkachenko. "Leakage of current from MITL with ceramic coating cathode." In 8th International Congress on Energy Fluxes and Radiation Effects. Crossref, 2022. http://dx.doi.org/10.56761/efre2022.s2-o-009807.

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At the Angara-5-1 installation the experiments were carried out to study the processes occurring during the passage of current in a vacuum transporting line in which the cathode was protected by a ceramic coating. The linear current density was about 1–2 MA/cm; the time of the current rise to the maximum was ~100 ns. It is shown that in the case of coating the MITL cathode with ceramics, not all the current entering the MITL reaches its end.
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Heydari, H., S. H. Pedramrazi, and F. Faghihi. "The effects of windings current density values on leakage reactance in a 25 kA current injection transformer." In 2005 International Power Engineering Conference. IEEE, 2005. http://dx.doi.org/10.1109/ipec.2005.206988.

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Akashe, Shyam, Sushil Bhushan, and Sanjay Sharma. "High density and low leakage current based 5T SRAM cell using 45 nm technology." In International Conference on Nanoscience, Engineering and Technology (ICONSET 2011). IEEE, 2011. http://dx.doi.org/10.1109/iconset.2011.6167978.

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Schmidt, Christian, Cheryl Hartfield, Stephen T. Kelly, Luke England, and Sukeshwar Kannan. "Nanoscale 3D X-ray Microscopy for High Density Multi-Chip Packaging FA." In ISTFA 2018. ASM International, 2018. http://dx.doi.org/10.31399/asm.cp.istfa2018p0424.

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Abstract An effective method is presented to locate certain failure sites on exposed junction of insulated-gate bipolar transistor (IGBT) devices. High emitter to collector leakage current, hereafter called ICESR, is an IGBT failure mode. The leakage current is typically related to the exposed P+/N+ junction on the die sidewall. Solder die attach residue bridging or silicon damage at this exposed P+/N+ junction are common causes of ICESR leakage. The die attach residue can be dislodged during decapsulation resulting in loss of failure information. A failure analysis flow will be described to precisely locate the ICESR leakage site without disturbing any possible die attach residue.
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Matsuda, K., S. Tada, M. Nagata, Y. Li, T. Sugawara, M. Iwamoto, K. Ohta, K. Sakiyama, and N. Miura. "An Information Leakage Sensor Based on Measurement of Laser-Induced Opto-Electric Bulk Current Density." In 2019 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2019. http://dx.doi.org/10.7567/ssdm.2019.m-1-03.

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Tian, Lixin, Fei Yang, Zhanwei Shen, Feng Zhang, Xingfang Liu, Guoguo Yan, Wanshun Zhao, et al. "Low leakage current and high unipolar current density in a 4H-SiC trench gate MOSFET with integrated Schottky barrier diode." In 2020 17th China International Forum on Solid State Lighting & 2020 International Forum on Wide Bandgap Semiconductors China (SSLChina: IFWS). IEEE, 2020. http://dx.doi.org/10.1109/sslchinaifws51786.2020.9308886.

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Serincan, Mustafa F., Ugur Pasaogullari, and Nigel M. Sammes. "A Computational Analysis to Identify the Current Density Characteristics of a Micro-Tubular Solid Oxide Fuel Cell." In ASME 2008 6th International Conference on Fuel Cell Science, Engineering and Technology. ASMEDC, 2008. http://dx.doi.org/10.1115/fuelcell2008-65199.

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A computational fluid dynamics model is developed to study the effects of operational parameters on the performance of a micro-tubular SOFC. Coupled partial differential equations for heat, momentum, species and charge balances are solved with a commercial software using finite element method. Effect of temperature on the power characteristics of the system is addressed. Current density distributions for different temperatures are compared with the inclusion of electronic leakage currents in the electrolyte. Current density profiles for different conditions are examined thoroughly and related to the transport properties.
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Gao, Kai, Maoxin Ren, Haifeng Jin, Haoyang Tian, Jianming He, and Lijun Jin. "Pollution Flashover Prediction of Insulators Based on Combined Probability Density of Infrared Image Temperature and Leakage Current." In 2022 IEEE 5th International Electrical and Energy Conference (CIEEC). IEEE, 2022. http://dx.doi.org/10.1109/cieec54735.2022.9846194.

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Banik, Apu, Sovan Dalai, and Biswendu Chatterjee. "Studies the effect of Equivalent Salt Deposit Density on leakage current and flashover voltage of artificially contaminated disc insulators." In 2015 1st Conference on Power, Dielectric and Energy Management at NERIST (ICPDEN). IEEE, 2015. http://dx.doi.org/10.1109/icpden.2015.7084495.

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