Dissertations / Theses on the topic 'Layout automation'
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Lööf, Kajsa. "Strategy for automation and layout change in production systems." Thesis, KTH, Industriell produktion, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-61076.
Full textSundelin, Niklas. "Produktionsoptimering av Fladder-avgradningssystem : Framtagning av layout för materialhanteringen runt Fladder-avgradningssystem." Thesis, Mittuniversitetet, Avdelningen för kvalitets- och maskinteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-36870.
Full textThe bachelor thesis was performed to investigate how material handling around the deburring system Fladder can be developed and automated. The reason is due to today's manual handling which is inefficient and time consuming and therefore needs to be optimized. The work was carried out with methodology from the product development process to offer layout suggestions on how material handling can be improved. First, a feasibility study was conducted in which a data collection, literature study and current situation analysis were done to identify the needs. Concepts were generated based on the requirements of the system and through various decision matrices, two solutions were chosen for further development. The solutions were reviewed and analyzed in more detail and calculations of their efficiency and profitability were made. The solutions were refined and resulted in two layouts on how the material handling can be improved. The first concept is a simple system for the situation today and the second concept is a more advanced solution for future investments.
Betyg 2019-07-24
Simon, Matthew. "Evaluation and automation of space habitat interior layouts." Diss., Georgia Institute of Technology, 2016. http://hdl.handle.net/1853/54938.
Full textBrito, Eliseu Silveira. "Aplicativo para modelamento 3D de layout celular com base em tecnologia de grupo." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2010. http://hdl.handle.net/10183/29421.
Full textThe constant evolution of production systems increases the importance given to industrial installation projects where the cellular systems have a special importance because of their strong trend to be used today by industrial engineering. The cellular system adopt concepts of group technology making it possible to produce small batches and gain economic advantages similar to those obtained with mass production without losing flexibility in the manufacturing process. With the evolution of computing, integrated systems that give support to the decision process in planning and implementing these designs arose and helped to have physical arrangements adequate for the new production requirements, but the cost of acquiring and developing specific software is still quite high. This paper presents a computational solution for the design of cells by developing an application that translates the result of a group technology algorithm into graphical options of different physical concepts for cell layout, proposing an integrative function, associating a library of machine-tool graphical models to represent on the plant floor different flow options for the layout. The interface is developed in Visual Basic and allows both the processing of the algorithm for defining groups of machines based on production flow analysis as well as a representation on the graphic system and interaction necessary with the database in a Microsoft Access standard. The modeling is represented in a graphical environment using Solid Edge software, which allows the customization needed to generate, in an automated manner, an interface for the layout design. When defining the boundaries of the clusters or limiting the cell, a methodology is used that automatically identifies them, and in most of the designs done previously they did not plan for automatic routines and often this identification became the responsibility of the user. The system developed has an application as an important tool in planning and designing the layout as it makes use of resources of a commercial graphics platform (CAD) to represent automatically the result of algorithms that would normally be just textual information. This paper complements other applications made before that were limited to the definitions of cells without representing them graphically, and makes it possible to choose the form of flow to be assumed by the cell, representing an important element in the decision making process for those who are designing or promoting improvements in an industrial environment.
Vallander, Karolina, and Malin Lindblom. "Lean line layouts in highly automated machining environments : ensuring consideration to important aspects when designing line layouts." Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-25862.
Full textGavrell, Cecilia, and Ludvig Reuterswärd. "An Automated Process for Concrete Reinforcement Layout Design." Thesis, KTH, Bro- och stålbyggnad, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-231263.
Full textI takt med att fler delar av projekteringen av anläggningskonstruktioner blir digitaliserade ökar möjligheterna för att effektivisera arbetet. Utvecklandet av datorprogram som kan hantera mycket information och ge stöd till beslutsfattande ställer också krav på hanterandet av denna data för att utnyttja den fulla potentialen av ett digitaliserat arbetsflöde. Arbetsprocessen vid armering av betongkonstruktioner är tidskrävande och utförs idag ofta helt eller delvis för hand. Sådana processer bär karaktärsdrag som tyder på att de är lämpade för automatisering. Målet med studien är att undersöka problematiken kring att automatisera arbetsprocesser vid projektering av anläggningskonstruktioner med inriktning på armering av betongkonstruktioner. Specifikt, så har valet av raka armeringsjärn och dess placering i betongkonstruktioner studerats med avseende på byggbarhet och armeringsmängder. Ett datorprogram har utvecklats för att välja armeringsjärn och dess placering för ett givet behov och ett antal krav som ställs enligt Eurokod. För att hitta en möjlig lösning är problemet formulerat som en optimering av armeringsmängd och olika mått på byggbarhet. Optimeringen genomfördes med en genetisk algoritm. Resultatet från två fallstudier visar att programmet lyckades genomföra konstruktörens arbetsuppgifter och skapa lösningar som minskade mängden använd armering och antalet olika typer av armeringsjärn samtidigt som de identifierade måtten på byggbarhet främjades. Vidare visade resultatet att de identifierade byggbarhetsparametrarna spelade en viktig roll för att finna en optimal lösning. Detta indikerar att det är möjligt att automatisera denna process och att ett effektivare arbetsflöde kan erhållas.
SAMPATH, HEMANTH KUMAR. "A MODULE GENERATION ENVIRONMENT FOR MIXED-SIGNAL CIRCUITS." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1052321882.
Full textMarolt, Daniel [Verfasser], and Jörg [Akademischer Betreuer] Schulze. "Layout automation in analog IC design with formalized and nonformalized expert knowledge / Daniel Marolt ; Betreuer: Jörg Schulze." Stuttgart : Universitätsbibliothek der Universität Stuttgart, 2018. http://d-nb.info/1177800616/34.
Full textKlevbrink, Anna-Charlotta. "Evaluation of Aptivia and a Place and Route tool." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-3768.
Full textThis master thesis tells about Aptivia, what it contains and how i works (inluding a manual). As well as problems with it.
It also consists of an evaluation of a Place and Route tool, telling the discovered problems with it and ideas for solving them.There is also several different descriptions of the code that implements the Place and Route tool.
Ekebrand, Terese, and Nils Funke. "A Parameterizable Standard Cell Generator." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1712.
Full textThis master thesis describes the creation of a fully parameterizable design tool, intended for automatic generation of standard cell layouts from basic schematic information. The thesis covers general background on programs for automatic layout generation, standard cells and basics in IC design. Algorithms commonly used in various parts of such programs are presented, and the ones used to implement the tool are described in depth.
MEHTA, ADVAIT, and Mahalingam Subramanian. "Investigating the barriers to increase Levels of Automation. : A case study in pre-assembly of tap changer assembly line." Thesis, Tekniska Högskolan, Högskolan i Jönköping, JTH, Produktionsutveckling, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-47039.
Full textGiovanardi, Samuele. "Study and development of an autonomous layout entering algorithm for an industrial AGV." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021.
Find full textKameswar, Rao Vaddina. "Evaluation of A Low-power Random Access Memory Generator." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7823.
Full textIn this work, an existing RAM generator is analysed and evaluated. Some of the aspects that were considered in the evaluation are the optimization of the basic SRAM cell, how the RAM generator can be ported to newer technologys, automating the simulation process and the creation of the workflow for the energy model.
One of the main focus of this thesis work is to optimize the basic SRAM cell. The SRAM cell which is used in the RAM generator is not optimized for area nor power. A compact layout is suggested which saves a lot of area and power. The technology that is used to create the RAM generator is old and a suitable way to port it to newer technology has also been found.
To create an energy model one has to simulate a lot of memories with a lot of data. This cannot be done in the traditional way of simulating circuits using the GUI. Hence an automation procedure has been suggested which can be made to work to create energy models by simulating the memories comprehensively.
Finally, basic ground work has been initiated by creating a workflow for the creation of the energy model.
Andersson, Mikaela, Henrik Johansson, and David Lindkvist. "Design av lagerlayout - En fallstudie med inriktning på ergonomi, effektivitet och flexibilitet." Thesis, Malmö universitet, Fakulteten för kultur och samhälle (KS), 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:mau:diva-23062.
Full textThe purpose of the case study was to investigate what Airshoppen Travel Retail could take into consideration when designing their new warehouse layout. In order to carry out the study, a theoretical model was developed, the model focuses on how warehouse layout could be designed. The theoretical model analyzes the warehouse layout of two companies. The findings were then used to analyze and give recommendations to Airshoppen Travel Retail regarding what the company could take into consideration when designing their new warehouse layout. Interviews and observations showed that the development of the warehouses processes was adapted and limited by the lack of space in their warehouses. Previous research suggested that the design of a warehouse should be based on the choice of system, either manual or automatic. Inadequate design can lead to high costs, limited flexibility and reduced efficiency. An interesting aspect that the study highlighted was that the previous research mainly focuses on reducing travel distance, while the study's empirical basis showed that companies primarilyfocus on decreasing picking errors and increasing productivity. The results of the study were presented as recommendations to Airshoppen Travel Retail on how the company could design their new warehouse layout. The results showed the importance of choosing systems and control policies simultaneously to avoid limitations in the layout. Furthermore, with a manual system, implementation of zone picking could lead to increased efficiency. On a final note, careful calculations are required for the company to properly determine whether automation is a necessary and profitable investment.
Donati, Giulio. "Analisi di fattibilità per l'ottimizzazione della produzione di Gimco - Bucci Industries Taiwan." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2018. http://amslaurea.unibo.it/17436/.
Full textКучеренко, Ольга Костянтинівна. "Система керування процесом відділення ретурної кальцинації гідрокарбонату натрію у виробництві кальцинованої соди." Master's thesis, Київ, 2018. https://ela.kpi.ua/handle/123456789/27106.
Full textObject of development: the automation system of the returne calcination of sodium bicarbonate in the production of soda ash and in particular the automated control system (ACS) by a steam calciner (SC). The purpose of the work: the development and research of ACS SC, as well as the development of a common functional scheme of soda production, implemented on the basis of analog and discrete automation tools. Based on the processes occurring in the SC, a mathematical model of the PC was developed as an object of control of the temperature of the raw material at its output. This model describes the SC through the control channel and the channel of perturbation. The mathematical model of the SC used for the development and research of ACS SC.
Yampratoom, Ed. "Automatic layout for pedigree diagram." Thesis, Massachusetts Institute of Technology, 1991. http://hdl.handle.net/1721.1/13061.
Full textSchoon, Benjamin Durant. "Fishpaper : automatic personalized newspaper layout." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/34336.
Full textIncludes bibliographical references (leaf 48).
by Benjamin Durant Schoon.
B.S.
Chen, Zimin, and Huan Xie. "Kravbaserad layout - Algoritm för automatisk grafritning." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-205328.
Full textA prototype of an automatic graph drawing tool was designed and implemented in this thesis project. In this process various well-known and important algorithms were analyzed and evaluated. Algorithms applied in the prototype were modified and improved to fulfill FindOut’s special requirements. Besides this, a pursuit of an improvement on visualizations and performance of algorithms was conducted by studying the latest research works. Through these theoretical and empirical studies, we concluded that the Sugiyama framework is the most suitable algorithm to generate the workflow type of graph. The generated graphs are stable, readable and follows most aesthetic standards. Furthermore, force-directed algorithms were utilized to put graphs at appropriate positions. The attraction and repulsion force between sub-graphs can make the whole graph compact without overlapping, which fulfills the company’s requirement. However some of the problems, such as importing new nodes and edges, have not been perfectly resolved due to the conflict between the aesthetic and user requirements. Thus we think that a user-constraints based algorithm is suitable to be integrated into our next generation prototype. Some of the heuristics also have room for improvement. We discussed the possible solutions and suggested that a comparative study of different algorithms should be included in the future work.
Caliano, Antonio. "Automatic layout Diplomarbeit 10. März 2003 /." Zürich : ETH, Eidgenössische Technische Hochschule Zürich, Institut für Informations- und Kommunikationssysteme, 2003. http://e-collection.ethbib.ethz.ch/show?type=dipl&nr=89.
Full textSlade, Andrew John. "Automatic graph layout in software architecture." Thesis, University of Sunderland, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.429914.
Full textMekonnen, Michael. "Automatic protoboard layout from circuit schematics." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/91847.
Full textCataloged from PDF version of thesis.
Includes bibliographical references (page 101).
As an important component of the Circuits module of the first Introduction to Electrical Engineering and Computer Science course at MIT (6.01), students design and build several circuits over the course of three weeks. When working on the more intricate circuits, an unfortunately large proportion of students' lab time is spent on laying out the circuits on protoboards. This project introduces a new circuit schematic entry tool for 6.01, capable of automatically generating protoboard layouts for circuits that students may design in the course. The tool allows for students to build, analyze, and save circuit schematics through a graphical user interface and automatically generates protoboard layouts that are almost always easy to build and debug. The layout problem is solved by utilizing the A* search algorithm exactly as presented in 6.01.
by Michael Mekonnen.
M. Eng.
Závodský, Martin. "Návrh robotické buňky pro výrobu plošných dílů." Master's thesis, Vysoké učení technické v Brně. Fakulta strojního inženýrství, 2021. http://www.nusl.cz/ntk/nusl-443246.
Full textVIJAY, VIKAS. "A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1100584283.
Full textMoura, Gisell Borges. "Síntese automática do leiaute usando o ASTRAN." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/184645.
Full textThe work uses the synthesis of the layout through ASTRAN in circuits that have been optimized through the SCCG technique (Static CMOS Complex Gates) in order to achieve reductions in the number of transistors. The presented methodology allows the flexibility of using cells of any size or transistor networks in the optimized circuits. The work compares these circuits optimized by the ASTRAN method and circuits using the standard cell methodology. The synthesis flow is composed by the netlist optimization, verification / extraction and cell characterization steps. The work adapted 600nm and 180nm CMOS fabrication technologies for the ASTRAN tool from the design information of the XFAB standard cell XC06 and XC018 libraries. The synthesis of the complex cells generated is performed by the ASTRAN tool. The experiments were performed on the 180nm and 600nm technologies for a set of ITC'99 bechmarks circuits. Comparisons were made between the optimized netlist and two netlists generated for each XFAB library. A netlist covers all cells in the library and the other netlist has a restriction of cells that are considered complex (adders, multiplexers, XOR / XNOR, AOI, and OAI). The netlist with restrictions was designed with the motivation to check if a netlist with complex cells generated exclusively for the target circuit would become more beneficial in terms of reducing the number of transistors. The results for 180nm showed reductions in the best cases in the number of transistors with up to 15%, in dynamic power up to 24% and in leakage power with up to 22%. The results for 600nm showed reductions in the best cases in the number of transistors with up to 17%, in an area up to 14%, in dynamic power with up to 22%, in leakage power with up to 29%. The experiments showed that it is possible to achieve reductions in the number of transistors by combining the use of ASTRAN with the optimization technique using SCCG.
Xu, Ken. "Automatic object layout using 2D constraints and semantics." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ62976.pdf.
Full textStott, Jonathan. "Automatic Layout of Metro Maps Using Multicriteria Optimisation." Thesis, University of Kent, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.499775.
Full textMcDonald, Benjamin Thomas. "Automating the Layout of Image for Large, Shared Displays." Thesis, University of Canterbury. Computer Science and Software Engineering, 2011. http://hdl.handle.net/10092/7012.
Full textŠinkarovs, Artjoms. "Data layout types : a type-based approach to automatic data layout transformations for improved SIMD vectorisation." Thesis, Heriot-Watt University, 2015. http://hdl.handle.net/10399/2880.
Full textWatanabe, Toyohide, and Xiaoou Huang. "Automatic acquisition of layout knowledge for understanding business cards." IEEE, 1997. http://hdl.handle.net/2237/6913.
Full textPhillips, Shawn A. "Automating layout of reconfigurable subsystems for systems-on-a-chip /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5979.
Full textWu, Patrick B. "A hierarchical design automation methodology for CMOS analogue IC layouts." Thesis, University of Essex, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.397726.
Full textGuan, Bingzhong. "Automatic layout generation of static CMOS combinational cells and blocks /." Thesis, Connect to this title online; UW restricted, 1996. http://hdl.handle.net/1773/6059.
Full textRobinson, David Lyle. "Automatic Synthesis of VLSI Layout for Analog Continuous-time Filters." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4913.
Full textLazzari, Cristiano. "Transistor level automatic generation of radiation-hardened circuits." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/15506.
Full textDeep submicron (DSM) technologies have increased the challenges in circuit designs due to geometry shrinking, power supply reduction, frequency increasing and high logic density. The reliability of integrated circuits is significantly reduced as a consequence of the susceptibility to crosstalk and substrate coupling. In addition, radiation effects are also more significant because particles with low energy, without importance in older technologies, start to be a problem in DSM technologies. All these characteristics emphasize the need for new Electronic Design Automation (EDA) tools. One of the goals of this thesis is to develop EDA tools able to cope with these DSM challenges. This thesis is divided in two major contributions. The first contribution is related to the development of a new methodology able to generate optimized circuits in respect to timing and power consumption. A new design flow is proposed in which the circuit is optimized at transistor level. This methodology allows the optimization of every single transistor according to the capacitances associated to it. Different from the traditional standard cell approach, the layout is generated on demand after a transistor level optimization process. Results show an average 11% delay improvement and more than 30% power saving in comparison with the traditional design flow. The second contribution of this thesis is related with the development of techniques for radiation-hardened circuits. The Code Word State Preserving (CWSP) technique is used to apply timing redundancy into latches and flipflops. This technique presents low area overhead, but timing penalties are totally related with the glitch duration is being attenuated. Further, a new transistor sizing methodology for Single Event Transient (SET) attenuation is proposed. The sizing method is based on an analytic model. The model considers independently pull-up and pull-down blocks. Thus, only transistors directly related to the SET attenuation are sized. Results show smaller area, timing and power consumption overhead in comparison with TMR and CWSP techniques allowing the development of high frequency circuits, with lower area and power overhead.
Lefebvre, Martin C. (Martin Claude) Carleton University Dissertation Engineering Electrical. "Automatic generation of C.M.O.S. standard cell layout from logic level descriptions." Ottawa, 1986.
Find full textLazzari, Cristiano. "Automatic layout generation of static CMOS circuits targeting delay and power." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2003. http://hdl.handle.net/10183/5690.
Full textThe evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.
Kadlec, Jaroslav. "Charakterizace Kódu pro Automatické Generování Uživatelského Rozhraní." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2011. http://www.nusl.cz/ntk/nusl-261250.
Full textMeister, Tilo. "Pinzuordnungs-Algorithmen zur Optimierung der Verdrahtbarkeit beim hierarchischen Layoutentwurf." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-96764.
Full textThis work deals with the optimization of pin assignments for which an accurate routability prediction is a prerequisite. Therefore, this contribution introduces methods for routability prediction. The optimization of pin assignments, for which these methods are needed, is done after initial placement and before routing. Known methods of routability prediction are compiled, compared, and analyzed for their usability as part of the pin assignment step. These investigations lead to the development of a routability prediction method, which is adapted to the specific requirements of pin assignment. So far pin assignment of complex electronic devices has been a predominantly manual process. Hence, practical experience exists, yet, it had not been transferred to an algorithmic formulation. This contribution develops pin assignment methods in order to automate and improve pin assignment. Distinctive characteristics of the thereby developed algorithms are their usability during layout planning, their capability to integrate into a hierarchical design flow, and the consideration of differential pairs. Both aspects, routability prediction and assignment algorithms, are finally brought together by using the newly developed routability prediction to evaluate and select the assignment algorithms
Elkington, Michael Philip. "The evolution and automation of sheet prepreg layup." Thesis, University of Bristol, 2015. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.682486.
Full textSchulze, Christoph Daniel [Verfasser]. "Text in Diagrams: Challenges to and Opportunities of Automatic Layout. / Christoph Daniel Schulze." Kiel : Universitätsbibliothek Kiel, 2019. http://d-nb.info/120172709X/34.
Full textAntinori, Luca. "Approccio dichiarativo alla generazione automatica del layout per testo a fronte su piattaforma web." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2015. http://amslaurea.unibo.it/9699/.
Full textNikolaus, Ulrich, and Julia Dobroschke. "Automatic conversion of PDF-based, layout-oriented typesetting data to DAISY: potentials and limitations." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-38042.
Full textRay, William J. "Automatic layout techniques for the graphical editor in the Computer Aided Prototyping System (CAPS)." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1997. http://handle.dtic.mil/100.2/ADA341244.
Full textXia, Hongxia Carleton University Dissertation Engineering Electronics. "Transistor placement algorithm for automatic layout synthesis of CMOS/BiCMOS logic and interface circuits." Ottawa, 1993.
Find full textNikolaus, Ulrich, and Julia Dobroschke. "Automatic conversion of PDF-based, layout-oriented typesetting data to DAISY: potentials and limitations." Tagungsband zu: DAISY International Technical Conference : Barrierefreie Aufbereitung von Dokumenten, 21. - 27. September 2009, Leipzig/Germany. - Leipzig : DZB, 2009. - S. 115 - 127, 2009. https://slub.qucosa.de/id/qucosa%3A797.
Full textAspegren, Villiam. "CluStic – Automatic graph drawing with clusters." Thesis, KTH, Skolan för datavetenskap och kommunikation (CSC), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-179251.
Full textMålet med automatiserad grafritning är att utifrån en uppsättning noder och kanter hitta en layout som är visuellt tillfredställande. Ett delområde som inte utforskats nog är möjligheten till att låsa vissa komponenter i grafen som sedan inte får alterneras av grafritningsalgoritmen. En användare som exempel, strukturerar vissa delar av grafen manuellt och applicerar sedan automatisk layout av resterande element utan att förstöra den struktur som manuellt skapats. CluStic, grafritningsverktyget som skapats och utvärderats i denna masters uppsats fyller denna funktion. CluStic bevarar den interna strukturen för ett kluster genom att tilldela en högre prioritet för noder i klustret med avseende på övriga element i grafen. Efter att högprioritets element placerats tilldelas resterande element sina bäst tillgängliga positioner. Utöver detta så uppfyller CluStic några av de vanligaste estetiska mål inom grafritning: minimera antalet kantkorsningar, minimera höjden, och räta ut kanter. Metoden som används i denna master uppsatts var att först gör en inledande studie där vi undersöker fyra populära grafritnings verktyg: Cytogate, GraphDraw, Diagram.Net och GraphNet. En uppsättning grafer genereras av dessa verktyg och vi mäter hur lång tid det tar för en användare att hitta den längsta vägen i grafen. Genom denna studie konstaterar vi att Cytogate presenterade grafer med best kvalitet. Från kunskap samlad i den inledande studien utvecklar vi CluStic och utför uppsatsens huvud studie där vi jämför CluStic med avseende på Cytogate och en bas layout Breddenförst algoritm. CluStic uppnår ett visualiserings effektivitetsvärde på 1,4 vilket är en ökning jämtemot Bredden-först algoritmen (-3,8). CluStic levererar inte layouter som är mer visuellt tillfredställande än de som skapats av Cytogate som får ett visualiserings effektivitetsvärde på 1,9. CluStic tillskillnad från Cytogate bevarar den internt fixa strukturen mellan element med hög prioritet vilket gör CluStic till det bättre verktyget för grafer med statiska element.
Zarka, Nathalie. "Conception d'un système d'archivage électronique de documents numérisés : réalisation sur une machine SM90." Paris 6, 1986. http://www.theses.fr/1986PA066524.
Full text"Analog layout automation." 2012. http://library.cuhk.edu.hk/record=b5549410.
Full textIn this thesis, we will present an effective layout method for analog circuits. We consider symmetry constraint, common centroid constraint, device merging and device clustering during the placement step. Symmetric routing will then be performed. In order to have successful routing, we will perform analog-based routability-driven adjustment during the placement process, taking into account for analog circuits that wires are not preferred to be layout on top of active devices. All these concepts were put together in our tool. Experimental results show that we can generate quality analog layout within minutes of time that passes the design rule check, layout-schematic verification and the simulation results are comparable to those of manual design, while a manual design will take a designer a couple of days to generate.
Xiao, Linfu.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2012.
Includes bibliographical references (leaves 146-154).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract --- p.i
Acknowledgement --- p.ii
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Analog Layout Problem --- p.2
Chapter 1.1.1 --- Analog Circuit Design Flow --- p.3
Chapter 1.1.2 --- An Example: μA741 Operational Amplifier --- p.5
Chapter 1.1.3 --- Analog Layout Problem --- p.6
Chapter 1.2 --- Thesis Contribution and Organization --- p.8
Chapter 2 --- Background --- p.11
Chapter 2.1 --- Analog Layout Basics --- p.11
Chapter 2.1.1 --- Parasitic Effects --- p.12
Chapter 2.1.2 --- Signal Coupling Effects --- p.13
Chapter 2.1.3 --- Process Variation Effects --- p.15
Chapter 2.2 --- Previous Analog Layout Automation Tools --- p.18
Chapter 2.3 --- Previous Analog Layout Automation Approaches --- p.22
Chapter 2.3.1 --- Device Generation --- p.23
Chapter 2.3.2 --- Analog Placement --- p.25
Chapter 2.3.3 --- Analog Routing --- p.37
Chapter 3 --- System Overview --- p.45
Chapter 3.1 --- System Flow Map --- p.45
Chapter 3.1.1 --- Device Generation --- p.46
Chapter 3.1.2 --- Analog Placement --- p.49
Chapter 3.1.3 --- Analog Routing --- p.51
Chapter 4 --- Analog Placement --- p.53
Chapter 4.1 --- Introduction --- p.53
Chapter 4.2 --- Symmetric Feasible Conditions on Sequence Pair --- p.55
Chapter 4.2.1 --- Properties of Sequence Pair --- p.56
Chapter 4.2.2 --- Symmetric Feasible Conditions --- p.58
Chapter 4.3 --- Common Centroid Grid Placement --- p.69
Chapter 4.3.1 --- Grid Placement Representation --- p.70
Chapter 4.3.2 --- Common Centroid Feasible Conditions in Grid Sequence --- p.71
Chapter 4.4 --- Methodology --- p.73
Chapter 4.4.1 --- Handling Symmetry Constraints --- p.74
Chapter 4.4.2 --- Device Merging --- p.75
Chapter 4.4.3 --- Device Clustering --- p.77
Chapter 4.4.4 --- Enhanced Common Centroid Placement --- p.78
Chapter 4.4.5 --- Placement Adjustment for Symmetry Groups --- p.82
Chapter 4.4.6 --- Congestion Aware Placement Expansion --- p.86
Chapter 4.4.7 --- Types of Moves --- p.87
Chapter 4.4.8 --- Annealing Schedule and Cost Function --- p.88
Chapter 5 --- Analog Routing --- p.90
Chapter 5.1 --- Introduction --- p.90
Chapter 5.2 --- Methodology --- p.91
Chapter 5.2.1 --- Symmetry Routing --- p.94
Chapter 5.2.2 --- Practical Concerns --- p.97
Chapter 6 --- Layer Assignment --- p.106
Chapter 6.1 --- Introduction --- p.106
Chapter 6.1.1 --- Problem Formulation --- p.108
Chapter 6.1.2 --- Previous Works --- p.109
Chapter 6.1.3 --- Background --- p.111
Chapter 6.2 --- Methodology --- p.114
Chapter 6.2.1 --- Global Conflict-Continuation Graph Construction --- p.114
Chapter 6.2.2 --- The Modified Two-layer Layer Assignment Scheme --- p.116
Chapter 6.2.3 --- Stacked Via Problem and Crosstalk --- p.120
Chapter 6.2.4 --- Max-Cut for planar graph --- p.121
Chapter 7 --- Experimental Results --- p.128
Chapter 7.1 --- Results of Analog Placement --- p.129
Chapter 7.2 --- Results of Layer Assignment --- p.133
Chapter 7.3 --- Simulation Results --- p.134
Bibliography --- p.136
Hsu, Chun-Chen, and 許鈞程. "CMOS Analog Circuit Layout Design Automation." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/62541285242114704365.
Full text國立成功大學
電機工程學系碩博士班
91
Layout design is a very important step in the analog CMOS IC design flow. Good layout quality should feature low susceptibility to digital noise and low sensitivity to process variation. It has historically been a time-consuming, manual task. The fast growth of complexity of VLSI systems and recent advances in System-On-Chip (SOC) developments, make it necessary to have powerful Computer-Aided-Design (CAD) tools to speed up the design process. This issue is especially important for analog circuit layout design. In this thesis, we present a tool to automate analog layout design with analog basic considerations (matching, symmetry, and noise coupling). It covers from device level module generation to block level placement and routing. Fist, we provide a module generator to transfer partitioned netlists to physical layout with matching consideration. Placement tool then places all cells with symmetric, wire length, and area constraints. Obstacle-avoiding shortest finding algorithm is used for our basic routing algorithm and we propose an approach to avoiding noise coupling between noisy and sensitive nets. According to experimental results, our tool can handle analog circuit layout with user specified constraints in the reasonable time and make analog layout design more efficient.