Journal articles: 'Kintex-7'

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Ye, Y., H. Li, J. Li, and G. Gong. "Sub-nanosecond synchronization implementation in pure Xilinx Kintex-7 FPGA." Journal of Instrumentation 16, no. 11 (November 1, 2021): P11036. http://dx.doi.org/10.1088/1748-0221/16/11/p11036.

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Abstract White Rabbit (WR) provides high-performance synchronization with sub-nanosecond accuracy and picoseconds precision, and it has been included in the new High Accuracy Default PTP Profile in the IEEE 1588-2019. As an open-source project, WR Precision Time Protocol (WR-PTP) core has been implemented in different FPGA platforms with dedicated clock circuits. This paper presents a novel approach to achieve the WR function in Xilinx Kintex-7 FPGA depending on the on-chip resource. This approach could achieve sub-nanosecond accuracy and tens of picoseconds precision, simplifying WR devices' hardware design and making it possible to port the WR PTP core to many mature hardware platforms.

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Pandey, Bishwajeet, Geetam S. Tomar, Rajina R. Mohamed, D. M. Akbar Hussain, and Amit Kant Pandit. "Energy Efficient Design on 16 nm Ultrascale Plus Architecture Using Static Probability and Toggle Rate." Journal of Computational and Theoretical Nanoscience 17, no. 11 (November 1, 2020): 5122–24. http://dx.doi.org/10.1166/jctn.2020.9351.

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Scientists in 2010 were using a 40 nanometer Process based FPGA called Virtex-6 and 45 nm Process Technology based FPGA called Spartan-6. After 2010, researchers shifted their focus towards 28 nm technology based 7 series FPGA (Artix-7, Kintex-7, and Virtex-7) due to their intrinsic capability of low power consumption than both 40 nm and 45 nm technology based FPGA. In December, 2013, Xilinx introduced the 20 nm process technology based UltraScale series: Virtex UltraScale and Kintex UltraScale families. But now in 2020, researchers are using 16 nm technology based UltraScale+ FPGA. In our work, we are also using 16 nm technology based UltraScale+ FPGA for implementing our memory using VIVADO 2018.3 hardware programming tool and Verilog Hardware Description Language. There is 49.42%, 25.28% saving in design power on UltraScale+ FPGA when we minimize static probabilities to 0.1 and 0.2 respectively.

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Rashid, Muhammad, Sajjad Shaukat Jamal, Sikandar Zulqarnain Khan, Adel R. Alharbi, Amer Aljaedi, and Malik Imran. "Elliptic-Curve Crypto Processor for RFID Applications." Applied Sciences 11, no. 15 (July 31, 2021): 7079. http://dx.doi.org/10.3390/app11157079.

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This work presents an Elliptic-curve Point Multiplication (ECP) architecture with a focus on low latency and low area for radio-frequency-identification (RFID) applications over GF(2163). To achieve low latency, we have reduced the clock cycles by using: (i) three-shift buffers in the datapath to load Elliptic-curve parameters as well as an initial point, (ii) the identical size of input/output interfaces in all building blocks of the architecture. The low area is preserved by using the same hardware resources of squaring and multiplication for inversion computation. Finally, an efficient controller is used to control the inferred logic. The proposed ECP architecture is modeled in Verilog and the synthesis results are given on three different 7-series FPGA (Field Programmable Gate Array) devices, i.e., Kintex-7, Artix-7, and Virtex-7. The performance of the architecture is provided with the integration of a schoolbook multiplier (implemented with two different logic styles, i.e., combinational and sequential). On Kintex-7, the combinational implementation style of a schoolbook multiplier results in power-optimized, i.e., 161 μW, values with an expense of (i) hardware resources, i.e., 3561 look-up-tables and 1527 flip-flops, (ii) clock frequency, i.e., 227 MHz, and (iii) latency, i.e., 11.57 μs. On the same Kintex-7 device, the sequential implementation style of a schoolbook multiplier provides, (i) 2.88 μs latency, (ii) 1786 look-up-tables and 1855 flip-flops, (iii) 647 μW power, and (iv) 909 MHz clock frequency. Therefore, the reported area, latency and power results make the proposed ECP architecture well-suited for RFID applications.

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Abu Al-Haija, Qasem, and Sharifah M. S. Ahmad. "Fast Radix-2 Sequential Multiplier Using Kintex-7 FPGA Chip Family." Open Cybernetics & Systemics Journal 12, no. 1 (March 9, 2018): 30–41. http://dx.doi.org/10.2174/1874110x01812010030.

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Wang, Zibo, Wei Chen, Zhibin Yao, Fengqi Zhang, Yinhong Luo, Xiaobin Tang, Xiaoqiang Guo, Lili Ding, and Cong Peng. "Proton-induced single-event effects on 28 nm Kintex-7 FPGA." Microelectronics Reliability 107 (April 2020): 113594. http://dx.doi.org/10.1016/j.microrel.2020.113594.

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Sano, Y., Y. Horii, M. Ikeno, O. Sasaki, M. Tomoto, and T. Uchida. "Subnanosecond time-to-digital converter implemented in a Kintex-7 FPGA." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 874 (December 2017): 50–56. http://dx.doi.org/10.1016/j.nima.2017.08.038.

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Rahman, Atiqur. "Thermal Aware Power Efficient Frame Buffer Design on Kintex-7 FPGA." Gyancity Journal of Engineering and Technology 1, no. 1 (January 1, 2015): 29–39. http://dx.doi.org/10.21058/gjet.2015.1104.

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Rashid, Muhammad, Harish Kumar, Sikandar Zulqarnain Khan, Ismail Bahkali, Ahmed Alhomoud, and Zahid Mehmood. "Throughput/Area Optimized Architecture for Elliptic-Curve Diffie-Hellman Protocol." Applied Sciences 12, no. 8 (April 18, 2022): 4091. http://dx.doi.org/10.3390/app12084091.

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This paper presents a high-speed and low-area accelerator architecture for shared key generation using an elliptic-curve Diffie-Hellman protocol over GF(2233). Concerning the high speed, the proposed architecture employs a two-stage pipelining and a Karatsuba finite field multiplier. The use of pipelining shortens the critical path which ultimately improves the clock frequency. Similarly, the employment of a Karatsuba multiplier decreases the required number of clock cycles. Moreover, an efficient rescheduling of point addition and doubling operations avoids data hazards that appear due to pipelining. Regarding the low area, the proposed architecture computes finite field squaring and inversion operations using the hardware resources of the Karatsuba multiplier. Furthermore, two dedicated controllers are used for efficient control functionalities. The implementation results after place-and-route are provided on Virtex-7, Spartan-7, Artix-7 and Kintex-7 FPGA (field-programmable gate arrays) devices. The utilized FPGA slices are 5102 (on Virtex-7), 5634 (on Spartan-7), 5957 (on Artix-7) and 6102 (on Kintex-7). In addition to this, the time required for one shared-key generation is 31.08 (on Virtex-7), 31.68 (on Spartan-7), 31.28 (on Artix-7) and 32.51 (on Kintex-7). For performance comparison, a figure-of-merit in terms of throughputarea is utilized which shows that the proposed architecture is 963.3 and 2.76 times faster as compared to the related architectures. In terms of latency, the proposed architecture is 302.7 and 132.88 times faster when compared to the most relevant state-of-the-art approaches. The achieved results and performance comparison prove the significance of presented architecture in all those shared key generation applications which require high speed with a low area.

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Rashid, Muhammad, Mohammad Mazyad Hazzazi, Sikandar Zulqarnain Khan, Adel R. Alharbi, Asher Sajid, and Amer Aljaedi. "A Novel Low-Area Point Multiplication Architecture for Elliptic-Curve Cryptography." Electronics 10, no. 21 (November 4, 2021): 2698. http://dx.doi.org/10.3390/electronics10212698.

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This paper presents a Point Multiplication (PM) architecture of Elliptic-Curve Cryptography (ECC) over GF(2163) with a focus on the optimization of hardware resources and latency at the same time. The hardware resources are reduced with the use of a bit-serial (traditional schoolbook) multiplication method. Similarly, the latency is optimized with the reduction in a critical path using pipeline registers. To cope with the pipelining, we propose to reschedule point addition and double instructions, required for the computation of a PM operation in ECC. Subsequently, the proposed architecture over GF(2163) is modeled in Verilog Hardware Description Language (HDL) using Vivado Design Suite. To provide a fair performance evaluation, we synthesize our design on various FPGA (field-programmable gate array) devices. These FPGA devices are Virtex-4, Virtex-5, Virtex-6, Virtex-7, Spartan-7, Artix-7, and Kintex-7. The lowest area (433 FPGA slices) is achieved on Spartan-7. The highest speed is realized on Virtex-7, where our design achieves 391 MHz clock frequency and requires 416 μs for one PM computation (latency). For power, the lowest values are achieved on the Artix-7 (56 μW) and Kintex-7 (61 μW) devices. A ratio of throughput over area value of 4.89 is reached for Virtex-7. Our design outperforms most recent state-of-the-art solutions (in terms of area) with an overhead of latency.

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Du, Boyang, Luca Sterpone, Sarah Azimi, David Merodio Codinachs, Veronique Ferlet-Cavrois, Cesar Boatella Polo, Ruben Garcia Alia, Maria Kastriotou, and Pablo Fernandez-Martinez. "Ultrahigh Energy Heavy Ion Test Beam on Xilinx Kintex-7 SRAM-Based FPGA." IEEE Transactions on Nuclear Science 66, no. 7 (July 2019): 1813–19. http://dx.doi.org/10.1109/tns.2019.2915207.

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Dong, X., C. Ma, X. Zhao, X. Li, and Z. Huang. "A high resolution multi-phase clock Time-Digital Convertor implemented on Kintex-7 FPGA." Journal of Instrumentation 15, no. 11 (November 17, 2020): T11005. http://dx.doi.org/10.1088/1748-0221/15/11/t11005.

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Mhaske, Swapnil, Hojin Kee, Tai Ly, Ahsan Aziz, and Predrag Spasojevic. "FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis." International Journal of Reconfigurable Computing 2017 (2017): 1–23. http://dx.doi.org/10.1155/2017/3689308.

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We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing—digital signal processing and finite-state machines—LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.

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Shashidhara, K. S., and H. C. Srinivasaiah. "Implementation of 1024-point FFT Soft-Core to Characterize Power and Resource Parameters in Artix-7, Kintex-7, Virtex-7, and Zynq-7000 FPGAs." European Journal of Engineering Research and Science 4, no. 9 (September 16, 2019): 81–88. http://dx.doi.org/10.24018/ejers.2019.4.9.1515.

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This Paper presents implementation of 1024-point Fast Fourier Transform (FFT). The MatLab simulink environment approach is used to implement the complex 1024-point FFT. The FFT is implemented on different FPGAs such as the following four: Artix-7, Kintex-7, Virtex-7, and Zynq-7000. The comparative study on power and resource consumption has been carried out as design parameters of prime concern. The results show that Artix-7 FPGA consumes less power of 3.402W when compared with its contemporary devices, mentioned above. The resource consumption remains same across all the devices. The resource estimation on each FPGA is carried on and its results are presented for 1024-point FFT function implementation. This Comprehensive analysis provides a deep insight with respect to power and resources. The synthesis and implementation results such as RTL Schematic, I/O Planning, and Floor Planning are generated and analyzed for all the above devices.

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Shashidhara, K. S., and H. C. Srinivasaiah. "Implementation of 1024-point FFT Soft-Core to Characterize Power and Resource Parameters in Artix-7, Kintex-7, Virtex-7, and Zynq-7000 FPGAs." European Journal of Engineering and Technology Research 4, no. 9 (September 16, 2019): 81–88. http://dx.doi.org/10.24018/ejeng.2019.4.9.1515.

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This Paper presents implementation of 1024-point Fast Fourier Transform (FFT). The MatLab simulink environment approach is used to implement the complex 1024-point FFT. The FFT is implemented on different FPGAs such as the following four: Artix-7, Kintex-7, Virtex-7, and Zynq-7000. The comparative study on power and resource consumption has been carried out as design parameters of prime concern. The results show that Artix-7 FPGA consumes less power of 3.402W when compared with its contemporary devices, mentioned above. The resource consumption remains same across all the devices. The resource estimation on each FPGA is carried on and its results are presented for 1024-point FFT function implementation. This Comprehensive analysis provides a deep insight with respect to power and resources. The synthesis and implementation results such as RTL Schematic, I/O Planning, and Floor Planning are generated and analyzed for all the above devices.

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Zhang, Jianfeng, Yonggang Wang, and Zhengqi Song. "A ring-oscillator based multi-mode time-to-digital converter on Xilinx Kintex-7 FPGA." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 1011 (September 2021): 165578. http://dx.doi.org/10.1016/j.nima.2021.165578.

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Wang, Zibo, Wei Chen, Zhibin Yao, Fengqi Zhang, Yinhong Luo, Xiaobin Tang, Cong Peng, Lili Ding, and Xiaoqiang Guo. "Analyzing single event upset on Kintex-7 Field-Programmable-Gate-Array with random fault injection method." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 966 (June 2020): 163866. http://dx.doi.org/10.1016/j.nima.2020.163866.

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Kuang, Jie, Yonggang Wang, Qiang Cao, and Chong Liu. "Implementation of a high precision multi-measurement time-to-digital convertor on a Kintex-7 FPGA." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 891 (May 2018): 37–41. http://dx.doi.org/10.1016/j.nima.2018.02.064.

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Wirthlin, M. J., H. Takai, and A. Harding. "Soft error rate estimations of the Kintex-7 FPGA within the ATLAS Liquid Argon (LAr) Calorimeter." Journal of Instrumentation 9, no. 01 (January 16, 2014): C01025. http://dx.doi.org/10.1088/1748-0221/9/01/c01025.

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Bani-Hani, Raed, Khaldoon Mhaidat, and Salah Harb. "Very Compact and Efficient 32-Bit AES Core Design Using FPGAs for Small-Footprint Low-Power Embedded Applications." Journal of Circuits, Systems and Computers 25, no. 07 (April 22, 2016): 1650080. http://dx.doi.org/10.1142/s0218126616500808.

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In this paper, a very compact and efficient 32-bit FPGA design for the Advanced Encryption Standard (AES) algorithm is presented. The design is very well suited for small foot-print low-power embedded applications. The design is validated and synthesized using the Xilinx ISE Design Suite. To the best of our knowledge, our design is the most efficient in terms of throughput to area ratio and requires the smallest number of lookup tables (LUTs), logic slices, and registers. It also achieves the highest throughput among designs that do not use DSPs. It is also very power-efficient; it can process more than 10 Gbps/W on Kintex-7 FPGA.

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Zhou, Yuzhi, Xi Jin, and Tianqi Wang. "FPGA Implementation of A∗ Algorithm for Real-Time Path Planning." International Journal of Reconfigurable Computing 2020 (August 17, 2020): 1–11. http://dx.doi.org/10.1155/2020/8896386.

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The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list. To achieve real-time path-planning performance, a hardware accelerator’s architecture called A∗ accelerator has been designed and implemented in field programmable gate array (FPGA). The specially designed 8-port cache and OPEN list array are introduced to tackle the calculation bottleneck. The system-on-a-chip (SOC) design is implemented in Xilinx Kintex-7 FPGA to evaluate A∗ accelerator. Experiments show that the hardware accelerator achieves 37–75 times performance enhancement relative to software implementation. It is suitable for real-time path-planning applications.

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Mosleh, Mahmood Farhan, Fadhil Sahib Hasan, and Ruaa Majeed Azeez. "Design and implementation of log domain decoder." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (April 1, 2020): 1454. http://dx.doi.org/10.11591/ijece.v10i2.pp1454-1468.

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Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex 7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs high data rate with very low BER.

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Wang, Yonggang, Jie Kuang, Chong Liu, and Qiang Cao. "A 3.9-ps RMS Precision Time-to-Digital Converter Using Ones-Counter Encoding Scheme in a Kintex-7 FPGA." IEEE Transactions on Nuclear Science 64, no. 10 (October 2017): 2713–18. http://dx.doi.org/10.1109/tns.2017.2746626.

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Farhan, Aumama M., and M. F. Al-Gailani. "Iris Matching Step Implementation in FPGA." Iraqi Journal of Information & Communications Technology 2, no. 1 (August 25, 2019): 26–36. http://dx.doi.org/10.31987/ijict.2.1.63.

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Iris recognition system is broadly being utilized as it has distinctive patterns that gives it a powerful strategy to distinguish between persons for identification purposes. However, this system in this implementation requires large memory capacity and high computation time. These factors make us in a challenge to find a way to run this algorithm in a hardware platform. The hardware implementation features reduce the execution time by exploiting the parallelism and pipeline. The present work addresses this issue when reducing execution time by implementing the matching step using hamming distance algorithm on the target device FPGA KINTEX 7 using Xilinx system generator. The obtained result demonstrates that the execution time has been accelerated to 1.32 ns, which is almost at least four times faster than existing works

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Deng, Bin Wei, and Chong Han Liu. "Design and Implementation of Error Simulator Based FPGA for Optical Data Link Transfer Test." Applied Mechanics and Materials 727-728 (January 2015): 951–54. http://dx.doi.org/10.4028/www.scientific.net/amm.727-728.951.

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There is the extremely high radiation in the detector of ATLAS for LHC (Large Hadron Collider). The upgrading ATLAS Liquid Argon Calorimeter readout optical data link includes on-detector (front-end) and off-detector (back-end). There are the data stream burst continuous multi-bits errors and bit slip when the high-speed data are collected and transferred under the extremely high levels of radiation environment on the front-end. The data is restored on the back-end by FPGA. The design and implementation of error simulator based a Xilinx Kintex 7 for front-end is proposed in this paper to support the design and simulation test of the decoder and encoder of LOCic. Experimental and data analysis show it is valid.

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Tabra, Yasmine M., and Bayan Mahdi Sabbar. "FPGA implementation of new LM-SPIHT colored image compression with reduced complexity and low memory requirement compatible for 5G." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 1 (March 1, 2019): 1. http://dx.doi.org/10.11591/ijres.v8.i1.pp1-13.

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<span lang="EN-US">The revolution in 5G mobile systems require changes to how image is handled. These changes are represented by the required processing time, the amount of space for uploading and downloading. In this paper, a development on WT (Wavelet Transform) along with LM-SPIHT (Listless-Modified Set Partitioning in Hierarchical tree) coding and with additional level of Runlength encoding for image compression has been proposed. The new implementation reduces the amount of data needed to be stored in several stages, also the amount of time required for processing. The compression has been implemented using VHDL (Very High Descriptive Language) on netFPGA-1G-CLM Kintex-7 board. The new implementation results show a reduction in the complexity as processing time.</span>

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Dheeb, Khadija Omran, and Bayan Sabbar. "DIFFERENT FPGA PRODUCTS BASED IMPLEMENTATION OF LTE TURBO CODE." Iraqi Journal of Information & Communications Technology 3, no. 1 (April 11, 2020): 40–51. http://dx.doi.org/10.31987/ijict.3.1.65.

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Abstract —In the long-term evolution (LTE) physical layer, using turbo code is considered as the paramount one in error-correcting coding. This paper presents an implementation of LTE turbo decoding using the Log- Maximum a posteriori (MAP) algorithm with reduced number of required cycles approximately by 75% based on serial to parallel operation. Also an improvement for this algorithm based on polynomial regression function to reduce the implementation complexity. All this system implementation design with 40 bit block size of the input using Xilinx System Generator (XSG). This system implementation in hardware to show its applicability in real time using two approaches; Hardware Co-Simulation and HDL Netlist based on three devices, Xilinx Kintex-7, Spartan-6 and Artix-7. Observe from the hardware implementation, the system become completely real time by controlled from the user using the switches on the board. Also, this system taken the resources utilization from the devices less than other works.

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Islam, S. M. Mohaiminul, Mahbub E. Noor, Bishwajeet Pandey, Tanesh Kumar, Md Atiqur Rahman, and Teerath Das. "Low Power Devnagari Unicode Checker Design Using CGVS Approach." Advanced Materials Research 984-985 (July 2014): 1282–85. http://dx.doi.org/10.4028/www.scientific.net/amr.984-985.1282.

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In this paper we have introduced a new approach called Clock Gating and Voltage Scaling (CGVS), which is the combination of two existing techniques i.e. Clock gating and Voltage Scaling. Our aim is to design a low power Devnagari Unicode Checker (DUC) using CGVS technique. This design is implemented on Kintex-7 FPGA families, XC7K70T device, -3 speed grade and FBG676 package. From our analysis, it is observed that, with the use of clock gated technique in our target circuit and with the scaling of voltage from 1.0V to 0.1V, we are achieving clock power reduction of 98.98% on 10GHz and 1THz operating frequencies. Under same voltage scaling scheme, there is 6.66%, 10.38%, 10.64% and 10.62% less reduction in IO power, when the target circuit is operating on 1GHz, 10GHz, 100GHz and 1THz operating frequencies.

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Davidson, Kyle, and Joey Bray. "Understanding Digital Radio Frequency Memory Performance in Countermeasure Design." Applied Sciences 10, no. 12 (June 15, 2020): 4123. http://dx.doi.org/10.3390/app10124123.

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This paper describes the design, implementation, and testing of a novel multi-function software defined Radio Frequency (RF) system designed for small airborne drone applications. The system was created using an inexpensive Field Programmable Gate Array (FPGA) to combine a coherent linear frequency modulated radar transmitter and receiver, with a Digital Radio Frequency Memory (DRFM) jammer for use with a common RF aperture in simultaneous operation. The system was implemented on a Xilinx Kintex-7 FPGA with a wideband analogue-to-digital/ digital-to-analogue (ADC/DAC) converter mezzanine board and tested using hardware-in-the-loop mode to validate its performance. This is the first known account of an integrated multifunction electronic attack and radar system on a single chip, capable of performing a simultaneous, not time shared, operation.

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Song, Z., Y. Wang, and J. Kuang. "A 256-channel, high throughput and precision time-to-digital converter with a decomposition encoding scheme in a Kintex-7 FPGA." Journal of Instrumentation 13, no. 05 (May 8, 2018): P05012. http://dx.doi.org/10.1088/1748-0221/13/05/p05012.

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Kwiatkowski, Paweł, Dominik Sondej, and Ryszard Szplet. "Bubble-Proof Algorithm for Wave Union TDCs." Electronics 11, no. 1 (December 22, 2021): 30. http://dx.doi.org/10.3390/electronics11010030.

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Nowadays state-of-the-art time-to-digital converters (TDCs) are commonly implemented in field-programmable gate array (FPGA) devices using different variations of the wave union method. To take full advantage of this method many design challenges need to be overcome, one of which is an efficient data encoding. In this work, we describe in detail an effective algorithm to decode raw output data from a newly designed multisampling wave union TDC. The algorithm is able to correct bubble errors and detect any number of transitions, which occur in the wave union TDC output code. This allows us to reach a mean resolution as high as 0.39 ps and a single shot precision of 2.33 ps in the Xilinx Kintex-7 FPGA chip. The presented algorithm can be used for any kind of wave union TDCs and is intended for partial hardware implementation.

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Tabra, Yasmine M., and Bayan M. Sabbar. "NEW COMPUTER GENERATED-SCMA CODEBOOK WITH MAXIMIZED EUCLIDIAN DISTANCE FOR 5G." Iraqi Journal of Information & Communications Technology 2, no. 2 (November 1, 2019): 9–24. http://dx.doi.org/10.31987/ijict.2.2.64.

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Sparse code multiple access (SCMA) is one of the Non-Orthogonal Multiple Access (NOMA) that attracts many researchers for its promising future uses in 5G systems. In this paper, a Computer Generated-Sparse Code Multiple Access (CG-SCMA) is proposed. CG-SCMA generates a complex SCMA codebook that maximizes the Minimum Euclidian Distance (MinED) of 16-point star-QAM. This codebook is generated using computer program to specify the most appropriate values for this constellation. Then Trellis Coded Modulation (TCM) is used to divide the constellation into four sub constellations to maximize MinED. The new codebook reaches MinED for four sub constellations {3.46, 2.16, 2.16, 3.46} and achieves increment over SCMA codebook based 16-point star-QAM by 10.1%. The multiplexer and de-multiplexer for proposed codebook and traditional SCAM codebook is implemented using netFPGA-1G-CML Kintex-7. it can speed up the process by 597.6 times over MATLAB simulator and decreasing BER compared to open literature codebooks.

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Mukhtar, Naila, Mohamad Mehrabi, Yinan Kong, and Ashiq Anjum. "Machine-Learning-Based Side-Channel Evaluation of Elliptic-Curve Cryptographic FPGA Processor." Applied Sciences 9, no. 1 (December 25, 2018): 64. http://dx.doi.org/10.3390/app9010064.

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Security of embedded systems is the need of the hour. A mathematically secure algorithm runs on a cryptographic chip on these systems, but secret private data can be at risk due to side-channel leakage information. This research focuses on retrieving secret-key information, by performing machine-learning-based analysis on leaked power-consumption signals, from Field Programmable Gate Array (FPGA) implementation of the elliptic-curve algorithm captured from a Kintex-7 FPGA chip while the elliptic-curve cryptography (ECC) algorithm is running on it. This paper formalizes the methodology for preparing an input dataset for further analysis using machine-learning-based techniques to classify the secret-key bits. Research results reveal how pre-processing filters improve the classification accuracy in certain cases, and show how various signal properties can provide accurate secret classification with a smaller feature dataset. The results further show the parameter tuning and the amount of time required for building the machine-learning models.

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Mohammed, Raya Kahtan, and Yoichiro UENO. "An FPGA-based Network Firewall with Expandable Rule Description." Indonesian Journal of Electrical Engineering and Computer Science 10, no. 3 (June 1, 2018): 1310. http://dx.doi.org/10.11591/ijeecs.v10.i3.pp1310-1318.

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<p>With the rapid growth of communications via the Internet, the need for an effective firewall system which has not badly affect the overall network performances has been increased. In this paper, a Field Programmable Gate Array (FPGA) -based firewall system with high performance has been implemented using Network FPGA (NetFPGA) with Xilinx Kintex-7 XC7K325T FPGA. Based on NetFPGA reference router project, a NetFPGA-based firewall system was implemented. The hardware module performs rule matching operation using content addressable memory (CAM) for higher speed data processing. To evaluate system performance, throughput, latency, and memory utilization were measured for different cases using different tools, also the number of rules that an incoming packet is subjected to was varied to get more readings using both software and hardware features. The results showed that the designed firewall system provides better performance than traditional firewalls. System throughput was doubled times of the one with Linux-Iptables firewalls.</p>

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Awaludin, Asep Muhamad, Harashta Tatimma Larasati, and Howon Kim. "High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA." Sensors 21, no. 4 (February 19, 2021): 1451. http://dx.doi.org/10.3390/s21041451.

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In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes digital signal processor (DSP) primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation for 256-bit modulus size on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020 yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

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Wang, Yonggang, Xiaoyu Zhou, Zhengqi Song, Jie Kuang, and Qiang Cao. "A 3.0-ps rms Precision 277-MSamples/s Throughput Time-to-Digital Converter Using Multi-Edge Encoding Scheme in a Kintex-7 FPGA." IEEE Transactions on Nuclear Science 66, no. 10 (October 2019): 2275–81. http://dx.doi.org/10.1109/tns.2019.2938571.

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Chervyakov, Nikolay, Pavel Lyakhov, Mikhail Babenko, Irina Lavrinenko, Maxim Deryabin, Anton Lavrinenko, Anton Nazarov, Maria Valueva, Alexander Voznesensky, and Dmitry Kaplun. "A Division Algorithm in a Redundant Residue Number System Using Fractions." Applied Sciences 10, no. 2 (January 19, 2020): 695. http://dx.doi.org/10.3390/app10020695.

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The residue number system (RNS) is widely used for data processing. However, division in the RNS is a rather complicated arithmetic operation, since it requires expensive and complex operators at each iteration, which requires a lot of hardware and time. In this paper, we propose a new modular division algorithm based on the Chinese remainder theorem (CRT) with fractional numbers, which allows using only one shift operation by one digit and subtraction in each iteration of the RNS division. The proposed approach makes it possible to replace such expensive operations as reverse conversion based on CRT, mixed radix conversion, and base extension by subtraction. Besides, we optimized the operation of determining the most significant bit of divider with a single shift operation of the modular divider. The proposed enhancements make the algorithm simpler and faster in comparison with currently known algorithms. The experimental simulation using Kintex-7 showed that the proposed method is up to 7.6 times faster than the CRT-based approach and is up to 10.1 times faster than the mixed radix conversion approach.

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Khurshid, Burhan. "LUT Based Generalized Parallel Counters for State - of - art FPGAs." Electronics ETF 21, no. 1 (July 14, 2017): 3. http://dx.doi.org/10.7251/els1721003k.

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Generalized Parallel Counters (GPCs) are frequently used in constructing high speed compressor trees. Previous work has focused on achieving efficient mapping of GPCs on FPGAs by using a combination of general Look-up table (LUT) fabric and specialized fast carry chains. The resulting structures are purely combinational and cannot be efficiently pipelined to achieve the potential FPGA performance. In this paper, we take an alternate approach and try to eliminate the fast carry chain from the GPC structure. We present a heuristic that maps GPCs on FPGAS using only general LUT fabric. The resultant GPCs are then easily re-timed by placing registers at the fan-out nodes of each LUT. We have used our heuristic on various GPCs reported in prior work. Our heuristic successfully eliminates the carry chain from the GPC structure with the same LUT count in most of the cases. Experimental results using Xilinx Kintex-7 FPGAs show a considerable reduction in critical path and dynamic power dissipation with same area utilization in most of the cases.

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Dinh, Phuong, and Minh. "Calibration of gain and timing mismatch for TI-ADCs with signals in all Nyquist zones using adaptive noise canceller." Journal of Military Science and Technology, no. 77 (February 25, 2022): 137–49. http://dx.doi.org/10.54939/1859-1043.j.mst.77.2022.137-149.

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This paper presents a novel all-digital background calibration technique for general Time-Interleaved Analog-to-Digital Converters (TIADCs). Calibration of gain and timing mismatch of TIADCs using the estimation technique is designed based on the principle of the Adaptive Noise Canceller (ANC). In this ANC, there are two stages in gain, timing mismatch estimation in which a cascade structure of the correction and estimation is proposed to guarantee that our calibration achieves high performance. Besides the first Nyquit zone, the input signal at different Nyquist zones is also experimented. It is shown through the result that our calibration performs excellently on all chosen Nyquist zones. It achieves the SNDR (Signal to Noise Ratio) and SFDR (Spurious Free Dynamic Range) improvement of 19dB and 49dB, respectively. Moreover, the synthesized design with hardware co-simulation carried on the Xilinx Kintex-7 field-programmable gate array (FPGA) platform consumes only 7.36 % of the hardware resources of the FPGA chip and reduces the mismatch tone level to -87 dB. In addition, our convergence speed of SNDR during calibration is approximately 1/3 others.

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Poudel, Bikash, Arslan Munir, Joonho Kong, and Muazzam A. Khan. "Design and Validation of Low-Power Secure and Dependable Elliptic Curve Cryptosystem." Journal of Low Power Electronics and Applications 11, no. 4 (November 12, 2021): 43. http://dx.doi.org/10.3390/jlpea11040043.

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The elliptic curve cryptosystem (ECC) has been proven to be vulnerable to non-invasive side-channel analysis attacks, such as timing, power, visible light, electromagnetic emanation, and acoustic analysis attacks. In ECC, the scalar multiplication component is considered to be highly susceptible to side-channel attacks (SCAs) because it consumes the most power and leaks the most information. In this work, we design a robust asynchronous circuit for scalar multiplication that is resistant to state-of-the-art timing, power, and fault analysis attacks. We leverage the genetic algorithm with multi-objective fitness function to generate a standard Boolean logic-based combinational circuit for scalar multiplication. We transform this circuit into a multi-threshold dual-spacer dual-rail delay-insensitive logic (MTD3L) circuit. We then design point-addition and point-doubling circuits using the same procedure. Finally, we integrate these components together into a complete secure and dependable ECC processor. We design and validate the ECC processor using Xilinx ISE 14.7 and implement it in a Xilinx Kintex-7 field-programmable gate array (FPGA).

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Liu, Chong, and Yonggang Wang. "A 128-Channel, 710 M Samples/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA." IEEE Transactions on Nuclear Science 62, no. 3 (June 2015): 773–83. http://dx.doi.org/10.1109/tns.2015.2421319.

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Song, Zhengqi, Yonggang Wang, and Jie Kuang. "Implementation of 5.3 ps RMS precision and 350 M samples/second throughput time-to-digital converters with event sampling architecture in a Kintex-7 FPGA." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 944 (November 2019): 162584. http://dx.doi.org/10.1016/j.nima.2019.162584.

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Nghia, Tran Van, Le Van Ky, Tran Minh Hai, and Le Thi Trang Linh. "EFFICIENT IMPLEMENTATION OF FPGA-BASED FORWARD ERROR CORRECTING COMBINATION AND BIT TO CELL WORD DE-MULTIPLEXER FOR A SECOND GENERATION DIGITAL TERRESTRIAL TELEVISION BROADCASTING SYSTEM." SYNCHROINFO JOURNAL 7, no. 2 (2021): 18–21. http://dx.doi.org/10.36724/2664-066x-2021-7-2-18-21.

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This article focus on the implementation of FEC part. The motivation of the design is that FEC is an effective tool to mitigate problems associated with OFDM which stem from multipath fading channel, high speed data rate. One of the key features of BCH codes is that during code design, there is a precise control over the number of symbol errors that are correctable by the code. BCH coder proccesses parralelly with high-speed operation. 8-bit parallel data input and output helps to maximize the throughput. DVB-T2 used LDPC coder, as inner codes with word length up to 64,800 bits, enabling significant proximity to Shannon limit. This encoder supports all code rates and both normal and short frames. Output of LDPC encoder is interleaved with bit interleaver. This project was fully optimized for speed and memory area, fully synchronized by using a single clock. The design was coded in VHDL, synthesized by using Xilinx ISE Design Suite 14.7. The design has been tested on development Kit NetFPGA-1G-CML of Digilent Corporation and the bit map was downloaded into Xilinx Kintex-7 XC7K325T-1FFG676, which is integrated on experimental transmitter system DVB-T2. This research product belong to program “Research of experimental testing of second generation digital terrestrial television broadcasting system DVB-T2” of Vietnamese Communications Television Development JSC.

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Mao, Xiangyu, Fei Yang, Fang Wei, Jiawen Shi, Jian Cai, and Haiwen Cai. "A Low Temperature Coefficient Time-to-Digital Converter with 1.3 ps Resolution Implemented in a 28 nm FPGA." Sensors 22, no. 6 (March 16, 2022): 2306. http://dx.doi.org/10.3390/s22062306.

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Time-to-digital converter (TDC) is the key technology to realize accurate time delay measurement in high-precision optical fiber time-frequency transmission and synchronization, optical sensing and many scientific applications. The performance of FPGA-TDC based on the carry chain is sensitive to the operating temperature. This paper presents a parallel multichain cross segmentation method, without multitime measurements, which merges multichain into an equivalent chain, achieving low temperature coefficient and maintaining high precision. The equivalent chain breaks the limit of the intrinsic cell delay of a single carry chain, improves the precision and reduces the impact of temperature variation significantly. A two-channel TDC based on parallel multichain cross segmentation method is implemented in a 28 nm fabrication process Kintex-7 FPGA. The results show that the performance of TDC is improved with the increase of the number of chains. The 10-chain TDC with 1.3 ps resolution, 4.6 ps single-shot precision performs much better than the plain TDC with 11.4 ps resolution, 8.7 ps single-shot precision. The resolution is stable with 0.0002 ps/°C temperature coefficient under an operating temperature range from 25 °C to 70 °C. Moreover, the proposed method reduces the complexity of the circuit and the resource usage.

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Wu, Chen, Mingyu Wang, Xinyuan Chu, Kun Wang, and Lei He. "Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration." ACM Transactions on Reconfigurable Technology and Systems 15, no. 1 (March 31, 2022): 1–21. http://dx.doi.org/10.1145/3474597.

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Low-precision data representation is important to reduce storage size and memory access for convolutional neural networks (CNNs). Yet, existing methods have two major limitations: (1) requiring re-training to maintain accuracy for deep CNNs and (2) needing 16-bit floating-point or 8-bit fixed-point for a good accuracy. In this article, we propose a low-precision (8-bit) floating-point (LPFP) quantization method for FPGA-based acceleration to overcome the above limitations. Without any re-training, LPFP finds an optimal 8-bit data representation with negligible top-1/top-5 accuracy loss (within 0.5%/0.3% in our experiments, respectively, and significantly better than existing methods for deep CNNs). Furthermore, we implement one 8-bit LPFP multiplication by one 4-bit multiply-adder and one 3-bit adder, and therefore implement four 8-bit LPFP multiplications using one DSP48E1 of Xilinx Kintex-7 family or DSP48E2 of Xilinx Ultrascale/Ultrascale+ family, whereas one DSP can implement only two 8-bit fixed-point multiplications. Experiments on six typical CNNs for inference show that on average, we improve throughput by over existing FPGA accelerators. Particularly for VGG16 and YOLO, compared to six recent FPGA accelerators, we improve average throughput by 3.5 and 27.5 and average throughput per DSP by 4.1 and 5 , respectively.

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Barrios, Yubal, Antonio Sánchez, Raúl Guerra, and Roberto Sarmiento. "Hardware Implementation of the CCSDS 123.0-B-2 Near-Lossless Compression Standard Following an HLS Design Methodology." Remote Sensing 13, no. 21 (October 31, 2021): 4388. http://dx.doi.org/10.3390/rs13214388.

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The increment in the use of high-resolution imaging sensors on-board satellites motivates the use of on-board image compression, mainly due to restrictions in terms of both hardware (computational and storage resources) and downlink bandwidth with the ground. This work presents a compression solution based on the CCSDS 123.0-B-2 near-lossless compression standard for multi- and hyperspectral images, which deals with the high amount of data acquired by these next-generation sensors. The proposed approach has been developed following an HLS design methodology, accelerating design time and obtaining good system performance. The compressor is comprised by two main stages, a predictor and a hybrid encoder, designed in Band-Interleaved by Line (BIL) order and optimized to achieve a trade-off between throughput and logic resources utilization. This solution has been mapped on a Xilinx Kintex UltraScale XCKU040 FPGA and targeting AVIRIS images, reaching a throughput of 12.5 MSamples/s and consuming only the 7% of LUTs and around the 14% of dedicated memory blocks available in the device. To the best of our knowledge, this is the first fully-compliant hardware implementation of the CCSDS 123.0-B-2 near-lossless compression standard available in the state of the art.

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Torres, Daniela A., Anthony Kopa, Sara C. Barron, Robert McCormick, Robert D. White, and Caprice Gray. "Characterization of Low-Inductance Microcoaxial Cables for Power Distribution." Journal of Microelectronics and Electronic Packaging 15, no. 4 (October 1, 2018): 171–78. http://dx.doi.org/10.4071/imaps.729301.

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Abstract Low-impedance microcoaxial cables have been developed to supply power to microchips. These uniquely low-inductance cables are enabled by a very thin dielectric compared with a conventional 50-Ω cable. These cables will be used in a novel packaging platform in which traditional interconnects are replaced by microscale coaxial cables. This method saves time and cost for small production volumes and custom electronics, compared with high density interconnects and silicon interposer technologies. These microcoaxial cables are designed to have minimal impedance to meet the stringent power supply requirements of today's electronics. As a concrete example, we consider a Kintex 7 Field-Programmable Gate Array (FPGA). To power this chip with interconnect lengths of 25 mm and a voltage ripple less than 30 mV, a resistance of 3.20–6.40 mΩ/mm and an inductance of 12–15 pH/mm is needed. The tight voltage ripple constraint is what makes this device challenging to design power distribution for. One cable fabricated by Draper, to achieve these power requirements, is the focus of this article. The Draper cable consists of a 127-μm Copper core, 12-μm polyesterimide dielectric layer, and 55-μm gold shield. The measured resistance per unit length at DC, inductance per unit length, capacitance per unit length, and characteristic impedance of the Draper cable are 2.0 mΩ/mm, 40 pH/mm, 118 pF/mm, and 6.56 Ω, respectively.

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Han, Mangi, and Youngmin Kim. "Efficient Implementation of Multichannel FM and T-DMB Repeater in FPGA with Automatic Gain Controller." Electronics 8, no. 5 (April 29, 2019): 482. http://dx.doi.org/10.3390/electronics8050482.

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In this study, we implemented a high-performance multichannel repeater, both for FM and T-Digital Multimedia Broadcasting (DMB) signals using a Field Programmable Gate Array (FPGA). In a system for providing services using wireless communication, a radio-shaded area is inevitably generated due to various obstacles. Thus, an electronic device that receives weak or low-level signals and retransmits them at a higher level is crucial. In addition, parallel implementation of digital filters and gain controllers is necessary for a multichannel repeater. When power level is too low or too high, the repeater is required to compensate the power level and ensure a stable signal. However, analog- and software-based repeaters are expensive and they are difficult to install. They also cannot effectively process multichannel in parallel. The proposed system exploits various digital signal-processing algorithms, which include modulation, demodulation, Cascaded Integrator Comb (CIC) filters, Finite Impulse Response (FIR) filters, Interpolated Second Ordered Polynomials (ISOP) filters, and Automatic Gain Controllers (AGCs). The newly proposed AGC is more efficient than others in terms of computation amount and throughput. The designed digital circuit was implemented by using Verilog HDL, and tested using a Xilinx Kintex 7 device. As a result, the proposed repeater can simultaneously handle 40 FM channels and 6 DMB channels in parallel. Output power level is also always maintained by the AGC.

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Ngọc. "THIẾT KẾ KHỐI TĂNG TỐC ĐỒNG BỘ DỮ LIỆU TỪ MÁY THU SỐ TRÊN NỀN TẢNG FPGA." Journal of Military Science and Technology, no. 71 (February 5, 2021): 88–97. http://dx.doi.org/10.54939/1859-1043.j.mst.71.2021.88-97.

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Hiện nay, mật độ tích hợp trên các vi mạch số đã đạt đến hàng tỷ transistor trên một chip đơn, cho phép tạo ra những thiết bị phần cứng chuyên dụng nhằm tăng tốc cho các bài toán xử lý, phân tích và tìm kiếm dữ liệu lớn. Bài toán xử lý dữ liệu lớn thu được từ các máy thu số thường gặp các vấn đề như tạp nhiễu và sai lệch pha, dẫn đến phải phân tích và sắp xếp lại chúng theo trật tự để thuận tiện cho các giai đoạn xử lý tiếp theo. Công việc này nếu thực hiện trên phần mềm thường kém hiệu quả do tốc độ xử lý không đáp ứng được yêu cầu. Bài báo đề xuất một thiết kế cho bộ tăng tốc tìm kiếm và xử lý từ luồng dữ liệu lớn nhận từ các máy thu thông tin số, sử dụng kết hợp kỹ thuật xử lý song song và phương pháp đường ống. Tiếp đó, tiến hành đánh giá các yếu tố ảnh hưởng đến tốc độ tìm kiếm và tài nguyên sử dụng để đưa ra giải pháp thiết kế tối ưu. Chúng tôi đã thực thi thiết kế trên mạch FPGA Kintex 7-XC7K325T áp dụng cho bài toán tìm kiếm song song dữ liệu có độ dài mẫu 128 bit, sử dụng tối đa 512 khối so sánh ở tần số xung nhịp 100 MHz và các kiểu điều chế PSK và QAM. Kết quả thực thi trên phần cứng nhanh gấp khoảng 945 lần so với thực thi trên phần mềm với giá trị băng thông đạt được khoảng 800 Mbps.

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Mahmood, Faisal, Märt Toots, Lars-Göran Öfverstedt, and Ulf Skoglund. "Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal." International Journal of Reconfigurable Computing 2018 (August 6, 2018): 1–17. http://dx.doi.org/10.1155/2018/1403181.

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Two-dimensional discrete Fourier transform (DFT) is an extensively used and computationally intensive algorithm, with a plethora of applications. 2D images are, in general, nonperiodic but are assumed to be periodic while calculating their DFTs. This leads to cross-shaped artifacts in the frequency domain due to spectral leakage. These artifacts can have critical consequences if the DFTs are being used for further processing, specifically for biomedical applications. In this paper we present a novel FPGA-based solution to calculate 2D DFTs with simultaneous edge artifact removal for high-performance applications. Standard approaches for removing these artifacts, using apodization functions or mirroring, either involve removing critical frequencies or necessitate a surge in computation by significantly increasing the image size. We use a periodic plus smooth decomposition-based approach that was optimized to reduce DRAM access and to decrease 1D FFT invocations. 2D FFTs on FPGAs also suffer from the so-called “intermediate storage” or “memory wall” problem, which is due to limited on-chip memory, increasingly large image sizes, and strided column-wise external memory access. We propose a “tile-hopping” memory mapping scheme that significantly improves the bandwidth of the external memory for column-wise reads and can reduce the energy consumption up to 53%. We tested our proposed optimizations on a PXIe-based Xilinx Kintex 7 FPGA system communicating with a host PC, which gives us the advantage of further expanding the design for biomedical applications such as electron microscopy and tomography. We demonstrate that our proposed optimizations can lead to 2.8× reduced FPGA and DRAM energy consumption when calculating high-throughput 4096×4096 2D FFTs with simultaneous edge artifact removal. We also used our high-performance 2D FFT implementation to accelerate filtered back-projection for reconstructing tomographic data.

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Bandura, K., A. N. Bender, J. F. Cliche, T. de Haan, M. A. Dobbs, A. J. Gilbert, S. Griffin, et al. "ICE: A Scalable, Low-Cost FPGA-Based Telescope Signal Processing and Networking System." Journal of Astronomical Instrumentation 05, no. 04 (December 2016): 1641005. http://dx.doi.org/10.1142/s2251171716410051.

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We present an overview of the ‘ICE’ hardware and software framework that implements large arrays of interconnected field-programmable gate array (FPGA)-based data acquisition, signal processing and networking nodes economically. The system was conceived for application to radio, millimeter and sub-millimeter telescope readout systems that have requirements beyond typical off-the-shelf processing systems, such as careful control of interference signals produced by the digital electronics, and clocking of all elements in the system from a single precise observatory-derived oscillator. A new generation of telescopes operating at these frequency bands and designed with a vastly increased emphasis on digital signal processing to support their detector multiplexing technology or high-bandwidth correlators — data rates exceeding a terabyte per second — are becoming common. The ICE system is built around a custom FPGA motherboard that makes use of an Xilinx Kintex-7 FPGA and ARM-based co-processor. The system is specialized for specific applications through software, firmware and custom mezzanine daughter boards that interface to the FPGA through the industry-standard FPGA mezzanine card (FMC) specifications. For high density applications, the motherboards are packaged in 16-slot crates with ICE backplanes that implement a low-cost passive full-mesh network between the motherboards in a crate, allow high bandwidth interconnection between crates and enable data offload to a computer cluster. A Python-based control software library automatically detects and operates the hardware in the array. Examples of specific telescope applications of the ICE framework are presented, namely the frequency-multiplexed bolometer readout systems used for the South Pole Telescope (SPT) and Simons Array and the digitizer, F-engine, and networking engine for the Canadian Hydrogen Intensity Mapping Experiment (CHIME) and Hydrogen Intensity and Real-time Analysis eXperiment (HIRAX) radio interferometers.

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Journal articles on the topic 'Kintex-7'

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