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Ding, Hao. "FOUR TERMINAL JUNCTION FIELD-EFFECT TRANSISTOR MODEL FOR COMPUTER-AIDED DESIGN." Doctoral diss., University of Central Florida, 2007. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3129.
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A compact model for four-terminal (independent top and bottom gates) junction field-effect transistor (JFET) is presented in this dissertation. The model describes the steady-state characteristics with a unified equation for all bias conditions that provides a high degree of accuracy and continuity of conductance, which are important for predictive analog circuit simulations. It also includes capacitance and leakage equations. A special capacitance drop-off phenomenon at the pinch-off region is studies and modeled. The operations of the junction fieldeffect transistor (JFET) with an oxide top-gate and full oxide isolation are analyzed, and a semi-physical compact model is developed. The effects of the different modes associated with the oxide top-gate on the JFET steady-state characteristics of the transistor are discussed, and a single expression applicable for the description of the JFET dc characteristics for all operation modes is derived. The model has been implemented in Verilog-A and simulated in Cadence framework for comparison to experimental data measured at Texas Instruments.Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
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Wood, Neal Graham. "Silicon carbide junction field effect transistor integrated circuits for hostile environments." Thesis, University of Newcastle upon Tyne, 2018. http://hdl.handle.net/10443/4027.
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Silicon carbide (SiC), in particular its 4H polytype, has long been recognised as an appropriate semiconductor for producing hostile environment electronics due to its wide energy band gap, large chemical bond strength and high mechanical hardness. A strong research foundation has facilitated the development of numerous sensor structures capable of operating at high temperatures and in corrosive atmospheres. Front-end electronics suitable for in situ signal conditioning are however lacking. Junction field effect transistors (JFETs) circumvent the pitfalls of contemporary alternative SiC transistor variants and have been found to operate predictably and consistently under such extreme conditions. This thesis demonstrates for the first time the capability of producing the necessary stable and high-performance interface circuits from n-channel lateral depletion-mode (NLDM) JFETs. The temperature dependence of pertinent bulk 4H–SiC material parameters relevant for describing the operation of macroscopic JFETs were initially studied. An accurate phenomenological model was developed to account for the variation of the thermal equilibrium free carrier concentrations. The position of the electrochemical potential and the distribution of free electron energies were found to change markedly when conduction band nonparabolicity, higher energy intrinsic bands and extrinsic effects were accounted for. These in turn were found to influence the determination of p-n junction contact potentials. The worst case error introduced through use of the Boltzmann approximation when applied to the channel and gate regions of the JFETs under study, having nominal doping concentrations of 1 1017 cm�3 and 2 1019 cm�3, respectively, were approximately 0:1% and 2%, respectively. A set of efficient and well behaved closed form expressions were subsequently developed for the free carrier concentrations in the framework of the Joyce- Dixon approximation (JDA) which are ideally suited for use in circuit simulations. Expressions for the electron conductively effective mass and an appropriate weighting function for the momentum relaxation time were subsequently identified. While the conductivity effective mass along the basal plane remained almost independent of temperature the non-parabolic band dispersion in the direction of principle axis introduced a temperature variation of 19% and 21% between 25 C and 400 C in the first and second conduction bands, respectively. Monolithically integrated 4H–SiC signal-level homo-epitaxial NLDM JFETs, p-n junction diodes and resistors were electrically characterised between room temperature and 400 C and their static and dynamic properties studied. Their behaviours were found to be well represented by macroscopic drift-diffusion models and were in agreement with predictions based on the bulk material properties. The intrinsic voltage gain of the fabricated JFET structures with nominal 9 μm gate length, 300nm channel depth and 250 μm gate width, under typical bias conditions, was roughly 100. As a consequence of the finite doping concentration in the buffer layer beneath the active device channel, with an experimentally determined value of approximately 3 1015 cm�3, the devices under study were found to exhibit a strong body-effect. The thermal performance of the utilised tungsten capped annealed nickel-titanium and aluminium-titanium contacts, on highly doped n- and p-type regions, respectively, were investigated and appropriate methods for their characterisation described. The lowest recorded value of specific contact resistance was 1:90(50) 10�5 cm2 with a corresponding sheet resistance of 7:89(9) 102 = . Lateral current flow through the contact side wall and the difference in sheet resistance under the contact were found to increase the value of the specific contact resistance determined from transfer length method (TLM) test structures by as much as 10% for n-type contacts. While exhibiting much larger contact resistance, the p-type contacts were found to have negligible impact on device performance due to the high impedance of the gate-channel and body-channel p-n junctions under typical operation. Physics based, Simulation Program with Integrated Circuit Emphasis (SPICE) compatible, integrated circuit (IC) consistent compact models were developed that are congruent with experimental measurements over the aforementioned range of temperature and across all essential bias levels. Most notably, a self-contained, asymmetric double-gated, non-selfaligned JFET model was developed that accurately accounts for the body-effect, voltage dependent mobility and temperature. An accurate yet efficient solver of the charge neutrality equation within each region of the device is utilised to account for incomplete ionisation of dopants and the temperature dependence of the p-n junction contact potentials. Meticulous agreement with experimental measurements was attained from a minimal number of input parameters. The modelled devices were used to simulate pertinent IC building blocks, including single stage and differential amplifiers, level-shifters and voltage buffers. The finite bodytransconductance of active load transistors were identified as a major degrading factor for the voltage gain. Practical methods to circumvent this are discussed with the aid of appropriate small-signal equivalent models. Finally, a design was presented for a two-stage 4H–SiC operational amplifier (op-amp) with direct current (DC) stability over the entire temperature range of study. Low-frequency small-signal voltage gains of 80 dB and 70 dB were achieved at 25 C and 400 C, respectively when utilising a 30V supply. A closed-loop non-inverting op-amp configuration with an ideal gain of 11 was then simulated and found to vary by just 1% between 25 C and 400 C. Such amplifiers are of great utility and form the cornerstone of numerous useful and important electronic systems.
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Blaser, Markus. "Monolithically integrated InGaAs/InP photodiode-junction field-effect transistor receivers for fiber-optic telecommunication /." [S.l.] : [s.n.], 1996. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=11998.
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Wake, D. "The development of an indium gallium arsenide junction field effect transistor for use in optical receivers." Thesis, University of Surrey, 1987. http://epubs.surrey.ac.uk/843424/.
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The objective of this work was to design and develop a high performance field effect transistor to be suitable for monolithic integration with a photodetector for use in long wavelength optical communication systems. It was decided that the most promising type of device for this application was a junction field effect transistor (JFET), fabricated using the alloy In.53Ga.47As grown epitaxially onto an InP substrate. The requirements for such a device were that it should have high transconductance, low input capacitance, and low gate leakage current (for high receiver sensitivity), and that it should have a structure which would be easily integrated monolithically with the desired type of photodetector - an In.53Ga.47As PIN-photodiode. Although this alloy semiconductor has favourable electron transport properties, at the start of this work, high performance field effect transistors had not been realised in this material. In particular, the In.53Ga.47AS FETs that had been made at that time were characterised by low transconductance. Using a device design that incorporated many novel and efficacious features, the JFET described in this work gave results which greatly surpassed all previous (and current) published results of similar devices. This device not only showed high performance, but the novel design features also enabled a simple fabrication scheme. Having developed this very high performance discrete device, the feasibility of monolithic integration with a In.53Ga.47As PIN-photodiode was demonstrated. Although the physical size and material requirements of these two devices were very different, novel design features enabled the construction of a monolithic PIN-FET combination, in which the performance of the JFET was not compromised.
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Alwardi, Milad. "Design and characterization of integrating silicon junction field-effect transistor amplifiers for operation in the temperature range 40-77 K." Diss., The University of Arizona, 1989. http://hdl.handle.net/10150/184871.
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The very low photon backgrounds to be achieved by future cryogenic astronomical telescopes present the ultimate challenge to the sensitivity of infrared detectors and associated readout electronics. Cooled silicon JFETs, operated around 70 K in transimpedance amplifiers, have shown excellent performance and stability. However, due to Johnson noise in the feedback resistor, the read noise in one second achieved by such amplifiers is about 500 electrons per second. A drastic improvement in sensitivity was demonstrated using a simple form of integrating JFET amplifiers. Therefore, the excellent performance obtained with cooled silicon JFETs has led to the investigation of their properties in the temperature range 33-77 K to explore their full potential and improve the performance of the integrating amplifier. The freezeout effect in silicon JFETs has been characterized both experimentally and theoretically using a simple analytical simulation program. The effect of variation in device parameters on the freezeout characteristic has been studied, and test results showed that an effective channel mobility must be used instead of a bulk mobility in order to simulate accurately the device current and transconductance freezeout at low temperatures. Many types of commercially available JFETs have been characterized below 77 K and measurements revealed that a balanced source follower or a common-source amplifier with active load can operate well down to 38 Kelvin with extremely low power dissipation. The open gate equivalent input noise voltage was found to be optimum below 77 K, due to a decrease in the gate leakage current, in agreement with theoretical prediction. Based on the superior performance of the balanced source follower with active load, a single channel hybrid integrating JFET amplifier with a JFET reset and a compensation capacitor was developed for operation in the temperature range 40-77 K. Read noise as low as 10 electrons in 128 seconds integration was achieved when the integrator was operated at an optimum temperature of about 55 K. Using a similar design, a 16-channel monolithic integrating amplifier array was designed and built. Preliminary test results at 77 K showed noise performance comparable to the single channel hybrid integrator.
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Liu, Wei. "Electro-thermal simulations and measurements of silicon carbide power transistors." Doctoral thesis, Stockholm, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-86.
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Purohit, Siddharth. "Compact modeling of silicon carbide (SiC) vertical junction field effect transistor (VJFET) in PSpice using Angelov model and PSpice simulation of analog circuit building blocks using SiC VJFET model." Master's thesis, Mississippi State : Mississippi State University, 2006. http://sun.library.msstate.edu/ETD-db/ETD-browse/browse.
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Guédon, Florent Dominique. "Power converters with normally-on SiC JFETs." Thesis, University of Cambridge, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.610394.
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Mohammad, Azhar. "EMERGING COMPUTING BASED NOVEL SOLUTIONS FOR DESIGN OF LOW POWER CIRCUITS." UKnowledge, 2018. https://uknowledge.uky.edu/ece_etds/125.
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The growing applications for IoT devices have caused an increase in the study of low power consuming circuit design to meet the requirement of devices to operate for various months without external power supply. Scaling down the conventional CMOS causes various complications to design due to CMOS properties, therefore various non-conventional CMOS design techniques are being proposed that overcome the limitations. This thesis focuses on some of those emerging and novel low power design technique namely Adiabatic logic and low power devices like Magnetic Tunnel Junction (MTJ) and Carbon Nanotube Field Effect transistor (CNFET). Circuits that are used for large computations (multipliers, encryption engines) that amount to maximum part of power consumption in a whole chip are designed using these novel low power techniques.
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Hamieh, Youness. "Caractérisation et modélisation du transistor JFET en SiC à haute température." Phd thesis, INSA de Lyon, 2011. http://tel.archives-ouvertes.fr/tel-00665817.
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Dans le domaine de l'électronique de puissance, les dispositifs en carbure de silicium (SiC) sont bien adaptés pour fonctionner dans des environnements à haute température, haute puissance, haute tension et haute radiation. Le carbure de silicium (SiC) est un matériau semi-conducteur à large bande d'énergie interdite. Ce matériau possède des caractéristiques en température et une tenue aux champs électriques bien supérieure à celles de silicium. Ces caractéristiques permettent des améliorations significatives dans une grande variété d'applications et de systèmes. Parmi les interrupteurs existants, le JFET en SiC est l'interrupteur le plus avancé dans son développement technologique, et il est au stade de la pré-commercialisation. Le travail réalisé au cours de cette thèse consiste à caractériser électriquement des JFET- SiC de SiCED en fonction de la température (25°C-300°C). Des mesures ont été réalisé en statique (courant-tension), en dynamique (capacité-tension) et en commutation sur charge R-L (résistive-inductives) et dans un bras d'onduleur. Un modèle multi-physique du transistor VJFET de SiCED à un canal latéral a été présenté. Le modèle a été développé en langage MAST et validé aussi bien en mode de fonctionnement statique que dynamique en utilisant le simulateur SABER. Ce modèle inclut une représentation asymétrique du canal latéral et les capacités de jonction de la structure. La validation du modèle montre une bonne concordance entre les mesures et la simulation.
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Sadik, Diane-Perle. "On Reliability of SiC Power Devices in Power Electronics." Doctoral thesis, KTH, Elkraftteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-207763.
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Silicon Carbide (SiC) is a wide-bandgap (WBG) semiconductor materialwhich has several advantages such as higher maximum electric field, lowerON-state resistance, higher switching speeds, and higher maximum allowablejunction operation temperature compared to Silicon (Si). In the 1.2 kV - 1.7kV voltage range, power devices in SiC are foreseen to replace Si Insulatedgatebipolar transistors (IGBTs) for applications targeting high efficiency,high operation temperatures and/or volume reductions. In particular, theSiC Metal-oxide semiconductor field-effect transistor (MOSFET) – which isvoltage controlled and normally-OFF – is the device of choice due to the easeof its implementation in designs using Si IGBTs.In this work the reliability of SiC devices, in particular that of the SiCMOSFET, has been investigated. First, the possibility of paralleling two discreteSiC MOSFETs is investigated and validated through static and dynamictests. Parallel-connection was found to be unproblematic. Secondly, drifts ofthe threshold voltage and forward voltage of the body diode of the SiC MOSFETare investigated through long-term tests. Also these reliability aspectswere found to be unproblematic. Thirdly, the impact of the package on thechip reliability is discussed through a modeling of the parasitic inductancesof a standard module and the impact of those inductances on the gate oxide.The model shows imbalances in stray inductances and parasitic elementsthat are problematic for high-speed switching. A long-term test on the impactof humidity on junction terminations of SiC MOSFETs dies and SiCSchottky dies encapsulated in the same standard package reveals early degradationfor some modules situated outdoors. Then, the short-circuit behaviorof three different types (bipolar junction transistor, junction field-effect transistor,and MOSFET) of 1.2 kV SiC switching devices is investigated throughexperiments and simulations. The necessity to turn OFF the device quicklyduring a fault is supported with a detailed electro-thermal analysis for eachdevice. Design guidelines towards a rugged and fast short-circuit protectionare derived. For each device, a short-circuit protection driver was designed,built and validated experimentally. The possibility of designing diode-lessconverters with SiC MOSFETs is investigated with focus on surge currenttests through the body diode. The discovered fault mechanism is the triggeringof the npn parasitic bipolar transistor. Finally, a life-cycle cost analysis(LCCA) has been performed revealing that the introduction of SiC MOSFETsin already existing IGBT designs is economically interesting. In fact,the initial investment is saved later on due to a higher efficiency. Moreover,the reliability is improved, which is beneficial from a risk-management pointof-view. The total investment over 20 years is approximately 30 % lower fora converter with SiC MOSFETs although the initial converter cost is 30 %higher.Kiselkarbid (SiC) är ett bredbandgapsmaterial (WBG) som har flera fördelar,såsom högre maximal elektrisk fältstyrka, lägre ON-state resitans, högreswitch-hastighet och högre maximalt tillåten arbetstemperatur jämförtmed kisel (Si). I spänningsområdet 1,2-1,7 kV förutses att effekthalvledarkomponenteri SiC kommer att ersätta Si Insulated-gate bipolar transistorer(IGBT:er) i tillämpningar där hög verkningsgrad, hög arbetstemperatur ellervolymreduktioner eftersträvas. Förstahandsvalet är en SiC Metal-oxidesemiconductor field-effect transistor (MOSFET) som är spänningsstyrd ochnormally-OFF, egenskaper som möjliggör enkel implementering i konstruktionersom använder Si IGBTer.I detta arbete undersöks tillförlitligheten av SiC komponenter, specielltSiC MOSFET:en. Först undersöks möjligheten att parallellkoppla tvådiskretaSiC MOSFET:ar genom statiska och dynamiska prov. Parallellkopplingbefanns vara oproblematisk. Sedan undersöks drift av tröskelspänning ochbody-diodens framspänning genom långtidsprov. Ocksådessa tillförlitlighetsaspekterbefanns vara oproblematiska. Därefter undersöks kapslingens inverkanpåchip:et genom modellering av parasitiska induktanser hos en standardmoduloch inverkan av dessa induktanser pågate-oxiden. Modellen påvisaren obalans mellan de parasitiska induktanserna, något som kan varaproblematiskt för snabb switchning. Ett långtidstest av inverkan från fuktpåkant-termineringar för SiC-MOSFET:ar och SiC-Schottky-dioder i sammastandardmodul avslöjar tidiga tecken pådegradering för vissa moduler somvarit utomhus. Därefter undersöks kortslutningsbeteende för tre typer (bipolärtransistor,junction-field-effect transistor och MOSFET) av 1.2 kV effekthalvledarswitchargenom experiment och simuleringar. Behovet att stänga avkomponenten snabbt stöds av detaljerade elektrotermiska simuleringar för allatre komponenter. Konstruktionsriktlinjer för ett robust och snabbt kortslutningsskyddtas fram. För var och en av komponenterna byggs en drivkrets medkortslutningsskydd som valideras experimentellt. Möjligheten att konstrueradiodlösa omvandlare med SiC MOSFET:ar undersöks med fokus påstötströmmargenom body-dioden. Den upptäckta felmekanismen är ett oönskat tillslagav den parasitiska npn-transistorn. Slutligen utförs en livscykelanalys(LCCA) som avslöjar att introduktionen av SiC MOSFET:ar i existerandeIGBT-konstruktioner är ekonomiskt intressant. Den initiala investeringensparas in senare pågrund av en högre verkningsgrad. Dessutom förbättrastillförlitligheten, vilket är fördelaktigt ur ett riskhanteringsperspektiv. Dentotala investeringen över 20 år är ungefär 30 % lägre för en omvandlare medSiC MOSFET:ar även om initialkostnaden är 30 % högre.
QC 20170524
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Utard, Christian. "Les oscillateurs microondes faible bruit de fond a base de mesfet gaas, tegfet gaalas et transistor bipolaire silicium : modelisation, caracterisation et comparaison." Toulouse 3, 1988. http://www.theses.fr/1988TOU30078.
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On presente une methode simplifiee de modelisation fort signal des mesfet et tegfet et transistors bipolaires. Ces trois types de transistors sont utilises dans un montage oscillateur dont les caracteristiques ont ete determines de trois facons differentes, analytique par simulation electrique temporelle et par mesures experimentales. On presente enfin une etude en bruit bf et bruit mf des transistors et des oscillateurs afin de determiner le composant le plus performant. Nous proposons trois facons de determiner le coefficient de conversion bruit bf - bruit mf, par des mesures directes; indirectes et par simulation temporelle
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Song, Shiunn Luen Steven 1960. "Characterization and design of the complementary JFET LAMBDA-DIODE SRAM." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276882.
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The LAMBDA-DIODE was invented in integrated-circuit form in 1974. There was a proposal about this device's application in memory circuits at that time. This thesis is to evaluate the circuit performance of the COMPLEMENTARY JFET LAMBDA-DIODE SRAM. It investigates the speed, power consumption and chip area of this circuit compared with the JFET CROSS COUPLED SRAM by using SPICE and breadboard simulation techniques. The results show positive signs of the Λ-DIODE's feasibility for use in VLSI static memory circuits from the chip area aspect if the parasitic capacitance of the JFET device could be minimized to reduce the power delay product.
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De, Marco Anthony John. "Maskless fabrication of junction field effect transistors via focused ion beams." College Park, Md. : University of Maryland, 2004. http://hdl.handle.net/1903/231.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2004.Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Granier, André. "Etude et réalisation d'un transistor JFET vertical silicium et son évaluation en hyperfréquence." Grenoble 1, 1993. http://www.theses.fr/1993GRE10146.
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Cette etude presente la realisation d'un transistor a effet de champ vertical a jonction (jfet) compatible avec la technologie cmos du centre national d'etudes des telecommunications de meylan. Dans un premier temps, la structure du composant est presentee: elle est derivee de celle du transistor pmos et utilise un caisson de phosphore implante a haute energie en tant que drain et un siliciure de titane autoaligne. Nous decrivons les procedures et les outils de caracterisation mis en jeu. La physique du dispositif est apprehendee. Nous analysons l'observation d'un courant de grille et de substrat induit par l'ionisation par impact dans ce transistor. Un regime particulier de fonctionnement, le regime bipolaire, est decrit. Une analyse statistique des parametres electriques demontre que les dispersions sont liees a celles de la largeur de source. L'effet avantageux de la siliciuration sur les caracteristiques electriques est mis en evidence. A l'aide de la simulation numerique, nous definissons les caracteristiques technologiques de deux types de transistor dans le cadre de la filiere cmos 0,7 m. Ils se distinguent par une dose du caisson retrograde differente. A partir de mesures statiques et dynamiques, nous donnons une evaluation de ces dispositifs. Chacun presente des performances en frequence de coupure d'environ 4 ghz, limitees par la capacite de la jonction grille-drain et de la resistance de drain, et des tensions de claquages superieures a 10 v. Ainsi, nous montrons qu'un jfet vertical peut etre developpe pour des applications de puissance hyperfrequence avec un excellent compromis cout-performance. Enfin une approche du jfet vertical realise sur une couche enterree est etudiee
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Koo, Sang-Mo. "Design and process issues of junction- and ferroelectric-field effect transistors in silicon carbide." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3526.
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In todays solid-state electronics, Si and SiO2 are thedominant materials used. However, new materials such as SiC orferroelectrics are required for some special applications sincesuperior characteristics can be achieved in electronic devices.The main objective of this work is the design, fabrication andcharacterization of different field effect transistors (FETs)including the new device structures referred to asjunction-gated metal-oxide-semiconductor FET (JMOSFET) andferroelectric-FETs (FeFET) as well as the conventionaljunction-FET (JFET).
Buried-gate JFETs with two different structures have beenfabricated in epitaxial layers of 4H-SiC using only 2- to3-mask steps. It has been shown that the trenching effectduring dry etching can induce static induction transistor(SIT)-like drain conduction for JFETs with small channelthickness (less than 0.5 micro-meter). The conduction mechanismin these JFETs is examined by the potential profiles fromtwo-dimensional numerical simulations. The trenching effect canbe reduced for JFETs using an oxide mask for dry etching withsloped etch profile (an angle of around 30o). It has also beendemonstrated that, by introducing a sacrificial oxidation (SO)step on the inductively coupled plasma (ICP)-etched surface ofSiC, the electrical properties of MOS capacitors and Ohmiccontacts can be effectively recovered after dry etch damage.The switching performance of JFETs in a test circuit has beeninvestigated with an inductive load and compared with numericaldevice simulations. A drain voltage rise/fall time of around 30ns has been observed for turn-off and turn-on. The results havebeen compared to numerical mixed-mode circuit simulations withfinite element structures.
To improve the high temperature stability and to lower theon-state resistance, we have designed the so-calledJMOSFET, which is a buried-gate JFET with anadditional MOS-gate on top. The JMOSFETs have shown thefeasibility for operation with a constant current level fromroom temperature all the way up to 300 oC by applying properbackside-gate voltage. An advantage of this device is theimproved channel transconductance (2.5 times), which resultsfrom accumulating the n-channel with the MOS gate.
In realizing ferroelectric devices above room temperatureand in severe environment, high temperature polarizationbehavior and retention of ferroelectric thin films are criticalfactors to explore. Thus SiC is one of the most attractivesemiconductor material for these applications. We have found anoptimum ferroelectric gate structure (using pulsed laserdeposition) of PZT/Al2O3/4H-SiC (large C-V memory window of 10V, low conductance<0.1 mS/cm2, tangent delta of 0.0007 at400kHz). Based on this structure, the nonvolatile operation ofFeFETs in SiC has been shown for the first timeat elevatedtemperatures. The transistor showed a memory effect from roomtemperature up to 200oC and stable transistor operation wasobserved up to 300 oC. The retention of the nonvolatile memorywas 2´104 seconds at 150 oC without applying bias on thegate.
Keywords:silicon carbide, ferroelectrics, PZT, fieldeffect transistor, FET, JFET, MOSFET, device simulation,capacitance-voltage measurements, pulsed laser deposition
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Laariedh, Farah. "Technologie d’intégration monolithique des JFET latéraux." Thesis, Lyon, INSA, 2013. http://www.theses.fr/2013ISAL0031/document.
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Le carbure de silicium (SiC) est un semi-conducteur à large bande d’énergie interdite, remarquable par ses propriétés physiques situées à mi-chemin entre le silicium et le diamant. Ceci suscite actuellement un fort intérêt industriel pour son utilisation dans la fabrication de composants susceptibles de fonctionner dans des conditions extrêmes : forte puissance et haute température. Les travaux de thèse se sont focalisés sur la levée de verrous technologiques pour réaliser des composants latéraux de type JFET (Junction Field Effect Transistor) et les intégrer monolithiquement dans des substrats SiC-4H. L’objectif est de réaliser un bras d’onduleur intégré en SiC avec deux étages commande et puissance. Dans un premier temps, nous avons entamé cette thèse par une caractérisation de deux lots de composants JFET latéraux à canaux N et P réalisés dans le cadre de deux projets ANR précédents cette thèse. De cette étude nous avons extrait plusieurs points positifs, comme celui qui concerne la tenue en tension des JFET de puissance et l’intégration monolithique des JFET basse tension. Mais, nous avons aussi mis en évidence, la nécessité d’optimiser la structure de composants et d’améliorer certaines étapes technologiques, principalement, la définition des canaux par implantation ionique, le contact ohmique et la gravure profonde. Des études approfondies pour réaliser le contact ohmique sur SiC type P et des procédés pour réaliser une gravure profonde dans le SiC ont été développés. Ces études ont permis d’obtenir une faible résistance de contact comparable à l’état de l’art mondial, d’avoir des calibres en courant plus élevés et par conséquent une meilleure modulation. Pour la gravure, un masque dur à base de silicium et nickel (NiSi), nous a permis de mettre en place un procédé original qui permet des gravures profondes du SiC et réaliser les structures intégrés des JFET. L’ensemble de ces améliorations technologiques nous a permis d’obtenir des nouveaux lots de composants JFET P et N intégrés sur la même puce, avec des meilleures performances par rapport aux précédentes réalisations, notamment avec une conduction dans les canaux 10 à 100 fois plus importante. Nous avons également obtenu une modulation du courant Ids en fonction de la tension Vgs sur un nombre très important de JFET en augmentant significativement le rendement par rapport aux lots précédentsSilicon carbide (SiC) a semiconductor is as wide band gap, notable for its physical properties located between silicon and diamond. The inherent properties of silicon carbide (SiC) high thermal conductivity, and high breakdown voltage make it a very promising material for high power, high temperature and high-frequency device applications. The thesis focused on the removal of technological barriers to achieve lateral components JFET (Junction Field Effect Transistor) and monolithically integrated in SiC-4H substrates. The objective is to realize an arm of inverter integrated there SIC with two floors command and power. Initially, we started this thesis by a characterization of two lots of components JFET with channels N and P realized during two previous ANR this thesis. In this study, we extracted several positive points, such, the breakdown voltage of the JFET power and monolithic integration of low voltage JFET. But we have also highlighted the need to optimize the structure of components and improve some technological steps, mainly the definition channels by ion implantation, the ohmic contact and deep etching. Extensive to achieve ohmic contact on SiC P type and methods for performing deep etching in SiC studies have been developed. These studies have resulted in a low resistance comparable to the state of the art world contact, having sizes in higher current and therefore a better modulation. For etching, a hard mask to silicon and nickel (NiSi) has enabled us to develop a novel method that allows deep etching of SiC JFETs achieve integrated structures. All these technological improvements allowed us to get new batches of P and N JFET integrated on the same chip components with better performance compared to previous achievements, especially with conduction channels 10 to 100 times important. We also got a modulation current Ids as a function of the voltage Vgs on a large number of JFET significantly increasing the performance compared to previous batches
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Falahi, Khalil El. "Contribution à la conception de driver en technologie CMOS SOI pour la commande de transistors JFET SiC pour un environnement de haute température." Thesis, Lyon, INSA, 2012. http://www.theses.fr/2012ISAL0056/document.
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Dans le domaine aéronautique, les systèmes électriques remplacement progressivement les systèmes de contrôle mécaniques ou hydrauliques. Les bénéfices immédiats sont la réduction de la masse embarquée et des performances accrues à condition que l’électronique supporte l’absence de système de refroidissement. Si la haute température de fonctionnement n’empêche pas d’atteindre une fiabilité suffisante, il y aura réduction des coûts opérationnels. Des étapes clefs ont été franchies en introduisant des systèmes à commande électriques dans les aéronefs en lieu et place de systèmes conventionnels : freins électriques, inverseur de poussée, vérins électriques de commandes de vol… Toutes ces avancées se sont accélérées ces dernières années grâce entre autre à l’utilisation de nouveaux matériaux semiconducteurs, dit à grand gap (SiC, GaN…), opérant à haute température et palliant ainsi une faiblesse des dispositifs classiques en silicium (Si). Des composants de puissance haute température, diode Schottky ou transistor JFET SiC, sont ainsi disponibles commercialement et peuvent supporter des ambiantes de plus de 220°C. Des modules de puissances (onduleur) à base de transistor JFET SiC ont été réalisés et validés à haute température. Finalement la partie « commande » de ces modules de puissance reste à concevoir pour les environnements sévères pour permettre leur introduction dans le module de puissance. C’est dans ce contexte de faiblesse concernant l’étage de commande rapprochée qu’a été construit le projet FNRAE COTECH, et où s’inscrivent les travaux de cette thèse, Dans un premier temps, un état de l’art sur les drivers et leurs technologies nous a permis de souligner le lien complexe entre électronique et température ainsi que le potentiel de la technologie CMOS sur Silicium sur Isolant (SOI) pour des applications hautes températures. La caractérisation en température de drivers SOI disponibles dans le commerce nous a fourni des données d’entrée sur le comportement de tels dispositifs. Ces caractérisations sont essentielles pour visualiser et interpréter l’effet de la température sur les caractéristiques du dispositif. Ces mesures mettent aussi en avant les limites pratiques des technologies employées. La partie principale de cette thèse concerne la conception et la caractérisation de blocs ou IPs pour le cœur d’un driver haute température de JFET SiC. Elle est articulée autour de deux runs SOI (TFSmart1). Les blocs développés incluent entre autres des étages de sortie et leurs buffers associés et des fonctions de protection. Les drivers ainsi constitués ont été testés sur un intervalle de température allant de -50°C à plus de 250°C sans défaillance constatée. Une fonction originale de protection des JFETs contre les courts-circuits a été démontrée. Cette fonction permet de surmonter la principale limitation de ces transistors normalement passant (Normaly-ON). Finalement, un module de bras d’onduleur a été conçu pour tester ces driver in-situIn aeronautics, electrical systems progressively replace mechanical and hydraulic control systems. If the electronics can stand the absence of cooling, the immediate advantages will be the reduction of mass, increased performances, admissible reliability and thus reduction of costs. In aircraft, some important steps have already been performed successfully when substituting standard systems by electrical control system such as electrical brakes, thrust reverser, electrical actuators for flight control… Large band gap semiconductors (SiC, GaN…) have eased the operation in high temperature over the last decade and let overcome a weakness of conventional silicon systems (Si). High temperature power components such as Schottky diodes or JFET transistors, are already commercially available for a use up to 220°C, limited by package. Moreover inverters based on SiC JFET transistors have been realized and characterized at high temperature. Finally the control part of these power systems needs to be designed for harsh environment. It is in this context of lack of integrated control part that the FNRAE COTECH project and my doctoral research have been built. Based on a state of the art about drivers, the complex link between electronic and temperature and the potentialities of CMOS Silicon-On-Insulator technology (SOI) for high temperature applications have been underlined. The characterization of commercial SOI drivers gives essential data on these systems and their behavior at high temperature. These measurements also highlight the practical limitations of SOI technologies. The main part of this manuscript concerns the design and characterization of functions or IPs for high temperature JFET SiC driver. Two SOI runs in TFSmart1 have been realized. The developed functions include the driver output stage, associated buffers and protection functions. The drivers have been tested from -50°C up to 250°C without failure under short time-range. Moreover, an original protection function has been demonstrated against the short-circuit of an inverter leg. This function allows overcoming the main limitation of the normally on JFET transistor. Finally, an inverter module has been built for in-situ test of these new drivers
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Yoo, Kyung-Dong. "Two-dimensional dopant profiling for shallow junctions by TEM and AFM." Thesis, University of Oxford, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.342122.
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Manera, Leandro Tiago 1977. "Desenvolvimento de sistemas e medida de ruído de alta e baixa frequência em dispositivos semicondutores." [s.n.], 2010. http://repositorio.unicamp.br/jspui/handle/REPOSIP/261062.
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Orientador: Peter Jurgen TatschTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
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Resumo: Este trabalho teve como objetivo a montagem de um sistema de caracterização de ruído de alta e de baixa freqüência, utilizando equipamentos disponíveis no Centro de Componentes Semicondutores da Unicamp. Foi montado um sistema para a caracterização do ruído de baixa freqüência em dispositivos semicondutores e desenvolveu-se um método para a análise da qualidade de interfaces e cálculo de cargas, utilizando o ruído 1/f. Na descrição do ruído em baixa freqüência é apresentado em detalhes todo o arranjo utilizado para a medição, além dos resultados da medida em transistores nMOS e CMOS do tipo p e do tipo n fabricados no Centro. Detalhes importantes sobre o cuidado com a medição, tais como a utilização de baterias para a alimentação dos dispositivos e o correto aterramento, também são esclarecidos. A faixa de freqüência utilizada vai de 1 Hz até 100 KHz. Como aplicação, a medida de ruído é utilizada como ferramenta de diagnóstico de dispositivos semicondutores. Resultados destas medidas também são apresentados. Foi desenvolvido também um sistema para a medição do ruído em alta freqüência. A caracterização teve como objetivo determinar o parâmetro conhecido como Figura de Ruído. Apresenta-se além da descrição do arranjo utilizado na medição, os equipamentos e a metodologia empregada. Em conjunto com as medidas de ruído também são apresentados os resultados das medidas de parâmetros de espalhamento. Para a validação do método de obtenção desse conjunto de medidas, um modelo de pequenos sinais de um transistor HBT, incluindo as fontes de ruído é proposto, e é apresentado o resultado entre a medição e a simulação. A faixa disponível para medida vai de 45 MHz até 30 GHz para os parâmetros de espalhamento e de 10 MHz até 1.6 GHz para medida de figura de ruído
Abstract: The main goal of this work is the development of a noise characterization system for high and low frequency measurements using equipments available at the Center for Semiconductor Components at Unicamp. A low noise characterization system for semiconductors was built and by means of 1/f noise measurement it was possible to investigate semiconductor interface condition and oxide traps density. Detailed information about the test set-up is presented along with noise measurement data for nMOS, p and n type CMOS transistors. There is also valuable information to careful conduct noise measurements, as using battery powered devices and accurate grounding procedures. The low noise set-up frequency range is from 1 Hz up to 100 KHz. Noise as a diagnostic tool for quality and reliability of semiconductor devices is also presented. Measurement data is also shown. A measurement set-up for high frequency noise characterization was developed. Measurements were carried out in order to determine the noise figure parameter (NF) of the HBT devices. Comprehensive information about the test set-up and equipments are provided. Noise data measurements and s-parameters are also presented. In order to validate the measurement procedure, a small signal model for HBT transistor including noise sources is presented. Comparisons between simulation and measured data are performed. The s-parameters frequency range is from 45 MHz to 30 GHz, and noise set-up frequency range is from 10 MHz up to 1.6 GHz
Doutorado
Eletrônica, Microeletrônica e Optoeletrônica
Doutor em Engenharia Elétrica
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Kooistra, Floris Berend. "Fullerenes for organic electronics." [S.l. : Groningen : s.n. ; University Library of Groningen] [Host], 2007. http://irs.ub.rug.nl/ppn/305161504.
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Peftitsis, Dimosthenis. "On Gate Drivers and Applications of Normally-ON SiC JFETs." Doctoral thesis, KTH, Elektrisk energiomvandling, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-122679.
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In this thesis, various issues regarding normally-ON silicon carbide (SiC)Junction Field-Effect Transistors (JFETs) are treated. Silicon carbide powersemiconductor devices are able to operate at higher switching frequencies,higher efficiencies, and higher temperatures compared to silicon counterparts.From a system perspective, these three advantages of silicon carbide can determinethe three possible design directions: high efficiency, high switchingfrequency, and high temperature.The structure designs of the commercially-available SiC power transistorsalong with a variety of macroscopic characteristics are presented. Apart fromthe common design and performance problems, each of these devices suffersfrom different issues and challenges which must be dealt with in order to pavethe way for mass production. Moreover, the expected characteristics of thefuture silicon carbide devices are briefly discussed. The presented investigationreveals that, from the system point-of-view, the normally-ON JFET isone of the most challenging silicon carbide devices. There are basically twoJFET designs which were proposed during the last years and they are bothconsidered.The state-of-the-art gate driver for normally-ON SiC JFETs, which wasproposed a few years ago is briefly described. Using this gate driver, theswitching performance of both Junction Field-Effect Transistor designs wasexperimentally investigated.Considering the current development state of the available normally-ONSiC JFETs, the only way to reach higher current rating is to parallel-connecteither single-chip discrete devices or to build multichip modules. Four deviceparameters as well as the stray inductances of the circuit layout might affectthe feasibility of parallel connection. The static and dynamic performance ofvarious combinations of parallel-connected normally-ON JFETs were experimentallyinvestigated using two different gate-driver configurations.A self-powered gate driver for normally-ON SiC JFETs, which is basicallya circuit solution to the “normally-ON problem” is also shown. This gatedriver is both able to turn OFF the shoot-through current during the startupprocess, while it also supplies the steady-state power to the gate-drivecircuit. From experiments, it has been shown that in a half-bridge converterconsisting of normally-ON SiC JFETs, the shoot-through current is turnedOFF within approximately 20 μs.Last but not least, the potential benefits of employing normally-ON SiCJFETs in future power electronics applications is also presented. In particular,it has been shown that using normally-ON JFETs efficiencies equal 99.8% and99.6% might be achieved for a 350 MW modular multilevel converter and a40 kVA three-phase two-level voltage source converter, respectively.Conclusions and suggestions for future work are given in the last chapterof this thesis.I denna avhandling behandlas olika aspekter av normally–ON junction–field–effect–transistorer (JFETar) baserade på kiselkarbid (SiC). Effekthalvledarkomponenteri SiC kan arbeta vid högre switchfrekvens, högre verkningsgradoch högre temperatur än motsvarigheterna i kisel. Ur ett systemperspektivkan de tre nämnda fördelarna användas i omvandlarkonstruktionen för attuppnå antingen hög verkningsgrad, hög switchfrekvens eller hög temperaturtålighet.Såväl halvledarstrukturen som de makroskopiska egenskaperna för kommersiellttillgängliga SiC–transistorer presenteras. Bortsett från de vanligakonstruktions–och prestandaproblemen lider de olika komponenterna av ettantal tillkortakommanden som måste övervinnas för att bana väg för massproduktion.Även framtida SiC–komponenter diskuteras.Ur ett systemperspektiv är normally-ON JFETen en av de mest utmanandeSiC-komponenterna. De två varianter av denna komponent som varittillgängliga de senaste åren har båda avhandlats.State–of–the–art–drivdonet för normally-ON JFETar som presenteradesför några år sedan beskrivs i korthet. Med detta drivdon undersöks switchegenskapernaför båda JFET-typerna experimentellt.Vid beaktande av det aktuella utvecklingsstadiet av de tillgängliga normally–ON JFETarna i SiC, är det möjligt att uppnå höga märkströmmar endastom ett antal single–chip–komponenter parallellkopplas eller om multichipmodulerbyggs. Fyra komponentparametrar samt strö-induktanser för kretsenkan förutses påverka parallellkopplingen. De statiska och dynamiska egenskapernaför olika kombinationer av parallellkopplade normally-ON JFETarundersöks experimentellt med två olika gate–drivdonskonfigurationer.Ett självdrivande gate-drivdon för normally-ON JFETar presenteras också.Drivdonet är en kretslösning till “normally–ON–problemet”. Detta gatedrivdonkan både stänga av kortslutningsströmmen vid uppstart och tillhandahållaströmförsörjning vid normal drift. Med hjälp av en halvbrygga medkiselkarbidbaserade normally–ON JFETar har det visats att kortslutningsströmmenkan stängas av inom cirka 20 μs.Sist, men inte minst, presenteras de potentiella fördelarna med användningenav SiC-baserade normally-ON JFETar i framtida effektelektroniskatillämpningar. Speciellt visas att verkningsgrader av 99.8% respektive 99.5%kan uppnås i fallet av en 350 MW modular multilevel converter och i en40 kVA tvånivåväxelriktare. Sista kaplitet beskriver slutsatser och föreslagetframtida arbete.
QC 20130527
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Chevalier, Florian. "Conception, fabrication et caractérisation de transistors à effet de champ haute tension en carbure de silicium et de leur diode associée." Phd thesis, INSA de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-01016687.
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Dans le contexte des transports plus électriques, les parties mécaniques tendent à être remplacées par leurs équivalents électriques plus petits. Ainsi, le composant lui-même doit supporter un environnement plus sévère et de lourdes contraintes (haute tension, haute température). Les composants silicium deviennent alors inappropriés. Depuis la commercialisation des premières diodes Schottky en 2001, le carbure de silicium est le matériau reconnu mondialement pour la fabrication de dispositifs haute tension avec une forte intégration. Sa large bande d'énergie interdite et son fort champ électrique critique permettent la conception de transistors à effet de champ avec jonction (JFET) pour les hautes tensions ainsi que les diodes associées. Les structures étudiées dépendent de nombreux paramètres, et doivent ainsi être optimisées. L'influence d'un paramètre ne pouvant être isolée, des méthodes mathématiques ont été appelées pour trouver la valeur optimale. Ceci a conduit à la mise en place d'un critère d'optimisation. Ainsi, les deux grands types de structures de JFET verticaux ont pu être analysés finement. D'une part, la recherche d'une structure atteignant les tensions les plus élevées possible a conduit à l'élaboration d'un procédé de fabrication complexe. D'autre part, un souci de simplification et de stabilisation des procédés de fabrication a permis le développement d'un composant plus simple, mais avec une limite en tension un peu plus modeste.
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LIU, JING-MENG, and 劉景萌. "GaAs P/N junction field effect transistor." Thesis, 1988. http://ndltd.ncl.edu.tw/handle/86509850216458815066.
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Liu, Chu-Kuang, and 劉莒光. "Power Trench Junction Field Effect Transistor Integrated with Schottky Barrier Diode." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/49020093428820678056.
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碩士國立交通大學
理學院碩士在職專班應用科技學程
97
Nowadays, Power MOSFETs are dominant products of switching converters in the application field of power supply. For high power conversion efficiency and high frequency operating consideration, adopting synchronous buck converter (SBC) design would meet this requirement. However, for the low-side switch device of SBC, there are still some drawback characteristics such as physical limit of on-state resistance of channel, high power loss during the dead time due to the inherent PN body diode etc. In this study, a novel structure of power trench junction field effect transistor (JFET) integrated with Schottky barrier diode (SBD) is the first time being proposed. This design provides a new alternative solution for the low side switch of synchronous buck converter. From the simulation result, we find the larger pitch size of JFET and mesa width of SBD causing higher pinch-off voltage, lower breakdown voltage of drain to source if it was under the same pinch-off voltage. On the other hand, it would result in lower specific on-resistance due to the larger channel width. There is no significant correlation between different mesa widths of Schottky diode and reverse recovery characteristics of diode. The lighter epitaxial doping concentration would get the lower pinch-off voltage. The lower resistively of epitaxial layer is in inverse proportional to breakdown voltage, but is in proportional to on-state resistance of drain to source. This novel structure is achievable for ultra high cell density, competitive on-state resistance, desirable breakdown voltage, excellent low reverse leakage level and lower forward voltage drop. The overall characteristic comparison shows it is a good candidate for switch device of DC-DC convertor application.
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Ho, Guang-Tzer, and 何光澤. "The design and fabrication of InGaAs/GaAs and AlGaAs/InGaAs heterostructure junction field effect transistor." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/63135915582187665277.
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碩士國立中央大學
電機工程學系
85
In our research,we derive an equation of the relation between the depletion width and the bias of the pn junction of heterostructure JFET to determine the threshold voltage of the device and prove it by experiments. We fabricated two sets of HJFET,one is InGaAs/GaAs JFET and the other is AlGaAs/InGaAs JFET. In the former set,we demonstrate the good device linearity of buried channel doping =1x10^18cm^-3 by experiments and 2-D simulations. And its current and transconductance are 149.4mA/mm and 146mS/mm at Vds=3V and Vgs=0.8V. The later set, we demonstrate the good device linearity of channel doping=2x10 ^18cm^-3 by experiments. And its current and transconductance are 156mA/mm and 193.4mS/mm at Vds=3V and Vgs=1V. Its gate turn-on voltage can amount to 1V,and its reverse bias current is as low as 9.78uA/mm at reverse bias=6V,that it means its leakage current is very low.Besides,we can control the gate capacitance in 2fF/um by all epitaxy process.
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Tseng, Po Yuan, and 曾柏元. "Fabrication of Graphene/Zinc Oxide Junction Field Effect Transistor with High On-off Ratio and High Mobility." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/90919428678831289348.
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碩士國立清華大學
材料科學工程學系
103
Graphene possesses excellent chemical stability, high carrier mobility, and unique optoelectrical properties at atomic level, which was considered as a promising material to replace Si in semiconductor industry. In this study, the chemical vapor deposition method was adopted to grow monolayer graphene on the electropolished Cu foil, followed by transferring the as-synthesized graphene to zinc oxide film, which was prepared by atomic layer deposition, forming graphene/zinc oxide junction field effect transistor. Graphene growth and transferring were characterized using Raman spectrum, optical microscopy; thickness and absorbance were measured using atomic force microscopy and UV-visable spectrometer, respectively. In other side, zinc oxide deposited at different temperature were also characterized using X-ray diffractometer and photoluminescence spectroscopy, investigating the effect of different growth temperature on zinc oxide. Electrical properties of the fabricated FETs were examined by a multi-probe system and the influences of irradiation of UV on electrical properties were also analyzed. The results indicate that the thickness, absorbance, and hole(electron) mobility of the graphene were 0.4-0.7 nm, 3.35%, and 4638(5470) cm2/V∙s, respectively. The current on-off ratio of hole and electron was 2.91 and 2.12, respectively. Graphene/zinc oxide junction field effect transistor was formed combining with graphene and zinc oxide film, showed high electron mobility of 670 cm2/V∙s and high current on-off ratio of 2.87 × 105.
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Hsu, Ching-Yi, and 徐慶議. "Optimization of Vertical InAs/GaSb Hetero-Junction Tunneling Field-Effect Transistors." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/nq64s2.
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博士國立交通大學
電子研究所
105
The semiconductors technology has entered 10 nanometers generation node by 2016. In the near future, the semiconductors technology will reach 7/5 nanometers generation or even move toward the 3 dimensional stacking. However, accompanying the increase of device density, the heat dissipation of the IC chip becomes a major issue. Hence the reduction of the supply voltage and suppressing the leakage current are important for sustaining the Moore’s law in the future. Meanwhile, the scaling of the transistors dimension requires the transistors to maintain the low subthreshold slope and the high ION/IOFF under low supplied voltage. Recently, several MOSFETs architectures had been proposed to push the switching characteristics close to their thermionic emission physical limitation (60 mV/dec), like finFETs and nanowire FETs. At present, finFET technology has already been applied to the advanced IC fabrication in industry. Recently, several novel transistor concepts have been proposed to further suppress the subthreshold swing to lower than 60 mV/dec, like tunneling FETs, negative capacitance FET and nano-mechanical switching. The switching mechanism of the tunneling FET is the gate-controlled band to band tunneling between source and channel. The tunneling FETs can result in very sharp switching characteristics. The tunneling barrier in tunneling FETs can cause a very low on-current level, hence the narrow bandgap materials and hetero-junction materials have been proposed as channel materials to decrease the tunneling barrier and to enhance the on-current level of tunneling FETs. Using InAs/GaSb hetero-junction with type-III near to type-II hetero-junction, a very small tunneling barrier can be achieved by modulation of the device structure. A recent study indicates that the on-current level of InAs/GaSb double gate tunneling FET can reach 752 mA/mm. Gate electrical field of vertical tunneling FETs is parallel to tunneling direction, and vertical to tunneling junction, which leads to a very good tunneling junction control. With InAs/GaSb hetero-junction, the on-current of tunneling FETs can be much improved. This dissertation will focus on the fabrication, electrical characteristics and simulation of the vertical InAs/AlSb/GaSb tunneling FETs. The insertion of AlSb layer can result in adjustable band offset between InAs/GaSb and the on-current and switching characteristics can be further improved. Experimental results show that the device has 22 µA/µm2 on-current density at VDS = 0.4 V and VGS = 0.4 V, 194 mV/decade subthreshold swing (SS) at VDS = 0.1 V with an Ion/Ioff > 10^3. This study also investigates the impact of lateral etching depth to the device performance. In addition to the transistors characteristics, we also develop the physical model to demonstrate the multi-peak negative differential resistance phenomena which were observed in the forward bias region. TCAD Sentaurus simulation is also performed in this study to optimize the vertical InAs/GaSb tunneling FETs design. It is found that some factors can degrade the switching characteristics of the vertical InAs/GaSb tunneling FET due to the tunneling onset voltage non-uniformity: (1) Fermi pinning at the exposed InAs surface makes the Fermi level pin at close to or even higher than conduction band of InAs, (2) Geometry of L-shape leads to the non-uniformity of gate to channel coupling over the junction. For the inherent coupling non-uniformity issue, the developed model suggests that the tunneling onset voltage non-uniformity can be eliminated by (1) band offset modulation and (2) coupling ratio matching. On the other hand, for the Fermi-pinning induced switching characteristics degradation, the use of dual-metal gate structure can suppress the issue.
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Li, Yuzhu. "Design, fabrication and process developments of 4H-silicon carbide TIVJFET." 2008. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17256.
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Tschumak, Elena [Verfasser]. "Cubic AlGaN/GaN hetero-junction field-effect transistors : fabrication and characterisation / von Elena Tschumak." 2010. http://d-nb.info/1003699693/34.
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Lim, Jang-Kwon. "Simulation and Electrical Evaluation of 4H-SiC Junction Field Effect Transistors and Junction Barrier Schottky Diodes with Buried Grids." Doctoral thesis, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-173340.
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Silicon carbide (SiC) has higher breakdown field strength than silicon (Si), which enables thinner and more highly doped drift layers compared to Si. Consequently, the power losses can be reduced compared to Si-based power conversion systems. Moreover, SiC allows the power conversion systems to operate at high temperatures up to 250 oC. With such expectations, SiC is considered as the material of choice for modern power semiconductor devices for high efficiencies, high temperatures, and high power densities. Besides the material benefits, the typeof the power device also plays an important role in determining the system performance. Compared to the SiC metal-oxide semiconductor field-effect transistor (MOSFET) and bipolar junction transistor (BJT), the SiC junction field-effect transistor (JFET) is a very promising power switch, being a voltage-controlled device without oxide reliability issues. Its channel iscontrolled by a p-n junction. However, the present JFETs are not optimized yet with regard to on-state resistance, controllability of threshold voltage, and Miller capacitance. In this thesis, the state-of-the-art SiC JFETs are introduced with buried-grid (BG) technology.The buried grid is formed in the channel through epitaxial growth and etching processes. Through simulation studies, the new concepts of normally-on and -off BG JFETs with 1200 V blocking capability are investigated in terms of static and dynamic characteristics. Additionally, two case studies are performed in order to evaluate total losses on the system level. These investigations can be provided to a power circuit designer for fully exploiting the benefit of power devices. Additionally, they can serve as accurate device models and guidelines considering the switching performance. The BG concept utilized for JFETs has been also used for further development of SiC junctionbarrier Schottky (JBS) diodes. Especially, this design concept gives a great impact on high temperature operation due to efficient shielding of the Schottky interface from high electric fields. By means of simulations, the device structures with implanted and epitaxial p-grid formations, respectively, are compared regarding threshold voltage, blocking voltage, and maximum electric field at the Schottky interface. The results show that the device with an epitaxial grid can be more efficient at high temperatures than that with an implanted grid. To realize this concept, the device with implanted grid was optimized using simulations, fabricated and verified through experiments. The BG JBS diode clearly shows that the leakage current is four orders of magnitude lower than that of a pure Schottky diode at an operation temperature of 175 oC and 2 to 3 orders of magnitude lower than that of commercial JBS diodes. Finally, commercialized vertical trench JFETs are evaluated both in simulations andexperiments, while it is important to determine the limits of the existing JFETs and study their performance in parallel operation. Especially, the influence of uncertain parameters of the devices and the circuit configuration on the switching performance are determined through simulations and experiments.Kiselkarbid (SiC) har en högre genombrottsfältstyrka än kisel, vilket möjliggör tunnare och mer högdopade driftområden jämfört med kisel. Följaktligen kan förlusterna reduceras jämfört med kiselbaserade omvandlarsystem. Dessutom tillåter SiC drift vid temperatures upp till 250 oC. Dessa utsikter gör att SiC anses vara halvledarmaterialet för moderna effekthalvledarkomponenter för hög verkningsgrad, hög temperature och hög kompakthet. Förutom materialegenskaperna är också komponenttypen avgörande för att bestämma systemets prestanda. Jämfört med SiC MOSFETen och bipolärtransistorn i SiC är SiC JFETen en mycket lovande component, eftersom den är spänningsstyrd och saknar tillförlitlighetsproblem med oxidskikt. Dess kanal styrs an en PNövergång. Emellertid är dagens JFETar inte optimerade med hänseende till on-state resistans, styrbarhet av tröskelspänning och Miller-kapacitans. I denna avhandling introduceras state-of-the-art SiC JFETar med buried-grid (BG) teknologi. Denna åstadkommes genom epitaxi och etsningsprocesser. Medelst simulering undersöks nya concept för normally-on och normally-off BG JFETar med blockspänningen 1200 V. Såvä statiska som dynamiska egenskper undersöks. Dessutom görs två fallstudier vad avser totalförluster på systemnivå. Dessa undersökningar kan vara värdefulla för en konstruktör för att till fullo utnyttja fördelarna av komponenterna. Dessutom kan resultaten från undersökningarna användas som komponentmodeller och anvisningar vad gäller switch-egenskaper. BG konceptet som använts för JFETar har också använts för vidareutveckling av så kallade JBS-dioder. Speciellt ger denna konstruktion stora fördelar vid höga temperature genom en effektiv skärmning av Schottkyövergången mot höga elektriska fält. Genom simuleringar har komponentstrukturer med implanterade och epitaxiella grids jämförst med hänseende till tröskelspänning, genombrottspänning och maximalt elektriskt fält vid Schottky-övergången. Resultaten visar att den epitaxiella varianten kan vara mer effektiv än den implanterade vid höga temperaturer. För att realisera detta concept optimerades en komponent med implanterat grid med hjälp av simuleringar. Denna component tillverkades sedan och verifierades genom experiment. BG JBS-dioden visar tydligt att läckströmmen är fyra storleksordningar lägre än för en ren Schottky-diod vid 175 oC, och två till tre storleksordningar lägre än för kommersiella JBS-dioder. Slutligen utvärderas kommersiella vertical trench-JFETar bade genom simuleringar och experiment, eftersom det är viktigt att bestämma gränserna för existerande JFETar och studera parallelkoppling. Speciellt studeras inverkan av obestämda parametrar och kretsens konfigurering på switchegenskaperna. Arbetet utförs bade genom simuleringar och experiment.
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Chen, Jin-Yang, and 陳妗仰. "Design and Simulation of P-channel InGaAs/GaAsSb Staggered Hetero-Junction Tunneling Field-Effect Transistors." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/pgn936.
Full textAbstract:
碩士國立中央大學
電機工程學系
106
With the progress of semiconductor science and technology, the number of metal-oxide-semiconductor field-effect transistors (MOSFETs) in integrated circuits continuely increases over the last 50 years following Moore’s Law. The rapidly increasing power consumption associated with transistor density becomes one of the major bottlenecks in the development of future integrated circuits. An intuitive approach to this problem is to lower the operation voltage and threshold voltage simultaneously. Since the channel current of MOSFETs is governed by the drift-diffusion mechanism, their subthreshold swing (S.S.) is limited to 60 mV/decade or higher at room temperature. Whereas, tunneling field-effect transistors (TFETs) is considered as a promising candidate device for low voltage and low power integrated circuits, which is based on band-to-band tunneling (BTBT) to generate current that can break through the limit of S.S. (60 mV/decade). In III-V compound semiconductors, InGaAs/GaAsSb material system allows us to modulate band lineups by changing their compositions to form staggered type heterojunction TFETs. In this study, pTFETs based on this material system is investigated using Synopsys Sentaurus TCAD tool. The effects of band alignment, doping concentration, gate position and traps at III-V/oxide interface on the electrical properties of InGaAs/GaAsSb TFETs are systematically studied. Simulation results show that there is a strong correlation between tunneling barrier (Ebeff) with on/off-currents (ION and IOFF). Higher Ebeff leads to lower ION and IOFF, while the lower Ebeff results in higher ION and IOFF. To reach high ION and low IOFF, In0.53Ga0.47As/GaAs0.51Sb0.49 TFET with a GaSb insertion layer is proposed to reduce Ebeff from 0.63 eV to 0.38 eV at the source/channel junction, which leads to an ION current equal to 24 μA/μm at VDS = - 0.3 V，VGS = - 0.5 V, while IOFF remains at 4×10-11 μA/μm at VGS = 0 V, simultaneously. To improve the device performance further and increase the switching speed, a low IOFF of In0.53Ga0.47As/GaAs0.51Sb0.49 TFET combination with a high ION of InAs/GaAs0.1Sb0.9 insertion layer is proposed. Based on this design, ION can be further enhanced to 86 μA/μm and the threshold voltage can be reduced to - 40 mV. The effects of strain introduced by lattice mismatch between GaAsSb and In0.53Ga0.47As on the device performance are also studied. A 2 % compressive strain makes ION increase to 28 μA/μm, which is equal to the ION of In0.53Ga0.47As/GaAs0.51Sb0.49 TFET with a GaSb insertion layer, and its IOFF also remains at 10-11 μA/μm.
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Cheng-KuangWang and 王澄光. "Influence of interfacial reaction at organic/metal junction on n-type pentacene-based field-effect transistors." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/36739410831670654840.
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Gupta, Rakhee. "Analog integrated circuit design using GaAs C-HFETs." Thesis, 1992. http://hdl.handle.net/1957/37042.
Full textAbstract:
Present day data processing technology requires very high speed signal processing and data conversion rates. One such application which requires high speed is switched capacitor circuits used in Sigma-Delta modulators. A major active component of switched capacitor circuits is the monolithic operational amplifier(opamp). Because of the relatively poor speed performance of the currently available silicon based technology, such high speed circuits can not be designed. GaAs technology appears to be a promising alternative technology for high speed switched capacitor circuits.
One problem with GaAs is the lack of complementary technology. Until now, most of the design of GaAs analog integrated circuits has been implemented using depletion mode n-MESFETs, where operational amplifiers and switched capacitors have been developed by various groups. This thesis develops the techniques for implementation of analog integrated circuits using complementary GaAs Heterojunction Field Effect Transistors(HFETs). Several operational amplifiers have been designed and their performance studied via simulation. The designs studied predict superior high frequency performance for C-HFETs over conventional GaAs MESFET and Silicon CMOS technology. The opamp designs are currently being implemented at Oregon State University for fabrication in the future.Graduation date: 1993
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Wu, Zhi-Cheng, and 吳治成. "Bandgap Engineering for Normally-off GaAsSb/InGaAs Hetero-junction Tunneling Field-Effect Transistors with High On-state Current." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/31815109273558924388.
Full textAbstract:
碩士國立中央大學
電機工程學系
104
Since the channel current of MOSFETs is governed by the drift-diffusion mechanism, their subthreshold swing is limited to 60 mV/decade or higher at room temperature. Whereas, tunnel field-effect transistors (TFETs), whose current conduction is based on quantum mechanical band-to-band tunneling mechanism that gives a sub-60 mV/decade subthreshold slope, have been considered a promising energy-efficient device for low voltage and low power circuits. Since the inception of this proposal, TFETs based on Si/Ge material system have been demonstrated by a few groups. However, the devices are limited by either a low on-current or a high off-current due to the unfavored bandgap and band alignment of Si/Ge. Attention is then switched to narrow bandgap III-V compounds as the aforementioned issues could be solved by band gap engineering. This study is focused on III-V TFETs, aiming at the design and analysis of a normally-off TFET with high-on current. It covers the setup of a physical model in the TCAD tool, the effects of band alignments, gate position, and doping concentration on the electrical properties of the type-II band lineup GaAsxSb1-x/InyGa1-yAs heterojunction TFETs. Our simulation indicate that although GaAsxSb1-x/InyGa1-yAs TFETs could be designed to have a small Ebeff at the hetero-interface for high-on current, their high off-state current manifest themselves unacceptable for practical use. To solve this issue, a GaAs0.51Sb0.49/InAs/In0.53Ga0.47As TFET with an InAs quantum well (QW) is proposed to reduce the Ebeff from 0.5 eV to 0.1 eV at the source/channel interface, leading to an on-state current increasing from 27 A/m to 89 A/m at VGS=VDS=0.5 V, while the IOFF still maintains on the order of 10-7 μA/μm at VGS=0 V, simultaneously. To improve the device performance further and increase noise immunity at the gate, a graded InGaAs QW is designed to replace the InAs QW in the GaAs0.51Sb0.49/In0.53Ga0.47As TFET above. On this design, a normally-off TFET with high on-state current and threshold voltage greater than 50 mV has been achieved.
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Cheng, Chih-Chieh, and 鄭致杰. "Silicon Waveguide Modulators Incorporating the Hybrid Structures of Junction Field-Effect Transistors (JFET) and p-i-n Diodes." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/15274448837494195188.
Full textAbstract:
碩士國立成功大學
微電子工程研究所碩博士班
96
We have fabricated and characterized a Si-based optical waveguide modulator working at the wavelength of 1.55 μm. It consists of a joint version of JFET and p-i-n diode structures integrated with a silicon rib waveguide on epitaxial Si wafers. Besides, the optical modulation mechanism was achieved via free carrier dispersion effect. Above all, the waveguide modulator successfully integrates the functions of optical and electronic devices altogether in a silicon substrate. The spin-on-dopant (SOD) method was utilized to define the p- and n-doped regions. The results of our experiments revealed that the devices present transistor characteristics. According to CCD images, we can observe that the light is absorbed by the plasma sitting within the optical channel. The device exhibits both the static and dynamic modulation depth of ~100% at the chosen driving conditions. In addition, a modulation depth above 95% was observed for modulation frequency up to 5 kHz.