Relevant bibliographies by topics / Junction field-effect transistor

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Junction field-effect transistor'

Author: Grafiati
Published: 4 June 2021
Last updated: 4 February 2022

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Journal articles on the topic "Junction field-effect transistor"

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Lüssem, Björn, Hans Kleemann, Daniel Kasemann, Fabian Ventsch, and Karl Leo. "Organic Junction Field-Effect Transistor." Advanced Functional Materials 24, no. 7 (October 24, 2013): 1011–16. http://dx.doi.org/10.1002/adfm.201301417.

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Chaw, Chaw Su Nandar Hlaing, and Thiri Nwe. "Analysis on Band Layer Design and J-V characteristics of Zinc Oxide Based Junction Field Effect Transistor." Journal La Multiapp 1, no. 2 (June 21, 2020): 14–21. http://dx.doi.org/10.37899/journallamultiapp.v1i2.108.

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This paper presents the band gap design and J-V characteristic curve of Zinc Oxide (ZnO) based on Junction Field Effect Transistor (JFET). The physical properties for analysis of semiconductor field effect transistor play a vital role in semiconductor measurements to obtain the high-performance devices. The main objective of this research is to design and analyse the band diagram design of semiconductor materials which are used for high performance junction field effect transistor. In this paper, the fundamental theory of semiconductors, the electrical properties analysis and bandgap design of materials for junction field effect transistor are described. Firstly, the energy bandgaps are performed based on the existing mathematical equations and the required parameters depending on the specified semiconductor material. Secondly, the J-V characteristic curves of semiconductor material are discussed in this paper. In order to achieve the current-voltage characteristic for specific junction field effect transistor, numerical values of each parameter which are included in analysis are defined and then these resultant values are predicted for the performance of junction field effect transistors. The computerized analyses have also mentioned in this paper.
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NAKAMURA, Shigeki, and Shinichi OKAMOTO. "Radiation Dosimetry with Junction Field-effect Transistor." RADIOISOTOPES 36, no. 1 (1987): 1–6. http://dx.doi.org/10.3769/radioisotopes.36.1.

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Zolper, J. C., R. J. Shul, A. G. Baca, R. G. Wilson, S. J. Pearton, and R. A. Stall. "Ion‐implanted GaN junction field effect transistor." Applied Physics Letters 68, no. 16 (April 15, 1996): 2273–75. http://dx.doi.org/10.1063/1.115882.

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Simmons, J. G., and G. W. Taylor. "New heterostructure junction field-effect transistor (HJFET)." Electronics Letters 22, no. 22 (1986): 1167. http://dx.doi.org/10.1049/el:19860799.

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Marcoux, J., J. Orchard-Webb, and J. F. Currie. "Complementary metal oxide semiconductor-compatible junction field-effect transistor characterization." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 982–86. http://dx.doi.org/10.1139/p87-156.

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We report on the fabrication and electrical characterization of a vertical junction-gate field-effect transistor (JFET) that is compatible with all complementary metal oxide semiconductor (CMOS) technologies. It can be used as a buried load for an enhancement n-channel metal oxide semiconductor field-effect transistor (n-MOSFET), replacing the p-MOSFET within the standard CMOS inverter configuration and resulting in a 40% net area economy in standard cells. To be entirely CMOS process compatible, this JFET device differs from others in the literature in that dopant concentrations in the n substrates (1014) and in the p wells (1015) are substantially lower. For integrated-circuit applications, one seeks to use the JFET with the smallest area to minimize parasitic capacitances and to maximize switching speeds. However, at these concentration levels, the dc current–voltage characteristics depend critically on the lateral dimension of the JFET's square channel. Above 10 μm, the characteristics are pentode-like and similar to those of a classic MOSFET. Below 10 μm, the channel is naturally pinched-off, and for reverse gate bias, the small JFETs are triode-like. There is also a nonreciprocity between the source and the drain when the source-to-drain voltage polarity is changed, which is due to the distance between the channel and the electrode collecting the carriers. When its gate is forward-biased, the small JFETs behave as bipolar transistors. Depending on source-to-drain voltage polarities, I–V characteristics exhibit saturation effects caused by base-widening phenomena at the JFET's drain contact.
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Das, N. C., C. Monroy, and M. Jhabvala. "Germanium junction field effect transistor for cryogenic applications." Solid-State Electronics 44, no. 6 (June 2000): 937–40. http://dx.doi.org/10.1016/s0038-1101(00)00013-7.

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Duane, Michael. "Metal–oxide–semiconductor field-effect transistor junction requirements." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 16, no. 1 (January 1998): 306. http://dx.doi.org/10.1116/1.589800.

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Gity, Farzan, P. K. Hurley, and Lida Ansari. "Schottky-Junction TMD-Based Monomaterial Field-Effect Transistor." ECS Meeting Abstracts MA2020-01, no. 10 (May 1, 2020): 860. http://dx.doi.org/10.1149/ma2020-0110860mtgabs.

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Raj, D. V. "Radiation dosimetry using junction field-effect transistor detectors." Physics in Medicine and Biology 38, no. 8 (August 1, 1993): 1165–72. http://dx.doi.org/10.1088/0031-9155/38/8/015.

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Dissertations / Theses on the topic "Junction field-effect transistor"

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Ding, Hao. "FOUR TERMINAL JUNCTION FIELD-EFFECT TRANSISTOR MODEL FOR COMPUTER-AIDED DESIGN." Doctoral diss., University of Central Florida, 2007. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3129.

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A compact model for four-terminal (independent top and bottom gates) junction field-effect transistor (JFET) is presented in this dissertation. The model describes the steady-state characteristics with a unified equation for all bias conditions that provides a high degree of accuracy and continuity of conductance, which are important for predictive analog circuit simulations. It also includes capacitance and leakage equations. A special capacitance drop-off phenomenon at the pinch-off region is studies and modeled. The operations of the junction fieldeffect transistor (JFET) with an oxide top-gate and full oxide isolation are analyzed, and a semi-physical compact model is developed. The effects of the different modes associated with the oxide top-gate on the JFET steady-state characteristics of the transistor are discussed, and a single expression applicable for the description of the JFET dc characteristics for all operation modes is derived. The model has been implemented in Verilog-A and simulated in Cadence framework for comparison to experimental data measured at Texas Instruments.
Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
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Wood, Neal Graham. "Silicon carbide junction field effect transistor integrated circuits for hostile environments." Thesis, University of Newcastle upon Tyne, 2018. http://hdl.handle.net/10443/4027.

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Silicon carbide (SiC), in particular its 4H polytype, has long been recognised as an appropriate semiconductor for producing hostile environment electronics due to its wide energy band gap, large chemical bond strength and high mechanical hardness. A strong research foundation has facilitated the development of numerous sensor structures capable of operating at high temperatures and in corrosive atmospheres. Front-end electronics suitable for in situ signal conditioning are however lacking. Junction field effect transistors (JFETs) circumvent the pitfalls of contemporary alternative SiC transistor variants and have been found to operate predictably and consistently under such extreme conditions. This thesis demonstrates for the first time the capability of producing the necessary stable and high-performance interface circuits from n-channel lateral depletion-mode (NLDM) JFETs. The temperature dependence of pertinent bulk 4H–SiC material parameters relevant for describing the operation of macroscopic JFETs were initially studied. An accurate phenomenological model was developed to account for the variation of the thermal equilibrium free carrier concentrations. The position of the electrochemical potential and the distribution of free electron energies were found to change markedly when conduction band nonparabolicity, higher energy intrinsic bands and extrinsic effects were accounted for. These in turn were found to influence the determination of p-n junction contact potentials. The worst case error introduced through use of the Boltzmann approximation when applied to the channel and gate regions of the JFETs under study, having nominal doping concentrations of 1 1017 cm�3 and 2 1019 cm�3, respectively, were approximately 0:1% and 2%, respectively. A set of efficient and well behaved closed form expressions were subsequently developed for the free carrier concentrations in the framework of the Joyce- Dixon approximation (JDA) which are ideally suited for use in circuit simulations. Expressions for the electron conductively effective mass and an appropriate weighting function for the momentum relaxation time were subsequently identified. While the conductivity effective mass along the basal plane remained almost independent of temperature the non-parabolic band dispersion in the direction of principle axis introduced a temperature variation of 19% and 21% between 25 C and 400 C in the first and second conduction bands, respectively. Monolithically integrated 4H–SiC signal-level homo-epitaxial NLDM JFETs, p-n junction diodes and resistors were electrically characterised between room temperature and 400 C and their static and dynamic properties studied. Their behaviours were found to be well represented by macroscopic drift-diffusion models and were in agreement with predictions based on the bulk material properties. The intrinsic voltage gain of the fabricated JFET structures with nominal 9 μm gate length, 300nm channel depth and 250 μm gate width, under typical bias conditions, was roughly 100. As a consequence of the finite doping concentration in the buffer layer beneath the active device channel, with an experimentally determined value of approximately 3 1015 cm�3, the devices under study were found to exhibit a strong body-effect. The thermal performance of the utilised tungsten capped annealed nickel-titanium and aluminium-titanium contacts, on highly doped n- and p-type regions, respectively, were investigated and appropriate methods for their characterisation described. The lowest recorded value of specific contact resistance was 1:90(50) 10�5 cm2 with a corresponding sheet resistance of 7:89(9) 102 = . Lateral current flow through the contact side wall and the difference in sheet resistance under the contact were found to increase the value of the specific contact resistance determined from transfer length method (TLM) test structures by as much as 10% for n-type contacts. While exhibiting much larger contact resistance, the p-type contacts were found to have negligible impact on device performance due to the high impedance of the gate-channel and body-channel p-n junctions under typical operation. Physics based, Simulation Program with Integrated Circuit Emphasis (SPICE) compatible, integrated circuit (IC) consistent compact models were developed that are congruent with experimental measurements over the aforementioned range of temperature and across all essential bias levels. Most notably, a self-contained, asymmetric double-gated, non-selfaligned JFET model was developed that accurately accounts for the body-effect, voltage dependent mobility and temperature. An accurate yet efficient solver of the charge neutrality equation within each region of the device is utilised to account for incomplete ionisation of dopants and the temperature dependence of the p-n junction contact potentials. Meticulous agreement with experimental measurements was attained from a minimal number of input parameters. The modelled devices were used to simulate pertinent IC building blocks, including single stage and differential amplifiers, level-shifters and voltage buffers. The finite bodytransconductance of active load transistors were identified as a major degrading factor for the voltage gain. Practical methods to circumvent this are discussed with the aid of appropriate small-signal equivalent models. Finally, a design was presented for a two-stage 4H–SiC operational amplifier (op-amp) with direct current (DC) stability over the entire temperature range of study. Low-frequency small-signal voltage gains of 80 dB and 70 dB were achieved at 25 C and 400 C, respectively when utilising a 30V supply. A closed-loop non-inverting op-amp configuration with an ideal gain of 11 was then simulated and found to vary by just 1% between 25 C and 400 C. Such amplifiers are of great utility and form the cornerstone of numerous useful and important electronic systems.
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Blaser, Markus. "Monolithically integrated InGaAs/InP photodiode-junction field-effect transistor receivers for fiber-optic telecommunication /." [S.l.] : [s.n.], 1996. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=11998.

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Wake, D. "The development of an indium gallium arsenide junction field effect transistor for use in optical receivers." Thesis, University of Surrey, 1987. http://epubs.surrey.ac.uk/843424/.

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The objective of this work was to design and develop a high performance field effect transistor to be suitable for monolithic integration with a photodetector for use in long wavelength optical communication systems. It was decided that the most promising type of device for this application was a junction field effect transistor (JFET), fabricated using the alloy In.53Ga.47As grown epitaxially onto an InP substrate. The requirements for such a device were that it should have high transconductance, low input capacitance, and low gate leakage current (for high receiver sensitivity), and that it should have a structure which would be easily integrated monolithically with the desired type of photodetector - an In.53Ga.47As PIN-photodiode. Although this alloy semiconductor has favourable electron transport properties, at the start of this work, high performance field effect transistors had not been realised in this material. In particular, the In.53Ga.47AS FETs that had been made at that time were characterised by low transconductance. Using a device design that incorporated many novel and efficacious features, the JFET described in this work gave results which greatly surpassed all previous (and current) published results of similar devices. This device not only showed high performance, but the novel design features also enabled a simple fabrication scheme. Having developed this very high performance discrete device, the feasibility of monolithic integration with a In.53Ga.47As PIN-photodiode was demonstrated. Although the physical size and material requirements of these two devices were very different, novel design features enabled the construction of a monolithic PIN-FET combination, in which the performance of the JFET was not compromised.
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Alwardi, Milad. "Design and characterization of integrating silicon junction field-effect transistor amplifiers for operation in the temperature range 40-77 K." Diss., The University of Arizona, 1989. http://hdl.handle.net/10150/184871.

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The very low photon backgrounds to be achieved by future cryogenic astronomical telescopes present the ultimate challenge to the sensitivity of infrared detectors and associated readout electronics. Cooled silicon JFETs, operated around 70 K in transimpedance amplifiers, have shown excellent performance and stability. However, due to Johnson noise in the feedback resistor, the read noise in one second achieved by such amplifiers is about 500 electrons per second. A drastic improvement in sensitivity was demonstrated using a simple form of integrating JFET amplifiers. Therefore, the excellent performance obtained with cooled silicon JFETs has led to the investigation of their properties in the temperature range 33-77 K to explore their full potential and improve the performance of the integrating amplifier. The freezeout effect in silicon JFETs has been characterized both experimentally and theoretically using a simple analytical simulation program. The effect of variation in device parameters on the freezeout characteristic has been studied, and test results showed that an effective channel mobility must be used instead of a bulk mobility in order to simulate accurately the device current and transconductance freezeout at low temperatures. Many types of commercially available JFETs have been characterized below 77 K and measurements revealed that a balanced source follower or a common-source amplifier with active load can operate well down to 38 Kelvin with extremely low power dissipation. The open gate equivalent input noise voltage was found to be optimum below 77 K, due to a decrease in the gate leakage current, in agreement with theoretical prediction. Based on the superior performance of the balanced source follower with active load, a single channel hybrid integrating JFET amplifier with a JFET reset and a compensation capacitor was developed for operation in the temperature range 40-77 K. Read noise as low as 10 electrons in 128 seconds integration was achieved when the integrator was operated at an optimum temperature of about 55 K. Using a similar design, a 16-channel monolithic integrating amplifier array was designed and built. Preliminary test results at 77 K showed noise performance comparable to the single channel hybrid integrator.
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Liu, Wei. "Electro-thermal simulations and measurements of silicon carbide power transistors." Doctoral thesis, Stockholm, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-86.

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Purohit, Siddharth. "Compact modeling of silicon carbide (SiC) vertical junction field effect transistor (VJFET) in PSpice using Angelov model and PSpice simulation of analog circuit building blocks using SiC VJFET model." Master's thesis, Mississippi State : Mississippi State University, 2006. http://sun.library.msstate.edu/ETD-db/ETD-browse/browse.

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Guédon, Florent Dominique. "Power converters with normally-on SiC JFETs." Thesis, University of Cambridge, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.610394.

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Mohammad, Azhar. "EMERGING COMPUTING BASED NOVEL SOLUTIONS FOR DESIGN OF LOW POWER CIRCUITS." UKnowledge, 2018. https://uknowledge.uky.edu/ece_etds/125.

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The growing applications for IoT devices have caused an increase in the study of low power consuming circuit design to meet the requirement of devices to operate for various months without external power supply. Scaling down the conventional CMOS causes various complications to design due to CMOS properties, therefore various non-conventional CMOS design techniques are being proposed that overcome the limitations. This thesis focuses on some of those emerging and novel low power design technique namely Adiabatic logic and low power devices like Magnetic Tunnel Junction (MTJ) and Carbon Nanotube Field Effect transistor (CNFET). Circuits that are used for large computations (multipliers, encryption engines) that amount to maximum part of power consumption in a whole chip are designed using these novel low power techniques.
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Hamieh, Youness. "Caractérisation et modélisation du transistor JFET en SiC à haute température." Phd thesis, INSA de Lyon, 2011. http://tel.archives-ouvertes.fr/tel-00665817.

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Dans le domaine de l'électronique de puissance, les dispositifs en carbure de silicium (SiC) sont bien adaptés pour fonctionner dans des environnements à haute température, haute puissance, haute tension et haute radiation. Le carbure de silicium (SiC) est un matériau semi-conducteur à large bande d'énergie interdite. Ce matériau possède des caractéristiques en température et une tenue aux champs électriques bien supérieure à celles de silicium. Ces caractéristiques permettent des améliorations significatives dans une grande variété d'applications et de systèmes. Parmi les interrupteurs existants, le JFET en SiC est l'interrupteur le plus avancé dans son développement technologique, et il est au stade de la pré-commercialisation. Le travail réalisé au cours de cette thèse consiste à caractériser électriquement des JFET- SiC de SiCED en fonction de la température (25°C-300°C). Des mesures ont été réalisé en statique (courant-tension), en dynamique (capacité-tension) et en commutation sur charge R-L (résistive-inductives) et dans un bras d'onduleur. Un modèle multi-physique du transistor VJFET de SiCED à un canal latéral a été présenté. Le modèle a été développé en langage MAST et validé aussi bien en mode de fonctionnement statique que dynamique en utilisant le simulateur SABER. Ce modèle inclut une représentation asymétrique du canal latéral et les capacités de jonction de la structure. La validation du modèle montre une bonne concordance entre les mesures et la simulation.
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Books on the topic "Junction field-effect transistor"

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Blaser, Markus. Monolithically integrated InGaAs/Inp photodiode-junction field-effect transistor receivers for fiber-optic telecommunication. Konstanz: Hartung-Gorre, 1997.

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Zetex. Junction field effect transistors. Chadderton: Zetex, 1991.

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Soclof, Sidney. Junction field-effect transistors (JFETS): Principles and applications. Boston: ArtechHouse, 1996.

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Physics of semiconductor devices. Englewood Cliffs, N.J: Prentice Hall, 1990.

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Shur, Michael. Physics of semiconductor devices: Software and manual. London: Prentice-Hall, 1990.

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Solymar, L., D. Walsh, and R. R. A. Syms. Principles of semiconductor devices. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780198829942.003.0009.

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p–n junctions are examined initially and the potential distribution in the junction region is derived based on Poisson’s equation. Next the operation of the transistor is discussed, both in terms of the physics and of equivalent circuits. Potential distributions in metal–semiconductor junctions are derived and the concept of surface states is introduced. The physics of tunnel junctions is discussed in terms of their band structure. The properties of varactor diodes are described and the possibility of parametric amplification is touched upon. Further devices discussed are field effect transistors, charge-coupled devices, controlled rectifiers, and the Gunn effect. The fabrication of microelectronic circuits is discussed, followed by the more recent but related field of micro-electro-mechanical systems. The discipline of nanoelectronics is introduced including the role of carbon nanotubes. Finally, the effect of the development of semiconductor technology upon society is discussed.
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Amara, Amara, and Rozeau Olivier, eds. Planar double-gate transistor: From technology to circuit. [Dordrecht?]: Springer, 2009.

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J, Frasca A., and United States. National Aeronautics and Space Administration., eds. Neutron and gamma irradiation effects on power semiconductor switches. [Washington, D.C.]: NASA, 1990.

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Book chapters on the topic "Junction field-effect transistor"

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Prasad, R. "Transistor Bipolar Junction (BJT) and Field-Effect (FET) Transistor." In Undergraduate Lecture Notes in Physics, 457–581. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-65129-9_6.

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Kelner, G., M. Shur, S. Binari, K. Sleger, and H. Kong. "A High Transconductance β-SiC Buried-Gate Junction Field Effect Transistor." In Springer Proceedings in Physics, 184–90. Berlin, Heidelberg: Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/978-3-642-75048-9_38.

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Dubey, Avashesh, Rakhi Narang, Manoj Saxena, and Mridula Gupta. "Floating Gate Junction-Less Double Gate Radiation Sensitive Field Effect Transistor (RADFET) Dosimeter: A Simulation Study." In Springer Proceedings in Physics, 571–76. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-97604-4_89.

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Yuan, J. S., and J. J. Liou. "Junction Field-Effect Transistors." In Semiconductor Device Physics and Simulation, 99–125. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4899-1904-5_4.

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Srikant, Satya Sai, and Prakash Kumar Chaturvedi. "Junction Transistors and Field-Effect Transistors." In Basic Electronics Engineering, 105–54. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-13-7414-2_3.

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Singh, Ranbir, and B. Jayant Baliga. "Power Junction Field Effect Transistors." In Cryogenic Operation of Silicon Power Devices, 95–103. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5751-7_8.

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El-Kareh, Badih, and Lou N. Hutter. "Bipolar and Junction Field-Effect Transistors." In Silicon Analog Components, 151–219. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-15085-3_5.

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El-Kareh, Badih, and Lou N. Hutter. "Bipolar and Junction Field-Effect Transistors." In Silicon Analog Components, 147–204. New York, NY: Springer New York, 2015. http://dx.doi.org/10.1007/978-1-4939-2751-7_5.

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Kim, Dae Mann, Bong Koo Kang, and Yoon-Ha Jeong. "P–N Junction Diode: I–V Behavior and Applications." In Nanowire Field Effect Transistors: Principles and Applications, 39–62. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-8124-9_3.

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Manfredi, P. F., and V. Speziali. "Silicon Junction Field-Effect Transistors in Low-Noise Circuits: Research in Progress and Perspectives." In Techniques and Concepts of High-Energy Physics VI, 423–35. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4684-6006-3_8.

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Conference papers on the topic "Junction field-effect transistor"

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Ou, Tzu-Min, Tomoko Borsa, and Bart Van Zeghbroeck. "Graphene junction field-effect transistor." In 2015 73rd Annual Device Research Conference (DRC). IEEE, 2015. http://dx.doi.org/10.1109/drc.2015.7175594.

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Zeisse, C. R., R. Nguyen, T. T. Vu, L. J. Messick, and K. L. Moazed. "An indium phosphide diffused junction field effect transistor." In International Conference on Indium Phosphide and Related Materials. IEEE, 1990. http://dx.doi.org/10.1109/iciprm.1990.203037.

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Jahangir, Ifat, Shafat Jahangir, and Quazi Deen Mohd Khosru. "Transport characteristics of GaInAs nanowire junction field effect transistor." In 2012 IEEE International Conference on Electro/Information Technology (EIT 2012). IEEE, 2012. http://dx.doi.org/10.1109/eit.2012.6220771.

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Baca, A. G., J. C. Zolper, M. E. Sherwin, P. J. Robertson, R. J. Shul, A. J. Howard, D. J. Rieger, and J. F. Klem. "Complementary GaAs junction-gated heterostructure field effect transistor technology." In Proceedings of 1994 IEEE GaAs IC Symposium. IEEE, 1994. http://dx.doi.org/10.1109/gaas.1994.636920.

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Vardhan Reddy, Isukapalli Vishnu, and Suman Lata Tripathi. "Double Gate-Pocket-Junction-less Tunnel Field Effect Transistor." In 2021 Devices for Integrated Circuit (DevIC). IEEE, 2021. http://dx.doi.org/10.1109/devic50843.2021.9455895.

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Benner, O., A. Lysov, C. Gutsche, G. Keller, C. Schmidt, W. Prost, and F. J. Tegude. "Junction field-effect transistor based on GaAs core-shell nanowires." In 2013 25th International Conference on Indium Phosphide and Related Materials (IPRM). IEEE, 2013. http://dx.doi.org/10.1109/iciprm.2013.6562589.

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Tomioka, K., M. Yoshimura, and T. Fukui. "First Demonstration of Tunnel Field-Effect Transistor Using InGaAs/Si Junction." In 2012 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2012. http://dx.doi.org/10.7567/ssdm.2012.e-4-3.

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Kumar, Parveen, and Balwinder Raj. "Design and Simulation of Silicon Nanowire Tunnel Field Effect Transistor." In International Conference on Women Researchers in Electronics and Computing. AIJR Publisher, 2021. http://dx.doi.org/10.21467/proceedings.114.62.

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This paper analyses the different parameters of tunnel field-effect transistor (TFET) based on silicon Nanowire in vertical nature by using a Gaussian doping profile. The device has been designed using an n-channel P+-I-N+ structure for tunneling junction of TFET with gate-all-around (GAA) Nanowire structure. The gate length has been taken as 100 nm using silicon Nanowire to obtain the various parameters such as ON-current (ION), OFF-current (IOFF), current ratio, and Subthreshold slope (SS) by applying different values of work function at the gate, the radius of Nanowire and oxide thickness of the device. The simulations are performed on Silvaco TCAD which gives a better parametric analysis over conventional tunnel field-effect transistor.
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9

Jiang, Zhi, Yiqi Zhuang, Cong Li, and Wang Ping. "The hetero material gateand hetero-junction tunnel field-effect transistor with pocket." In 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT). IEEE, 2014. http://dx.doi.org/10.1109/icsict.2014.7021632.

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10

Tripathi, Ball Mukund Mani, and Shyama Prasad Das. "Vertical Channel GaN Field Effect Transistor Without Junction for High Power Application." In 2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT). IEEE, 2018. http://dx.doi.org/10.1109/conecct.2018.8482384.

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Reports on the topic "Junction field-effect transistor"

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Griffin, Timothy E. Development of Gate and Base Drive Using SiC Junction Field Effect Transistors. Fort Belvoir, VA: Defense Technical Information Center, May 2008. http://dx.doi.org/10.21236/ada482448.

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