Dissertations / Theses on the topic 'Interleaved buck converter'

in electric vehicle (ev) systems, bi-directional dc-dc converters are used to interface the rechargeable energy storage system (ress) such as the battery bank with the high voltage dc-link of the inverter. currently multi-cell batteries used in automotive systems, such as ev or hev, are subject to a higher failure rate than single cell batteries. the more cells are used in series, the greater the opportunities to fail and the worse the reliability. when a cell has failed the entire string or even worse the battery must be replaced, which is extremely costly [1]. so, to have less cells in series increases the reliability of the system, which also leads to a lower voltage of the dc link. for this reason and many others, in a hybrid or electric vehicle powertrain, a boost dc-dc converter enables optimization of the battery system. this work aims to investigate all the benefits that come with interleaving technique in dc-dc converters for automotive systems. indeed, these kind of converters for use in high-performance and high-power applications have received increasing interest in recent years. in particular this research work, done with sevcon ltd focuses on the theory behind bi-directional multiphase interleaved (imc) converter and how it could be used to interface a rechargeable energy storage system (ress) to the powertrain of a hybrid or electric vehicle. more specifically, it was investigated if it is possible to use (after appropriate hardware and software amendments) a standard three phase ac motor inverter as a multiphase interleaved converter. for this purpose two motor controller, produced by sevcon have been analysed. both the gen4 size 10 and the hvlp inverters were considered for use as a dc-dc converter. the voltage can step up or down based on the power flow direction. each phase is indeed a bi-directional buck or boost converter, which is composed of a bridge of power switches and inductor.

The power requirements for microprocessors have been increasing per Moore's Law. According to International Technology Roadmap (ITRS), Voltage Regulator Module (VRM) for microprocessors will be about 200 W at 1 V output in 2010. With the VRM’s topology of synchronous buck, serious technical challenges such as small duty cycle, high switching frequencies, and higher current demands, contribute to decreased power density and increased cost. This thesis proposes a Continuous Input Current Multiphase Interleaved Buck topology to solve the technical challenges of powering future microprocessors. This new topology is aimed to improve past topologies by providing continuous input current and improved efficiency. An open loop system of the proposed new topology is simulated using OrCAD PSpice to evaluate the performance criteria of the VRM. A hardware prototype of a four-phase Continuous Input Current Multiphase Interleaved Buck Converter is constructed and tested to assess the targeted improvements.

Photovoltaic panels are widely used to harvest solar energy. In the general application the panels are connected to an inverter that allows the power to be feed to the grid. The possibility to emulate a photovoltaic panel in a laboratory environment simplifies the development of inverters. Existing solutions are either expensive or not performing good enough. This thesis presents a real-time model that has fast enough transient response to be used with the future’s solar panel inverters. The solution is based on an interleaved synchronous buck converter with an analogue current control loop. A micro-controller is utilizing a look up table to steer the power stage to mimic the output of a real panel. The content of the look up table can be exchanged to emulate an arbitrary photovoltaic panel in different environmental conditions. The emulator output is stable in the load case with a typical inverter connected to it. It is oscillating with a limited amplitude under open circuit. A hardware implementation of the system confirms the functionality. The current controller can correct a load step in 20 μs. The output switching ripple is below 1 mA.
Fotovoltaiska paneler är ett väl etablerat sätt att ta tillvara på solenergi. Den vanligaste tillämpningen är att panelerna är anslutna till en växelriktare för att möjliggöra att energin matas ut på elnätet. Att kunna emulera en solcellspanel i laboratoriemiljö förenklar utvecklingen av växelriktare. Befintliga system är antingen dyra eller presterar inte bra nog. Denna avhandling presenterar en realtidsmodell som kan hantera transienta förlopp tillräckligt snabbt för att kunna användas med framtidens solpanelsväxelriktare. Lösningen är baserad på en tvåfas synkron buck-omvandlare med en analog strömreglering. En mikroprocessor använder uppslagstabell för att styra effektsteget till att efterlikna utsignalen från en verklig panel. Innehållet i uppslagstabellen kan bytas ut för att emulera en godtycklig solpanel i olika driftsförhållanden. Emulatorns utsignal är stabil med en typisk växelriktare ansluten som last. Utsignalen svänger med en begränsad amplitud under öppen krets. Experimentiella tester bekräftar funktionen. Strömregleringen kan korrigera ett belastningssteg inom 20 μs. Utgångens strömrippel är under 1 mA.

In this work, a DC off-board fast battery charger topology is presented, designed, and tested. It is expected to be able to fight the range anxiety by significantly diminish the EVs' charging times up to 15-20 minutes, meanwhile keeping low manufacturing, Operation and Maintenance (O&M) costs. The charger is made out of two main power stages the AC/DC and DC/DC converters. In order to keep the costs lower as possible, both parts are designed using interleaved topologies organized by using the same two-level three-phase modules coupled through reactors. This architecture allows to use the already well-known industrial three-phase modules taking advantage of the benefits guaranteed by mass production and at the same time permitting an effortless expansion thanks to its modularity. Thanks to the interleaved connections, it is possible to reach a high efficiency by distributing current and power evenly among the legs. Furthermore, this topology can handle bidirectional power flows, and it might be used for operating in both Grid to Vehicle (G2V) and Vehicle to Grid (V2G) modalities. In order to reduce the dimensions, and the costs of the filters, a control strategy able to keep a zero current ripple at any operative condition is developed. The proposed charger architecture uses an AC input BUS followed by an active rectifier stage. A ripple-free strategy acts on the variable DC BUS voltage according to the chopper duty cycle keeping the current ripple null. Meanwhile, DC/DC provides the requested output current. This strategy involves the AC/DC with the tasks to regulate the DC BUS voltage level and correcting the input power factor. A model-based control system ensures that every leg’s current follows an average current reference signal. Legs’ currents are actively rebalanced throughout a current rebalancing network. Finally, the simulation results are carried out trough MATLAB Simulink and validated with laboratory measurements on an adequately scaled prototype.

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
Uma das principais dificuldades para a adoção dos veículos elétricos (VE) é o tempo de abastecimento (carregamento elétrico), considerado elevado quando comparado com o tempo requerido para abastecer um veículo com motor a combustão interna. O carregamento do VE típico de passageiros é geralmente realizado na residência do proprietário, ligando o carregador interno do VE em uma tomada convencional monofásica. Este método de carregamento é conhecido como de Corrente Alternada (CA), requer, tipicamente pelo menos 7 horas para fornecer uma carga completa. Por outro lado, o método de carregamento por Corrente Continua (CC) oferece tempos de carregamento entre 10 e 80 minutos. Contudo, para obter este nível de desempenho, são empregados carregadores externos de alta potência ligados de forma direta ao banco de baterias do VE. Devido ao custo e aos requerimentos de alimentação, estes carregadores rápidos são usados principalmente em aplicações públicas e comerciais. As pesquisas pelas melhores topologias a serem empregadas nos carregadores rápidos ainda são, neste ano de 2017 objeto de estudos em escala mundial. Neste contexto, este trabalho descreve a análise e implementação de um protótipo de carregador externo rápido para VE, o qual é composto por um retificador híbrido trifásico com correção ativa do fator de potência (Etapa CA-CC), seguido de um conversor tipo Buck entrelaçado (Etapa CC-CC). Na etapa CA-CC são impostas correntes de entrada senoidais, obtendo desta forma uma reduzida distorção harmônica total (DHT). Nesta etapa são empregados retificadores SEPIC comutados sob corrente nula (Zero Current Switching, ZCS) controlados por uma simples modulação por histerese, em paralelo com um retificador trifásico a diodos de seis pulsos. O estágio SEPIC processa apenas uma fração da potência total entregue pelo retificador híbrido, reduzindo deste modo os esforços de corrente dos semicondutores empregados, permitindo o uso desta topologia em elevados níveis de potência. Na etapa CC-CC o conversor Buck entrelaçado é controlado por modulação de largura de pulso (Pulse-Width Modulation, PWM), permitindo assim a implantação da técnica de carregamento por corrente constante e tensão constante (Constant Current-Constant Voltage, CC-CV), comumente empregada em baterias de íons de lítio e supercapacitores (SC). Como principal resultado foi obtido o carregamento de um banco de supercapacitores de 2,54 F, com corrente constante de 20 A, variando sua tensão de 180 V a 270 V com uma duração de 40 s, obtendo uma distorção harmônica total de 3,52% na corrente de entrada, ajustando-se ao padrão IEEE 2030.1.1-2015.
One of the main barriers against electric vehicle (EV) adoption is related to the battery recharging time, which is relatively high when compared to the time required to fill up a gasoline/diesel internal combustion engine vehicle. EV charging generally is done at home, using the on-board EV charger tied to conventional single phase power inlet, this charging method is known as Alternating Current (AC) and takes at least 7 hours to provide a full charge. On the other hand, the Direct Current (DC) method offers charging times from 1.2 hours to 10 minutes. However, to reach this performance, high power off-board chargers also known as fast-chargers (FC), directly charge the EV battery bank. Due to its cost and power supply requirements FC are used only in public or commercial applications. The researches for the best FC topologies are an active area of studies over the world. This work describes the analysis and implementation of an off-board electric vehicle (EV) Fast Charger prototype. It is composed by a three-phase hybrid rectifier with power factor correction (AC/DC stage), followed by an interleaved buck converter (DC/DC stage). At AC/DC stage, sinusoidal input phase currents are imposed, and consequently low Total Harmonic Distortion (THD) is obtained by the use of Zero Current Switching (ZCS) SEPIC rectifiers, applying a simple hysteresis control technique, in parallel with a conventional three-phase six pulses diode rectifier. The SEPIC converters manage only a fraction of the total power delivered by the hybrid rectifier, reducing the semiconductors current stresses, and allowing the use of this topology for high power levels. At DC/DC stage, the interleaved buck converter is controlled by Pulse Width Modulation (PWM), allowing Constant Current–Constant Voltage (CC-CV) charging technique, typically used for Lithium-ion (Li) batteries and Supercapacitors (SC). As main result of this implementation was obtained a charging process using constant a constant current of 20A over a supercapacitor bank of 2,54 F, raising its voltage from 180V to 270V in less than 40s, having a input phase current THD of 3,52%, fulfilling the requirements of IEEE 2030.1.1-2015 standard.

Orientador: Carlos Alberto Canesin
Resumo: Uma das principais dificuldades para a adoção dos veículos elétricos (VE) é o tempo de abastecimento (carregamento elétrico), considerado elevado quando comparado com o tempo requerido para abastecer um veículo com motor a combustão interna. O carregamento do VE típico de passageiros é geralmente realizado na residência do proprietário, ligando o carregador interno do VE em uma tomada convencional monofásica. Este método de carregamento é conhecido como de Corrente Alternada (CA), requer, tipicamente pelo menos 7 horas para fornecer uma carga completa. Por outro lado, o método de carregamento por Corrente Continua (CC) oferece tempos de carregamento entre 10 e 80 minutos. Contudo, para obter este nível de desempenho, são empregados carregadores externos de alta potência ligados de forma direta ao banco de baterias do VE. Devido ao custo e aos requerimentos de alimentação, estes carregadores rápidos são usados principalmente em aplicações públicas e comerciais. As pesquisas pelas melhores topologias a serem empregadas nos carregadores rápidos ainda são, neste ano de 2017 objeto de estudos em escala mundial. Neste contexto, este trabalho descreve a análise e implementação de um protótipo de carregador externo rápido para VE, o qual é composto por um retificador híbrido trifásico com correção ativa do fator de potência (Etapa CA-CC), seguido de um conversor tipo Buck entrelaçado (Etapa CC-CC). Na etapa CA-CC são impostas correntes de entrada senoidais, obtendo desta forma uma r... (Resumo completo, clicar acesso eletrônico abaixo)
Mestre

Face aux enjeux énergétiques d’aujourd’hui et de demain, le développement des énergies renouvelables semble inéluctable. Cependant, la production électrique de sources renouvelables prometteuses comme le photovoltaïque ou l’éolien est intermittente et difficilement prévisible du fait de la dépendance de ces sources aux conditions météorologiques. Afin de s’affranchir du caractère discontinu de la production d’électricité et de l’inadéquation de la production avec la consommation, un moyen de stockage de l’énergie électrique est nécessaire. Dans ce contexte, la batterie hydrogène est une des solutions envisagées. Lors de périodes de surproduction d’énergie renouvelable, un électrolyseur produit de l’hydrogène par électrolyse de l’eau. Lorsque cela est nécessaire, une pile à combustible fournit de l’électricité à partir du gaz stocké. Couplé avec des sources d’énergie renouvelable, la batterie hydrogène produit de l’énergie électrique non carbonée, c’est-à-dire non émettrice de gaz à effet de serre. L’intérêt majeur de cette technologie est le découplage entre l’énergie et la puissance du système. Tant que la pile à combustible est alimentée en gaz, elle fournit de l’électricité, l’énergie dépend des réservoirs de gaz. La puissance, quant à elle, dépend des caractéristiques des composants électrochimiques et du dimensionnement des chaînes de conversions de puissance. Les chaînes de conversion de puissance relient les composants électrochimiques au réseau électrique. Dans le cas de la chaîne de conversion sans transformateur qui est ici envisagée, la présence d’un convertisseur DC-DC à haut rendement à fort ratio de conversion est rendue nécessaire de par la caractéristique basse tension fort courant des composants électrochimiques. Avec pour but principal l’optimisation du rendement, deux axes de recherche sont développés. Le premier axe développe un convertisseur multicellulaire innovant à haut rendement à fort ratio de conversion. Les résultats expérimentaux du convertisseur appelé « miroir » obtenus dans deux expérimentations ont démontré la supériorité de cette topologie en terme d’efficacité énergétique par rapport aux convertisseurs conventionnels. Le deuxième axe porte sur de nouveaux composants de puissance en nitrure de gallium (GaN) annoncés comme une rupture technologique. Un convertisseur buck multi-phases illustre les défis technologiques et scientifiques de cette technologie et montre le fort potentiel de ces composants.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
This work presents a detailed analysis about the interleaved buck converter applied to electronic ballasts to supply high power HID lamps, assuming the input voltage as a PFC stage output. As the output capacitor has a maximum value to be applied in parallel with the lamp, parallel operated converters are a suitable choice because the output current ripple cancellation characteristic. Besides, the output current ripple cannot be greater than 5% of the nominal current to avoid acoustic resonance phenomena. Also, interleaved converters allow magnetic and semiconductors losses reduction. The applied topology was the interleaved buck converter, because its inherent characteritstic of the output as a current source. A generalized model for the IBC operating in CCM was obtained, including inductors and semiconductors losses, besides an analysis to achieve the optimum point of design in terms of efficiency, size and complexity of implementation. To apply the IBC in CCM supplying HID lamps, it is necessary inductors current control, which means to guarantee a current source behavior of the converter. For that, two current control loop were designed, one for each inductor being measured via a shunt resistor located at the circuit input. Also, stability was analyzed based on impedance criterion. Finally, complete electronic ballast was presented, gathering a two-cell IBC, full-bridge inverter, measuring circuits for current and voltage and an external circuit for the correct delay of the IBC MOSFETs gate signals. Obtained experimental results were satisfatory, showing equal current sharing, once warm-up stage and closed-loop implementation were via an 8-bits microcontroller.
Este trabalho apresenta uma análise detalhada do conversor buck intercalado como reator eletrônico aplicado à alimentação de lâmpadas de descarga em alta pressão (HID) de alta potência, assumindo a entrada como a saída de uma etapa de correção de fator de potência (PFC). A característica de diminuição da ondulação da corrente de saída de conversores operando em paralelo é uma grande vantagem, pois o capacitor em paralelo com a lâmpada tem um valor limite a fim de garantir a estabilidade do sistema. Aliada a essa condição, a ondulação de corrente na lâmpada não pode ultrapassar 5% da corrente nominal para garantir que não ocorra o fenômeno da ressonância acústica de forma destrutiva. Além disso, permitem redução de perdas magnéticas e nos semicondutores, além de apresentar diminuição na ondulação da corrente de saída através da defasagem dos sinais de comando dos interruptores, diminuindo o capacitor de saída a ser empregado. Em termos de análise do conversor buck intercalado (IBC), foi obtida uma modelagem generalizada para o conversor operando em modo de condução contínua (CCM) incluindo as perdas nos interruptores, indutores e diodo. Também foi realizada uma análise de ponto ótimo de projeto contemplando tamanho, eficiência e complexidade de implementação. Para a utilização do IBC em CCM na alimentação de lâmpadas HID é necessário o controle de corrente dos indutores, ou seja, garantir que o conversor tenha o comportamento semelhante à uma fonte de corrente. Para tal, foram utilizadas duas malhas de controle de corrente, uma para cada indutor, sendo o sinal de controle medido através de um resistor shunt localizado na entrada do conversor. Ainda, foi apresentada uma análise de estabilidade baseada na relação entre as impedâncias da lâmpada e do conversor, com realimentação em modo corrente. Finalmente, o reator completo foi apresentado, constituído do IBC com duas células, inversor full-bridge, circuito inibidor para defasagem dos sinais de comando do IBC e o circuito de medição das correntes e tensão. Os resultados experimentais obtidos foram satisfatórios, com correntes equilibradas, uma vez que o IBC com malha fechada em ambos os indutores foi implementado com um microcontrolador de 8-bits, com frequência de barramento de 16 MHz.

碩士
國立東華大學
電機工程學系
100
Because of the progress of chip manufacturing technique, the transistor count inside one single CPU increases a lot, which elevates the current necessity of the chip. In order to reduce the power consumption in CPU, the supplied voltage has to be lower down. Therefore, to power CPUs, the voltage regulation modules should be featured with high current output capability at reduced voltage. The purpose of this thesis is to propose a soft-switching interleaved buck converter, which is able to provide high current at reduced output voltage. This converter is composed of several parallel-connected basic buck converter cells, associated with auxiliary capacitors. All the active switches can be soft-switched off to minimize their turn-off switching loss. Besides, synchronous rectification technique is applied to alleviate the conduction loss, which diodes might be suffered at especially high current condition. This is helpful for raising converter efficiency and power density. All the converter cells are designed with the same specification to facilitate the converter’s steady-state analysis and design. At last, a laboratory prototype circuit is built to verify the theory. The experimental results illustrate convincible agreement to theoretical analyses. The highest converter efficiency achieved is 92.5%.

碩士
國立中山大學
電機工程學系研究所
106
This thesis studies the active power factor correction. In terms of converters, this thesis proposes a novel bridgeless interleaved buck converter for power factor correction, and uses digitalized average current control method to control the AC input voltage in positive half-cycle and negative half-cycle to achieve power factor correction. The interleaved architecture not only controls simplicity, but also can effectively reduce the component current stress at high output power, improve the high current resistance of the power components, the overlarge volume of the inductors, and the overlarge of output capacitors. This thesis actually produces a 480W bridgeless interleaved buck converter to verify whether the analysis and design considerations are reasonable. Unlike most power factor correction converters, which are used in the boost architecture, the bridgeless interleaved buck converter proposed in this thesis can be used in lower voltage applications, can reduce the values of output electrolytic capacitor and reduce the cost, and also because of the interleaved buck architecture, it can be applied to applications with high output power. The feasibility of the proposed architecture is verified by the experimental results in this thesis, and the total harmonic distortion and power factor of the input current can meet the international specifications.

碩士
國立中山大學
電機工程學系研究所
97
A twin-buck converter with zero-voltage-transition (ZVT) is proposed in this thesis. The converter comprises two identical buck conversion units connected in parallel by an interleaved inductor. The ZVT is accomplished by the resonating the currents between the interleaved inductor and the parasitic capacitances of the power MOSFETs. The circuit efficiency can be further improved by introducing synchronous rectification to reduce the condition loss on the diodes. The detailed circuit analysis and operation characteristics are provided. A laboratory circuit rated at 300 W is designed and tested. Experimental results show that the switching losses can be effectively reduced by smoothly transiting the currents of the active power switches.

碩士
國立東華大學
電機工程學系
101
The thesis proposes a frequency-modulation based sliding mode control (SMC), which is applied on control of an interleaved buck-boost converter with zero-voltage transition.The merit of a SMC is its robustness upon disturbance; that is, even variation of component parameter or other disturbance happen, the system trajectory can be clamped on the designed sliding surface to provide stabilized output. In this thesis, matrix transforming method is first applied to appropriately transform to an appropriate form. Then pole assignment method is used to obtain the required sliding function to stabilize the system. Finally, the approaching sliding condition is proven by Lyapunov condition that the system can reach sliding mode within bounded time. By sliding mode control, even load adjusting or existing disturbance situations, the interleaved buck-boost converter can be stabilized. The controller used here is a 32-bit digital signal processor - TMS320F2812. The system is verified by experiment that the controller can handle the load changes and maintaining stabilized output.

碩士
國立臺北科技大學
電機工程研究所
103
This thesis develops a charger with high output current for EV batteries, the structure of the charger is an interleaved buck converter with synchronous rectification. The interleaved buck converter can reduce the ripple of output current, it also can decrease the current stress and voltage stress of power components in high power application. The synchronous rectification is utilized to replace the free-wheeling diode to MOSFET, and it is useful to improve power efficiency of the interleaved buck converter. Using current sharing method can average the output current for each phase and make the power more evenly dispersed in each phase. This thesis uses TMS320F28035 by TI as the digital core controller to control the implemented interleaved buck converter. The specification of the used Lithium-ion battery stack is 16V/40Ah.The validity of the charger formed of the designed interleaved buck converter is confirmed by the experiment results with constant current 40A output.

碩士
國立臺灣科技大學
電子工程系
103
This thesis proposed an interleaved three-phase DC-DC buck converter which is composed of three identical paralleled buck converters. Compared to the conventional paralleled buck converter, the proposed solution has three resonant inductors connected between each other of the three converters. By making use of the principle of quasi-resonant converter, the imposed inductors and the MOSFET parasitic capacitances will resonate to achieve zero-voltage-switching. Besides, the current through the free-wheeling diodes can be zero-current turned off to minimize their reverse-recovery losses. Paralleled topology can help sharing the load currents on each converter and is able to provide higher output power. MOSFETs are controlled by interleaved PWM (Pulse-Width-Modulation) signals to reduce the ripples of input and output currents. Therefore, the filtering capacitances on the input and output sides can be reduced and the power density can be improved. Circuit operation analyses, characteristic equations and simulations are given to understand the circuit. Finally, a 150W three-phase interleaved buck converter is designed, implemented and tested. According to the experimental results, high conversion efficiency over 97 % can be achieved.

碩士
明新科技大學
電機工程研究所
98
This paper presents a novel interleaved and isolated DC to DC buck converter with high voltage ratio. The converter consists of a half-bridge converter and a forward converter which are connected in parallel with a common load. As being one of interleaved DC to DC converters, it has smaller output current ripples within wide duty ratio, and it also has isolated input/output parts and higher voltage ratio due to applying transformers. So the converter presented in this paper is an isolated DC to DC buck converter with advantages of wide duty ratio, small output current ripple, and high voltage ratio. Simulation and experimental results are shown to verify the performance of the proposed converter.

碩士
國立臺北科技大學
電機工程系研究所
97
The objective of this thesis is to design and implement a digital controlled interleaved buck converter. The details of the specifications are as follows: input voltage is 12V, output voltage is 3.3V, maximum output current is 20A and switching frequency is 300 kHz. The digital control is realized by RENESAS MCU SH7203 and Altera FPGA Stratix EP2S30F484C4N. MCU is used to implement the digital control methodology. FPGA is used to implement the DPWM and converts the serial data to parallel data. The fully digital controlled interleaved buck DC/DC converter with current sharing function is implemented by MCU and FPGA. The experimental results show that the output voltage is well regulated and its ripple is less the ±1% under both light load and full loads, and current sharing is achieved. These results confirm the controller design and implementation.

碩士
國立臺北科技大學
電機工程系所
97
In this thesis, minimization of the output voltage ripple is presented based on the pulse width modulation (PWM) along with the pulse amplitude modulation (PAM), and applied to a DC-DC buck converter with the input voltage of 48V±20% and the rated output voltage of 12V. This system is implemented by two converters cascaded. The first-stage converter is a buck-boost converter used to regulate the output voltage of the second stage; the second-stage converter is an interleaved two-phase buck converter used to offer a large output current. In theory, if the duty cycle of the second-stage converter is set to 0.5 and the difference in phase between the two phases is , then the output current ripple is cancelled entirely, and hence the output voltage is ripple-free. However, if the duty cycle of the second-stage converter is fixed, then the output voltage is changed due to variations in load current or input voltage. Consequently, one additional converter, buck-boost converter, is used as the first-stage converter, which can regulate the output voltage of the second-stage converter to the prescribed value as closely as possible all over the load current and input voltage ranges. Furthermore, in actuality, there exist some differences in circuit parameter between the two phases, and hence current sharing is required so as to make the load current extracted from two phases as evenly as possible by finely adjusting duty cycles. In this thesis, the proposed control strategy is firstly simulated by IsSpice, secondly the corresponding program is verified by AHDL cooperated with Matlab/Simulink, and finally one field programmable gate array (FPGA) chip, named EP2C20F484C8 and made by Altera, is used as a control kernel of the system, so as to demonstrate the feasibility of the proposed control scheme.

碩士
國立雲林科技大學
電機工程系碩士班
100
This thesis presents an interleaved bridgeless high power factor buck-boost converter. The efficiency of conventional power factor correction circuit is poor due to power loss of diode bridge rectifier. By replacing diode bridge rectifier with power MOSFET, the conduction losses can be reduced. In addition, the benefit of an interleaved pulse-width modulation (PWM) scheme can reduce the input/output current ripples, decrease the current stresses of all semiconductor components and minimize the electro-magnetic interference (EMI). Thus, the capacitances of input and output side can be reduced. The operation principle and design consideration are discussed. Finally, the simulation and measured results are presented to confirm the effectiveness of the proposed converter.

碩士
國立臺灣科技大學
電子工程系
103
This thesis proposes a new control algorithm to improve the defect of the cited interleaved twin-buck converter in the literature. The algorithm can adjust the voltage gain by modulating the duty cycle. And by asymmetrically phase-shift the turn-on periods of the two active switches, i.e. partially overlapping the turn-on intervals, one of the active switch can benefit from zero-voltage-switching. When duty cycle is less than 50%, the problem of failure to zero-voltage switching on of the cited interleaved twin-buck converter can be improved. The switch with soft-switching will enhance the converter’s efficiency. In addition, heat issue cause by switching loss can be decreased and output voltage ripple can be lowered. In this thesis, a 120 -W prototype with input voltage ranging from 54 V to 84 V and 24 V output voltage is designed and implemented. According to the experimental results, the maximum efficiency is up to 96%.

碩士
國立臺灣海洋大學
電機工程學系
101
This paper proposes a new interleaved buck converter that combines the synchronous rectification technique to reduce the switching losses. The advantages of the proposed converter include lower current ripple and faster transient response. Besides, the normal inductor is replaced by coupled inductors with improvement and minimize output ripple. Finally, a 50W prototype converter with input 12VDC and output 5VDC is implemented. Experimental results show that the interleaved buck converter with coupled inductors performs well and provides power to a computer.

碩士
國立臺北科技大學
電機工程系研究所
98
In this thesis, a control technique combining pulse width modulation (PWM) and pulse amplitude modulation (PAM) is presented so as to make the output voltage ripple of the converter reduced as minimum as possible. Such a converter takes two-stage structure. The first stage is the active-clamped buck-boost converter which is used to adjust the output voltage of the second stage, whereas the second stage is the two-phase interleaved buck converter with active clamp based on only one resonant circuit is used to reduce the output voltage ripple. In theory, two phases of the second stage operate under the condition of individual duty cycles of 50% with a phase difference of between the two, and hence the currents in two phases are cancelled for any time, thereby making the output voltage of the converter voltage-free. However, in actuality, there exists a difference in circuit layout and component characteristic between the two phases, and hence the currents flowing through two phases are different. Consequently, a current sharing control technique via finely tuning the duty cycles of two phases is indispensable for the second stage, so as to make the load current extracted from two phases as evenly as possible. In this thesis, the behavior of the proposed topology along with the associated mathematical deduction is firstly described, secondly the proposed topology is simulated by IsSpice to evaluate its feasibility, thirdly the program to be executed is checked by Active-HDL and Matlab/Simulink/SimPowerSystems, and eventually one FPGA chip, named EP2C20F484C8 and made by Altera, is used as a system control kernel, so as to verify the effectiveness of the proposed topology.

碩士
國立成功大學
電機工程學系碩博士班
98
In this thesis, the design and implementation of an interleaved series buck converter with low output current ripple is presented. The converter is constructed by two series step-down converters to acquire high-step-down conversion ratio. The voltage transfer ratio of the converter is D square. By adopting the interleaved control technique, the output current ripple can be reduced and thus the volume of energy storage elements is reduced. The operating principles and circuit characteristics are discussed in this thesis. Also, the small signal models at CCM with voltage mode control are derived for system stability analysis and compensating network design. Finally, a laboratory prototype circuit with input voltage 12 V and output 1.5 V/50 A is implemented to verify the performance of the proposed converter.

M. Tech. (Engineering: Electrical, Department Electronic Engineering, Faculty of Engineering and Technology), Vaal University of Technology,
“If we think oil is a problem now, just wait 20 years. It’ll be a nightmare.” — Jeremy Rifkin, Foundation of Economic Trends, Washington, D.C., August 2003. This statement harmonises with the reality that human civilisation faces today. As a result, humankind has been forced to look for alternatives to fossil fuels. Among possible solutions, fuel cell (FC) technology has received a lot of attention because of its potential to generate clean energy. Fuel cells have the advantage that they can be used in remote telecommunication sites with no grid connectivity as the majority of telecommunication equipment operates from a DC voltage supply. Power plants based on phosphoric acid fuel cell (PAFC) have been installed worldwide supplying urban areas, shopping centres and medical facilities with electricity, heat and hot water. Although these are facts regarding large scale power plants for on-site use, portable units have been explored as well. Like any other fuel cell, the PAFC output power is highly unregulated leading to a drastic drop in the output voltage with changing load value. Therefore, various DC–DC converter topologies with a wide range of input voltages can be used to regulate the fuel cell voltage to a required DC load. An interleaved synchronous buck converter intended for efficiently stepping down the energy generated by a PAFC was designed and developed. The design is based on the National Semiconductor LM5119 IC. A LM5119 evaluation board was redesigned to meet the requirements for the application. The measurements were performed and it was found that the converter achieved the expectations. The results showed that the converter efficiently stepped down a wide range of input voltages (22 to 46 V) to a regulated 13.8 V while achieving a 93 percent efficiency. The conclusions reached and recommendations for future research are presented.
Telkom Centre of Excellence, TFMC, M-Tech, THRIP.

The popularity of the internal combustion engine (ICE) vehicles has contributed to global warming problem and degradation of air quality around the world. Furthermore, the vehicles??? massive demand on gas has played a role in the depletion of fossil fuel reserves and the considerable rise in the gas price over the past twenty years. Those existing challenges force the auto-industry to move towards the technology development of vehicle electrification. An electrified vehicle is driven by one or more electric motors. And the electricity comes from the onboard energy storage system (ESS). Currently, no single type of green energy source could meet all the requirements to drive a vehicle. A hybrid energy storage system (HESS), as a combination of battery and ultra-capacitor units, is expected to improve the overall performance of vehicles??? ESS. This thesis focuses on the design of HESS and the development of a HESS prototype for electric vehicles (EVs) and hybrid electric vehicles (HEVs). Battery unit (BU), ultra-capacitor unit (UC) and a DC/DC converter interfacing BU and UC are the three main components of HESS. The research work first reviews literatures regarding characteristics of BU, UC and power electronic converters. HESS design is then conducted based on the considerations of power capability, energy efficiency, size and cost optimization. Besides theoretical analysis, a HESS prototype is developed to prove the principles of operation as well. The results from experiment are compared with those from simulation.

Dissertação de mestrado em Engenharia Eletrónica e de Computadores
A presença da tecnologia através de dispositivos móveis na vida quotidiana dos cidadãos é, cada vez mais, imprescindível, apresentando notórias vantagens. Contudo, a evolução tecnológica dos dispositivos torna-os fortemente dependentes de fontes de energia. Consequentemente, torna-se imprescindível que, do ponto de vista tecnológico, estes sejam energeticamente eficientes, contribuindo também para maximizar a sua autonomia. Neste contexto, é de primordial importância o estudo e a caracterização de sistemas de alimentação baseados em baterias, nomeadamente, no que concerne aos processos de carga e descarga. No contexto desta dissertação são consideradas, em particular, as baterias do tipo Lítio Ferro Fosfato (LiFePO4). As baterias do tipo LiFePO4 apresentam-se como uma das tecnologias de armazenamento de energia elétrica mais evoluídas no que diz respeito às baterias secundárias, principalmente, devido às suas variadas vantagens em comparação com outras tecnologias existentes. Posto isto, destacam-se aspetos como a durabilidade, reduzida taxa de autodescarga, não possuem efeito memória e não contêm materiais poluentes. Além disso, estão presentes em diversas áreas, como por exemplo, mobilidade elétrica, sistemas de armazenamento de energia e interface com dispositivos/sistemas de energias renováveis. Assim, a finalidade desta dissertação consiste no desenvolvimento de um conversor bidirecional para testes de baterias de LiFePO4 e, posteriormente, efetuar vários testes com o intuito de obter as curvas caraterísticas de carga/descarga da mesma. Com o objetivo de efetuar vários ensaios à bateria de LiFePO4, foi desenvolvido um equipamento de eletrónica de potência que permite carregar e descarregar a bateria em estudo, com diferentes níveis de tensão e de corrente. Para visualizar a evolução das principais variáveis em análise, foi também desenvolvida uma aplicação gráfica que permite, em tempo real, efetuar a interface com o utilizador. O equipamento desenvolvido é composto por um conversor de eletrónica de potência do tipo CC-CC buck-boost, com topologia interleaved, sendo este controlado por um sistema baseado no Digital Signal Processor TMS320F28027FPTT da Texas Instruments.
The technologies’ presence in citizens’ everyday life, mainly in mobile form, is indubitably essential, presenting itself with numerous advantages. On the other hand, it comes with a large dependency, power sources. Therefore, to reduce these very same energy dependencies, it is imperative, from a technology point of view, that these devices become more energy efficient, maximizing the autonomy. With this taken in account it is extremely important to study and review the battery-based systems, mainly the processes of charging and discharging. On this dissertation’s context is considered LiFePO4 batteries, since they are one of the most promisor kind of batteries available in the market. LiFePO4 batteries are one of the most evolved ways of electric energy storing in secondary batteries, this being backed up by the numerous advantages in comparison to the other existent technologies. From which are highlighted the durability, the reduced self-discharging rate and the lack of memory effect as well as the nonexistence of polluting materials. Apart from that they are present in several areas such as smart grids, electric mobility and interface with renewable energy devices/systems. The main focus of this dissertation is to implement a bidirectional charging and discharging system made for LiFePO4 batteries, later performing a series of test to obtain charging and discharging characteristic curves. With the intuit of performing several tests to the LiFePO4 battery, the development of a power electronics equipment based on a bidirectional CC-CC convertor was required, to allow charging and discharging the battery with different levels of current and voltage. To visualize the evolution of the main variables, a graphic application was developed allowing real time interface with the user. The developed equipment consists on a CC-CC buck-boost with interleaved topology power electronics converter, controlled by a DSP based system, Texas Instruments TMS320F28027FPTT.

碩士
國立臺灣科技大學
電機工程系
105
This thesis is concerned with the design of high efficiency, low voltage, high current, six-arm interleaved synchronous buck converter. The appropriate arm number, from 1 to 6, is determined by the load level to reduce the loss as well as the voltage and current ripples. In the proposed converter, output voltage control is achieved by adjusting the pulse-width output of the modulation controller in accordance with the change of feedback voltage from the output inductor. Whereas, the output current control is conducted by determining the required number of converter arm from the actual current obtained through the load current feedback. The overall circuit structure uses voltage and current closed-loop control strategy to adjust modulation pulse-width and switching frequency according to dynamic current change, thereby improving the efficiency as well as the stability of the output voltage. The six-arm interleaved synchronous buck converter has an input and output voltages of 12V and 1.7V, respectively. The tolerance of the output voltage is±1%, and the switching frequency of power transistors is 400kHz. Each additional load current of 20A requires extra converter arm. This indicates that all the 6 converter arms needs to be operated for the rated output current of 100A. In addition, Intel CPU specification requires the virtual resistance for voltage adjustment to be within 1.5mΩ ± 5%. The corresponding value from the test result is 1.5mΩ ± 2.3%. Besides, the experimental results yield the efficiencies of 86.65% and 90.96% for one-arm, 20A and six-arm, 100A operations, respectively, with the best transfer efficiency of 92.57% occurred at the load current of 60A. In addition, the measured component temperature is below 70℃under rated operation with evenly distributed currents among the six converter arms. In conclusion, the experimental results show that the proposed design meets the circuit specification and confirms the feasibility of the presented six-arm interleaved synchronous buck converter.

碩士
國立臺北科技大學
電力電子產業研發碩士專班
96
The objective of this thesis is to design and implement an interleaved buck converter for lower voltage and high current applications. The advantages of the designed and implemented converter include low output current ripples and high current slew rate. An Intersil control IC is used to realize the PWM control of interleaved buck converter. The specifications of the converter are: input voltage = 12 V, output voltage = 3.3 V, output current = 10 A, two phases, and switching frequency for each phase = 100 kHz. The small signal model of the converter is derived to design the controller. A three-pole-two-zero controller is designed based upon the derived small signal model and realized using operation amplifier and passive components. Experimental results show that the output voltage is well regulated, and confirms the design and implementation.

博士
國立成功大學
電機工程學系
102
Proton exchange membrane (PEM) fuel cells (FCs) are widely used in electrical vehicle systems. Since the PEM FCs can not provide very high levels of instant current to the load, lithium batteries and supercapacitors are usually used in combination with the FCs to provide higher instant power to the load. In addition, the lithium battery and supercapacitor can also supply extra energy to the load when the PEM FCs can not provide enough. In this dissertation, two types of buck/boost DC - DC converters with interleaved control techniques are proposed for the PEM FC, lithium battery, and supercapacitor hybrid energy system. The ripple current on the input and output can be reduced by using interleaved control, compared with the traditional single converter topology. Thus, the overall performance of the interleaved control can be improved with a smaller-sized capacitor. The proposed novel non-inverting buck/boost converter is used to transfer the PEM FC energy to the DC-bus and also provide energy to the load. The common ground issue can be solved by the proposed non-inverting buck/boost converter. In addition, the output power can be increased with the interleaved control technique. The counts of power switches and diodes can also be decreased by the integrated converter. The operating principles and steady-state analysis of the proposed non-inverting buck/boost converter are discussed in detail. Finally, a laboratory prototype is implemented to verify the performance of the proposed converter; the FC output voltage is 24~45 V and the output is 28 V/800 W. Synchronous rectifiers are also adopted to improve the system efficiency. This dissertation also proposes a three-ports interleaved buck/boost DC - DC converter, which transfers energy from the FC to the lithium battery, and from the lithium battery to the DC-bus voltage by using an integrated coupled inductor. A digital signal processor (dsPIC30F4011) is also adopted to control the power flow. When the FC can not provide sufficient energy to the load, the lithium battery energy and supercapacitor will supply extra to the load. When the FC supplies sufficient energy, the digital signal processor (DSP) can also control the proposed three-ports converter to charge the battery appropriately. The operating principles and steady-state analysis of the proposed three ports non-inverting buck/boost converter are discussed in detail. A laboratory prototype is implemented with an FC output voltage of 24~45 V and battery output of 24 V/ 10Ah. The DSP is used to control the proposed two converters to manage the energy among the FC, lithium battery, and load. A laboratory prototype is implemented to verify the effectiveness of the proposed converters.