Journal articles: 'Interconnect architectures'

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Marrakchi, Zied, Hayder Mrabet, Umer Farooq, and Habib Mehrez. "FPGA Interconnect Topologies Exploration." International Journal of Reconfigurable Computing 2009 (2009): 1–13. http://dx.doi.org/10.1155/2009/259837.

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This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the area, performance, and power of the Tree-based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most efficient in terms of area and static power dissipation, whereas the architectures with higher LUT and cluster size are efficient in terms of performance. We also show that unifying a Mesh with this Tree topology leads to an architecture which has good layout scalability and better interconnect efficiency compared to VPR-style Mesh.

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Farahani, Esmat Kishani, and Reza Sarvari. "Design of n-Tier Multilevel Interconnect Architectures by Using Carbon Nanotube Interconnects." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 10 (October 2015): 2128–34. http://dx.doi.org/10.1109/tvlsi.2014.2360713.

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Hollman, Richard. "High Speed Electroplating of 200um High Cu Bumps for Die Stacking Architectures." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, DPC (January 1, 2016): 000611–30. http://dx.doi.org/10.4071/2016dpc-tp13.

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Recent advanced packaging architectures pose a number of challenges for metal deposition by electroplating, including shrinking RDL and pillar interconnects, via fills, and interconnect lines over topography. However, there is a class of die stacking designs which incorporate extremely tall Cu pillars, or

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Suboh, Suboh, Vikram Narayana, Mohamed Bakhouya, Jaafar Gaber, and Tarek El‐Ghazawi. "Methodology for adapting on‐chip interconnect architectures." IET Computers & Digital Techniques 8, no. 3 (May 2014): 109–17. http://dx.doi.org/10.1049/iet-cdt.2013.0021.

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Ezhumalai, P., A. Chilambuchelvan, and C. Arun. "Novel NoC Topology Construction for High-Performance Communications." Journal of Computer Networks and Communications 2011 (2011): 1–6. http://dx.doi.org/10.1155/2011/405697.

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Different intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-on-Chip(NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale systems-on-chip (SoC) design. We proposed an idea on building customizing synthesis network—on-chip with the better flow partitioning and also considered power and area reduction as compared to the already presented regular topologies. Hence to improve the performance of SoC, first, we did a performance study of regular interconnect topologies MESH, TORUS, BFT and EBFT, we observed that the overall latency and throughput of the EBFT is better compared to other topologies, The next best in case of latency and throughput is BFT. Experimental results on a variety of NoC benchmarks showed that our synthesis results were achieved reduction in power consumption and average hop count over custom topology implementation.

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Neumann, B., T. von Sydow, H. Blume, and T. G. Noll. "Design and quantitative analysis of parametrisable eFPGA-architectures for arithmetic." Advances in Radio Science 4 (September 6, 2006): 251–57. http://dx.doi.org/10.5194/ars-4-251-2006.

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Abstract. Future SoCs will feature embedded FPGAs (eFPGAs) to enable flexible and efficient implementations of high-throughput digital signal processing applications. Current research projects on and emerging products containing FPGAs are mainly based on "standard FPGA"-architectures that are optimised for a very wide range of applications. The implementation costs of these FPGAs are dominated by a very complex interconnect network. This paper presents a method to improve the efficiency of eFPGAs by tailoring them for a certain application domain using a parametrisable architecture template derived from the results of a systematic evaluation of the requirements of the application domain. Two different architectures are discussed, a reference architecture to illustrate the methodology and possible optimisation measures as well as a specialised arithmetic-oriented eFPGA for applications like correlators, decoders, and filters. For the arithmetic-oriented architecture, a novel logic element (LE) and a special interconnect architecture that was designed with respect to the connectivity characteristics of regular datapaths, are presented. For both architecture templates, physically optimised implementations based on an automatic design approach have been created. As a first cost comparison of these implementations with standard FPGAs, the LE-density (number of logic elements per mm2) is evaluated. For the arithmetic-oriented architecture, the LE-density could be increased by an order of magnitude compared to standard architectures.

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Yanushkevich, S. N., V. P. Shmerko, and B. Steinbach. "Spatial Interconnect Analysis for Predictable Nanotechnologies." Journal of Computational and Theoretical Nanoscience 5, no. 1 (January 1, 2008): 56–69. http://dx.doi.org/10.1166/jctn.2008.007.

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This paper addresses the interconnect problem for the representation of logic networks in spatial dimensions. Interest in spatial interconnects is motivated by the advent of nanotechnologies and by consequent attempts to evaluate and explore the appropriate nanoscale architectures. It have been shown in our previous study that a 3D logic network with target topology can be designed by replacing each elementary logic block in a network by its 3D model. In this paper, we study the problem of the partitioning of these 3D blocks with respect to the constraints of logic function interconnects and hypercube-like topology. We found that decomposition techniques provide flexibility in choosing switching functions for assembling the decomposed sub-networks.

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Krishnan, Gokul, Sumit K. Mandal, Chaitali Chakrabarti, Jae-Sun Seo, Umit Y. Ogras, and Yu Cao. "Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks." ACM Journal on Emerging Technologies in Computing Systems 18, no. 2 (April 30, 2022): 1–22. http://dx.doi.org/10.1145/3460233.

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With the widespread use of Deep Neural Networks (DNNs), machine learning algorithms have evolved in two diverse directions—one with ever-increasing connection density for better accuracy and the other with more compact sizing for energy efficiency. The increase in connection density increases on-chip data movement, which makes efficient on-chip communication a critical function of the DNN accelerator. The contribution of this work is threefold. First, we illustrate that the point-to-point (P2P)-based interconnect is incapable of handling a high volume of on-chip data movement for DNNs. Second, we evaluate P2P and network-on-chip (NoC) interconnect (with a regular topology such as a mesh) for SRAM- and ReRAM-based in-memory computing (IMC) architectures for a range of DNNs. This analysis shows the necessity for the optimal interconnect choice for an IMC DNN accelerator. Finally, we perform an experimental evaluation for different DNNs to empirically obtain the performance of the IMC architecture with both NoC-tree and NoC-mesh. We conclude that, at the tile level, NoC-tree is appropriate for compact DNNs employed at the edge, and NoC-mesh is necessary to accelerate DNNs with high connection density. Furthermore, we propose a technique to determine the optimal choice of interconnect for any given DNN. In this technique, we use analytical models of NoC to evaluate end-to-end communication latency of any given DNN. We demonstrate that the interconnect optimization in the IMC architecture results in up to 6 × improvement in energy-delay-area product for VGG-19 inference compared to the state-of-the-art ReRAM-based IMC architectures.

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GAO, Shanghua, Hiroaki YOSHIDA, Kenshu SETO, Satoshi KOMATSU, and Masahiro FUJITA. "Interconnect-Aware Pipeline Synthesis for Array-Based Architectures." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A, no. 6 (2009): 1464–75. http://dx.doi.org/10.1587/transfun.e92.a.1464.

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Palaniappan, Arun, and Samuel Palermo. "Power Efficiency Comparisons of Interchip Optical Interconnect Architectures." IEEE Transactions on Circuits and Systems II: Express Briefs 57, no. 5 (May 2010): 343–47. http://dx.doi.org/10.1109/tcsii.2010.2047319.

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Snider, Gregory S., and R. Stanley Williams. "Nano/CMOS architectures using a field-programmable nanowire interconnect." Nanotechnology 18, no. 3 (January 3, 2007): 035204. http://dx.doi.org/10.1088/0957-4484/18/3/035204.

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Yang, Xiaokuo, Li Cai, Weidong Peng, and Peng Bai. "Fast and robust magnetic quantum cellular automata interconnect architectures." Micro & Nano Letters 6, no. 8 (2011): 636. http://dx.doi.org/10.1049/mnl.2011.0187.

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Wang, Haitong, Neil C. Audsley, Xiaobo Sharon Hu, and Wanli Chang. "Meshed Bluetree: Time-Predictable Multimemory Interconnect for Multicore Architectures." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 11 (November 2020): 3787–98. http://dx.doi.org/10.1109/tcad.2020.3012239.

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Coiffic, J. C., M. Fayolle, S. Maitrejean, L. E. F. Foa Torres, and H. Le Poche. "Conduction regime in innovative carbon nanotube via interconnect architectures." Applied Physics Letters 91, no. 25 (December 17, 2007): 252107. http://dx.doi.org/10.1063/1.2826274.

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R. Murthy, A. S., and Sridhar T. "Power Efficient Clock Distribuition for Switched Capacitor DC-DC Converters." Indonesian Journal of Electrical Engineering and Computer Science 10, no. 1 (April 1, 2018): 27. http://dx.doi.org/10.11591/ijeecs.v10.i1.pp27-36.

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<p>In various VLSI based digital systems, on-chip interconnects have become the system bottleneck in state-of-the-art chips, limiting the performance of high-speed clock distributions and data communication devices in terms of propagation delay and power consumption. Increasing power requirements and power distribution to multi-core architectures is also posing a challenge to power distribution networks in the integrated circuits. Clock distribution networks for the switched capacitor converters becomes a non-trivial task and the increased interconnect lengths cause clock degradation and power dissipation. Therefore, this paper introduce low swing signaling schemes to decrease delay and power consumption. A comparative study presented of low voltage signaling schemes in terms of delay, power consumption and power delay product. Here, we have presented a power efficient signaling topology for driving the clocks to higher interconnect lengths.</p>

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Bakhouya, M., S. Suboh, J. Gaber, T. El-Ghazawi, and S. Niar. "Performance evaluation and design tradeoffs of on-chip interconnect architectures." Simulation Modelling Practice and Theory 19, no. 6 (June 2011): 1496–505. http://dx.doi.org/10.1016/j.simpat.2010.10.008.

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Gangwar, Anup, M. Balakrishnan, Preeti Ranjan Panda, and Anshul Kumar. "Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures." International Journal of Parallel Programming 35, no. 6 (May 25, 2007): 507–27. http://dx.doi.org/10.1007/s10766-007-0045-2.

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Venkatesan, R., J. A. Davis, K. A. Bowman, and J. D. Meindl. "Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9, no. 6 (December 2001): 899–912. http://dx.doi.org/10.1109/92.974903.

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Pitwon, Richard, Kai Wang, and Alex Worrall. "Embedded Photonics Interconnect Eco-system for Data Center Applications." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000361–66. http://dx.doi.org/10.4071/isom-2013-tp54.

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The exponential increase in data center system bandwidth densities necessitates the migration of optical connectivity into the system enclosure. This is reflected by the emergence of a new technology eco-system including board-mountable optical engines and board-level optical interconnect. We consider how data center architectures are evolving and investigate the relative maturity and viability of various optical interconnect technologies. We also discuss current European research activities to develop disruptive optical interconnect solutions across all hierarchical levels of the data system from rack-to-rack, board-to-board, chip-to-chip and ultimately on-chip photonic interconnect. An early outcome of these activities has been the successful demonstration of an optically enabled data storage system.

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Elsherbini, Adel. "(Invited) Advancing 3D Packaging for Heterogenous Systems Integration." ECS Meeting Abstracts MA2022-02, no. 17 (October 9, 2022): 848. http://dx.doi.org/10.1149/ma2022-0217848mtgabs.

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Next generation computing architectures including those for machine learning and AI (Artificial Intelligence) have increasing demands on bandwidth, memory capacity and energy efficiency. All of which can be improved through the increased integration density offered by advanced packaging technologies. In this talk, we will provide an overview of the different 3D integration technologies and cover their scaling and application considerations. These include technologies for direct die to die connections such as advanced solder interconnects at 20 and 10 µm pitch and hybrid bonding or Foveros Direct to support increased interconnect density to below 10 µm pitch or more than 10,000 connections/mm2. The increased interconnect density can dramatically improve the bandwidth capability and energy efficiency. We will also cover some of the considerations for 3D die stacking such as thermal hot spots and power delivery constraints and how these can be addressed through design and packaging technology combinations. Finally, we will discuss some future directions to support continued performance improvement.

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MOKRIAN, PEDRAM, MAJID AHMADI, and GRAHAM JULLIEN. "ON THE REDUCTION OF INTERCONNECT EFFECTS IN DEEP SUBMICRON IMPLEMENTATIONS OF DIGITAL MULTIPLICATION ARCHITECTURES." Journal of Circuits, Systems and Computers 15, no. 01 (February 2006): 83–106. http://dx.doi.org/10.1142/s0218126606002952.

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The conventional trend in algorithm implementation has been the reliance on advancements in process technology in order to satisfy the ever-increasing demand for high-speed and low power processors, and computational systems. As current device technology approaches sub-100 nm minimum device size, not only does the device geometry decrease, but switching times and operating voltages also scale down. These gains come at the expense of increased layout complexity, and a greater susceptibility to parasitic effects in the interconnections. In this paper we briefly overview the challenges that digital arithmetic designers will have to face in the imminent future, and we provide suggestions on algorithmic measures which may be taken in order to overcome some of these challenges. To illustrate our point, we will present an analysis of a digital multiplication algorithm, which is predicted to outperform currently preferred architectures for future technologies. We then apply the algorithm to form a multiplier architecture that alleviates many of the problems associated with interconnect scaling; in addition, our new architecture allows for simple variable precision reconfiguration.

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Harris, I. G., and R. Tessier. "Testing and diagnosis of interconnect faults in cluster-based FPGA architectures." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21, no. 11 (November 2002): 1337–43. http://dx.doi.org/10.1109/tcad.2002.804108.

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Pande, Sandeep, Fearghal Morgan, Gerard Smit, Tom Bruintjes, Jochem Rutgers, Brian McGinley, Seamus Cawley, Jim Harkin, and Liam McDaid. "Fixed latency on-chip interconnect for hardware spiking neural network architectures." Parallel Computing 39, no. 9 (September 2013): 357–71. http://dx.doi.org/10.1016/j.parco.2013.04.010.

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Chaintoutis, Charidimos, Behnam Shariati, Adonis Bogris, Paul Dijk, Chris Roeloffzen, Jerome Bourderionnet, Ioannis Tomkos, and Dimitris Syvridis. "Free Space Intra-Datacenter Interconnects Based on 2D Optical Beam Steering Enabled by Photonic Integrated Circuits." Photonics 5, no. 3 (August 1, 2018): 21. http://dx.doi.org/10.3390/photonics5030021.

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Data centers are continuously growing in scale and can contain more than one million servers spreading across thousands of racks; requiring a large-scale switching network to provide broadband and reconfigurable interconnections of low latency. Traditional data center network architectures, through the use of electrical packet switches in a multi-tier topology, has fundamental weaknesses such as oversubscription and cabling complexity. Wireless intra-data center interconnection solutions have been proposed to deal with the cabling problem and can simultaneously address the over-provisioning problem by offering efficient topology re-configurability. In this work we introduce a novel free space optical interconnect solution for intra-data center networks that utilizes 2D optical beam steering for the transmitter, and high bandwidth wide-area photodiode arrays for the receiver. This new breed of free space optical interconnects can be developed on a photonic integrated circuit; offering ns switching at sub-μW consumption. The proposed interconnects together with a networking architecture that is suitable for utilizing those devices could support next generation intra-data center networks, fulfilling the requirements of seamless operation, high connectivity, and agility in terms of the reconfiguration time.

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Ryan, E. Todd, Andrew J. McKerrow, Jihperng Leu, and Paul S. Ho. "Materials Issues and Characterization of Low-k Dielectric Materials." MRS Bulletin 22, no. 10 (October 1997): 49–54. http://dx.doi.org/10.1557/s0883769400034205.

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Continuing improvement in device density and performance has significantly affected the dimensions and complexity of the wiring structure for on-chip interconnects. These enhancements have led to a reduction in the wiring pitch and an increase in the number of wiring levels to fulfill demands for density and performance improvements. As device dimensions shrink to less than 0.25 μm, the propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant. Accordingly the interconnect delay now constitutes a major fraction of the total delay limiting the overall chip performance. Equally important is the processing complexity due to an increase in the number of wiring levels. This inevitably drives cost up by lowering the manufacturing yield due to an increase in defects and processing complexity.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILDs) and alternative architectures have surfaced to replace the current Al(Cu)/SiO2 interconnect technology. These alternative architectures will require the introduction of low-dielectric-constant k materials as the interlayer dielectrics and/or low-resistivity conductors such as copper. The electrical and thermomechanical properties of SiO2 are ideal for ILD applications, and a change to material with different properties has important process-integration implications. To facilitate the choice of an alternative ILD, it is necessary to establish general criterion for evaluating thin-film properties of candidate low-k materials, which can be later correlated with process-integration problems.

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Keller, Robert. "(Invited) Assessing Reliability of Materials for Electronic Interconnects." ECS Meeting Abstracts MA2022-02, no. 17 (October 9, 2022): 861. http://dx.doi.org/10.1149/ma2022-0217861mtgabs.

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Reliability of materials refers to how well an engineered material performs its intended function over a targeted design lifetime. Quantitatively, reliability is defined as (1 − probability of failure). Because a material’s physical properties are determined by its atomic makeup, reliable material function fundamentally depends on the stability of atomic structure as that material sees continued exposure to operational conditions. From the interconnect perspective, the primary functions include routing signal and power within and between devices or other subcomponents. Any disruptions to the atomic arrangement of materials used as interconnects therefore change the ability of those interconnects to perform those functions. An important aspect of designing these structures for high reliability therefore involves measuring and understanding how operational stressors can lead to the formation and evolution of defects in atomic structure over time. This type of knowledge can then at a minimum be used to predict when those effects unacceptably compromise interconnect functionality. Better yet, it can be used to improve material processing to slow or even eliminate damage. While interconnect technology has undergone significant changes and improvements over the years due to new materials, material systems, dimensions, and architectures, the fundamental factors that remain a chronic concern for reliability of interconnects used in BEOL and packaging are a combination of temperature, electric current, and mechanical strain. Our work addresses methods to test, detect, and ultimately control material defects, reliability, and failure. In this contribution, I will summarize some of our work to measure damage due to thermal fatigue and electromigration in several materials, including aluminum, copper, carbon nanotubes, and 2D molybdenum disulfide. I will also summarize some of our recent developments in material characterization, which we believe can play an important role in assessing material reliability for the semiconductor industry.

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Rajan, Mahesh, Douglas Doerfler, Courtenay T. Vaughan, Marcus Epperson, and Jeff Ogden. "Application Performance on the Tri-Lab Linux Capacity Cluster - TLCC." International Journal of Distributed Systems and Technologies 1, no. 2 (April 2010): 23–39. http://dx.doi.org/10.4018/jdst.2010040102.

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In a recent acquisition by DOE/NNSA several large capacity computing clusters called TLCC have been installed at the DOE labs: SNL, LANL and LLNL. TLCC architecture with ccNUMA, multi-socket, multi-core nodes, and InfiniBand interconnect, is representative of the trend in HPC architectures. This paper examines application performance on TLCC contrasting them with Red Storm/Cray XT4. TLCC and Red Storm share similar AMD processors and memory DIMMs. Red Storm however has single socket nodes and custom interconnect. Micro-benchmarks and performance analysis tools help understand the causes for the observed performance differences. Control of processor and memory affinity on TLCC with the numactl utility is shown to result in significant performance gains and is essential to attenuate the detrimental impact of OS interference and cache-coherency overhead. While previous studies have investigated impact of affinity control mostly in the context of small SMP systems, the focus of this paper is on highly parallel MPI applications.

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Mohamed, Khaled Salah. "Work around Moore’s Law: Current and next Generation Technologies." Applied Mechanics and Materials 110-116 (October 2011): 3278–83. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.3278.

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Interconnect dimensions and CMOS transistor feature size approach their physical limits, therefore scaling will no longer play an important role in performance improvement. So, instead of trying to improve the performance of traditional CMOS circuits, integration of multiple technologies and different components in a heterogeneous system that is high performance will be introduced “moore than more” and CMOS replacement”beyond CMOS” will be explored. This paper focuses on Technology level trends where it presents “More Moore”:New Architectures (SOI, FinFET, Twin-Well),”More Moore” :New Materials (High-K, Metal Gate, Strained-Si) ,”More than Moore”:New Interconnects Schemes (3D, NoC, Optical, Wireless), and ”Beyond CMOS” :New Devices (Molecular Computer, Biological computer, Quantum Computer) .

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Berbes Villalón, Dalia M., Laura Sánchez Jiménez, Manuel de la Iglesia Campos, María E. Díaz Aguirre, and Tatiana Delgado Fernández. "An IoT architecture for smart cities based on the FIWARE platform." Revista de Ciencia y Tecnología, no. 38 (October 31, 2022): 20–27. http://dx.doi.org/10.36995/j.recyt.2022.38.003.

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The Internet of Things (IoT) is a concept that has been gaining considerable popularity today. It attempts to represent everyday things that are connected to the internet, but in reality it is much more than that. The overall aim is to interconnect the physical with the digital world, as the physical world is measured by sensors which translates into actionable data, and also the data can be translated into commands to be executed by actuators. Currently, the number of designed IoT architectures has increased considerably as a result of different approaches, standards and use cases. This leads to difficulties in understanding, selecting and using these architectures. In this work, an IoT architecture based on the FIWARE platform is proposed with the aim of facilitating the development of smart cities. With the proposal made, it was possible to integrate the main elements to be considered in this technology, thus offering a basis that serves as a guide, both for developing IoT systems and for creating more specific architectures that respond to the particular characteristics of a given application.

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Khitun, Alexander. "Magnetic Interconnects Based on Composite Multiferroics." Micromachines 13, no. 11 (November 17, 2022): 1991. http://dx.doi.org/10.3390/mi13111991.

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The development of magnetic logic devices dictates a need for a novel type of interconnect for magnetic signal transmission. Fast signal damping is one of the problems which drastically differs from conventional electric technology. Here, we describe a magnetic interconnect based on a composite multiferroic comprising piezoelectric and magnetostrictive materials. Internal signal amplification is the main reason for using multiferroic material, where a portion of energy can be transferred from electric to magnetic domains via stress-mediated coupling. The utilization of composite multiferroics consisting of piezoelectric and magnetostrictive materials offers flexibility for the separate adjustment of electric and magnetic characteristics. The structure of the proposed interconnect resembles a parallel plate capacitor filled with a piezoelectric, where one of the plates comprises a magnetoelastic material. An electric field applied across the plates of the capacitor produces stress, which, in turn, affects the magnetic properties of the magnetostrictive material. The charging of the capacitor from one edge results in the charge diffusion accompanied by the magnetization change in the magnetostrictive layer. This enables the amplitude of the magnetic signal to remain constant during the propagation. The operation of the proposed interconnects is illustrated by numerical modeling. The model is based on the Landau–Lifshitz–Gilbert equation with the electric field-dependent anisotropy term included. A variety of magnetic logic devices and architectures can benefit from the proposed interconnects, as they provide reliable and low-energy-consuming data transmission. According to the estimates, the group velocity of magnetic signals may be up to 105 m/s with energy dissipation less than 10−18 J per bit per 100 nm. The physical limits and practical challenges of the proposed approach are also discussed.

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García-Ortiz, A., T. Murgan, L. Indrusiak, L. Kabulepa, and M. Glesner. "High Level Estimation of Power Consumption in Point-to-Point Interconnect Architectures." Journal of Integrated Circuits and Systems 1, no. 1 (November 16, 2004): 23–31. http://dx.doi.org/10.29292/jics.v1i1.251.

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As technology shrinks, the importance of the communication architecture in the overall system performance and power consumption increases dramatically. In this work, a framework is developed to estimate the consumption in point-to-point interconnect structures at high levels of abstraction. To model the effect of cross coupled capacitances, the spatial correlationbetween adjacent wire lines is considered together with the transition activity, and both are efficiently estimated using word-level statistics. Based on a set of increasing complexity stochastic data models, an analytical estimation procedure is proposed and validated with both synthetic and real data sets. Extensive bit level simulations have been carried out to show the accuracy of the proposed models.

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Pande, P. P., C. Grecu, M. Jones, A. Ivanov, and R. Saleh. "Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures." IEEE Transactions on Computers 54, no. 8 (August 2005): 1025–40. http://dx.doi.org/10.1109/tc.2005.134.

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Murali, S., D. Atienza, P. Meloni, S. Carta, L. Benini, G. De Micheli, and L. Raffo. "Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15, no. 8 (August 2007): 869–80. http://dx.doi.org/10.1109/tvlsi.2007.900742.

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Lambrechts, A., P. Raghavan, M. Jayapala, Bingfeng Mei, F. Catthoor, and D. Verkest. "Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 1 (January 2009): 151–55. http://dx.doi.org/10.1109/tvlsi.2008.2002993.

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BHATELÉ, ABHINAV, and LAXMIKANT V. KALÉ. "QUANTIFYING NETWORK CONTENTION ON LARGE PARALLEL MACHINES." Parallel Processing Letters 19, no. 04 (December 2009): 553–72. http://dx.doi.org/10.1142/s0129626409000419.

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In the early years of parallel computing research, significant theoretical studies were done on interconnect topologies and topology aware mapping for parallel computers. With the deployment of virtual cut-through, wormhole routing and faster interconnects, message latencies reduced and research in the area died down. This article shows that network topology has become important again with the emergence of very large supercomputers, typically connected as a 3D torus or mesh. It presents a quantitative study on the effect of contention on message latencies on torus and mesh networks. Several MPI benchmarks are used to evaluate the effect of hops (links) traversed by messages, on their latencies. The benchmarks demonstrate that when multiple messages compete for network resources, link occupancy or contention can increase message latencies by up to a factor of 8 times on some architectures. Results are shown for three parallel machines – ANL's IBM Blue Gene/P (Surveyor), RNL's Cray XT4 (Jaguar) and PSC's Cray XT3 (BigBen). Findings in this article suggest that application developers should now consider interconnect topologies when mapping tasks to processors in order to obtain the best performance on large parallel machines.

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MOADELI, MAHMOUD, WIM VANDERBAUWHEDE, and ALI SHAHRABI. "COMMUNICATION MODELING OF QoS-AWARE WORMHOLE-ROUTED NoCs." Journal of Interconnection Networks 09, no. 04 (December 2008): 409–23. http://dx.doi.org/10.1142/s0219265908002357.

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Network on-Chips (NoC) have emerged as an attractive communication architecture to address the increasing demand for communication in performance-sensitive applications. Employing differentiated services is a widely used approach to support QoS (Quality of Service) by relatively prioritizing traffic in the networks employing connection-less communication mechanisms. In this paper we present an analytical evaluation of the average message latency for wormhole-routed interconnect architectures exploiting a traffic prioritization mechanism to achieve differentiated services-based QoS. To verify the validity of the model we apply the method to the Spidergon NoC and compare the model against the results obtained from a discrete-event simulator developed using OMNET++.

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Krishnan, Gokul, Sumit K. Mandal, Manvitha Pannala, Chaitali Chakrabarti, Jae-Sun Seo, Umit Y. Ogras, and Yu Cao. "SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–24. http://dx.doi.org/10.1145/3476999.

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In-memory computing (IMC) on a monolithic chip for deep learning faces dramatic challenges on area, yield, and on-chip interconnection cost due to the ever-increasing model sizes. 2.5D integration or chiplet-based architectures interconnect multiple small chips (i.e., chiplets) to form a large computing system, presenting a feasible solution beyond a monolithic IMC architecture to accelerate large deep learning models. This paper presents a new benchmarking simulator, SIAM, to evaluate the performance of chiplet-based IMC architectures and explore the potential of such a paradigm shift in IMC architecture design. SIAM integrates device, circuit, architecture, network-on-chip (NoC), network-on-package (NoP), and DRAM access models to realize an end-to-end system. SIAM is scalable in its support of a wide range of deep neural networks (DNNs), customizable to various network structures and configurations, and capable of efficient design space exploration. We demonstrate the flexibility, scalability, and simulation speed of SIAM by benchmarking different state-of-the-art DNNs with CIFAR-10, CIFAR-100, and ImageNet datasets. We further calibrate the simulation results with a published silicon result, SIMBA. The chiplet-based IMC architecture obtained through SIAM shows 130 and 72 improvement in energy-efficiency for ResNet-50 on the ImageNet dataset compared to Nvidia V100 and T4 GPUs.

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John Famoriji, Oluwole, Xu Yan, Mehdi Khan, Rao Kashif, Akinwale Fadamiro, Md Sadek Ali, and Fujiang Lin. "Wireless Interconnect in Multilayer Chip-Area-Networks for Future Multimaterial High-Speed Systems Design." Wireless Communications and Mobile Computing 2017 (2017): 1–8. http://dx.doi.org/10.1155/2017/6083626.

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Wireless chip area network which enables wireless communication among chips fosters development in wireless communication and it is envisioned that future hardware system and developmental functionality will require multimaterial. However, the traditional system architecture is limited by channel bandwidth-limited interfaces, throughput, delay, and power consumption and as a result limits the efficiency and system performance. Wireless interconnect has been proposed to overcome scalability and performance limitations of multihop wired architectures. Characterization and modeling of channel become more important for specification of choice of modulation or demodulation techniques, channel bandwidths, and other mitigation techniques for channel distortion and interference such as equalization. This paper presents an analytical channel model for characterization, modeling, and analysis of wireless chip-to-chip or interchip interconnects in wireless chip area network with a particular focus on large-scale analysis. The proposed model accounts for both static and dynamic channel losses/attenuation in high-speed systems. Simulation and evaluation of the model with experimental data conducted in a computer desktop casing depict that proposed model matched measurement data very closely. The transmission of EM waves via a medium introduces molecular absorption due to various molecules within the material substance. This model is a representative of channel loss profile in wireless chip-area-network communication and good for future electronic circuits and high-speed systems design.

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Lee, Jaechul, Cédric Killian, Sebastien Le Beux, and Daniel Chillet. "Distance-aware Approximate Nanophotonic Interconnect." ACM Transactions on Design Automation of Electronic Systems 27, no. 2 (March 31, 2022): 1–30. http://dx.doi.org/10.1145/3484309.

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The energy consumption of manycore architectures is dominated by data movement, which calls for energy-efficient and high-bandwidth interconnects. To overcome the bandwidth limitation of electrical interconnects, integrated optics appear as a promising technology. However, it suffers from high power overhead related to low laser efficiency, which calls for the use of techniques and methods to improve its energy costs. Besides, approximate computing is emerging as an efficient method to reduce energy consumption and improve execution speed of embedded computing systems. It relies on allowing accuracy reduction on data at the cost of tolerable application output error. In this context, the work presented in this article exploits both features by defining approximate communications for error-tolerant applications. We propose a method to design realistic and scalable nanophotonic interconnect supporting approximate data transmission and power adaption according to the communication distance to improve the energy efficiency. For this purpose, the data can be sent by mixing low optical power signal and truncation for the Least Significant Bits (LSB) of the floating-point numbers, while the overall power is adapted according to the communication distance. We define two ranges of communications, short and long, which require only four power levels. This reduces area and power overhead to control the laser output power. A transmission model allows estimating the laser power according to the targeted BER and the number of truncated bits, while the optical network interface allows configuring, at runtime, the number of approximated and truncated bits and the laser output powers. We explore the energy efficiency provided by each communication scheme, and we investigate the error resilience of the benchmarks over several approximation and truncation schemes. The simulation results of ApproxBench applications show that, compared to an interconnect involving only robust communications, approximations in the optical transmission led to up to 53% laser power reduction with a limited degradation at the application level with less than 9% of output error. Finally, we show that our solution is scalable and leads to 10% reduction in the total energy consumption, 35× reduction in the laser driver size, and 10× reduction in the laser controller compared to state-of-the-art solution.

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Zhang, R., K. Roy, C. K. Koh, and D. B. Janes. "Exploring SOI device structures and interconnect architectures for low-power high-performance circuits." IEE Proceedings - Computers and Digital Techniques 149, no. 4 (2002): 137. http://dx.doi.org/10.1049/ip-cdt:20020451.

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Bakhouya, Mohamed. "Evaluating the energy consumption and the silicon area of on-chip interconnect architectures." Journal of Systems Architecture 55, no. 7-9 (July 2009): 387–95. http://dx.doi.org/10.1016/j.sysarc.2009.07.002.

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Jaadouni, Hatim, Chaimae Saadi, and Habiba Chaoui. "SDN/NFV architectures for edge-cloud oriented IoT." ITM Web of Conferences 46 (2022): 02004. http://dx.doi.org/10.1051/itmconf/20224602004.

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Thanks to Software Defined Networking (SDN) and Network Functions Virtualization (NFV), the use and behaviour of interconnect network backhauls to provide virtualization services has changed completely. Several benefits have been discovered in various application areas that combine SDN and NFV. As a result, we explored the SDN / NFV paradigm to determine if network services could be efficiently deployed, managed, and distributed to end users. The Internet of Things (IoT) is inseparable from improving SDN / b NFV to improve this task. However, until now, problems related to Edge cloud communications and network services have not been effectively mitigated. The rest of this article is organized as follows. We first present the background of this work. Then we present the new technologies around these topics and the extended architecture, and e. Finally, we conclude this work.

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Kaloyeros, Alain E., and Michael A. Fury. "Chemical Vapor Deposition of Copper for Multilevel Metallization." MRS Bulletin 18, no. 6 (June 1993): 22–29. http://dx.doi.org/10.1557/s0883769400047291.

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Since the birth of integrated circuitry about thirty five years ago, microelectronics design and manufacturing technologies have evolved toward higher integration density with smaller design rules. As the semiconductor industry moves into ultra-large-scale integration (ULSI), device geometries continue to shrink into the sub-half-micron region while circuit densities increase to optimize reliability and improve performance. The resulting demands on interconnect technologies necessitate the exploitation of all development avenues: design, materials, and manufacturing.Emerging sub-half-micron technologies require multilevel metallization (MLM) design schemes that reduce interconnection lengths and lead to lower signal transmission delays and enhanced device speeds. MLM schemes also permit increased device density, due to the ability to use the third (vertical) dimension, and easier signal routing because of higher flexibility in architectural design. These schemes, in turn, demand interconnect metals that can handle the higher current densities resulting from the decreasing size of device features, without the loss of electrical and structural integrity, and deliver the sheet resistance needed to meet performance demands. They also require reliable deposition techniques to successfully fabricate the increasingly complex architectures as lateral feature sizes are scaled down more rapidly than conductor or insulator thicknesses.

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Lee, Wei William, and Paul S. Ho. "Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications." MRS Bulletin 22, no. 10 (October 1997): 19–27. http://dx.doi.org/10.1557/s0883769400034151.

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Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

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Lyke, James C. "An Overview of Molecular Computing Approaches (Part II)." EDFA Technical Articles 6, no. 4 (November 1, 2004): 18–25. http://dx.doi.org/10.31399/asm.edfa.2004-4.p018.

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Abstract This is the second part of an article on molecular electronics. The first part, published in the August 2004 issue of EDFA, discussed the development of molecular devices including nanowires, rectifiers, switches, and transistors. Here, the author describes nontraditional molecular computing architectures based on crosspoint arrays, randomized nanocells, and cellular automata. Challenges associated with interconnect demand, lithography alternatives, and defect tolerance are also discussed.

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Shekhawat, Gajendra, Arvind Srivastava, Shraddha Avasthy, and Vinayak Dravid. "Ultrasound holography for noninvasive imaging of buried defects and interfaces for advanced interconnect architectures." Applied Physics Letters 95, no. 26 (December 28, 2009): 263101. http://dx.doi.org/10.1063/1.3263716.

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Shearer, Catherine. "Transient Liquid Phase Sintering Pastes in Heterogeneous Integration." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (January 1, 2017): 1–26. http://dx.doi.org/10.4071/2017dpc-wp1_presentation5.

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Integrated package technologies continue to be the dominant trend in the electronics packaging industry. In particular, heterogeneous integration of logic and memory or sensing is an enormous growth segment for both mobile electronics and IoT applications. In the mobile microprocessor segment of the field, the most advanced technologies will be implemented in the early adopter class. New package architectures and interconnect schemes will be vetted and implemented without significant cost pressure, performance is the driver. In the IoT segment and downstream mobile, however; lower cost alternatives to cutting edge packaging architectures are needed to drive market growth. Sintering pastes offer an opportunity to cost-effectively enable cutting edge 3D package capability for a wider variety of applications. In this paper we will explore the use of transient liquid phase sintering (TLPS) pastes in package-on-package (POP) schemes for integrated logic with memory or sensing functions in through mold via architectures. Through mold via technology has been well established in the industry and has significantly contributed to the adoption of three dimensional packaging architectures. The advantages of using TLPS pastes in similar structures will be detailed.

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ROY, KRISHNENDU, RAMACHANDRAN VAIDYANATHAN, and JERRY L. TRAHAN. "ROUTING MULTIPLE WIDTH COMMUNICATIONS ON THE CIRCUIT SWITCHED TREE." International Journal of Foundations of Computer Science 17, no. 02 (April 2006): 271–85. http://dx.doi.org/10.1142/s0129054106003826.

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Dynamically reconfigurable architectures offer extremely fast solutions to various problems. The Circuit Switched Tree (CST) is an important interconnect used to implement such architectures. A CST has a binary tree structure with processing elements (PEs) as leaves and switches as internal nodes. PEs communicate among themselves using the links of the tree. Key components for successful communication are scheduling individual communications and configuring the CST switches. This paper presents a scheduling and configuration algorithm for communications on a CST where conflicts necessitate multiple rounds of routing to perform all communications. The algorithm is distributed and requires only local information, yet it captures the global picture to ensure proper communication. The paper also explains how to apply the algorithm to an important class, "well-nested communications", for which the algorithm is optimal and efficient.

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Ahmed, Moustafa, Yas Al-Hadeethi, Ahmed Bakry, Hamed Dalir, and Volker J. Sorger. "Integrated photonic FFT for photonic tensor operations towards efficient and high-speed neural networks." Nanophotonics 9, no. 13 (June 26, 2020): 4097–108. http://dx.doi.org/10.1515/nanoph-2020-0055.

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AbstractThe technologically-relevant task of feature extraction from data performed in deep-learning systems is routinely accomplished as repeated fast Fourier transforms (FFT) electronically in prevalent domain-specific architectures such as in graphics processing units (GPU). However, electronics systems are limited with respect to power dissipation and delay, due to wire-charging challenges related to interconnect capacitance. Here we present a silicon photonics-based architecture for convolutional neural networks that harnesses the phase property of light to perform FFTs efficiently by executing the convolution as a multiplication in the Fourier-domain. The algorithmic executing time is determined by the time-of-flight of the signal through this photonic reconfigurable passive FFT ‘filter’ circuit and is on the order of 10’s of picosecond short. A sensitivity analysis shows that this optical processor must be thermally phase stabilized corresponding to a few degrees. Furthermore, we find that for a small sample number, the obtainable number of convolutions per {time, power, and chip area) outperforms GPUs by about two orders of magnitude. Lastly, we show that, conceptually, the optical FFT and convolution-processing performance is indeed directly linked to optoelectronic device-level, and improvements in plasmonics, metamaterials or nanophotonics are fueling next generation densely interconnected intelligent photonic circuits with relevance for edge-computing 5G networks by processing tensor operations optically.

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Belli, Laura, Simone Cirani, Luca Davoli, Gianluigi Ferrari, Lorenzo Melegari, and Marco Picone. "Applying Security to a Big Stream Cloud Architecture for the Internet of Things." International Journal of Distributed Systems and Technologies 7, no. 1 (January 2016): 37–58. http://dx.doi.org/10.4018/ijdst.2016010103.

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The Internet of Things (IoT) is expected to interconnect billions (around 50 by 2020) of heterogeneous sensor/actuator-equipped devices denoted as “Smart Objects” (SOs), characterized by constrained resources in terms of memory, processing, and communication reliability. Several IoT applications have real-time and low-latency requirements and must rely on architectures specifically designed to manage gigantic streams of information (in terms of number of data sources and transmission data rate). We refer to “Big Stream” as the paradigm which best fits the selected IoT scenario, in contrast to the traditional “Big Data” concept, which does not consider real-time constraints. Moreover, there are many security concerns related to IoT devices and to the Cloud. In this paper, we analyze security aspects in a novel Cloud architecture for Big Stream applications, which efficiently handles Big Stream data through a Graph-based platform and delivers processed data to consumers, with low latency. The authors detail each module defined in the system architecture, describing all refinements required to make the platform able to secure large data streams. An experimentation is also conducted in order to evaluate the performance of the proposed architecture when integrating security mechanisms.

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Journal articles on the topic 'Interconnect architectures'

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