Log in

Relevant bibliographies by topics / Interconnect architectures

Academic literature on the topic 'Interconnect architectures'

Author: Grafiati

Published: 10 December 2022

Last updated: 28 January 2023

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Contents

Journal articles
Dissertations / Theses
Books
Book chapters
Conference papers
Reports

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Interconnect architectures.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Interconnect architectures"

1

Marrakchi, Zied, Hayder Mrabet, Umer Farooq, and Habib Mehrez. "FPGA Interconnect Topologies Exploration." International Journal of Reconfigurable Computing 2009 (2009): 1–13. http://dx.doi.org/10.1155/2009/259837.

Full text

Abstract:

This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the area, performance, and power of the Tree-based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most efficient in terms of area and static power dissipation, whereas the architectures with higher LUT and cluster size are efficient in terms of performance. We also show that unifying a Mesh with this Tree topology leads to an architecture which has good layout scalability and better interconnect efficiency compared to VPR-style Mesh.

APA, Harvard, Vancouver, ISO, and other styles

2

Farahani, Esmat Kishani, and Reza Sarvari. "Design of n-Tier Multilevel Interconnect Architectures by Using Carbon Nanotube Interconnects." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 10 (October 2015): 2128–34. http://dx.doi.org/10.1109/tvlsi.2014.2360713.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Hollman, Richard. "High Speed Electroplating of 200um High Cu Bumps for Die Stacking Architectures." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, DPC (January 1, 2016): 000611–30. http://dx.doi.org/10.4071/2016dpc-tp13.

Full text

Abstract:

Recent advanced packaging architectures pose a number of challenges for metal deposition by electroplating, including shrinking RDL and pillar interconnects, via fills, and interconnect lines over topography. However, there is a class of die stacking designs which incorporate extremely tall Cu pillars, or

APA, Harvard, Vancouver, ISO, and other styles

4

Suboh, Suboh, Vikram Narayana, Mohamed Bakhouya, Jaafar Gaber, and Tarek El‐Ghazawi. "Methodology for adapting on‐chip interconnect architectures." IET Computers & Digital Techniques 8, no. 3 (May 2014): 109–17. http://dx.doi.org/10.1049/iet-cdt.2013.0021.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Ezhumalai, P., A. Chilambuchelvan, and C. Arun. "Novel NoC Topology Construction for High-Performance Communications." Journal of Computer Networks and Communications 2011 (2011): 1–6. http://dx.doi.org/10.1155/2011/405697.

Full text

Abstract:

Different intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-on-Chip(NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale systems-on-chip (SoC) design. We proposed an idea on building customizing synthesis network—on-chip with the better flow partitioning and also considered power and area reduction as compared to the already presented regular topologies. Hence to improve the performance of SoC, first, we did a performance study of regular interconnect topologies MESH, TORUS, BFT and EBFT, we observed that the overall latency and throughput of the EBFT is better compared to other topologies, The next best in case of latency and throughput is BFT. Experimental results on a variety of NoC benchmarks showed that our synthesis results were achieved reduction in power consumption and average hop count over custom topology implementation.

APA, Harvard, Vancouver, ISO, and other styles

6

Neumann, B., T. von Sydow, H. Blume, and T. G. Noll. "Design and quantitative analysis of parametrisable eFPGA-architectures for arithmetic." Advances in Radio Science 4 (September 6, 2006): 251–57. http://dx.doi.org/10.5194/ars-4-251-2006.

Full text

Abstract:

Abstract. Future SoCs will feature embedded FPGAs (eFPGAs) to enable flexible and efficient implementations of high-throughput digital signal processing applications. Current research projects on and emerging products containing FPGAs are mainly based on "standard FPGA"-architectures that are optimised for a very wide range of applications. The implementation costs of these FPGAs are dominated by a very complex interconnect network. This paper presents a method to improve the efficiency of eFPGAs by tailoring them for a certain application domain using a parametrisable architecture template derived from the results of a systematic evaluation of the requirements of the application domain. Two different architectures are discussed, a reference architecture to illustrate the methodology and possible optimisation measures as well as a specialised arithmetic-oriented eFPGA for applications like correlators, decoders, and filters. For the arithmetic-oriented architecture, a novel logic element (LE) and a special interconnect architecture that was designed with respect to the connectivity characteristics of regular datapaths, are presented. For both architecture templates, physically optimised implementations based on an automatic design approach have been created. As a first cost comparison of these implementations with standard FPGAs, the LE-density (number of logic elements per mm2) is evaluated. For the arithmetic-oriented architecture, the LE-density could be increased by an order of magnitude compared to standard architectures.

APA, Harvard, Vancouver, ISO, and other styles

7

Yanushkevich, S. N., V. P. Shmerko, and B. Steinbach. "Spatial Interconnect Analysis for Predictable Nanotechnologies." Journal of Computational and Theoretical Nanoscience 5, no. 1 (January 1, 2008): 56–69. http://dx.doi.org/10.1166/jctn.2008.007.

Full text

Abstract:

This paper addresses the interconnect problem for the representation of logic networks in spatial dimensions. Interest in spatial interconnects is motivated by the advent of nanotechnologies and by consequent attempts to evaluate and explore the appropriate nanoscale architectures. It have been shown in our previous study that a 3D logic network with target topology can be designed by replacing each elementary logic block in a network by its 3D model. In this paper, we study the problem of the partitioning of these 3D blocks with respect to the constraints of logic function interconnects and hypercube-like topology. We found that decomposition techniques provide flexibility in choosing switching functions for assembling the decomposed sub-networks.

APA, Harvard, Vancouver, ISO, and other styles

8

Krishnan, Gokul, Sumit K. Mandal, Chaitali Chakrabarti, Jae-Sun Seo, Umit Y. Ogras, and Yu Cao. "Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks." ACM Journal on Emerging Technologies in Computing Systems 18, no. 2 (April 30, 2022): 1–22. http://dx.doi.org/10.1145/3460233.

Full text

Abstract:

With the widespread use of Deep Neural Networks (DNNs), machine learning algorithms have evolved in two diverse directions—one with ever-increasing connection density for better accuracy and the other with more compact sizing for energy efficiency. The increase in connection density increases on-chip data movement, which makes efficient on-chip communication a critical function of the DNN accelerator. The contribution of this work is threefold. First, we illustrate that the point-to-point (P2P)-based interconnect is incapable of handling a high volume of on-chip data movement for DNNs. Second, we evaluate P2P and network-on-chip (NoC) interconnect (with a regular topology such as a mesh) for SRAM- and ReRAM-based in-memory computing (IMC) architectures for a range of DNNs. This analysis shows the necessity for the optimal interconnect choice for an IMC DNN accelerator. Finally, we perform an experimental evaluation for different DNNs to empirically obtain the performance of the IMC architecture with both NoC-tree and NoC-mesh. We conclude that, at the tile level, NoC-tree is appropriate for compact DNNs employed at the edge, and NoC-mesh is necessary to accelerate DNNs with high connection density. Furthermore, we propose a technique to determine the optimal choice of interconnect for any given DNN. In this technique, we use analytical models of NoC to evaluate end-to-end communication latency of any given DNN. We demonstrate that the interconnect optimization in the IMC architecture results in up to 6 × improvement in energy-delay-area product for VGG-19 inference compared to the state-of-the-art ReRAM-based IMC architectures.

APA, Harvard, Vancouver, ISO, and other styles

9

GAO, Shanghua, Hiroaki YOSHIDA, Kenshu SETO, Satoshi KOMATSU, and Masahiro FUJITA. "Interconnect-Aware Pipeline Synthesis for Array-Based Architectures." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A, no. 6 (2009): 1464–75. http://dx.doi.org/10.1587/transfun.e92.a.1464.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Palaniappan, Arun, and Samuel Palermo. "Power Efficiency Comparisons of Interchip Optical Interconnect Architectures." IEEE Transactions on Circuits and Systems II: Express Briefs 57, no. 5 (May 2010): 343–47. http://dx.doi.org/10.1109/tcsii.2010.2047319.

Full text

APA, Harvard, Vancouver, ISO, and other styles

More sources

Dissertations / Theses on the topic "Interconnect architectures"

1

Venkatesan, Raguraman. "Multilevel interconnect architectures for gigascale integration (GSI)." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/13370.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Meng, Wang. "Verifying Deadlock-Freedom for Advanced Interconnect Architectures." Thesis, Linköpings universitet, Institutionen för datavetenskap, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-171922.

Full text

Abstract:

Modern advanced Interconnects, such as those orchestrated by the ARM AMBA AXI protocol, can have fatal deadlocks in the connection between Masters and Slaves if those transactions are not properly arranged. There exists some research about the deadlock problems in an on-chip bus system and also methods to avoid those deadlocks which could happen. This project aims to verify those situations could make deadlock happens and also the countermeasures for those deadlocks. In this thesis, the ARM AMBA AXI protocol and countermeasures are modelled in NuSMV. Based on these models, we verified the non-trivial cycles of transactions could cause deadlocks and also some bus techniques which can mitigate deadlock problems efficiently. The results from model checking several instances of the protocol and corresponding countermeasures show the techniques could indeed avoid deadlocks.

APA, Harvard, Vancouver, ISO, and other styles

3

Cook, Jason Todd. "Interconnect Thermal Management of High Power Packaged Electronic Architectures." Thesis, Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5013.

Full text

Abstract:

Packaged microelectronic technology provides an efficient means to connecting high performance chips to PCBs. As area array bump density increases, joule heating will play an important role in chip and interconnect reliability. Joule heating, in addition to chip heating can significantly reduce the clock speed and I/O while increasing noise, electromigration, and leakage power. Direct cooling of the solder bumps is a new innovative approach to removing heat from packaged high heat dissipating chips. This could be used in conjunction with top surface mounted thermal management devices to maximize heat removal. The solder bumps leave a small gap between the packaged chip and PCB, which can be utilized for incorporating a thermal management scheme. Since space is very limited, fans and conventional heat sinks are not practical solutions. Jet impingement presents a unique solution for cooling solder bumps. It has been shown that micro jets can effectively cool the top surface of laptop computer processors. They can also be used to cool the solder bumps and bottom of the chip. Micro jets are easily implemented into the PCB without compromising the electrical leads powering the chip. A prototype printed wiring board containing micro jets was built and a dummy plastic ball grid array packaged chip with a heating element embedded in it was attached on top. A mini compressor supplied the pressure and flow rates needed to push air through the micro jet holes. The pressure, flow rate, and temperatures were measured and analyzed. A numerical model was created based on the results of the experiments. Both the experiments and model show the effectiveness of interconnect cooling.

APA, Harvard, Vancouver, ISO, and other styles

4

Chen, Hongyu. "On-chip interconnect architectures perspectives of layout, circuits, and systems /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2006. http://wwwlib.umi.com/cr/ucsd/fullcit?p3237549.

Full text

Abstract:

Thesis (Ph. D.)--University of California, San Diego, 2006.
Title from first page of PDF file (viewed December 12, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 131-137).

APA, Harvard, Vancouver, ISO, and other styles

5

Bhide, Kanchan P. "DESIGN ENHANCEMENT AND INTEGRATION OF A PROCESSOR-MEMORY INTERCONNECT NETWORK INTO A SINGLE-CHIP MULTIPROCESSOR ARCHITECTURE." UKnowledge, 2004. http://uknowledge.uky.edu/gradschool_theses/253.

Full text

Abstract:

This thesis involves modeling, design, Hardware Description Language (HDL) design capture, synthesis, implementation and HDL virtual prototype simulation validation of an interconnect network for a Hybrid Data/Command Driven Computer Architecture (HDCA) system. The HDCA is a single-chip shared memory multiprocessor architecture system. Various candidate processor-memory interconnect topologies that may meet the requirements of the HDCA system are studied and evaluated related to utilization within the HDCA system. It is determined that the Crossbar network topology best meets the HDCA system requirements and it is therefore used as the processormemory interconnect network of the HDCA system. The design capture, synthesis, implementation and HDL simulation is done in VHDL using XILINX ISE 6.2.3i and ModelSim 5.7g CAD softwares. The design is validated by individually testing against some possible test cases and then integrated into the HDCA system and validated against two different applications. The inclusion of crossbar switch in the HDCA architecture involved major modifications to the HDCA system and some minor changes in the design of the switch. Virtual Prototype testing of the HDCA executing applications when utilizing crossbar interconnect revealed proper functioning of the interconnect and HDCA. Inclusion of the interconnect into the HDCA now allows it to implement dynamic node level reconfigurability and multiple forking functionality.

APA, Harvard, Vancouver, ISO, and other styles

6

Bhaduri, Debayan. "Tools and Techniques for Evaluating Reliability Trade-offs for Nano-Architectures." Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/9918.

Full text

Abstract:

It is expected that nano-scale devices and interconnections will introduce unprecedented level of defects in the substrates, and architectural designs need to accommodate the uncertainty inherent at such scales. This consideration motivates the search for new architectural paradigms based on redundancy based defect-tolerant designs. However, redundancy is not always a solution to the reliability problem, and often too much or too little redundancy may cause degradation in reliability. The key challenge is in determining the granularity at which defect tolerance is designed, and the level of redundancy to achieve a specific level of reliability. Analytical probabilistic models to evaluate such reliability-redundancy trade-offs are error prone and cumbersome, and do not scalewell for complex networks of gates. In this thesiswe develop different tools and techniques that can evaluate the reliability measures of combinational circuits, and can be used to analyze reliability-redundancy trade-offs for different defect-tolerant architectural configurations. In particular, we have developed two tools, one of which is based on probabilistic model checking and is named NANOPRISM, and another MATLAB based tool called NANOLAB. We also illustrate the effectiveness of our reliability analysis tools by pointing out certain anomalies which are counter-intuitive but can be easily discovered by these tools, thereby providing better insight into defecttolerant design decisions. We believe that these tools will help furthering research and pedagogical interests in this area, expedite the reliability analysis process and enhance the accuracy of establishing reliability-redundancy trade-off points.
Master of Science

APA, Harvard, Vancouver, ISO, and other styles

7

Solkowski, Tomasz. "Multimedia workstation architecture with ATM interconnect." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ28851.pdf.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Nousias, Ioannis. "Reconfigurable instruction cell architecture : reconfiguration and interconnects." Thesis, University of Edinburgh, 2009. http://hdl.handle.net/1842/11222.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Dines, Julian A. B. "Optoelectronic computing : interconnects, architectures and a systems demonstrator." Thesis, Heriot-Watt University, 1997. http://hdl.handle.net/10399/647.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Dennison, Larry R. (Larry Robert). "The reliable router : an architecture for fault tolerant interconnect." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/11001.

Full text

Abstract:

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.
Includes bibliographical references (p. 152-154).
by Larry R. Dennison.
Ph.D.

APA, Harvard, Vancouver, ISO, and other styles

More sources

Books on the topic "Interconnect architectures"

1

Dubois, Michel. Cache and Interconnect Architectures in Multiprocessors. Boston, MA: Springer US, 1990.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

2

Bamberg, Lennart, Jan Moritz Joseph, Alberto García-Ortiz, and Thilo Pionteck. 3D Interconnect Architectures for Heterogeneous Technologies. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-98229-4.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Dubois, Michel, and Shreekant S. Thakkar, eds. Cache and Interconnect Architectures in Multiprocessors. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

1953-, Dubois Michel, and Thakkar S. S, eds. Cache and interconnect architectures in multiprocessors. Boston: Kluwer Academic Publishers, 1990.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

5

O'Connor, Ian, and Gabriela Nicolescu, eds. Integrated Optical Interconnect Architectures for Embedded Systems. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4419-6193-8.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Pasricha, Sudeep. On-chip communication architectures: System on chip interconnect. Boston: Elsevier/Morgan Kaufmann, 2008.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

7

Pasricha, Sudeep. On-chip communication architectures: System on chip interconnect. Amsterdam: Elsevier / Morgan Kaufmann Publishers, 2008.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

8

Pasricha, Sudeep. On-Chip Communication Architectures: System on Chip Interconnect. Burlington: Elsevier, 2008.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

9

Solkowski, Tomasz. Multimedia workstation architecture with ATM interconnect]. Ottawa: National Library of Canada = Bibliothèque nationale du Canada, 1999.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

10

Roopchansingh, Ajay. Nearest neighbour interconnect architecture in deep-submicron FPGAs. Ottawa: National Library of Canada, 2002.

Find full text

APA, Harvard, Vancouver, ISO, and other styles

More sources

Book chapters on the topic "Interconnect architectures"

1

Chai, S. M., and D. Scott Wills. "Interconnect-Centric Computer Architectures." In Interconnect Technology and Design for Gigascale Integration, 263–92. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0461-0_7.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Bamberg, Lennart, Jan Moritz Joseph, Alberto García-Ortiz, and Thilo Pionteck. "Interconnect Architectures for 3D Technologies." In 3D Interconnect Architectures for Heterogeneous Technologies, 27–47. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-98229-4_2.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Srini, Vason P. "Crossbar-Multi-Processor Architecture." In Cache and Interconnect Architectures in Multiprocessors, 223–43. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_12.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Teller, Patricia J. "The Cost of TLB Consistency." In Cache and Interconnect Architectures in Multiprocessors, 1–14. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_1.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

James, David V. "SCI (Scalable Coherent Interface) Cache Coherence." In Cache and Interconnect Architectures in Multiprocessors, 189–208. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_10.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Hopper, Andy, Alan Jones, and Dimitris Lioupis. "Performance Evaluation of Wide Shared Bus Multiprocessors." In Cache and Interconnect Architectures in Multiprocessors, 209–22. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_11.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Lioupis, Dimitris, and Nikos Kanellopoulos. "“CHESS” Multiprocessor A Processor-Memory Grid for Parallel Programming." In Cache and Interconnect Architectures in Multiprocessors, 245–57. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_13.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Cheong, Hoichi, and Alexander V. Veidenbaum. "Software-directed Cache Management in Multiprocessors." In Cache and Interconnect Architectures in Multiprocessors, 259–76. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_14.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Cekleov, Michel, Michel Dubois, Jin-Chin Wang, and Fayé A. Briggs. "Virtual-Address Caches in Multiprocessors." In Cache and Interconnect Architectures in Multiprocessors, 15–35. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_2.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Bitar, Philip. "A Critique of Trace-Driven Simulation for Shared-Memory Multiprocessors." In Cache and Interconnect Architectures in Multiprocessors, 37–52. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_3.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Interconnect architectures"

1

Lu, Mei-Chien. "Enabling Packaging Architectures and Interconnect Technologies for Image Sensors." In ASME 2020 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2020. http://dx.doi.org/10.1115/ipack2020-2526.

Full text

Abstract:

Abstract Image sensors have become a crucial technology platform for many applications in the past decades. Market demands continue to grow at a fast pace accelerated by innovations, performance improvement, and new applications. Efficient package architectures and advanced interconnect technologies are among the enablers for the commercialization of image sensors. This study examines how image sensor pixel electronics design and form factor drives innovations in chip stacking and high-density interconnects. 3D chip stacking architectures for CMOS image sensors are analyzed. Cases of image sensors for imaging at visible light, single photon avalanche photodiode (SPAD) for wide dynamic range, rolling shutter and global shutter, and depth sensing and light detection and ranging (LiDAR) are explored based on the pixel electronics requirements. Interconnect methods are also explored. Wafer direct bonding followed by through silicon via (TSV) and hybrid bonding technologies have recently been implemented in the image sensor industry. The preferences and challenges of these two interconnect technologies for image sensor chip stacking are discussed. As TSV technology is relatively mature, this study includes the process flow for one example of the hybrid bonding method. Challenges and future advancement are briefed along with the outlook of the technology and market momentum of image sensors.

APA, Harvard, Vancouver, ISO, and other styles

2

Wiatr, Pawel, Di Yuan, Lena Wosinska, and Jiajia Chen. "Optical Interconnect Architectures for Datacenters." In 2018 IEEE Photonics Conference (IPC). IEEE, 2018. http://dx.doi.org/10.1109/ipcon.2018.8527245.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Markov, I. "Session details: Advanced interconnect architectures." In SLIP07: International Workshop on System Level Interconnect Prediction. New York, NY, USA: ACM, 2007. http://dx.doi.org/10.1145/3246484.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Rabaey, Jan M. "Brain-inspired interconnect architectures and technologies." In 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC). IEEE, 2016. http://dx.doi.org/10.1109/iitc-amc.2016.7507737.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Du Nguyen, H. A., Lei Xie, Jintao Yu, Mottaqiallah Taouil, and Said Hamdioui. "Interconnect networks for resistive computing architectures." In 2017 12th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE, 2017. http://dx.doi.org/10.1109/dtis.2017.7929872.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Ziakas, Dimitrios, Allen Baum, Robert A. Maddox, and Robert J. Safranek. "Intel® QuickPath Interconnect Architectural Features Supporting Scalable System Architectures." In 2010 IEEE 18th Annual Symposium on High-Performance Interconnects (HOTI). IEEE, 2010. http://dx.doi.org/10.1109/hoti.2010.24.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Xie, Lei, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui, and Koen Bertels. "Interconnect networks for memristor crossbar." In 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH'15). IEEE, 2015. http://dx.doi.org/10.1109/nanoarch.2015.7180598.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Harris, Ian G., and Russell Tessier. "Interconnect testing in cluster-based FPGA architectures." In the 37th conference. New York, New York, USA: ACM Press, 2000. http://dx.doi.org/10.1145/337292.337310.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Peter, Eldhose, Janibul Bashir, and Smruti R. Sarangi. "POSTER: BigBus: A Scalable Optical Interconnect." In 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT). IEEE, 2017. http://dx.doi.org/10.1109/pact.2017.18.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Liu, Jiangjiang, Jianyong Zhang, and Nihar Mahapatra. "Interconnect system compression analysis for multi-core architectures." In 2010 IEEE International SOC Conference (SOCC). IEEE, 2010. http://dx.doi.org/10.1109/socc.2010.5784654.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Reports on the topic "Interconnect architectures"

1

Akers, Lex A., Mark R. Walker, and Siamack Haghighi. Design and Training of Limited-Interconnect Architectures. Fort Belvoir, VA: Defense Technical Information Center, July 1991. http://dx.doi.org/10.21236/ada251598.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Akers, Lex. Adaptable Locally-Interconnected Architectures. Fort Belvoir, VA: Defense Technical Information Center, August 1996. http://dx.doi.org/10.21236/ada311781.

Full text

APA, Harvard, Vancouver, ISO, and other styles

3

Malas, D., and J. Livingood, eds. Session PEERing for Multimedia INTerconnect (SPEERMINT) Architecture. RFC Editor, November 2011. http://dx.doi.org/10.17487/rfc6406.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Murdocca, Miles, Apostolos Gerasoulis, and Saul Levy. Novel Optical Computer Architecture Utilizing Reconfigurable Interconnects. Fort Belvoir, VA: Defense Technical Information Center, October 1991. http://dx.doi.org/10.21236/ada244057.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Drake, J., N. Bitar, G. Swallow, D. Ceccarelli, and X. Zhang. Problem Statement and Architecture for Information Exchange between Interconnected Traffic-Engineered Networks. Edited by A. Farrel. RFC Editor, July 2016. http://dx.doi.org/10.17487/rfc7926.

Full text

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!