Dissertations / Theses on the topic 'Integrated services digital networks; ISDN; broadband communication'

A structured organisation of tasks, possibly hierarchical, is necessary in a BISDN network due to the complexity of the system, its large dimension and its physical distribution in space. Feedback (possibly supplemented by feedforward) control has an essential role in the effective and efficient control of BISDN. Additionally, due to the nonstationarity of the network and its complexity, a number of different (dynamic) modelling techniques are required at each level of the hierarchy. Also, to increase the efficiency of the network and allow flexibility in the control actions (by extending the control horizon) the (dynamic) tradeoff between service-rate, buffer-space, cell-delay and cell-loss must be exploited. In this thesis we take account of the above and solve three essential control problems, required for the effective control of BISDN. These solutions are suitable for both stationary and nonstationary conditions. Also, they are suitable for implementation in a decentralised coordinated form, that can form a part of a hierarchical organisation of control tasks. Thus, the control schemes aim for global solutions, yet they are not limited by the propagation delay, which can be high in comparison to the dynamics of the controlled events. Specifically, novel control approaches to the problems of Connection Admission Control (CAC), flow control and service-rate control are developed. We make use of adaptive feedback and adaptive feedforward control methodologies to solve the combined CAC and flow control problem. Using a novel control concept, based on only two groups of traffic (the controllable and uncontrollable group) we formulate a problem aimed at high (unity) utilisation of resources while maintaining quality of service at prescribed levels. Using certain assumptions we have proven that in the long term the regulator is stable and that it converges to zero regulation error. Bounds on operating conditions are also derived, and using simulation we show that high utilisation can be achieved as suggested by the theory, together with robustness for unforeseen traffic connections and disconnections. Even with such a high efficiency and strong properties on the quality of service provided, the only traffic descriptor required from the user is that of the peak rate of the uncontrollable traffic. A novel scheme for the dynamic control of service-rate is formulated, using feedback from the network queues. We use a unified dynamic fluid flow equation to describe the virtual path (VP) and hence formulate two illustrative examples for the control of service-rate (at the VP level). One is a nonlinear optimal multilevel implementation, that features a coordinated decentralised solution. The other is a single level implementation that turns out to be computationally complex. Therefore, for the single level implementation the costate equilibrium solution is also derived. For the optimal policies derived, we discuss their implementation complexity and provide implementable solutions. Their performance is evaluated using simulation. Additionally, using an ad hoc approach we have extended previous published works on the decentralised coordinated control of large scale nonlinear systems to also deal with time-delayed systems.

The research presented in this thesis aims to demonstrate that fuzzy logic is a useful tool for developing mechanisms for controlling traffc flow in ATM based multimedia networks to maintain quality of service (QoS) requirements and maximize resource utilization. The study first proposes a hierarchical, multilevel control structure for ATM networks to exploit the reported strengths of fuzzy logic at various control levels. Then, an extensive development and evaluation is presented for a subset of the proposed control architecture at the congestion control level. An ATM based multimedia network must have quite sophisticated traffc control capabilities to effectively handle the requirements of a dynamically varying mixture of voice, video and data services while meeting the required levels of performance. Feedback control techniques have an essential role for the effective and efficient management of the resources of ATM networks. However, development of conventional feedback control techniques relies on the availability of analytical system models. The characteristics of ATM networks and the complexity of service requirements cause the analytical modeling to be very difficult, if not impossible. The lack of realistic dynamic explicit models leads to substantial problems in developing control solutions for B-ISDN networks. This limits the ability of conventional techniques to directly address the control objectives for ATM networks. In the literature, several connection admission and congestion control methods for B-ISDN networks have been reported, and these have achieved mixed success. Usually they either assume heavily simplified models, or they are too complicated to implement, mainly derived using probabilistic (steady-state) models. Fuzzy logic controllers, on the other hand, have been applied successfully to the task of controlling systems for which analytical models are not easily obtainable. Fuzzy logic control is a knowledge-based control strategy that can be utilized when an explicit model of a system is not available or, the model itself, if available, is highly complex and nonlinear. In this case, the problem of control system design is based on qualitative and/or empirically acquired knowledge regarding the operation of the system. Representation of qualitative or empirically acquired knowledge in a fuzzy logic controller is achieved by linguistic expressions in the form of fuzzy relational equations. By using fuzzy relational equations, classifications related to system parameters can be derived without explicit description. The thesis presents a new predictive congestion control scheme, Fuzzy Explicit Rate Marking (FERM), which aims to avoid congestion, and by doing so minimize the cell losses, attain high server utilization, and maintain the fair use of links. The performance of the FERM scheme is extremely competitive with that of control schemes developed using traditional methods over a considerable period of time. The results of the study demonstrate that fuzzy logic control is a highly effective design tool for this type of problems, relative to the traditional methods. When controlled systems are highly nonlinear and complex, it keeps the human insight alive and accessible at the lower levels of the control hierarchy, and so higher levels can be built on this understanding. Additionally, the FERM scheme has been extended to adaptively tune (A-FERM) so that continuous automatic tuning of the parameters can be achieved, and thus be more adaptive to system changes leading to better utilization of network bandwidth. This achieves a level of robustness that is not exhibited by other congestion control schemes reported in the literature. In this work, the focus is on ATM networks rather than IP based networks. For historical reasons, and due to fundamental philosophical differences in the (earlier) approach to congestion control, the research for control of TCP/IP and ATM based networks proceeded separately. However, some convergence between them has recently become evident. In the TCP/IP literature proposals have appeared on active queue management in routers, and Explicit Congestion Notication (ECN) for IP. It is reasonably expected that, the algorithms developed in this study will be applicable to IP based multimedia networks as well.

International Telemetering Conference Proceedings / October 25-28, 1993 / Riviera Hotel and Convention Center, Las Vegas, Nevada<br>As technology progresses we are faced with ever increasing volumes and rates of raw and processed telemetry data along with digitized high resolution video and the less demanding areas of video conferencing, voice communications and general LAN-based data communications. The distribution of all this data has traditionally been accomplished by solutions designed to each particular data type. With the advent of Asynchronous Transfer Modes or ATM, a single technology now exists for providing an integrated solution to distributing these diverse data types. This allows an integrated set of switches, transmission equipment and fiber optics to provide multi-session connection speeds of 622 Megabits per second. ATM allows for the integration of many of the most widely used and emerging low, medium and high speed communications standards. These include SONET, FDDI, Broadband ISDN, Cell Relay, DS-3, Token Ring and Ethernet LANs. However, ATM is also very well suited to handle unique data formats and speeds, as is often the case with telemetry data. Additionally, ATM is the only data communications technology in recent times to be embraced by both the computer and telecommunications industries. Thus, ATM is a single solution for connectivity within a test center, across a test range, or between ranges. ATM can be implemented in an evolutionary manner as the needs develop. This means the rate of capital investment can be gradual and older technologies can be replaced slowly as they become the communications bottlenecks. However, success of this evolution requires some planning now. This paper provides an overview of ATM, its application to test ranges and telemetry distribution. A road map is laid out which can guide the evolutionary changeover from today's technologies to a full ATM communications infrastructure. Special applications such as the support of high performance multimedia workstations are presented.

Since the emergence of the Asynchronous Transfer Mode ( A TM ) concept, various switching architectures have been proposed. The multistage interconnection networks have been proposed for the switching architecture under the A TM environment. In this thesis, we propose a new model for the performance analysis of an A TM switching fabric based on single-buffered Banyan network. In this model, we use a three-state, i.e., "empty", "new" and "blocked" Markov chain model to describe the behavior of the buffer within a switching element. In addition to traditional statistical analysis including throughput and delay, we also examine the delay variation. Performance results show that the proposed model is more accurate in describing the switch behavior under uniform traffic environment in comparison with the "two-state" Markov chain model developed by Jenq, et. al.[4] [6] . Based on the "three-state" model, we study a packet priority scheme which gives the blocked packet higher priority to be routed forward during contention. It is found that the standard deviation of the network delay is reduced by about 30%.

The growth of Asynchronous Transfer Mode (ATM) was considered to be the ideal carrier of the high bandwidth applications like video on demand and multimedia e-learning. ATM emerged commercially in the beginning of the 1990's. It was designed to provide a different quality of service at a speed up 100 Gbps for both real time and non real time application. The turn of the 90's saw a variety of technologies being developed. This project analyzes these technologies, compares them to the Asynchronous Transfer Mode and assesses the future of ATM.

by Chi-yin Tse.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1995.<br>Includes bibliographical references (leaves 118-[121]).<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Video Compression and Transport --- p.2<br>Chapter 1.2 --- VBR-CBR Adaptation of Video Traffic --- p.5<br>Chapter 1.3 --- Research Contributions --- p.7<br>Chapter 1.3.1 --- Spatial Smoothing: Video Aggregation --- p.8<br>Chapter 1.3.2 --- Temporal Smoothing: A Control-Theoretic Study。 --- p.8<br>Chapter 1.4 --- Organization of Thesis --- p.9<br>Chapter 2 --- Preliminaries --- p.13<br>Chapter 2.1 --- MPEG Compression Scheme --- p.13<br>Chapter 2.2 --- Problems of Transmitting MPEG Video --- p.17<br>Chapter 2.3 --- Two-layer Coding and Transport Strategy --- p.19<br>Chapter 2.3.1 --- Framework of MPEG-based Layering --- p.19<br>Chapter 2.3.2 --- Transmission of GS and ES --- p.20<br>Chapter 2.3.3 --- Problems of Two-layer Video Transmission --- p.20<br>Chapter 3 --- Video Aggregation --- p.24<br>Chapter 3.1 --- Motivation and Basic Concept of Video Aggregation --- p.25<br>Chapter 3.1.1 --- Description of Video Aggregation --- p.28<br>Chapter 3.2 --- MPEG Video Aggregation System --- p.29<br>Chapter 3.2.1 --- Shortcomings of the MPEG Video Bundle Scenario with Two-Layer Coding and Cell-Level Multiplexing --- p.29<br>Chapter 3.2.2 --- MPEG Video Aggregation --- p.31<br>Chapter 3.2.3 --- MPEG Video Aggregation System Architecture --- p.33<br>Chapter 3.3 --- Variations of MPEG Video Aggregation System --- p.35<br>Chapter 3.4 --- Experimental Results --- p.38<br>Chapter 3.4.1 --- Comparison of Video Aggregation and Cell-level Multi- plexing --- p.40<br>Chapter 3.4.2 --- Varying Amount of the Allocated Bandwidth --- p.48<br>Chapter 3.4.3 --- Varying Number of Sequences --- p.50<br>Chapter 3.5 --- Conclusion --- p.53<br>Chapter 3.6 --- Appendix: Alternative Implementation of MPEG Video Aggre- gation --- p.53<br>Chapter 3.6.1 --- Profile Approach --- p.54<br>Chapter 3.6.2 --- Bit-Plane Approach --- p.54<br>Chapter 4 --- A Control-Theoretic Study of Video Traffic Adaptation --- p.58<br>Chapter 4.1 --- Review of Previous Adaptation Schemes --- p.60<br>Chapter 4.1.1 --- A Generic Model for Adaptation Scheme --- p.60<br>Chapter 4.1.2 --- Objectives of Adaptation Controller --- p.61<br>Chapter 4.2 --- Motivation for Control-Theoretic Study --- p.64<br>Chapter 4.3 --- Linear Feedback Controller Model --- p.64<br>Chapter 4.3.1 --- Encoder Model --- p.65<br>Chapter 4.3.2 --- Adaptation Controller Model --- p.69<br>Chapter 4.4 --- Analysis --- p.72<br>Chapter 4.4.1 --- Stability --- p.73<br>Chapter 4.4.2 --- Robustness against Coding-mode Switching --- p.83<br>Chapter 4.4.3 --- Unit-Step Responses and Unit-Sample Responses --- p.84<br>Chapter 4.5 --- Implementation --- p.91<br>Chapter 4.6 --- Experimental Results --- p.95<br>Chapter 4.6.1 --- Overall Performance of the Adaptation Scheme --- p.97<br>Chapter 4.6.2 --- Weak-Control verus Strong-Control --- p.99<br>Chapter 4.6.3 --- Varying Amount of Reserved Bandwidth --- p.101<br>Chapter 4.7 --- Conclusion --- p.103<br>Chapter 4.8 --- Appendix I: Further Research --- p.103<br>Chapter 4.9 --- Appendix II: Review of Previous Adaptation Schemes --- p.106<br>Chapter 4.9.1 --- Watanabe. et. al.'s Scheme --- p.106<br>Chapter 4.9.2 --- MPEG's Scheme --- p.107<br>Chapter 4.9.3 --- Lee et.al.'s Modification --- p.109<br>Chapter 4.9.4 --- Chen's Adaptation Scheme --- p.110<br>Chapter 5 --- Conclusion --- p.116<br>Bibliography --- p.118

Thesis (Ph.D.) - Swinburne University of Technology, School of Biophysical Sciences and Electrical Engineering, 2000.<br>Submitted for the degree of Doctor of Philosophy, School of Biophysical Science & Electrical Engineering, 2000. Typescript. Includes bibliographical references (p. 133-145).

by Yeung Ming Sang.<br>Thesis (Ph.D.)--Chinese University of Hong Kong, 1994.<br>Includes bibliographical references (leaves 191-[201]).<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Background --- p.1<br>Chapter 1.1.1 --- Broadband Integrated Services Network --- p.1<br>Chapter 1.1.2 --- ATM Switching Technology --- p.3<br>Chapter 1.2 --- Broadband ATM Switching ´ؤ A Review --- p.4<br>Chapter 1.2.1 --- Shared Memory Switches --- p.5<br>Chapter 1.2.2 --- Shared Medium Switches --- p.5<br>Chapter 1.2.3 --- Space-division Type Switches --- p.6<br>Chapter 1.3 --- Motivation and Contributions --- p.13<br>Chapter 1.4 --- Overview of the Thesis --- p.13<br>Chapter 2 --- Pipeline Banyan Switch Architecture --- p.15<br>Chapter 2.1 --- Switch Architecture --- p.15<br>Chapter 2.2 --- Switch Operation --- p.17<br>Chapter 2.3 --- Switch Design --- p.19<br>Chapter 2.4 --- "Priority, Broadcasting and Multicasting Mechanisms" --- p.21<br>Chapter 2.5 --- Switch Speed Reduction at the Control Plane --- p.23<br>Chapter 3 --- Performance Evaluation of Pipeline Banyan --- p.27<br>Chapter 3.1 --- Performance under Uniform and Independent Traffic Pattern --- p.27<br>Chapter 3.1.1 --- Analysis of Packet Loss Performance --- p.27<br>Chapter 3.1.2 --- Throughput Performance --- p.32<br>Chapter 3.1.3 --- Delay Performance --- p.36<br>Chapter 3.1.4 --- Comparison of Loss Performance of Banyan-type Networks --- p.37<br>Chapter 3.1.5 --- Output Queueing Capability --- p.41<br>Chapter 3.2 --- Performance of the Switch under Special Traffic Pattern --- p.45<br>Chapter 3.2.1 --- Performance under Bursty Traffic --- p.45<br>Chapter 3.2.2 --- Performance under Hot Spot Traffic --- p.48<br>Chapter 3.2.3 --- Performance under Point-to-Point Traffic --- p.51<br>Chapter 3.2.4 --- Performance under Permutation Traffic --- p.52<br>Chapter 3.3 --- Switch Complexity Discussion --- p.54<br>Chapter 4 --- Multi-Channel Pipeline Banyan (MCPB) --- p.57<br>Chapter 4.1 --- Background --- p.57<br>Chapter 4.2 --- Switch Architecture --- p.59<br>Chapter 4.3 --- Performance Evaluation --- p.64<br>Chapter 4.3.1 --- Packet loss probability --- p.64<br>Chapter 4.3.2 --- Throughput performance --- p.69<br>Chapter 4.3.3 --- Delay performance --- p.69<br>Chapter 4.4 --- Application of MCPB --- p.71<br>Chapter 4.4.1 --- ATM Cross-connect --- p.71<br>Chapter 4.4.2 --- Switch Interconnection Fabric --- p.71<br>Chapter 5 --- VLSI Implementation --- p.75<br>Chapter 5.1 --- Outline of a typical ATM switching system --- p.75<br>Chapter 5.1.1 --- Line Interface Module --- p.75<br>Chapter 5.1.2 --- System Manager Module --- p.77<br>Chapter 5.1.3 --- Switch Module --- p.78<br>Chapter 5.2 --- "VLSI Design Technology, Procedures and Tools" --- p.78<br>Chapter 5.2.1 --- Design Technology --- p.78<br>Chapter 5.2.2 --- Procedures and Tools --- p.79<br>Chapter 5.3 --- Logic Design of ATM Switch Module --- p.80<br>Chapter 5.3.1 --- Switching Element in Control Plane --- p.80<br>Chapter 5.3.2 --- Switching Element in Data Plane --- p.86<br>Chapter 5.3.3 --- Clock Generator for Synchronization --- p.93<br>Chapter 5.3.4 --- Schematic of Control Plane --- p.98<br>Chapter 5.3.5 --- Schematic of Data Plane --- p.98<br>Chapter 5.3.6 --- Timing Diagrams --- p.98<br>Chapter 5.4 --- Chip Summary --- p.107<br>Chapter 5.5 --- Experiences --- p.109<br>Chapter 5.5.1 --- Core Size Limitation --- p.109<br>Chapter 5.5.2 --- Pin Count Limitation --- p.110<br>Chapter 5.5.3 --- Speed Limitation --- p.111<br>Chapter 5.5.4 --- Other Design Considerations --- p.111<br>Chapter 5.6 --- Discussions --- p.112<br>Chapter 6 --- Dynamic Priority Schemes for Fast Packet Switches --- p.114<br>Chapter 6.1 --- Motivation --- p.114<br>Chapter 6.2 --- Switch Architecture --- p.118<br>Chapter 6.3 --- QCPD: Queueing Controlled Priority Discipline --- p.121<br>Chapter 6.3.1 --- Algorithm QCPD --- p.121<br>Chapter 6.4 --- BCPD: Blocking Controlled Priority Discipline --- p.122<br>Chapter 6.4.1 --- Algorithm BCPD_FT --- p.122<br>Chapter 6.4.2 --- Delay Guarantee by Algorithm BCPD_FT --- p.123<br>Chapter 6.4.3 --- Algorithm BCPD_DT --- p.126<br>Chapter 6.4.4 --- Delay Guarantee by Algorithm BCPD_DT --- p.128<br>Chapter 6.5 --- HCPD: Hybrid Controlled Priority Discipline --- p.134<br>Chapter 6.5.1 --- Algorithms HCPD_FT and HCPD_DT --- p.135<br>Chapter 6.6 --- Performance Studies --- p.136<br>Chapter 6.6.1 --- Performance Comparison of the Priority Schemes --- p.136<br>Chapter 6.6.2 --- Cell Loss Performance of HCPD_DT --- p.140<br>Chapter 6.6.3 --- Input Queue Distribution of HCPD_DT --- p.142<br>Chapter 6.6.4 --- Delay Bound of HCPD_DT --- p.144<br>Chapter 6.6.5 --- Performance of HCPD_DT under Priority Traffic --- p.148<br>Chapter 6.7 --- The use of HCPD_DT in Pipeline Banyan --- p.152<br>Chapter 6.8 --- Conclusion --- p.153<br>Chapter 7 --- Summary and Future Work --- p.155<br>Chapter 7.1 --- Summary --- p.155<br>Chapter 7.2 --- Future Work --- p.156<br>Chapter A --- Verilog HDL descriptions of 16x16 Pipeline Banyan --- p.158<br>Chapter B --- User's Guide of 16x16 Pipeline Banyan Chip Set --- p.182<br>Chapter B.l --- Specification --- p.182<br>Chapter B.2 --- Control Plane Chip and Data Plane Chip Pinout --- p.183<br>Chapter B.2.1 --- Control Plane Chip Pinout --- p.183<br>Chapter B.2.2 --- Data Plane Chip Pinout --- p.183<br>Chapter B.3 --- Signal Descriptions --- p.186<br>Chapter B.3.1 --- Signal Descriptions of Control Plane Chip --- p.186<br>Chapter B.3.2 --- Signal Descriptions of Data Plane Chip --- p.187<br>Chapter B.4 --- Connection Examples --- p.188<br>Bibliography --- p.191

by Philip Pak-tung To.<br>Thesis (Ph.D.)--Chinese University of Hong Kong, 1997.<br>Includes bibliographical references (p. 126).<br>Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.<br>Mode of access: World Wide Web.

by Shum Kam Hong.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1992.<br>Includes bibliographical references (leaves 125-131).<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Background --- p.1<br>Chapter 1.2 --- Outline of the thesis --- p.6<br>Chapter 1.3 --- Current Art in Packet Switching --- p.9<br>Chapter 2 --- Management of Control Information --- p.17<br>Chapter 2.1 --- Inter-node Exchange of Link Congestion Status --- p.21<br>Chapter 2.2 --- Consistency of Control Information --- p.24<br>Chapter 2.3 --- Alternate Format of Control Information --- p.26<br>Chapter 3 --- Traffic Flow Control --- p.29<br>Chapter 3.1 --- Control of Traffic Influx into the Network --- p.29<br>Chapter 3.2 --- Control of Traffic Loading from the Node --- p.30<br>Chapter 3.3 --- Flow Control for Connection Oriented Traffic --- p.32<br>Chapter 3.4 --- Judgement of Link Status --- p.38<br>Chapter 3.5 --- Starvation-free and Deadlock-free --- p.42<br>Chapter 4 --- Call Set-up Algorithm Traffic Modelling --- p.47<br>Chapter 4.1 --- Basic Algorithm --- p.47<br>Chapter 4.2 --- Minimization of Bandwidth Overhead --- p.48<br>Chapter 4.3 --- Two-way Transmission --- p.51<br>Chapter 4.4 --- Traffic Modelling --- p.52<br>Chapter 4.4.1 --- Aggregate Traffic Models --- p.53<br>Chapter 4.4.2 --- Traffic Burstiness --- p.57<br>Chapter 5 --- Parameters Tuning and Analysis --- p.76<br>Chapter 5.1 --- Scheme I : Scout Pumping --- p.76<br>Chapter 5.2 --- Scheme II : Speed-up Scout Pumping --- p.85<br>Chapter 5.3 --- Blocking Probability --- p.90<br>Chapter 5.4 --- Scout Stream Collision --- p.92<br>Chapter 6 --- Simulation Modelling & Performance Evaluation --- p.96<br>Chapter 6.1 --- The Network Simulator --- p.96<br>Chapter 6.1.1 --- Simulation Event Scheduling --- p.97<br>Chapter 6.1.2 --- Input Traffic Regulation --- p.100<br>Chapter 6.1.3 --- Actual Offered Load --- p.101<br>Chapter 6.1.4 --- Static and Dynamic Parameters --- p.103<br>Chapter 6.2 --- Simulation Results --- p.107<br>Chapter 7 --- Conclusions --- p.123<br>Chapter A --- List of Symbols --- p.132

by Timothy Kai-Cheung Chung.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1996.<br>Includes bibliographical references.<br>Chapter 1. --- INTRODUCTION --- p.1<br>Chapter 2. --- ASYNCHRONOUS TRANSFER MODE SWITCHING --- p.4<br>Chapter 2.1 --- Transfer Modes --- p.4<br>Chapter 2.1.1 --- Circuit Switching --- p.4<br>Chapter 2.1.2 --- ATM Switching --- p.6<br>Chapter 2.1.3 --- Packet Switching --- p.8<br>Chapter 2.2 --- Different Types of ATM Switching System --- p.8<br>Chapter 2.2.1 --- Central Control Type --- p.9<br>Chapter 2.2.2 --- Self-Routing Type --- p.9<br>Chapter 2.3 --- Self-Routing Non-Buffering ATM Switching Node --- p.10<br>Chapter 3. --- FUNCTIONAL DESCRIPTION OF MODULE ´بA´ة --- p.16<br>Chapter 3.1 --- ATM Cell Format --- p.17<br>Chapter 3.2 --- Concentrator --- p.17<br>Chapter 3.3 --- Routing Cell --- p.19<br>Chapter 4. --- PHYSICAL STRUCTURE OF MODULE ´بA´ة --- p.23<br>Chapter 4.1 --- Clocking Scheme --- p.23<br>Chapter 4.2 --- Concentrator --- p.25<br>Chapter 4.2.1 --- 2-by-2 Sorter --- p.25<br>Chapter 4.2.2 --- Input Framer --- p.30<br>Chapter 4.2.3 --- Data Buffer --- p.38<br>Chapter 4.3 --- Routing Cell --- p.38<br>Chapter 4.3.1 --- Type I Router --- p.39<br>Chapter 4.3.2 --- Type II Router --- p.42<br>Chapter 4.4 --- Block By-Passed Function --- p.43<br>Chapter 5. --- SIMULATION AND TEST --- p.48<br>Chapter 5.1 --- Computer Simulation --- p.48<br>Chapter 5.2 --- Actual Chip Testing --- p.53<br>Chapter 5.3 --- Measurement Results --- p.55<br>Chapter 5.3.1 --- Functionality --- p.55<br>Chapter 5.3.2 --- Maximum Clock Frequency --- p.60<br>Chapter 5.3.3 --- Power Dissipation --- p.61<br>Chapter 6. --- CONCLUSION --- p.63<br>Chapter A. --- BRIEF HISTORY OF ATM SWITCH ARCHITECTURE DEVELOPMENT --- p.65<br>Chapter B. --- BIBLIOGRAPHY --- p.66<br>Chapter C. --- A N-WELL CMOS PROCESS --- p.70<br>Chapter D. --- CADENCE DESIGN FLOW --- p.73<br>Chapter E. --- YERILOG SIMULATION PROGRAMS --- p.77<br>Chapter F. --- SCHEMATIC DIAGRAMS --- p.100