Relevant bibliographies by topics / Integrated reconfigurable electronics interface

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Integrated reconfigurable electronics interface'

Author: Grafiati
Published: 25 May 2024

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Integrated reconfigurable electronics interface.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Integrated reconfigurable electronics interface"

1

Shi, Chuanqian, Zhanan Zou, Zepeng Lei, Pengcheng Zhu, Wei Zhang, and Jianliang Xiao. "Heterogeneous integration of rigid, soft, and liquid materials for self-healable, recyclable, and reconfigurable wearable electronics." Science Advances 6, no. 45 (November 2020): eabd0202. http://dx.doi.org/10.1126/sciadv.abd0202.

Full text
Abstract:
Wearable electronics can be integrated with the human body for monitoring physical activities and health conditions, for human-computer interfaces, and for virtual/augmented reality. We here report a multifunctional wearable electronic system that combines advances in materials, chemistry, and mechanics to enable superior stretchability, self-healability, recyclability, and reconfigurability. This electronic system heterogeneously integrates rigid, soft, and liquid materials through a low-cost fabrication method. The properties reported in this wearable electronic system can find applications in many areas, including health care, robotics, and prosthetics, and can benefit the well-being, economy, and sustainability of our society.
APA, Harvard, Vancouver, ISO, and other styles
2

Chiu, J. C., and T. L. Yeh. "IRES: An integrated software and hardware interface framework for reconfigurable embedded system." IET Computers & Digital Techniques 4, no. 1 (January 1, 2010): 27–37. http://dx.doi.org/10.1049/iet-cdt.2009.0010.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Guo, Zhiyong, Qiang Li, Haiqi Liu, Bo Yan, and Guangjun Li. "An integrated low-voltage ultra-low-power reconfigurable hardware interface in 0.18-µm CMOS." International Journal of Electronics 98, no. 6 (June 2011): 685–98. http://dx.doi.org/10.1080/00207217.2011.567038.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Bédard, Anne-Catherine, Andrea Adamo, Kosi C. Aroh, M. Grace Russell, Aaron A. Bedermann, Jeremy Torosian, Brian Yue, Klavs F. Jensen, and Timothy F. Jamison. "Reconfigurable system for automated optimization of diverse chemical reactions." Science 361, no. 6408 (September 20, 2018): 1220–25. http://dx.doi.org/10.1126/science.aat0650.

Full text
Abstract:
Chemical synthesis generally requires labor-intensive, sometimes tedious trial-and-error optimization of reaction conditions. Here, we describe a plug-and-play, continuous-flow chemical synthesis system that mitigates this challenge with an integrated combination of hardware, software, and analytics. The system software controls the user-selected reagents and unit operations (reactors and separators), processes reaction analytics (high-performance liquid chromatography, mass spectrometry, vibrational spectroscopy), and conducts automated optimizations. The capabilities of this system are demonstrated in high-yielding implementations of C-C and C-N cross-coupling, olefination, reductive amination, nucleophilic aromatic substitution (SNAr), photoredox catalysis, and a multistep sequence. The graphical user interface enables users to initiate optimizations, monitor progress remotely, and analyze results. Subsequent users of an optimized procedure need only download an electronic file, comparable to a smartphone application, to implement the protocol on their own apparatus.
APA, Harvard, Vancouver, ISO, and other styles
5

Dean, Robert N., Colin B. Stevens, and John J. Tatarchuk. "A Current-Controlled PCB Integrated MEMS Tilt Mirror." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (January 1, 2014): 000588–608. http://dx.doi.org/10.4071/2014dpc-ta32.

Full text
Abstract:
Introduction: MEMS Tilt Mirror - a miniature planar micro-mirror that can experience a 1-D or 2-D tilt in response to a control signal. Commonly used technologies- electrostatic, piezoelectric, electrothermal bimorph. Applications - laser beam steering, interferometers, dynamic signal analyzers, opticcal cross-connect switches. This paper describes the design, key features and applications of a System On Chip (SOC) ASIC (Application Specific Integrated Circuit) that has been developed under an Air Force SBIR program. The SOC device has been implemented by Honeywell International using their High Temperature SOI (Silicon On Insulator) Process. The objective of the Air Force SBIR program {1} was to investigate the potential for use of available High Temperature SOI technology devices for aerospace propulsion control system applications. Several prototype designs implemented by Embedded Systems LLC (ES-LLC) using available SOI devices identified significant limitations in the performance capability and level of integration. The diversity of propulsion system interfacing requirements demanded generic solutions so that they could be deployed in multiple applications without changes. The available devices were also not affordable due to the limited size of the market for this technology. It was therefore decided to develop a generic, reconfigurable SOC chipset {2} that could be implemented using Honeywell's HT200 Family of ASIC Gate Arrays. The paper will describe the architecture and key features of the SOC chipset solution which can be reconfigured to interface with most typical aerospace control system sensors and actuators. The SOC chipset captures all of the necessary functions required to interface with sensors such as RTD (resistance Temperature Detectors), Strain Gauges (SG) and thermocouples (TC), mass flow, speed and LVDT (Linear Variable Differential Transducer) position. The excitation circuitry required to power these interfaces is embedded in the chipset and can be reconfigured as required. The SOC chipset also contains all of the pre- and post-processing functions to convert electrical signals into digital words and send them on a data bus under the control of a host microprocessor. The SOC chipset can be powered from a Mil-Std 704F compliant power source or a conditioned DC power source. The SOC chipset when combined with other external devices can be implemented as a “Smart Node” for localized management of sensors and actuators as a part of a distributed architecture or used as a scalable building block in a more complex function such as a FADEC (Full Authority Digital Engine Control). The SOC chipset thus completes the set of all High Temperature SOI Integrated circuits required for implementation of typical Smart Nodes. It is believed that the versatility of the SOC chipset makes it a well suited, affordable, scalable building block for not only aerospace controls but also for diverse applications such as down-hole drilling, energy exploration, wind farms etc. where high temperature electronics is required.
APA, Harvard, Vancouver, ISO, and other styles
6

Primiani, Rurik A., Kenneth H. Young, André Young, Nimesh Patel, Robert W. Wilson, Laura Vertatschitsch, Billie B. Chitwood, Ranjani Srinivasan, David MacMahon, and Jonathan Weintroub. "SWARM: A 32 GHz Correlator and VLBI Beamformer for the Submillimeter Array." Journal of Astronomical Instrumentation 05, no. 04 (December 2016): 1641006. http://dx.doi.org/10.1142/s2251171716410063.

Full text
Abstract:
A 32[Formula: see text]GHz bandwidth VLBI capable correlator and phased array has been designed and deployed a at the Smithsonian Astrophysical Observatory’s Submillimeter Array (SMA). The SMA Wideband Astronomical ROACH2 Machine (SWARM) integrates two instruments: a correlator with 140[Formula: see text]kHz spectral resolution across its full 32[Formula: see text]GHz band, used for connected interferometric observations, and a phased array summer used when the SMA participates as a station in the Event Horizon Telescope (EHT) very long baseline interferometry (VLBI) array. For each SWARM quadrant, Reconfigurable Open Architecture Computing Hardware (ROACH2) units shared under open-source from the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER) are equipped with a pair of ultra-fast analog-to-digital converters (ADCs), a field programmable gate array (FPGA) processor, and eight 10 Gigabit Ethernet (GbE) ports. A VLBI data recorder interface designated the SWARM digital back end, or SDBE, is implemented with a ninth ROACH2 per quadrant, feeding four Mark6 VLBI recorders with an aggregate recording rate of 64 Gbps. This paper describes the design and implementation of SWARM, as well as its deployment at SMA with reference to verification and science data.
APA, Harvard, Vancouver, ISO, and other styles
7

Bal, Amrita, Jeffery W. Baur, Darren J. Hartl, Geoffrey J. Frank, Thao Gibson, Hong Pan, and Gregory H. Huff. "Multi-Layer and Conformally Integrated Structurally Embedded Vascular Antenna (SEVA) Arrays." Sensors 21, no. 5 (March 4, 2021): 1764. http://dx.doi.org/10.3390/s21051764.

Full text
Abstract:
This work presents the design and fabrication of two multi-element structurally embedded vascular antennas (SEVAs). These are achieved through advances in additively manufactured sacrificial materials and demonstrate the ability to embed vascular microchannels in both planar and complex-curved epoxy-filled quartz fiber structural composite panels. Frequency-reconfigurable antennas are formed by these structures through the pressure-driven transport of liquid metal through the embedded microchannels. The planar multi-layer topology examines the ability to fabricate two co-located radiating structures separated by a single ply of quartz fabric within the composite layup. The multi-element linear array topology composed of microchannels embedded on to a single-layer are used to demonstrate the ability to conformally-integrate these channels into a complex curved surface that mimics an array of antennas on the leading edge of an Unmanned Aerial Vehicle (UAV). A parallel-strip antipodal dipole feed structure provides excitation and serves as the interface for fluid displacement within the microchannels to facilitate reconfiguration. The nominal design of the SEVAs achieve over a decade of frequency reconfiguration with respect to the fundamental dipole mode of the antenna. Experimental and predicted results demonstrate the operation for canonical states of the antennas. Additional results for the array topology demonstrate beam steering and contiguous operation of interconnected elements in the multi-element structure.
APA, Harvard, Vancouver, ISO, and other styles
8

Tulpule, Bhal, Bruce Ohme, Mark Larson, Al Behbahani, John Gerety, and Al Steines. "A System On Chip (SOC) ASIC chipset for Aerospace and Energy Exploration Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000278–84. http://dx.doi.org/10.4071/hitec-tha11.

Full text
Abstract:
This paper describes the design, key features and applications of a System On Chip (SOC) ASIC (Application Specific Integrated Circuit) chipset which was developed by Embedded Systems LLC as a part of the Smart Node based distributed control system architecture under an Air Force SBIR (Small Business Innovative Research) program {4}. The analog part of the SOC chipset has been implemented by Honeywell International under a subcontract using their high temperature SOI (Silicon On Insulator) Process. The complete chipset is expected to be available in early 2015. The key feature of the SOC chipset is that it is a reconfigurable and scalable building block that can be used to interface with most typical aerospace control system sensors and actuators. The SOC chipset captures all of the necessary functions required to power and interface with sensors such as RTD (Resistance Temperature Detectors), Strain Gauges (SG), Thermo Couples (TC) and transducers for measuring mass flow, speed, position or angle. The SOC chipset also contains all of the pre- and post-processing functions to convert electrical signals into digital words and send them on a data bus under the control of a host microprocessor. Finally, the SOC chipset contains PWM (Pulse Width Modulation) circuitry required to interface with external drives for actuators, motors, shutoff Valves etc. The SOC chipset can be powered from a Mil-Std-704F compliant power source or a conditioned DC power source. The chipset can be combined with other devices, such as memory, processor and A to D Converter to implement a high temperature capable Smart Node for localized management of sensors and actuators as a part of a distributed architecture or used as a scalable building block in a more complex function such as a FADEC (Full Authority Digital Engine Control). It is believed that the versatility of the SOC chipset makes it a well suited, affordable, scalable building block for not only aerospace controls but also for diverse applications such as down-hole drilling, energy exploration, wind farms etc. where high temperature electronics and /or high level of miniaturization is required.
APA, Harvard, Vancouver, ISO, and other styles
9

Fresi, Francesco, Antonio Malacarne, Vito Sorianello, Gianluca Meloni, Philippe Velha, Michele Midrio, Veronica Toccafondo, Stefano Faralli, Marco Romagnoli, and Luca Poti. "Reconfigurable Silicon Photonics Integrated 16-QAM Modulator Driven by Binary Electronics." IEEE Journal of Selected Topics in Quantum Electronics 22, no. 6 (November 2016): 334–43. http://dx.doi.org/10.1109/jstqe.2016.2538725.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Shi, Chuanqian, Zhanan Zou, Zepeng Lei, Pengcheng Zhu, Guohua Nie, Wei Zhang, and Jianliang Xiao. "Stretchable, Rehealable, Recyclable, and Reconfigurable Integrated Strain Sensor for Joint Motion and Respiration Monitoring." Research 2021 (July 29, 2021): 1–14. http://dx.doi.org/10.34133/2021/9846036.

Full text
Abstract:
Cutting-edge technologies of stretchable, skin-mountable, and wearable electronics have attracted tremendous attention recently due to their very wide applications and promising performances. One direction of particular interest is to investigate novel properties in stretchable electronics by exploring multifunctional materials. Here, we report an integrated strain sensing system that is highly stretchable, rehealable, fully recyclable, and reconfigurable. This system consists of dynamic covalent thermoset polyimine as the moldable substrate and encapsulation, eutectic liquid metal alloy as the strain sensing unit and interconnects, and off-the-shelf chip components for measuring and magnifying functions. The device can be attached on different parts of the human body for accurately monitoring joint motion and respiration. Such a strain sensing system provides a reliable, economical, and ecofriendly solution to wearable technologies, with wide applications in health care, prosthetics, robotics, and biomedical devices.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Integrated reconfigurable electronics interface"

1

Tchoualack, Tchamako Armel. "Détecteur SiC de particules et électronique de conditionnement." Electronic Thesis or Diss., Aix-Marseille, 2021. http://www.theses.fr/2021AIXM0176.

Full text
Abstract:
Il s'agit à la fois d'étudier des détecteurs de particules (électrons et neutrons) en carbure de silicium à l'état de l'art, et de réaliser une interface électronique reconfigurable et intégrée adaptative à partir de technologies durcies pour le conditionnement et le traitement du signal électrique généré. Le front-end électronique (électronique de lecture) devra être capable d'extraire les signaux utiles (réponse en courant) des détecteurs ayant des caractéristiques différentes (dimensions, temps de réponse) et de fournir des données résolues (nature de la particule, spectroscopie, etc.) à l'aide de processeur embarqué. Plusieurs scénarios de co-intégration de l’ensemble " détecteur et électronique de lecture " prenant en compte l'environnement d'utilisation seront étudiés pour concevoir un détecteur de particules muni d'intelligence embarquée et plaçant ainsi l'étude à l'état de l’art
It involves both studying a state-of-the-art silicon carbide particles (electrons and neutrons) detector and producing an adaptive integrated reconfigurable electronics interface from hardened technologies for the conditioning and processing electrical signal generated. The electronics front-end will be capable to extract all useful signals (current answer) from the detector having different characteristics (dimensions, response times) and providing resolved data (nature of the particle, spectroscopy, etc.) using on-board processor. Several scenarios of co-integration of the "detector and electronic reading" assembly taking into account the environment of use will be studied to design a particle detector equipped with on-board intelligence and placing the study in the state of art
APA, Harvard, Vancouver, ISO, and other styles
2

Yuan, Xiaoyan. "Full-Wave Analyses of Nano-Electromechanical Systems Integrated Multifunctional Reconfigurable Antennas." DigitalCommons@USU, 2009. https://digitalcommons.usu.edu/etd/443.

Full text
Abstract:
This thesis work builds upon the theoretical studies and full-wave analysis of radio frequency micro- and nano-electromechanical systems (RF M/NEMS) integrated multi-functional reconfigurable antennas(MRAs). This is a part of the overall M/NEMS research efforts performed in the RF NEMS Laboratory at USU, which includes design, microfabrication, test, and characterization of M/NEMS integrated congitive wireless communication systems (fig. A.1). The thesis work focuses on two MRAs. 1) A triple bands patch antenna which can operate at 800, 2400, and 4900 MHz in response to public safety wireless communication systems. 2) A multi-frequency multi-polarization MRA for wireless personal area networking application (WPAN) operating at 57-64 GHz frequency range
APA, Harvard, Vancouver, ISO, and other styles
3

Tang, Xiao. "Vertically and Horizontally Self-assembled Magnetoelectric Heterostructures with Enhanced Properties for Reconfigurable Electronics." Diss., Virginia Tech, 2020. http://hdl.handle.net/10919/96334.

Full text
Abstract:
Magnetoelectric (ME) materials are attracting increasing attention due to the achievable reading/writing source (electric field and magnetic field in most cases), fast response time, and larger storage density. Therefore, nanocomposites featuring both magnetostriction and piezoelectricity were investigated to increase the converse magnetoelectric (CME, α) coefficient. Among all the nanocomposites, vertically/horizontally-integrated heterostructures were investigated; these materials offer intimate lattice contact, lower clamping effect, dramatically enhanced α, easier reading direction, and the potential to be patterned for complicated applications. In the present work, we focused on three principal goals: (a) creating two-phase vertically integrated heterostructures with different ME materials that provide much larger α, and enhanced strain-induced magnetic shape anisotropy compared with the single-phased ME nanomaterials; (b) creating a vertically integrated heterostructure with large α, lower loss, and higher efficiency; and (c) investigating the stable magnetization states that this heterostructure could achieve, and how it can be used in advanced memory devices and logic devices. Firstly, a BiFeO3-CoFe2O4 (BFO-CFO) heterostructure was epitaxially deposited on Pb(Mg1/3Nb2/3) O3-x at%PbTiO3 (PMN-xPT). The resulting PMN-xPT was proven to have a large piezoelectric effect capable of boosting the CME in the heterostructure to create a much higher α. Secondly, a novel material, CuFe2O4 (CuFO), featuring lower coercivity and loss, was chosen to be self-assembled with BFO. This low-loss could increase the efficiency of the ME effect. Also, our findings revealed a much larger α in the vertically integrated heterostructure compared to single-layer CuFO. Accordingly, the self-assembled structure represents a convenient method for increasing the CME in multiferroic materials. Thirdly, the magnetization states for all these vertically integrated heterostructures were studied. Note that vertically integrated heterostructures are typically fabricated using materials with volatile properties. However, these composites have shown a non-volatile nature with a multi-states (N≥4), which is favored for multiple applications such as multi-level-cell. Moreover, several self-assembled heterostructures were created that are conducive to magnetic anisotropy/coercivity manipulation. One such example is Ni0.65Zn0.35Al0.8Fe1.2O4 (NZAFO) with BFO, which forms a self-assembled nanobelt heterostructure that exhibits high induced magnetic shape anisotropy, and is capable of manipulating magnetic coercivity (from 2 Oe to 50 Oe) and magnetic anisotropy directions (both in-plane and out-of-plane). Finally, we deposited a SrRuO3-CoFe2O4 (SRO-CFO) vertically integrated composite thin film on the single crystal substrate PMN-30PT, with a CFO nanopillar and SRO matrix. In such a heterostructure, the SRO would serve as the conductive materials, while CFO offers the insulated property. This unique conductive/insulating heterostructure could be deposited on PMN-PT single crystals, thus mimicking patterned electrodes on the PMN-PT single crystals with enhanced dielectric constant and 33.
Doctor of Philosophy
Multi-ferroic materials, which contain multiple ferroic orders like ferromagnetism/ferroelectricity order, were widely studied nowadays. These orders are coupled together, which could manipulate one order via another one through the coupling. Due to the achievable reading/writing source (electric field and magnetic field in most of the case), fast response time and larger storage density, magnetoelectric (ME) materials aroused most interests to-date. To be used in different applications, such as memory devices and logic devices, a high transfer efficiency, or say a high coupling coefficient, is required. However, single-phase materials have nearly neglectable ME effect. Therefore, a nanocomposite that contents both magnetostriction and piezoelectricity were investigated to increase the converse magnetoelectric (CME, α) coefficient. Amongst all the nanocomposite, a vertically integrated heterostructure was revealed, which has intimate lattice contact, lower clamping effect, dramatically enhancedα, easier reading direction, and potential to be patterned for complicated applications. In this present work, we focused on several different aspects: (a) creating two-phase vertically integrated heterostructure with different ME materials, which provides much larger α, large strain-induced magnetic shape anisotropy comparing with the single-phased ME nanomaterials; (b): creating a vertically integrated heterostructure with large α and lower losses and higher efficiency; (c) investigate the stable magnetization states that this heterostructure could achieve, which shows the potential of being used in advanced memory devices and logic devices. Firstly, in this work, a BiFeO3-CoFe2O4 (BFO-CFO) heterostructure was epitaxially deposited on the Pb(Mg1/3Nb2/3) O3-x at%PbTiO3 (PMN-xPT), which could boost the CME in the heterostructure to create a much higher α. Then, a novel materials CuFe2O4 (CuFO), was chosen to be self-assembled with BFO, which has lower losses and higher efficiency of the ME effect. Secondly, several self-assembled heterostructures were created, such as Ni0.65Zn0.35Al0.8Fe1.2O4 (NZAFO) with BFO, which manipulated the magnetic coercivity (from 2 Oe to 50 Oe) and magnetic anisotropy directions (Both in-plane and out-of-plane). And a heterostructure: SrRuO3 with CFO, created a vertically integrated heterostructure, could be used as patterned electrodes in different applications. Moreover, magnetization states were studied in all these vertically integrated heterostructures. A multi-states (N≥4) was revealed, which was favored by multiple applications such as multi-level-cell or logical devices. Finally, we deposited a SrRuO3-CoFe2O4 (SRO-CFO) vertically integrated composite thin film on the single crystal substrate PMN-30PT, with a CFO nanopillar and SRO matrix. In such a heterostructure, the SRO would serve as the conductive materials, while CFO offers the insulated property. This unique conductive/insulating heterostructure could be deposited on PMN-PT single crystals, thus mimicking patterned electrodes on the PMN-PT single crystals with enhanced dielectric constant and d_33.
APA, Harvard, Vancouver, ISO, and other styles
4

Mopidevi, Hema Swaroop. "Micro Electro Mechanical Systems Integrated Frequency Reconfigurable Antennas for Public Safety Applications." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/744.

Full text
Abstract:
This thesis work builds on the concept of reconfiguring the antenna properties (frequency, polarization, radiation pattern) using Radio Frequency (RF) Micro Electro Mechanical Systems (MEMS). This is a part of the overall research performed at the RF Micro/Nano Electro Mechanical Systems (uNeMS) Laboratory at Utah State University, which includes design, microfabrication, test, and characterization of uNeMS integrated cognitive wireless communication systems (Appendix A). In the first step, a compact and broadband Planar Inverted F Antenna (PIFA) is designed with a goal to accommodate reconfigurability at a later stage. Then, a Frequency Reconfigurable Antenna (FRA) is designed using MEMS switches to switch between the Public Safety (PS) bands, 152-162 MHz and 406-512 MHz, while maintaining the integrity of radiation pattern for each band. Finally, robust mechanical designs of the RF MEMS switches accompanied by different analyses have been performed. These analyses are instrumental in obtaining high yield, reliable, robust microfabrication processes including thin film metal deposition and patterning.
APA, Harvard, Vancouver, ISO, and other styles
5

Gustafsson, E. Martin I. "Reconfigurable Analog to Digital Converters for Low Power Wireless Applications." Doctoral thesis, Kista : KTH School of Information and Communication Technology, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4774.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Zheng, Guizhen. "Low power reconfigurable microwave circuits using RF MEMS switches for wireless systems." Available online, Georgia Institute of Technology, 2005, 2005. http://etd.gatech.edu/theses/available/etd-05242005-135940/.

Full text
Abstract:
Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2006.
John Papapolymerou, Committee Chair ; Joy Laskar, Committee Member ; John Cressler, Committee Member ; Alan Doolittle, Committee Member ; Clifford Henderson, Committee Member.
APA, Harvard, Vancouver, ISO, and other styles
7

Zheng, Guizhen. "Low Power Reconfigurable Microwave Circuts Using RF MEMS Switches for Wireless Systems." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/11656.

Full text
Abstract:
This dissertation presents the research on several different projects. The first project is a via-less CPW RF probe pad to microstrip transition; The second, the third, and the fourth one are reconfigurable microwave circuits using RF MEMS switches: an X-band reconfigurable bandstop filter for wireless RF frontends, an X-band reconfigurable impedance tuner for a class-E high efficiency power amplifier using RF MEMS switches, and a reconfigurable self-similar antenna using RF MEMS switches. The first project was developed in order to facilitate the on-wafer measurement for the second and the third project, since both of them are microstrip transmission line based microwave circuits. A thorough study of the via-less CPW RF probe pad to microstrip transition on silicon substrates was performed and general design rules are derived to provide design guidelines. This research work is then expanded to W-band via-less transition up to 110 GHz. The second project is to develop a low power reconfigurable monolithic bandstop filter operating at 8, 10, 13, and 15 GHz with cantilever beam capacitive MEMS switches. The filter contains microstrip lines and radial stubs that provide different reactances at different frequencies. By electrically actuating different MEMS switches, the different reactances from different radial stubs connecting to these switches will be selected, thus, the filter will resonate at different frequencies. The third project is to develop a monolithic reconfigurable impedance tuner at 10 GHz with the cantilever DC contact MEMS switch. The impedance tuner is a two port network based on a 3bit-3bit digital design, and uses 6 radial shunt stubs that can be selected via integrated DC contact MEMS switches. By selecting different states of the switches, there will be a total of 2^6 = 64 states, which means 64 different impedances will be generated at the output port of the tuner. This will provide a sufficient tuning range for the output port of the power amplifier to maximize the power efficiency. The last project is to integrate the DC contact RF MEMS switches with self-similar planar antennas, to provide a reconfigurable antenna system that radiates with similar patterns over a wide range of frequencies.
APA, Harvard, Vancouver, ISO, and other styles
8

Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Uzelac, Lawrence Stevan. "A Multiple Coupled Microstrip Transmission Line Model for High-Speed VLSI Interconnect Simulation." PDXScholar, 1991. https://pdxscholar.library.pdx.edu/open_access_etds/4526.

Full text
Abstract:
A model is presented which incorporates the advantages of a mixed mode simulation to characterize transmission line behavior in multiple coupled Transmission line systems. The model is intended for use by digital circuit designers who wish to be able to obtain accurate transmission line behavior for complex digital systems for which continuous time simulation tools such as SPICE would time prohibitive. The model uses a transverse electromagnetic wave approximation to obtain solutions to the basic transmission line equations. A modal analysis technique is used to solve for the attenuation and propagation constants for the transmission lines. Modal analysis done in the frequency domain after a Fast Fourier Transform of the time-domain input signals. Boundary conditions are obtained from the Thevinized transmission line input equivalent circuit and the transmission line output load impedance. The model uses a unique solution queue system that allows n-line coupled transmission lines to be solved without resorting to large order matrix methods or the need to diagonals larger matrices using linear transformations. This solution queue system is based on the method of solution superposition. As a result, the CPU time required for the model is primarily a function of the number of transitions and not the number of lines modeled. Incorporation of the model into event driven circuit simulators such as Network C is discussed. It will be shown that the solution queue methods used in this model make it ideally suited for incorporation into a event-driven simulation network. The model presented in this thesis can be scaled to incorporate direct electromagnetic coupling between first, second, or third lines adjacent to the line transitioning. It is shown that modeling strictly adjacent line coupling is adequate for typical digital technologies. It is shown that the model accurately reproduces the transmission line behavior of systems modeled by previous authors. Example transitions on a 8-line system are reviewed. Finally, future model improvements are discussed.
APA, Harvard, Vancouver, ISO, and other styles
10

Gray, Richard Scott. "A study of disk performance optimization." [Johnson City, Tenn. : East Tennessee State University], 2000. http://etd-submit.etsu.edu/etd/theses/available/etd-0313100-181217/unrestricted/ScottGray2-final.pdf.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Books on the topic "Integrated reconfigurable electronics interface"

1

Incorporated, Texas Instruments, ed. Data acquisition circuits data book: Data conversion and DSP analog interface. [Dallas, TX]: Texas Instruments, 1998.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

Roermund, Arthur van. Analog Circuit Design:: Sensor and Actuator Interface Electronics, Integrated High-Voltage Electronics and Power Management, Low-Power and High-Resolution ADC's. U.S.: Springer, 2005.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

1938-, Huijsing Johan H., Steyaert Michiel 1959-, and Roermund, Arthur H. M. van., eds. Analog circuit design: Sensor and actuator interface electronics, integrated high-voltage electronics and power management, low-power and high-resolution ADC's. Boston: Kluwer Academic, 2004.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

1934-, Furukawa S., National Science Foundation (U.S.), Nihon Gakujutsu Shinkōkai, and U.S.-Japan Seminar on "Solid Phase Epitaxy and Interface Kinetics" (1983 : Ōise-machi, Japan), eds. Layered structures and interface kinetics: Their technology and applications. Tokyo: KTK Scientific, 1985.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

1966-, Baumann Konrad, and Thomas Bruce 1954-, eds. User interface design of electronic appliances. London: Taylor & Francis, 2001.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

Rumsey, Francis, and John Watkinson. Digital Interface Handbook. Taylor & Francis Group, 2013.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Watkinson, John. Digital Interface Handbook. Taylor & Francis Group, 2017.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

Rumsey, Francis, and John Watkinson. Digital Interface Handbook. Taylor & Francis Group, 2013.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
9

Einspruch, Norman G. Vlsi Electronics: Microstructure Science : Surface and Interface Effects in Vlsi (V L S I Electronics). Academic Pr, 1985.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
10

Einspruch, Norman G. Vlsi Electronics: Microstructure Science : Surface and Interface Effects in Vlsi (V L S I Electronics). Academic Pr, 1985.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Book chapters on the topic "Integrated reconfigurable electronics interface"

1

Sridevi, G., S. Satyanarayana, and P. Sravan Kumar. "Implementing the Reconfigurable Intelligent Sensor Interface in Wireless Networks." In Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications, 629–36. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-4280-5_66.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Jivet, I. "Architecture of an on Electrode Integrated Electronics with an All Digital Interface for Electrical Impedance Tomography." In IFMBE Proceedings, 205–8. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-04292-8_45.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Capmany, José, and Daniel Pérez. "Field Programmable Photonic Gate Arrays." In Programmable Integrated Photonics, 301–30. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198844402.003.0009.

Full text
Abstract:
The field programmable photonic gate array (FPPGA) is an integrated photonic device/subsystem that operates similarly to a field programmable gate array in electronics. It is a set of programmable photonics analogue blocks (PPABs) and of reconfigurable photonic interconnects (RPIs) implemented over a photonic chip. The PPABs provide the building blocks for implementing basic optical analogue operations (reconfigurable/independent power splitting and phase shifting). Broadly they enable reconfigurable processing just like configurable logic elements (CLE) or programmable logic blocks (PLBs) carry digital operations in electronic FPGAs or configurable analogue blocks (CABs) carry analogue operations in electronic field programmable analogue arrays (FPAAs). Reconfigurable interconnections between PPABs are provided by the RPIs. This chapter presents basic principles of integrated FPPGAs. It describes their main building blocks and discusses alternatives for their high-level layouts, design flow, technology mapping and physical implementation. Finally, it shows that waveguide meshes lead naturally to a compact solution.
APA, Harvard, Vancouver, ISO, and other styles
4

Capmany, José, and Daniel Pérez. "Introduction to Programmable Integrated Photonics." In Programmable Integrated Photonics, 1–37. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198844402.003.0001.

Full text
Abstract:
Programmable integrated photonics (PIP) aims at designing common integrated optical hardware configurations, which—by suitable programming—can implement a variety of functionalities that can be elaborated for basic or more complex operations in many application fields. It follows a different approach to that of application specific photonic integrated circuits (ASPICs), which have dominated during the last few decades. The interest in PIP is driven by the surge of a considerable number of emerging applications in the fields of telecommunications, quantum information processing, sensing and neurophotonics that will require flexible, reconfigurable, low-cost, compact and low-power-consuming devices, much as field programmable gate array (FPGA) devices operate in electronics. This chapter serves as a general introduction to the book and reviews the main basic principles and recent advances in PIP, including fabrication platforms, design principles, architecture choices, challenges and limitations. and provides a brief introduction to the applications of this new field.
APA, Harvard, Vancouver, ISO, and other styles
5

Hadj Youssef Wajih, El. "Secure Smart Card IP." In Biometrics and Cryptography [Working Title]. IntechOpen, 2024. http://dx.doi.org/10.5772/intechopen.112491.

Full text
Abstract:
This book chapter highlights the embedded system security by designing a secure smart card IP. Indeed, the smart card is recognized as a privileged means of both storing confidential information and performing secure transactions. Its main role comes from the security it provides inside the system it is a part of. The specification and development of the elaborate smart card architecture are very delicate steps that require the pooling of strong competences in computer security, electronics, and also cryptography. The developed secure smart card IP model is based on the Gaisler LEON2 processor. To ensure a maximum level of security and optimal performance, a hardware integration of cryptographic mechanisms through instruction extensions was carried out. The integrated mechanisms allow for ensuring confidentiality, hashing, random number generation, and digital signature. The proposed smart card IP was implemented on a reconfigurable FPGA platform, and then on ASIC using 40 nm CMOS technology. A surface area of 1.08 mm2 with a consumed dynamic power of 23 mW for a frequency of 13.5 MHz was achieved.
APA, Harvard, Vancouver, ISO, and other styles
6

Ramasamy, Prema, Shri Tharanyaa Jothimani Palanivelu, and Abin Sathesan. "Certain Applications of LabVIEW in the Field of Electronics and Communication." In LabVIEW - A Flexible Environment for Modeling and Daily Laboratory Use. IntechOpen, 2021. http://dx.doi.org/10.5772/intechopen.96301.

Full text
Abstract:
The LabVIEW platform with graphical programming environment, will help to integrate the human machine interface controller with the software like MATLAB, Python etc. This platform plays the vital role in many pioneering areas like speech signal processing, bio medical signals like Electrocardiogram (ECG) and Electroencephalogram (EEG) processing, fault analysis in analog electronic circuits, Cognitive Radio(CR), Software Defined Radio (SDR), flexible and wearable electronics. Nowadays most engineering colleges redesign their laboratory curricula for the students to enhance the potential inclusion of remote based laboratory to facilitate and encourage the students to access the laboratory anywhere and anytime. This would help every young learner to bolster their innovation, if the laboratory environment is within the reach of their hand. LabVIEW is widely recognized for its flexibility and adaptability. Due to the versatile nature of LabVIEW in the Input- Output systems, it has find its broad applications in integrated systems. It can provide a smart assistance to deaf and dumb people for interpreting the sign language by gesture recognition using flex sensors, monitor the health condition of elderly people by predicting the abnormalities in the heart beat through remote access, and identify the stage of breast cancer from the Computed tomography (CT) and Magnetic resonance imaging (MRI) scans using image processing techniques. In this chapter, the previous work of authors who have extensively incorporated LabVIEW in the field of electronics and communication are discussed in detail.
APA, Harvard, Vancouver, ISO, and other styles
7

Holmes-Siedle, Andrew, and Len Adams. "Metal-oxide-semiconductor (MOS) devices." In Handbook of Radiation Effects, 129–204. Oxford University PressOxford, 2002. http://dx.doi.org/10.1093/oso/9780198507338.003.0004.

Full text
Abstract:
Abstract MOS integrated circuits, particularly those of the complementary form (CMOS), are very suitable for use in high-performance electronics such as timers, battery-powered computers, robots, missiles, and space vehicles. The power consumed by the CMOS logic element is extraordinarily low compared with nMOS and bipolar circuits. In addition, the CMOS inverter employs voltage signals which can be made highly immune to noise. These features are uniquely suitable for advanced data-handling and control systems in severe, remote environments. It is unfortunate therefore that many MOS devices show strong, variable and long-lived response to total-dose radiation. In any radiation environment exceeding about one thousand rads ( 10 Gy), it is necessary to consider the effect of oxide charge trapping and interface-state generation; heavy ions and intense pulses of radiation can also cause the upset of logic states.
APA, Harvard, Vancouver, ISO, and other styles
8

Pool, Robert. "Business." In Beyond Engineering. Oxford University Press, 1997. http://dx.doi.org/10.1093/oso/9780195107722.003.0008.

Full text
Abstract:
In January 1975, the magazine Popular Electronics trumpeted the beginnings of a revolution. “Project Breakthrough,” the cover said: “World’s First Minicomputer Kit to Rival Commercial Models.” Inside, a six-page article described the Altair, an unassembled computer that could be ordered from MITS, a company in Albuquerque originally founded to sell radio transmitters for controlling model airplanes. To the uninitiated, it didn’t look like much of a revolution. For $397 plus shipping, a hobbyist or computer buff could get a power supply, a metal case with lights and switches on the front panel, and a set of integrated circuit chips and other components that had to be soldered into place. When everything was assembled, a user gave the computer instructions by flipping the panel’s seventeen switches one at a time in a carefully calculated order; loading a relatively simple program might involve thousands of flips. MITS had promised that the Altair could be hooked up to a Teletype machine for its input, but the circuit boards needed for the hookup wouldn’t be available for a number of months. To read the computer’s output, a user had to interpret the on/off pattern of flashing lights; it would be more than a year before MITS would offer an interface board to transform the output into text or figures on a television screen. And the computer had no software. A user had to write the programs himself in arcane computer code or else borrow the efforts of other enthusiasts. One observer of the early computer industry summed up the experience like this: “You buy the Altair, you have to build it, then you have to build other things to plug into it to make it work. You are a weird-type person. Because only weird-type people sit in kitchens and basements and places all hours of the night, soldering things to boards to make machines go flickety-flock.” But despite its shortcomings, several thousand weird-type people bought the Altair within a few months of its appearance. What inspired and intrigued them was the semiconductor chip at the heart of the computer.
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Integrated reconfigurable electronics interface"

1

Lu, Y. C., Julian Cheng, J. C. Zolper, and J. Klem. "Multi-functional Surface-Emitting Laser-Based Integrated Photonic/Optoelectronic Switch For Parallel High-Speed Optical Interconnects." In Photonics in Switching. Washington, D.C.: Optica Publishing Group, 1995. http://dx.doi.org/10.1364/ps.1995.pfb4.

Full text
Abstract:
The monolithic integration of vertical-cavity surface-emitting lasers (VCSELs) with active electronic devices combines the optical source array and its driver circuits into a single IC technology, which is usefill for parallel high-speed optical interconnects. Another motive for the integration of VCSELs with high speed electronics is to provide an optical switching network with a simple optoelectronic interface that allows individual electronic computer processors to communicate with each other through parallel optical channels. A dynamically reconfigurable optical switching network1-2 can simultaneously route optical data between many different electronic processors as they perform parallel processing sequences using shared resources. Each switch of the network must provide an optical link to all the other nodes, as well as an optical ⟺ electrical interface to an electronic processor. Each switch must thus perform both the optical and optoelectronic switching functions in order to convert data between various combinations of electrical and optical input/output (I/O) formats.
APA, Harvard, Vancouver, ISO, and other styles
2

Szypicyn, Jakub, Christos Papavassiliou, Georgios Papandroulidakis, Geoff Merrett, Alex Serb, Spyros Stathopoulos, and Themis Prodromakis. "Memristor-Enabled Reconfigurable Integrated Circuits." In 2020 International Conference on Electronics, Information, and Communication (ICEIC). IEEE, 2020. http://dx.doi.org/10.1109/iceic49074.2020.9051041.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Tan, Bo, Leibo Liu, Shouyi Yin, Min Zhu, Wen Jia, and Shaojun Wei. "An interconnect interface for reconfigurable multimedia system." In 2011 International Conference on Consumer Electronics, Communications and Networks (CECNet). IEEE, 2011. http://dx.doi.org/10.1109/cecnet.2011.5768526.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Seungkee Min, Sridhar Shashidharan, Mark Stevens, Tino Copani, Sayfe Kiaei, Bertan Bakkaloglu, and Sudipto Chakraborty. "A 2mW CMOS MICS-band BFSK transceiver with reconfigurable antenna interface." In 2010 IEEE Radio Frequency Integrated Circuits Symposium. IEEE, 2010. http://dx.doi.org/10.1109/rfic.2010.5477282.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Olsson, Roy H., Kyle Bunch, and Christal Gordon. "Reconfigurable Electronics for Adaptive RF Systems." In 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS). IEEE, 2016. http://dx.doi.org/10.1109/csics.2016.7751061.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Kachris, Christoforos, George Nikiforos, Stamatis Kavadias, Vassilis Papaefstathiou, and Manolis Katevenis. "Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface." In 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010). IEEE, 2010. http://dx.doi.org/10.1109/reconfig.2010.51.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Yu, Li, Xiaoying Wang, and Lei Wang. "A low-power fully differential reconfigurable biomedical electronics interface to detect heart signals." In Electronics (PrimeAsia). IEEE, 2010. http://dx.doi.org/10.1109/primeasia.2010.5604879.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Gan, Yuxiang, Zewei Wu, Li Chen, Minxing Wang, Youlei Pu, and Yong Luo. "A K-Band Waveguide With Integrated Reconfigurable Circular Polarizer." In 2023 24th International Vacuum Electronics Conference (IVEC). IEEE, 2023. http://dx.doi.org/10.1109/ivec56627.2023.10157145.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Kang, Yong Hoon, and Hyuk Lee. "Integrated interface between volume optical memories and electronics." In SPIE's 1994 International Symposium on Optics, Imaging, and Instrumentation, edited by Joseph L. Horner, Bahram Javidi, and Stephen T. Kowel. SPIE, 1994. http://dx.doi.org/10.1117/12.187315.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Gaggatur, Javed S., and Gaurab Banerjee. "Integrated temperature sensor for reconfigurable radio frequency synthesizer." In 2015 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT). IEEE, 2015. http://dx.doi.org/10.1109/conecct.2015.7383924.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Integrated reconfigurable electronics interface' for particular source types:
Journal articles Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography