Dissertations / Theses on the topic 'Integrated Computer Modeling'
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Wu, SunMan Patrick. "Modeling of micro-electro-mechanical integrated test structures." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36044.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.Includes bibliographical references (leaf 38).
by SunMan Patrick Wu.
M.Eng.
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Michael, Christopher I. "Statistical modeling for computer-aided design of analog MOS integrated circuits /." The Ohio State University, 1991. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487688973683252.
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Fan, Wei Ph D. Massachusetts Institute of Technology. "Advanced modeling of planarization processes for integrated circuit fabrication." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/78446.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 215-225).
Planarization processes are a key enabling technology for continued performance and density improvements in integrated circuits (ICs). Dielectric material planarization is widely used in front-end-of-line (FEOL) processing for device isolation and in back-end-of-line (BEOL) processing for interconnection. This thesis studies the physical mechanisms and variations in the planarization using chemical mechanical polishing (CMP). The major achievement and contribution of this work is a systematic methodology to physically model and characterize the non-uniformities in the CMP process. To characterize polishing mechanisms at different length scales, physical CMP models are developed in three levels: wafer-level, die-level and particle-level. The wafer-level model investigates the CMP tool effects on wafer-level pressure non-uniformity. The die-level model is developed to study chip-scale non-uniformity induced by layout pattern density dependence and CMP pad properties. The particle-level model focuses on the contact mechanism between pad asperities and the wafer. Two model integration approaches are proposed to connect wafer-level and particle-level models to the die-level model, so that CMP system impacts on die-level uniformity and feature size dependence are considered. The models are applied to characterize and simulate CMP processes by fitting polishing experiment data and extracting physical model parameters. A series of physical measurement approaches are developed to characterize CMP pad properties and verify physical model assumptions. Pad asperity modulus and characteristic asperity height are measured by nanoindentation and microprofilometry, respectively. Pad aging effect is investigated by comparing physical measurement results at different pad usage stages. Results show that in-situ conditioning keeps pad surface properties consistent to perform polishing up to 16 hours, even in the face of substantial pad wear during extended polishing. The CMP mechanisms identified from modeling and physical characterization are applied to explore an alternative polishing process, referred to as pad-in-a-bottle (PIB). A critical challenge related to applied pressure using pad-in-a-bottle polishing is predicted.
by Wei Fan.
Ph.D.
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Pang, Huey, and 彭栩怡. "Computer modeling of building-integrated photovoltaic systems using genetic algorithms for optimization." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2002. http://hub.hku.hk/bib/B31227764.
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Lin, Yi-Tzer. "Modeling and analysis for message reachability in distributed manufacturing systems." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/24292.
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Ma, Min. "Model order reduction for efficient modeling and simulation of interconnect networks." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103269.
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As operating frequency increases and device sizes shrink, the complexity of current state-of-the-art designs has increased dramatically. One of the main contributors to this complexity is high speed interconnects. At high frequencies, interconnects become dominant contributors to signal degradation, and their effects such as delays, reflections, and crosstalk must be accurately simulated. Time domain analysis of such structures is however very difficult because, at high frequencies, they must be modeled as distributed transmission lines which, after discretization, result in very large networks. In order to improve the simulation efficiency of such structures, model order reduction has been proposed in the literature. Conventional model order reduction methods based on Krylov subspace have a number of limitations in many practical simulation problems. This restricts their usefulness in general commercial simulators.In this thesis, a number of new reduction techniques were developed in order to address the key shortcomings of current model order reduction methods. Specifically a new approach for handling macromodels with a very large number of ports was developed, a multi-level reduction and sprasification method was proposed for regular as well as parametric macromodels, and finally a new time domain reduction method was presented for the macromodeling of nonlinear parametric systems. Using these approaches, CPU speedups of 1 to 2 orders of magnitude were obtained.
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Short, Kristin Ilene 1971. "Towards integrated Intranet services : modeling the costs of corporate IP technology." Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/43530.
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Abrokwah, Kwaku O. "Characterization and modeling of plasma etch pattern dependencies in integrated circuits." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37054.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Leaf 108 blank.
Includes bibliographical references (leaves 106-107).
A quantitative model capturing pattern dependent effects in plasma etching of integrated circuits (ICs) is presented. Plasma etching is a key process for pattern formation in IC manufacturing. Unfortunately, pattern dependent non-uniformities arise in plasma etching due to microloading and RIE lag. This thesis contributes a semi-empirical methodology for capturing and modeling microloading, RIE lag, and related pattern dependent effects. We apply this methodology to the study of interconnect trench etching, and show that an integrated model is able to predict both pattern density and feature size dependent non-uniformities in trench depth. Previous studies of variation in plasma etching have characterized microloading (due to pattern density), and RIE lag (aspect ratio dependent etching or ARDE) as distinct causes of etch non-uniformity for individual features. In contrast to these previous works, we present here a characterization and computational methodology for predicting IC etch variation on a chip scale that integrates both layout pattern density and feature scale or ARDE dependencies. The proposed integrated model performs well in predicting etch variation as compared to a pattern density only or feature scale only model.
by Kwaku O. Abrokwah.
M.Eng.
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Hickey, Ann Marie. "Integrated scenario and process modeling support for collaborative requirements elicitation." Diss., The University of Arizona, 1999. http://hdl.handle.net/10150/284823.
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Information systems development research has documented the importance and the difficulty of eliciting requirements from users. Research on the use of Group Support Systems (GSS) for requirements elicitation led to development of the Collaborative Software Engineering Methodology (CSEM) and identified the need for collaborative methods and tools to provide a dynamic picture of the business processes that a system must support. Recent research suggests that scenarios can fill this need. A review of the scenario literature showed that although there is widespread agreement on the usefulness of scenarios, there are many questions on how to implement a user-focused, scenario-based systems development process. The purpose of this research was to advance understanding in this area and to determine: What are the collaborative modeling processes, tools, and facilitation techniques needed to effectively elicit scenarios from users in a group environment? A two-phase, multi-method systems development research approach was used. The first phase focused on use of a general-purpose GSS for collaborative scenario elicitation. A conceptual framework and initial methodology were developed and then evaluated during exploratory case studies and a laboratory experiment. The second phase focused on development and evaluation of a special-purpose GSS and methodology. Phase I results showed that: users can easily define scenarios which provide rich pictures of the problem domain; an iterative, collaborative methodology with scenario and action prompts is needed to ensure scenario completeness; and limitations of general-purpose GSS negatively impacted productivity. The Collaborative Distributed Scenario and Process Analyzer (SPA) provides integrated textual scenario and graphical process modeling capabilities which successfully overcame these limitations. This research made several contributions. CSEM was extended to define scenario usage opportunities throughout development. Scenario content, form, group process and facilitation techniques were defined for collaborative scenario elicitation using a general-purpose GSS, which can be used now by practitioners. A special-purpose GSS tool (SPA) was developed and integrated into a comprehensive methodology which allows user groups to rapidly define and analyze scenarios in face-to-face and distributed settings. Finally, flexibility designed into SPA opens up opportunities for many other uses for SPA and serves as a first-step towards a build-your-own GSS tool.
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Park, Tae Hong 1973. "Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/8082.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 173-176).
Copper metallization has emerged as the leading interconnect technology for deep sub-micron features, where electroplating and chemical mechanical polish (CMP) processes have a vital role in the fabrication of integrated circuits. The processes both suffer from a similar problem: the copper electroplated profiles and the polished surface exhibit pattern dependent topography. In this thesis, a methodology for the characterization and modeling of pattern dependent problems in copper interconnect topography is developed. For the electroplating process, the methodology consists of test structure and mask design to examine feature scale copper step height and the height of copper array regions as a function of underlying layout parameters. Semi-empirical response surface models are then generated with model parameters extracted from conventional and superfill plating processes. Once the models are calibrated, layout parameters including pattern density, line width distributions, and line length are extracted for each cell in a 40 gm by 40 tm discretization of any random chip layout. Then, a chip-scale prediction is achieved by simulating generalized average heights for each grid cell across the entire chip. The prediction result shows root mean square errors of less than 1000 A for array height and around 500 A for step height. This methodology provides the first known chip-scale prediction of electroplated topography. For pattern dependencies in copper CMP, this thesis focuses on the development of test structures and masks (including multi-level structures) to identify key pattern effects in both single-level and multi-level polishing.
(cont.) Especially for the multi-level studies, electrical test structures and measurements in addition to surface profile scans are seen to be important in accurately determining thickness variations. The developed test vehicle and characterization of copper dishing and oxide erosion serve as a basis for further pattern dependent model development. Finally, integration of electroplating and CMP chip-scale models is illustrated; the simulated step and array heights as well as topography pattern density are used as an input for the initial starting topography for CMP simulation of subsequent polishing profile evolution.
by Tae Hong Park.
Ph.D.
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Hoffman, Joseph A. "VHDL modeling of ASIC power dissipation." Master's thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-10222009-124831/.
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Wan, Bo. "MCAST : automatic device modeling in model compiler for efficient and accurate circuit simulation /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5959.
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Yu, Jie Petropulu Athina P. "Modeling of high-speed wireline and wireless network traffic /." Philadelphia, Pa. : Drexel University, 2005. http://dspace.library.drexel.edu/handle/1860/469.
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Robinson, William Hugh. "Modeling and implementation of an integrated pixel processing tile for focal plane systems." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04072004-180157/unrestricted/robinson%5Fwilliam%5Fh%5F200312%5Fphd.pdf.
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MUKHERJEE, ANINDO. "AN INTEGRATED ARCHITECTURE FOR MULTI-HOP INFRASTRUCTURE WIRELESS NETWORKS." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1155834305.
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Patel, Girish N. "A neuromorphic architecture for modeling intersegmental coordination." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13528.
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Doustmohammadi, Ali. "Modeling and analysis of production systems." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/15776.
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Koh, Sau W. "Fatigue modeling of nano-structured chip-to-package interconnections." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28263.
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Thesis (M. S.)--Materials Science and Engineering, Georgia Institute of Technology, 2009.Committee Chair: Rao R. Tummala; Committee Co-Chair: Ashok Saxena; Committee Member: Karl Jacob; Committee Member: Suresh Sitaraman; Committee Member: Thomas H. Sanders, Jr.
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Cho, Choongeol. "RF circuit nonlinearity characterization and modeling for embedded test." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0013086.
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Gruener, Charles J. "Design and implementation of a computational cluster for high performance design and modeling of integrated circuits /." Online version of thesis, 2009. http://hdl.handle.net/1850/11204.
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Liang, Bowen. "Integrated Multi-Scale Modeling Framework for Simulating Failure Response of Materials with Complex Microstructures." The Ohio State University, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=osu1542233231302831.
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Sriwiriyarat, Tongchai. "Computer Program Development for the Design of IFAS Wastewater Treatment Processes." Thesis, Virginia Tech, 1999. http://hdl.handle.net/10919/32065.
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The Integrated Film Activated Sludge Process (IFAS) was developed to reduce the cost of additional facilities required to complete year round nitrification in the design of new or retrofit wastewater treatment plants. The purpose of this project was to develop a computer-based mechanistic model, called IFAS, which can be used as a tool by scientists and engineers to optimize their designs and to troubleshoot a full-scale treatment plant. The program also can be employed to assist researchers conducting their studies of IFAS wastewater treatment processes. IFAS enables the steady-state simulation of nitrification-denitrification processes as well as carbonaceous removal in systems utilizing integrated media, but this current version supports only sponge type media. The IFAS program was developed by incorporating empirical equations for integrated biofilm carbonaceous uptake and nitrification developed by Sen and Randall (1995) into the general activated sludge model, developed by the International Association on Water Quality (IAWQ, previously known as IAWRC), plus the biological phosphorus removal model of Wentzel et al (1989). The calibration and evaluation of the IFAS model was performed using existing data from both an IFAS system and a conventional activated sludge bench-scale plant operated over a wide range of Aerobic Mean Cell Residence Times (Aerobic MCRT's). The model developed provides a good fit and a reasonable prediction of the experimental data for both the IFAS and the conventional pilot-scale systems. The phosphorus removal component of the model has not yet been calibrated because of insufficient data and the lack of adequately defined parameters.Master of Science
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Johnson, Joy Marie. "Modeling of advanced integrated circuit planarization processes : electrochemical-mechanical planarization (eCMP), STI CMP using non-conventional slurries." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/52807.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student submitted PDF version of thesis.
Includes bibliographical references (p. 95-99).
Progression of technology nodes in integrated circuit design is only possible if there are sustainable, cost-efficient processes by which these designs can be implemented. As future technologies are increasing device density, shrinking device dimensions, and employing novel structures, semiconductor processing must also advance to effectively and eciently process these devices. Arguably one of the most critical, inefficient, poorly understood and costly processes is planarization. Thus, this thesis focuses on two types of planarization processes. Models of efficient and environmentally benign electrochemical-mechanical copper planarization (eCMP) are developed, with a focus on electrochemical mechanisms and wafer-scale uniformity. Specifically, previous models for eCMP are enhanced to consider the full electrochemical system driving planarization in eCMP. We explore the notion of electrochemical reactions at both the cathode and anode, in addition to lateral current flow in a time-averaged calculation. More ecient and accurate models for planarization of shallow-trench isolation (STI) structures are proposed, with a focus on die-scale and feature-scale uniformity. This thesis captures the fundamental weakness of CMP, pattern dependencies, and uses deposition prole effects as well as the pattern-density to more accurately model and physically represent STI structures during CMP. We model, for the first time, the evolution of pattern density as a function of time and step-height, and use layout biasing to account for deposition prole evolution for the accurate prediction of die and feature-scale CMP.
by Joy Marie Johnson.
S.M.
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Crutchfield, David Allen. "VERIFICATION AND DEBUG TECHNIQUES FOR INTEGRATED CIRCUIT DESIGNS." UKnowledge, 2009. http://uknowledge.uky.edu/gradschool_theses/631.
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Verification and debug of integrated circuits for embedded applications has grown in importance as the complexity in function has increased dramatically over time. Various modeling and debugging techniques have been developed to overcome the overwhelming challenge. This thesis attempts to address verification and debug methods by presenting an accurate C model at the bit and algorithm level coupled with an implemented Hardware Description Language (HDL). Key concepts such as common signal and variable naming conventions are incorporated as well as a stepping function within the implemented HDL. Additionally, a common interface between low-level drivers and C models is presented for early firmware development and system debug. Finally, selfchecking verification is discussed for delivering multiple test cases along with testbench portability.
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Kimoto, Daiki. "Characterization and Modeling of SiC Integrated Circuits for Harsh Environment." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-223422.
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Elektronik för extrema miljöer, som kan användas vid hög temperatur, hög strålning och omgivning med frätande gaser, har varit starkt önskvärd vid utforskning av rymden och övervakning av kärnreaktorer. Kiselkarbid (SiC) är en av kandidaterna inom material för extrema miljöer på grund av sin höga temperatur- och höga strålnings-tolerans. Syftet med denna avhandling är att karakterisera 4H-SiC MOSFETar vid hög temperatur och att konstruera SPICE modeller för 4H-SiC MOSFETar. MOSFET-transistorer karakteriserades till 500°C. Med användande av karaktäristik för en 4H-SiC NMOSFET med L/W = 10 µm / 50 µm, anpassades en SPICE LEVEL 2 kretsmodell. Modellen beskriver DC karakteristiska av 4H- SiC MOSFETar mellan 25ºC och 450ºC. Baserat på SPICE-kretsmodellen simulerades egenskaper för operationsförstärkare och digitala inverterar. Därutöver analyserades driften av pseudo-CMOS vid hög temperatur och principen för konstruktion av pseudo-CMOS föreslogs. Arean och utbytet (s.k. yield) av pseudo-CMOS integrerade kretsar uppskattades och det visar sig att SiC pseudo-CMOS integrerade kretsar kan använda mindre area än SiC CMOS integrerade kretsar.Harsh environment electronics, which can be operated at high-temperature, high-radiation, and corrosive gas environment, has been strongly desired in space exploration and monitoring of nuclear reactors. Silicon Carbide (SiC) is one of the candidates of materials for harsh environment electronics because of its high-temperature and high-radiation tolerance. The objective of this thesis is to characterize 4H-SiC MOSFETs at high- temperature and to construct SPICE models of the 4H-SiC MOSFETs. The MOSFET devices were characterized up to 500ºC. Using the characteristic of a 4H-SiC NMOSFET with L/W = 10 µm/50 µm, a SPICE LEVEL 2 circuit model was constructed. This model describes the DC characteristic of the 4H-SiC MOSFETs in the range of 25 – 450ºC. Based on the SPICE circuit model, the characteristics of operational amplifiers and digital inverters were simulated. Furthermore, the operation of pseudo-CMOS at high-temperature was analyzed and the operation principle of pseudo-CMOS was suggested. The device area and yield of pseudo-CMOS integrated circuits were estimated and it is shown that SiC pseudo-CMOS integrated circuits can use less area than SiC CMOS integrated circuits.
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Narayanan, Sundaram. "Design and development of an object-oriented architecture for modeling and simulation of discrete-part manufacturing systems." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/24374.
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Khakimbayev, Jasur S. "Development of integrated 3D terrain maps for Unmanned Aerial Vehicle (UAV) Flight and Mission Control Support System (FMCSS)." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2006. http://library.nps.navy.mil/uhtbin/hyperion/06Mar%5FKhakimbayev.pdf.
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Thesis (M.S. in Modeling, Virtual Environments, and Simulation (Moves))--Naval Postgraduate School, March 2006.Thesis Advisor(s): Wolfgang Baer, Curtis L. Blais. "March 2006." Includes bibliographical references (p.99-101). Also available online.
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Rendell, Gerard Vincent Alfred. "An integrated modeling framework for concept formation : developing number-sense, a partial resolution of the learning paradox." Thesis, Kingston University, 2012. http://eprints.kingston.ac.uk/27841/.
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The development of mathematics is foundational. For the most part in early childhood it is seldom insurmountable. Various constructions exhibit conceptual change in the child, which is evidence of overcoming the learning paradox. If one tries to account for learning by means of mental actions carried out by the learner, then it is necessary to attribute to the learner a prior structure , one that is as advanced or as complex as the one to be acquired, unless there is emergence. This thesis reinterprets Piaget's theory using research from neurophysiology, biology, machine learning and demonstrates a novel approach to partially resolve the learning paradox for a simulation that experiences a number line world, exhibiting emergence of structure using a model of Drosophila. In doing so, the research evaluates other models of cognitive development against a real-world, worked example of number-sense from childhood mathematics. The purpose is to determine if they assume a prior capacity to solve problems or provide parallel assumptions within the learning process as additional capabilities not seen in children. Technically, the research uses an artificial neural network with reinforcement learning to confirm the emergence of permanent object invariants. It then evaluates an evolved dialectic system with hierarchical finite state automata within a reactive Argos framework to confirm the reevaluated Piagetian developmental model against the worked example. This research thesis establishes that the emergence of new concepts is a critical need in the development of autonomous evolvable systems that can act, learn and plan in novel ways, in noisy situations.
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Joshi, Anand Mukund. "Behavioral delay fault modeling and test generation." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-07292009-090436/.
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Naber, John F. "The optimization of SPICE modeling parameters utilizing the Taguchi methodology." Diss., Virginia Tech, 1992. http://hdl.handle.net/10919/38542.
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A new optimization technique for SPICE modeling parameters has been developed in this dissertation to increase the accuracy of the
circuit simulation. The importance of having accurate circuit simulation models is to prevent the very costly redesign of an
Integrated Circuit (IC). This radically new optimization technique utilizes the Taguchi method to improve the fit between measured and
simulated I-V curves for GaAs MESFETs. The Taguchi method consists of developing a Signal-to-Noise Ratio (SNR) equation that will find the optimum combination of controllable signal levels in a design or process to make it robust or as insensitive to noise as
possible. In this dissertation, the control factors are considered the circuit model curve fitting parameters and the noise is
considered the variation in the simulated I-V curves from the measured I-V curves. This is the first known application of the
Taguchi method to the optimization of IC curve fitting model parameters. In addition, this method is not technology or device dependent and can be applied to silicon devices as well. Improvements in the accuracy of the simulated I-V curve fit reaching 80% has been achieved between DC test extracted parameters and the Taguchi optimized parameters. Moreover, the computer CPU execution time of the optimization process is 96% less than a commercial optimizer utilizing the Levenberg-Marquardt algorithm (optimizing 31 FETs). This technique does a least square fit on the data comparing measured currents versus simulated currents for various combinations of SPICE parameters. The mean and standard deviation of this least squares fit is incorporated in determining the SNR, providing the best combination of parameters within the evaluated range. Furthermore, the optimum values of the parameters are found without additional simulation by fitting the response curves to a quadratic equation and finding the local maximum. This technique can easily be implemented with any simulator that utilizes simulation modeling parameters extracted from measured DC test data. In addition, two methods are evaluated to obtain the worst case modeling parameters. One method lobks at the correlation coefficients between modeling parameters and the second looks at the actual device parameters that define the +/- 30 limits of the process. Lastly, an example is given that describes the applicability of the Taguchi methodology in the design of a differential amplifier, that accounts for the effect of offset voltage.Ph. D.
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Bounhieng, Vilaysane. "INTEGRATED IMPACT ASSESSMENT OF CLIMATE CHANGE ON HYDROLOGY OF THE XEDONE RIVER BASIN, LAO PDR." 京都大学 (Kyoto University), 2016. http://hdl.handle.net/2433/204586.
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Menezes, Gary. "Modeling, design, fabrication and characterization of glass package-to-PCB interconnections." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/51781.
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Emerging I/O density and bandwidth requirements are driving packages to low-CTE silicon, glass and organic substrates for higher wiring density and reliability of interconnections and Cu-low k dielectrics. These are needed for high performance applications as 2.5D packages in large-size, and also as ultra-thin packages for consumer applications that are directly assembled on the board without the need for an intermediate package.
The trend to low-CTE packages (CTE of 3-8ppm/°C), however, creates large CTE mismatch with the board on which they are assembled. Interconnection reliability is, therefore, a major concern when low CTE interposers are surface mounted onto organic system boards via solder joints. This reliability concern is further aggravated with large package sizes and finer pitch. For wide acceptance of low CTE packages in high volume production, it is also critical to assemble them on board using standard Surface Mount Technologies (SMT) without the need for under-fill. This research aims to demonstrate reliable 400 micron pitch solder interconnections from low CTE glass interposers directly assembled onto organic boards by overcoming the above challenges using two approaches; 1) Stress-relief dielectric build up layers on the back of the interposer, 2) Polymer collar around the solder bumps for shear stress re-distribution. A comprehensive methodology based on modeling, design, test vehicle fabrication and characterization is employed to study and demonstrate the efficacy of these approaches in meeting the interposer-to-board interconnection requirements. The effect of varying geometrical and material properties of both build-up layers and polymer collar is studied through Finite Element Modeling. Interposers were designed and fabricated with the proposed approaches to demonstrate process feasibility.
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Pop, Adrian. "Integrated Model-Driven Development Environments for Equation-Based Object-Oriented Languages." Doctoral thesis, Linköping : Department of Computer and Information Science, Linköpings universitet, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-11416.
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Park, Hoon. "Formal Modeling and Verification of Delay-Insensitive Circuits." PDXScholar, 2015. https://pdxscholar.library.pdx.edu/open_access_etds/2639.
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Einstein's relativity theory tells us that the notion of simultaneity can only be approximated for events distributed over space. As a result, the use of asynchronous techniques is unavoidable in systems larger than a certain physical size. Traditional design techniques that use global clocks face this barrier of scale already within the space of a modern microprocessor chip. The most common response by the chip industry for overcoming this barrier is to use Globally Asynchronous Locally Synchronous (GALS) design techniques. The circuits investigated in this thesis can be viewed as examples of GALS design. To make such designs trustworthy it is necessary to model formally the relative signal delays and timing requirements that make these designs work correctly. With trustworthy asynchrony one can build reliable, large, and scalable systems, and exploit the lower power and higher speed features of asynchrony.
This research presents ARCtimer, a framework for modeling, generating, verifying, and enforcing timing constraints for individual self-timed handshake components that use bounded-bundled-data handshake protocols. The constraints guarantee that the component's gate-level circuit implementation obeys the component's handshake protocol specification. Because the handshake protocols are delay insensitive, self-timed systems built using ARCtimer-verified components can be made delay insensitive. Any delay sensitivity inside a component is detected and repaired by ARCtimer. In short: by carefully considering time locally, we can ignore time globally.
ARCtimer applies early in the design process as part of building a library of verified components for later system use. The library also stores static timing analysis (STA) code to validate and enforce the component's constraints in any self-timed system built using the library. The library descriptions of a handshake component's circuit, protocol, timing constraints, and STA code are robust to circuit modifications applied later in the design process by technology mapping or layout tools.
New contributions of ARCtimer include:
1. Upfront modeling on a component by component basis to reduce the validation effort required to
(a) reimplement components in different technologies,
(b) assemble components into systems, and
(c) guarantee system-level timing closure.
2. Modeling of bounded-bundled-data timing constraints that permit the control signals to lead or lag behind data signals to optimize system timing.
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Liu, Xiang. "Reliability study of InGaP/GaAs heterojunction bipolar transistor MMIC technology by characterization, modeling and simulation." Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4967.
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HBT-based MMIC performance is very sensitive to the variation of core device characteristics and the reliability issues put the limit on its radio frequency (RF) behaviors. While many researchers have reported the observed stress-induced degradations of GaAs HBT characteristics, there has been little published data on the full understanding of stress impact on the GaAs HBT-based MMICs. If care is not taken to understand this issue, stress-induced degradation paths can lead to built-in circuit failure during regular operations. However, detection of this failure may be difficult due to the circuit complexity and lead to erroneous data or output conditions. Thus, a practical and analytical methodology has been developed to predict the stress impacts on HBT-based MMICs. It provides a quick way and guidance for the RF design engineer to evaluate the circuit performance with reliability considerations. Using the present existing EDA tools (Cadance SpectreRF and Agilent ADS) with the extracted pre- and post-stress transistor models, the electrothermal stress effects on InGaP/GaAs HBT-based RF building blocks including power amplifier (PA), low-noise amplifier (LNA) and oscillator have been systematically evaluated. This provides a potential way for the RF/microwave industry to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of advanced GaAs HBT MMIC technology and researchers have been exploring here for years. The reliability of GaAs HBT technology is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation provide methods and guidance for the RF designers to achieve more reliable RF circuits with advanced GaAs HBT technology in the future.; Recent years have shown real advances of microwave monolithic integrated circuits (MMICs) for millimeter-wave frequency systems, such as wireless communication, advanced imaging, remote sensing and automotive radar systems, as MMICs can provide the size, weight and performance required for these systems. Traditionally, GaAs pseudomorphic high electron mobility transistor (pHEMT) or InP based MMIC technology has dominated in millimeter-wave frequency applications because of their high fsubscript T] and fsubscript max] as well as their superior noise performance. But these technologies are very expensive. Thus, for low cost and high performance applications, InGaP/GaAs heterojunction bipolar transistors (HBTs) are quickly becoming the preferred technology to be used due to their inherently excellent characteristics. These features, together with the need for only one power supply to bias the device, make InGaP/GaAs HBTs very attractive for the design of high performance fully integrated MMICs. With the smaller dimensions for improving speed and functionality of InGaP/GaAs HBTs, which dissipate large amount of power and result in heat flux accumulated in the device junction, technology reliability issues are the first concern for the commercialization. As the thermally triggered instabilities often seen in InGaP/GaAs HBTs, a carefully derived technique to define the stress conditions of accelerated life test has been employed in our study to acquire post-stress device characteristics for the projection of long-term device performance degradation pattern. To identify the possible origins of the post-stress device behaviors observed experimentally, a two dimensional (2-D) TCAD numerical device simulation has been carried out. Using this approach, it is suggested that the acceptor-type trapping states located in the emitter bulk are responsible for the commonly seen post-stress base current instability over the moderate base-emitter voltage region.ID: 030423028; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 82-88).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
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Nugent, Steven Paul. "A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC)." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6885.
Full textAbstract:
Future opportunities for gigascale integration will be governed by a hierarchy of theoretical and practical limits that can be codified as follows: fundamental, material, device, circuit, and system. An exponential increase in on-chip integration is driving System-on-Chip (SoC) methodologies as a dominant design solution for gigascale ICs. Therefore, a second generation generic systems simulator (GENESYS) is developed to address a need for rapid assessment of technology/architecture tradeoffs for multi-billion transistor SoCs while maintaining the depth of core modeling codified in the hierarchy of limits. A newly developed system methodology incorporates a hiearchical block-based model, a dual interconnect distribution for both local and global interconnects, a generic on-chip bus model, and cell placement algorithms. A comparison of simulation results for five commercial SoC implementations shows increased accuracy in predicting die size, clock frequency, and total power dissipation. ITRS projections for future technology requirments are applied with results indicating that increasing static power dissipation is a key impediment to making continued improvements in chip performance. Additionally, simulations of a generic chip multi-processor architecture utilizing several interconnect schemes shows that the most promising candidate for the future of on-chip global interconnect networks will be hierarchical bus structures providing a high degree of connectivity while maintaining high operating frequencies.
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Panchal, Jitesh H. "A framework for simulation-based integrated design of multiscale products and design processes." Diss., Available online, Georgia Institute of Technology, 2005, 2005. http://etd.gatech.edu/theses/available/etd-11232005-112626/.
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Thesis (Ph. D.)--Mechanical Engineering, Georgia Institute of Technology, 2006.Eastman, Chuck, Committee Member ; Paredis, Chris, Committee Co-Chair ; Allen, Janet, Committee Member ; Rosen, David, Committee Member ; Tsui, Kwok, Committee Member ; McDowell, David, Committee Member ; Mistree, Farrokh, Committee Chair. Includes bibliographical references.
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Kumar, Sharad Kumar. "Analysis of Machine Learning Modeling Attacks on Ring Oscillator based Hardware Security." University of Toledo / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1541759752027838.
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Shiang, Jyue-Jon 1956. "APTMC: AN INTERFACE PROGRAM FOR USE WITH ANSYS FOR THERMAL AND THERMALLY INDUCED STRESS MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/291399.
Full textAbstract:
ANSYS Packaging Thermal/Mechanical Calculator (APTMC) is an interface program developed for use with ANSYS and specially designed to handle thermal and thermally induced stress modeling/simulation of Level 1 and Level 2 VLSI packaging structures and assemblies. APTMC is written in PASCAL and operates in an interactive I/O format mode. This user-friendly tool leads an analyst/designer through the process of creating appropriate thermal and thermally induced stress models and other operations necessary to run ANSYS. It includes such steps as the following: (1) construction of ANSYS commands through the string process; (2) creation of a dynamic data structure which expands and contracts during program execution based on the data storage requirements of the program sets to control model generation; (3) access of material data and model parameters from the developed INTERNAL DATABANK which contains: (a) material data list; (b) heat transfer modes; and (c) library of structures; (4) forming ANSYS PREP7 and POSTn command files. (Abstract shortened with permission of author.)
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Liu, Yidong. "CMOS RF cituits sic] variability and reliability resilient design, modeling, and simulation." Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4969.
Full textAbstract:
Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.; The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (Vsubscript T) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (Vsubscript T]) shift and 25% to electron mobility (mu subscript n]) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and device aging such as threshold voltage shift and electron mobility degradation.ID: 029809399; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 90-105).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
41
Wen, Yangyang. "MODELING AND DIGITAL CONTROL OF HIGH FREQUENCY DC-DC POWER CONVERTERS." Doctoral diss., University of Central Florida, 2007. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3671.
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The power requirements for leading edge digital integrated circuits have become increasingly demanding. Power converter systems must be faster, more flexible, more precisely controllable and easily monitored. Meanwhile, in addition to control process, the new functions such as power sequencing, communication with other systems, voltage dynamic programming,load line specifications, phase current balance, protection, power status monitoring and system diagnosis are going into today's power supply systems. Digital controllers, compared withanalog controllers, are in a favorable position to provide basic feedback control as well as those power management functions with lower cost and great flexibility. The dissertation gives an overview of digital controlled power supply systems bycomparing with conventional analog controlled power systems in term of system architecture,modeling methods, and design approaches. In addition, digital power management, as one of the most valuable and "cheap" function, is introduced in Chapter 2. Based on a leading-edge digital controller product, Chapter 3 focuses on digital PID compensator design methodologies, design issues, and optimization and development of digital controlled single-phase point-of-load (POL)dc-dc converter. Nonlinear control is another valuable advantage of digital controllers over analogcontrollers. Based on the modeling of an isolated half-bridge dc-dc converter, a nonlinear control method is proposed in Chapter 4. Nonlinear adaptive PID compensation scheme is implemented based on digital controller Si8250. The variable PID coefficient during transients improves power system's transient response and thus output capacitance can be reduced to save cost. In Chapter 5, another nonlinear compensation algorithm is proposed for asymmetric flybackforward half bridge dc-dc converter to reduce the system loop gain's dependence on the input voltage, and improve the system's dynamic response at high input line. In Chapter 6, a unified pulse width modulation (PWM) scheme is proposed to extend the duty-cycle-shift (DCS) control, where PWM pattern is adaptively generated according to the input voltage level, such that the power converter's voltage stress are reduced and efficiency is improved. With the great flexibility of digital PWM modulation offered by the digital controller Si8250, the proposed control scheme is implemented and verified. Conclusion of the dissertation work and suggestions for future work in related directions are given in final Chapter.Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD
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Elahi, Behin. "Integrated Optimization Models and Strategies for Green Supply Chain Planning." University of Toledo / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1467266039.
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Zhu, Wenhua. "3D modeling of city building and lifecycle simulation." Thesis, Compiègne, 2017. http://www.theses.fr/2017COMP2344/document.
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Avec la construction et le développement de la ville intelligente, la façon de construire le modèle 3D réaliste des grands bâtiments de la ville rapidement et efficacement devient le hotspot de recherche. Dans cette thèse, une méthode procédurale de modélisation intelligente est proposée pour construire rapidement et efficacement un modèle de construction de ville 3D à grande échelle basé sur la modélisation de la forme de la façade et de la grammaire de forme. La technologie de l'information du bâtiment (BIM) est un moyen technique important pour améliorer l'industrie de la construction, pour la conception du bâtiment de la ville et la construction de la meilleure recherche et l'application de la technologie BIM est la clé, de gérer efficacement les informations du cycle de vie du bâtiment et de réaliser le partage et l'échange. Cette thèse a étudié l'acquisition et le traitement des données de modélisation. Google Earth et le logiciel ArcGIS sont principalement utilisés pour acquérir et traiter des données d'images-cartes et des données de cartes d'élévation de la zone cible, ces deux types de correspondance et de superposition de données, qui peuvent générer des données de terrain urbain 3D avec des informations de localisation géographique. Ensuite OpenStreetMap est utilisé pour acquérir les données routières de la zone cible, et il peut être optimisé pour le réseau routier nécessaire par le logiciel JOSM. La technologie de balayage laser 3D est utilisée pour collecter des images de texture de surface de bâtiment et pour créer le modèle de nuages de points de la modélisation d'architecture cible afin d'obtenir les dimensions de modélisation par mesure. Sur cette base, cette thèse a principalement étudié le principe et le processus de la règle CGA pour créer des modèles de construction, et étudié la méthode qui peut séparer les éléments architecturaux en utilisant la segmentation d'image pour générer automatiquement la règle CGA et de créer ensuite le modèle de construction. Ainsi, des modèles de construction 3D ont été établis dans le logiciel CityEngine en utilisant les règles CGA et la technologie de segmentation des façades. Cette thèse a construit le modèle d'information intégré au bâtiment urbain (CBIIM) basé sur BIM. L'information sur la construction de la ville est classée et intégrée, et le bâtiment et la composante ont été décrits avec la norme IFC, afin de gérer efficacement les informations du cycle de vie du bâtiment. Cette thèse étudie la technologie du modèle d'association d'information intégrée, qui permet de réaliser une conception standardisée des composants avec des caractéristiques associées et une conception intelligente des bâtiments avec des paramètres associés dans les règles de connaissances combinées avec l'IFC. La technologie de simulation de la construction de visualisation est étudiée. Les règles de connaissance dans le modèle d'information intégré fournissent une référence fiable pour la simulation de construction, et la scène de simulation est créée en invoquant le modèle d'information intégré, ainsi le processus de simulation est terminé. En prenant le campus Baoshan de l'Université de Shanghai comme exemple, le processus de modélisation de la scène entière est illustré, et les étapes de modélisation de toutes sortes d'objets 3D sont décrites en détail pour résoudre les problèmes spécifiques dans le processus de modélisation réelle. Ainsi, la faisabilité et la validité de la méthode de modélisation intelligente procédurale sont vérifiées. Prenant comme exemple le dortoir de l'Université de Shanghai, une simulation et le modèle de simulation ont été créés par les informations intégrées, combinées aux informations de construction pertinentes, la simulation de construction a été complétée par le programme. Ainsi, la faisabilité et la validité du CBIIM sont vérifiéesWith the construction and development of the smart city, how to construct the realistic 3D model of the large-scale city buildings quickly and efficiently which becomes the research hotspot. In this thesis, a novel 3D modeling approach is proposed to quickly and efficiently build 3D model of large-scale city buildings based on shape grammar and facade rule modeling. Building Information Model (BIM) is an important technical means to enhance the construction industry, for the city building design and construction, how to better research and application of BIM technology which is the key, in this thesis City Building Integrated Information Model (CBIIM) is specified to manage the information of building lifecycle effectively and realize the information sharing and exchanging. This thesis has studied the acquisition and processing of the modeling data. Google Earth and ArcGIS software are mainly used to acquire and process image-maps data and elevation-maps data of the target area, these two kinds of data match and overlay, which can generate 3D city terrain data with geographic location information. Then OpenStreetMap is used to acquire road data of the target area, and it can be optimal processed to the necessary road network by JOSM software. 3D laser scanning technology is used to collect building surface texture images and create the point clouds model of the target architecture modeling so as to get the modeling dimensions by measurement. On this basis, this thesis mainly has studied the principle and the process of CGA rule to create building models, and studied the method that can separate architectural elements using image segmentation to generate CGA rule automatically and to create building model furtherly. Thus 3D building models have been established in the CityEngine software using CGA rules and facade modeling technology. This thesis has specified the City Building Integrated Information Model (CBIIM) based on BIM. The city building information are classified and integrated, and the building and component was described with the IFC standard, in order to manage the informations of building lifecycle effectively. This thesis studies the integrated information association model technology, that it can realize standardized component design with associated features and intelligent building design with associated parameters in knowledge rules combined with IFC. The construction simulation technology is studied. The knowledge rules in the integrated information model provide a reliable reference for the construction simulation, and the simulation scene is created through the invoking the integrated information model, thus the construction simulation process is completed by the program. Taking Baoshan Campus of Shanghai University as an example, the modeling process of the whole scene is illustrated, and the modeling steps of all kinds of 3D objects are described in detail to solve the specific problems in the actual modeling process. Thus the feasibility and validity of the procedural intelligent modeling approach are verified. Taking the dormitory of Shanghai University as an example, a simulation scene and the simulation model were created by the integrated informations, combined with the relevant construction information the construction simulation was completed by the program. Thus the feasibility and validity of the CBIIM are verified
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Seo, Chung-Seok. "Physical Design of Optoelectronic System-on-a-Chip/Package Using Electrical and Optical Interconnects: CAD Tools and Algorithms." Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-11102004-150844/.
Full textAbstract:
Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.David E. Schimmel, Committee Member ; C.P. Wong, Committee Member ; John A. Buck, Committee Member ; Abhijit Chatterjee, Committee Chair ; Madhavan Swaminathan, Committee Member. Vita. Includes bibliographical references.
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Varsamidis, Thomas. "Object-oriented information modelling for computer-aided control engineering." Thesis, Bangor University, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.245177.
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Long, Jianghua. "Computer-integrated information modelling for design of building structures /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?CIVL%202004%20LONG.
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Thesis (Ph. D.)--Hong Kong University of Science and Technology, 2004.Includes bibliographical references (leaves 223-232). Also available in electronic version. Access restricted to campus users.
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Zhong, Shida. "Fault modelling and accelerated simulation of integrated circuits manufacturing defects under process variation." Thesis, University of Southampton, 2013. https://eprints.soton.ac.uk/349929/.
Full textAbstract:
As silicon manufacturing process scales to and beyond the 65-nm node, process variation can no longer be ignored. The impact of process variation on integrated circuit performance and power has received significant research input. Variation-aware test, on the other hand, is a relatively new research area that is currently receiving attention worldwide. Research has shown that test without considering process variation may lead to loss of test quality. Fault modelling and simulation serve as a backbone of manufacturing test. This thesis is concerned with developing efficient fault modelling techniques and simulation methodologies that take into account the effect of process variation on manufacturing defects with particular emphasis on resistive bridges and resistive opens. The first contribution of this thesis addresses the problem of long computation time required to generate logic fault of resistive bridges under process variation by developing a fast and accurate modelling technique to model logic fault behaviour of resistive bridges.The new technique is implemented by employing two efficient voltage calculation algorithms to calculate the logic threshold voltage of driven gates and critical resistance of a fault-site to enable the computation of bridge logic faults without using SPICE. Simulation results show that the technique is fast (on average 53 times faster) and accurate (worst case is 2.64% error) when compared with HSPICE. The second contribution analyses the complexity of delay fault simulation of resistive bridges to reduce the computation time of delay fault when considering process variation. An accelerated delay fault simulation methodology of resistive bridges is developed by employing a three-step strategy to speed up the calculation of transient gate output voltage which is needed to accurately compute delay faults. Simulation results show that the methodology is on average 17.4 times faster, with 5.2% error in accuracy, when compared with HSPICE. The final contribution presents an accelerated simulation methodology of resistive opens to address the problem of long simulation time of delay fault when considering process variation. The methodology is implemented by using two efficient algorithms to accelerate the computation of transient gate output voltage and timing critical resistance of an open fault-site. Simulation results show that the methodology is on average up to 52 times faster than HSPICE, with 4.2% error in accuracy.
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Dupont, Lionel. "Algorithmes et ordonnancements." Phd thesis, Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37597342h.
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Richards, Andrew John. "An integrated approach to three-dimensional computer modelling of sedimentary basins." Thesis, Keele University, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.311738.
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Yu, Bing. "Hybrid modelling methodology for system design." Thesis, Loughborough University, 1995. https://dspace.lboro.ac.uk/2134/6999.
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In the face of rapid development in information technology coupled with a growing dynamism in global markets, manufacturing systems have to be re-constructed for short term or long term goal. Such innovations promise to lead to a new competitive stage, which typically involve design of function, information and behaviour of systems. In order to design the system, simulation has often been chosen. However, simulation has proved limited and fails to aid design of such a complex systems because of consuming much computing time and cost, especially when modelling larger systems. Thus, there is a need to seek a new approach, in a way that results in simulating such a large manufacturing system with less demand on computing time and cost. This study researches into a hybrid modelling approach to minimise these limitations. It includes proposing a hybrid modelling methodology and developing a hybrid modelling tool. The methodology integrates simulation and metamodelling techniques. The metamodel employed in the study possesses, not only characteristics of conventional metamodels in terms of representing relationships in quantity, but also in time lapse. This is the originality of the study and the significant distinction between this research and application of metamodelling in conventional ways. The hybrid modelling tool is developed to support and demonstrate the identified hybrid methodology. LISP has been used as the software language for the hybrid modelling tool. The result of this work concludes that the hybrid modelling approach is capable of simulating a complex manufacturing system with less demands on the computer. The work reported in this thesis has been carried out in conjunction with the EPSRC research project, Hierarchical Manufacturing System Modelling (HMSM) (GR/F96549), to produce an Integrated Design and Modelling Methodology (IDEM). The project was initially a collaborative research program including Loughborough University of Technology (LUT), Morris Crane Ltd., of Loughborough and GEC Large Machine, of Rugby. The experience of these collaborators has proved most valuable in supporting the research, and have provided a cross section of views and comments. The research reported in this thesis is set in the context of the HMSM Research group at Loughborough.