Dissertations / Theses on the topic 'Integrated circuits'
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1
Загулов, Станіслав Русланович. "Flexible integrated circuits." Thesis, Київський національний університет технологій та дизайну, 2020. https://er.knutd.edu.ua/handle/123456789/15297.
2
Pettazzi, Federico. "Integrated soliton circuits." Besançon, 2008. http://www.theses.fr/2008BESA2001.
Abstract:
Dans ce travail de thèse nous abordons le développement de circuits optiques intégrés tri-dimensionnels (3-D), la technique pour induire ces guides est basée sur les solitons spatiaux photorefractifs. Les démonstrations expérimentales sont réalisées dans le niobate de lithum (LiNbO3) ce qui permet de bénéficier de l'excellente qualité optique de ce matériau associée à une forte réponse photoréfractive, Dans un premier chapitre, les principaus problèmes liés aux interconnections optiques sont identifiés et une solution exploitant les solitons spatiaux photorefractifs est proposée. Dans un deuxième chapitre, les principales propriétés du LiNbO3 sont tout d'abord rappelées. Ensuite, la formation de solitons brillants photorefractifs est démontrée tant théoriquement qu'expérimentalement. Par la suite, le piégeage d'un faisceau dans le proche infra-rouge via la génération de deuxième harmonique est étudié en condition d'accord de phase et également loin de l'accord de phase. Les analyses expérimentale et numérique montrent que dans le premier cas la combinaison des processus quadratique et photoréfractif provoque l'induction d'une structure guidante dont le caractère multimode peut être contrôlé, Dans le cas d'un fort désaccord de phase nous avons démontré que le piégeage de la lumière est également effectif malgré la faiblesse de l'efficacité de conversion. Finalement, l'impact du dopage erbium d'échantillon de LiNbO3 est étudié, le but ultime étant de parvenir à démontrer l'amplification optique dans des guides photoinduits. Les résultats montrent que le LiNbO3 dopé erbium permet hl. Formation de guides photoinduits par effet photorefractifIn the present thesis the development of three dimensional integrated optical circuits exploiting the technique of photorefractive bright spatial solitons is addressed. The considered host material is Lithium Niobate (LiNbO3) that benefits from a well developed technological standard and possesses a large photorefractive response. Ln the first part, main problems related to optical interconnections are identified, and a solution based on photorefractive bright spatial solitons is proposed. Ln a second Chapter, after a brief review of the material properties, the formation of photorefractive bright solitons is demonstrated both tlleoretically and experimentally. Subsequently, the occurrence of photorefractive self-focusing via second hannonic generation is investigated in conditions near and far from perfect phase matching. Experimetal and numerical analysis shows that, in the case near phase matching, a complexe interaction between nonlinear quadratic process and photorefractivity causes multimode propagation inside self induced waveguide. Proper initial conditions can however lead to stable singlemode operation with high second harmonic conversion efficiency. For strongly mismatched condition we demonstrate that self-focusing effect can occur in the near infrared spectrum due to the weak second harmonic generated signal. Finally, the potentiality of erbium doped LiNbO3 has been tested by performing material characterization and self-focusing experiments. Results show that erbium doped crystals are suitable for formation of self-induced waveguides. Realisation of optical ciruits performing optical amplification and lasing in self-induced waveguides can be envisioned
3
Gustard, N. C. "Optimizes switched-capacitor filter circuits for integrated circuit realization." Thesis, University of Essex, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.294667.
4
Kapur, Kishen Narain. "Mechanical and electrical characterization of IC leads during fatigue cycling." Diss., Online access via UMI:, 2009.
Abstract:
Thesis (Ph. D.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Electrical and Computer Engineering, 2009.Includes bibliographical references.
5
Lee, Kyung Tek. "Crosstalk fault test generation and hierarchical timing verification in VLSI digital circuits /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
6
Fayed, Ayman Adel. "Adaptive techniques for analog and mixed signal integrated circuits." Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1097519730.
Abstract:
Thesis (Ph. D.)--Ohio State University, 2004.Title from first page of PDF file. Document formatted into pages; contains xix, 232 p.; also includes graphics (some col.). Includes bibliographical references (p. 222-230).
7
Bakir, Muhannad S. "Sea of Leads electrical-optical polymer pillar chip I/O interconnections for gigascale integration." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04082004-180010/unrestricted/bakir%5Fmuhannad%5Fs%5F200312%5Fphd.pdf.
8
Qazi, Masood. "Circuit design for embedded memory in low-power integrated circuits." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/75645.
Abstract:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 141-152).
This thesis explores the challenges for integrating embedded static random access memory (SRAM) and non-volatile memory-based on ferroelectric capacitor technology-into lowpower integrated circuits. First considered is the impact of process variation in deep-submicron technologies on SRAM, which must exhibit higher density and performance at increased levels of integration with every new semiconductor generation. Techniques to speed up the statistical analysis of physical memory designs by a factor of 100 to 10,000 relative to the conventional Monte Carlo Method are developed. The proposed methods build upon the Importance Sampling simulation algorithm and efficiently explore the sample space of transistor parameter fluctuation. Process variation in SRAM at low-voltage is further investigated experimentally with a 512kb 8T SRAM test chip in 45nm SOI CMOS technology. For active operation, an AC coupled sense amplifier and regenerative global bitline scheme are designed to operate at the limit of on current and off current separation on a single-ended SRAM bitline. The SRAM operates from 1.2 V down to 0.57 V with access times from 400ps to 3.4ns. For standby power, a data retention voltage sensor predicts the mismatch-limited minimum supply voltage without corrupting the contents of the memory. The leakage power of SRAM forces the chip designer to seek non-volatile memory in applications such as portable electronics that retain significant quantities of data over long durations. In this scenario, the energy cost of accessing data must be minimized. This thesis presents a ferroelectric random access memory (FRAM) prototype that addresses the challenges of sensing diminishingly small charge under conditions favorable to low access energy with a time-to-digital sensing scheme. The 1 Mb IT1C FRAM fabricated in 130 nm CMOS operates from 1.5 V to 1.0 V with corresponding access energy from 19.2 pJ to 9.8 pJ per bit. Finally, the computational state of sequential elements interspersed in CMOS logic, also restricts the ability to power gate. To enable simple and fast turn-on, ferroelectric capacitors are integrated into the design of a standard cell register, whose non-volatile operation is made compatible with the digital design flow. A test-case circuit containing ferroelectric registers exhibits non-volatile operation and consumes less than 1.3 pJ per bit of state information and less than 10 clock cycles to save or restore with no minimum standby power requirement in-between active periods.
by Masood Qazi.
Ph.D.
9
Paroski, Andrew John. "Deform a new approach for redistributing placements /." Diss., Online access via UMI:, 2006.
10
Agnihotri, Ameya Ramesh. "Combinatorial optimization techniques for VLSI placement." Diss., Online access via UMI:, 2007.
11
Micallef, Steven P. "Hierarchical testing of integrated circuits." Thesis, University of Oxford, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.291399.
12
Dixon, James Edward. "Towards integrated scalable nanophotonic circuits." Thesis, University of Sheffield, 2017. http://etheses.whiterose.ac.uk/18282/.
Abstract:
This thesis presents optical measurements used to explore nanophotonic circuits composed of III-V semiconductors with embedded quantum dots. The focus of this work is to investigate issues related to the scalability and performance of these structures. A technique to register the position of a quantum dot, relative to pre-fabricated registration markers, with the aid of a solid immersion lens, is developed. The variance in the repeatedly registered position of the quantum dot is shown to be significantly reduced as a result of the solid immersion lens, compared with positions registered without a solid immersion lens. The total error of the deterministic fabrication, using position registered quantum dots, is small when compared to the size of optical fields. Confirmation of this has been achieved through two independent methods. Re-registration of the position relative to deterministically positioned registration markers show that the total error of deterministic fabrication is small. Additionally, the demonstration of optical spin readout, via the deterministic positioning of a quantum dot at a chiral point of a suspended nanobeam waveguide, further confirms the positional accuracy of the technique. The demonstration of efficiently coupled single photons form an embedded quantum into a nanobeam waveguide, with enhanced coherence lengths due to resonant excitation, is achieved. A high level of resonant laser rejection is demonstrated due to the orthogonal excitation and waveguide propagation directions.
13
Al, Bastami Anas Ibrahim. "Power monitoring in integrated circuits." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/92973.
Abstract:
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 201-203).
Power monitoring is needed in most electrical systems, and is crucial for ensuring reliability in everything from industrial and telecom applications, to automotive and consumer electronics. Power monitoring of integrated circuits (ICs) is also essential, as today ICs exist in most electrical and electronic systems, in a vast range of applications. Many ICs, including power ICs, have functional blocks across the chip that are used for different purposes. Measuring circuit block currents in both analog and digital ICs is important in a wide range of applications, including power management as well as IC testing and fault detection and analysis. For example, the presence of different kinds of faults in IC circuit blocks during IC fabrication causes the currents flowing through these circuit blocks to change from the expected values. There has been general interest in monitoring currents through different circuit blocks in an attempt to identify the location and type of the faults. Previous works on non intrusive load monitoring as well as on power-line communications (PLCs) provide motivation for the work presented here. The techniques are extended and used to develop a new method for power monitoring in ICs. Most solutions to the challenge of measuring currents in different circuit blocks of the IC involve adding circuitry that is both costly and power consuming. In this work, a new method is proposed to enable individual measurement of current consumed in each circuit block within an IC while adding negligible area and power overhead. This method works by encoding the individual current signatures in the main supply current of the IC, which can then be sensed and sampled off-chip, and then disaggregated through signal processing. A demonstration of this power monitoring scheme is given on a modular discrete platform that is implemented based on the UC3842 current-mode controller IC, which can also be used for educational purposes.
by Anas Ibrahim Al Bastami.
S.M.
14
Neto, Hugo Daniel Barbosa. "Packaging of photonic integrated circuits." Master's thesis, Universidade de Aveiro, 2017. http://hdl.handle.net/10773/23552.
Abstract:
Mestrado em Engenharia Eletrónica e TelecomunicaçõesWith the continuous evolution of optical communication systems, emerged a need for high-performance optoelectronic elements at lower costs. Photonic packaging plays a key role for the next-generation of optical devices. In this work a standard packaging design rules is described, covering both the electrical and optical-packaging exploring both active and passive adjusting techniques, as well as the thermal management of the photonic integrated circuit (PIC). First a process for fiber-to-chip coupling with custom made ball-lensed fibers, is performed and tested initially in a testing-chip and thereafter in a manufactured practical study-case composed by a silicon holder with an InP distributed feedback (DFB) laser. The process of manufacturing etched V-grooves for fiber alignment is approached in detail. After this, for electrical interconnects and radio frequency (RF) packaging, both wire-bonding and flip-chip technique are discussed, and a characterization of the s-parameters in a PIC with wire-bonding is presented. A technique based on ruthenium-based sensors and platinum and titanium-based sensors for thermal control of the PIC is studied and the tested using a custom made PCB designed exclusively for that purpose.
Com a constante evolução dos sistemas de comunicação óticos veio a necessidade de componentes optoelectrónicos de elevada performance a custos relativamente baixos. O encapsulamento ótico tem um papel chave nos dispositivos óticos de última geração. Neste trabalho são descritas as regras de um processo de encapsulamento padrão, que abrange tanto o encapsulamento elétrico e ótico onde são exploradas técnicas de ajustamento ativas e passivas bem como o controlo térmico do circuito ótico integrado (PIC). No início foi efetuado um processo de acoplamento da fibra ao chip com fibras de lente esférica personalizadas, numa primeira usando um chip de teste e de seguida num caso de estudo prático que consiste numa estrutura composta por um holder de silício com um laser de realimentação distribuída (DFB). É abordado em detalhe o processo de fabricação de V-grooves para o alinhamento da fibra com o chip. De seguida são apresentadas e discutidas as técnicas de wire-bonding e flip-chip para o encapsulamento elétrico e ligação dos conectores de radiofrequência (RF), é feito um estudo onde são apresentados os resultados da caraterização dos parâmetros S de um PIC com wire-bonding. Para o controlo térmico do módulo é apresentada uma técnica baseada em sensores de temperatura de ruténio e sensores de Platina e titânio testada numa PCB personalizada
15
Yang, Gang. "Compact Photonic Integrated Passive Circuits." Thesis, The University of Sydney, 2021. https://hdl.handle.net/2123/26958.
Abstract:
Photonic Integrated Circuits (PICs) based on silicon photonics have received great interest due to the low loss caused by the high-refractive-index contrast and the complementary metal-oxide semiconductor compatibility. The need for high-density, high-yield, low-cost, low-power consumption, and large-scale on-chip photonic integration requires the technologies to further minimize the size while exhibiting high performance. Moreover, the fast development and expansion of silicon photonics devices for different applications and functionalities require effective design approaches to optimize the device performance while reducing the design complexity.
In this thesis, several fundamental components for PICs are presented as the building blocks for advanced photonic circuits. To test the effectiveness of the design, Mach–Zehnder interferometers are simulated and fabricated on a Silicon-on-Insulator (SOI) platform, which shows a good agreement between the experimental and simulation results. Moreover, compact vertical grating couplers with broad optical bandwidth are studied. Experimental results show the compact size and the light coupling capabilities.
Multimode Interference (MMI) splitter acts as one critical component in PICs. However, the minimum requirement of mid-to-mid channel spacing to avoid crosstalk limits the MMI size to be further reduced and thus limits the component density in the photonic integration. To solve this problem, a compact SOI MMI power splitter based on optical strip barriers is presented to achieve high crosstalk reduction. Three different MMI power splitters are designed and simulated with an ultra-small device footprint, high uniformity, while maintaining a low insertion loss of 0.4dB.
Inverse design methods with different optimization algorithms are utilized to design compact and high-performance PIC components. Firstly, a sequential least-squares programming algorithm is introduced to inverse design a waveguide crossing. This gradient-based algorithm is suitable for simple structures with fewer parameters, or a good starting point can be obtained from experience or physical theories.
Secondly, a novel dynamic iterative batch optimization method is presented in the thesis to design a high-performance segmented mode expander. In the simulation, the optimized structure achieves a coupling efficiency of 81% for TE polarization at the wavelength of 1550nm. It also shows a simulated transmission loss of lower than -1.137dB within 60nm bandwidth. This approach paves the way for the rapid design of PIC components with a compact footprint. Additionally, a Direct Binary Search (DBS) algorithm is introduced for designing pixel-like structures with binary-value-represented topology patterns, where a 3dB beam splitter is used in the design. DBS algorithm can be utilized to generate a high-quality dataset used for deep learning acceleration methods.
To solve the time-efficiency and non-scalable issues of conventional inverse design methods, a neural network-based inverse design approach is presented and applied on the design of a wavelength demultiplexer structure. The method solves the data domain shift problem that existed in the conventional tandem network architecture and improves the prediction accuracy with a 99% validation accuracy. It also shows high stability and robustness to the quantity and quality of training data. The demonstrated wavelength demultiplexer has an ultra-compact footprint of 2.6×2.6μm2, a high transmission efficiency with a transmission loss of -2dB, and a low crosstalk around -7dB simultaneously.
16
Leung, Lydia Lap Wai. "Low-loss on-chip interconnects for silicon integrated radio-frequency and microwave systems /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20LEUNG.
17
Chomicz, Thecla F. "A methodology for NMOS VLSI manufacturing : from design to test at the Rochester Institute of Technology /." Online version of thesis, 1990. http://hdl.handle.net/1850/11314.
18
Saxena, Nina. "Scalable solutions to specification and verification of large designs /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
19
Lee, Man. "Design, fabrication and characterization of an integrated micro heat pipe system /." View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?MECH%202002%20LEE.
Abstract:
Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002.Includes bibliographical references (leaves 74-77). Also available in electronic version. Access restricted to campus users.
20
Sekar, Deepak Chandra. "Optimal signal, power, clock and thermal interconnect networks for high-performance 2d and 3d integrated circuits." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26562.
Abstract:
Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Meindl, James; Committee Co-Chair: Davis, Jeffrey; Committee Member: Callen, Russell; Committee Member: Gaylord, Thomas; Committee Member: Kohl, Paul; Committee Member: Mukhopadhyay, Saibal. Part of the SMARTech Electronic Thesis and Dissertation Collection.
21
Shi, Shichang. "Lithography : friendly routing via forbidden pitch avoidance /." View the Table of Contents & Abstract, 2004. http://sunzi.lib.hku.hk/hkuto/record/B30469636.
22
Huang, Kuan Hsiang Nick, and 黃冠翔. "Electromagnetic compatibility modeling for integrated circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2014. http://hdl.handle.net/10722/206335.
Abstract:
The integrated circuit (IC) packaging electromagnetic compatibility (EMC)/signal integrity (SI)/power integrity (PI) problems have been broadly attested. But IC packaging electromagnetic interference (EMI) was seldom addressed. Because the electromagnetic emission from IC packagings becomes more critical as the data rate of digital system continues increasing. Its working mechanism and modeling technology are very important.
In this thesis, EM emission behaviors of IC packaging are systematically studied for the first time. It was never seen from other literatures. The fundamental principles and properties of electromagnetic radiations caused by heat sinks, vias, traces, and pin maps in IC packaging structures are carefully investigated and modeled. Both theoretical analysis based on first principles and simulated results based on numerical full wave solvers are provided to find out critical impact factors to IC packaging EMI. This work establishes basic modeling components for comprehensive radiation studies. It directly benefits fundamental understandings and guideline development for the optimization of the packaging EMI reduction. Some measurement results are also included to support concluded characterizations and analysis. A summary for IC packaging EMI design rules is discussed in details to conclude the derived design guidelines.
Second, a novel data pattern based electromagnetic superposition method is developed to model the IC packaging electromagnetic emission. It employs the equivalence principle to obtain the electromagnetic field response over a broad spectrum. Then it uses the linear property of the passive parasitic system to superimpose the contribution of different signals on the packaging. As a result, with certain pre-calculations, it is convenient to compute the electromagnetic emission efficiently from different signals with various signal pattern combinations, which benefits identifying the worst case scenario. The proposed method can be implemented between different tools for specific purposes. In addition, data reconstruction can be evaluated through the phase shift, and it benefits identifying the EMI of any pulse bit pattern. This work offers great convenience for the post-processing, and allows the flexibility of real digital pulse signals. It provides a basic modeling framework for comprehensive radiation studies for IC packaging and PCB EMI reductions.
Third, the performance of IC interconnects has been stretched tremendously in recently years by high speed IC systems. Their EM emission and SI modelings have to consider the existence of I/O active devices, such as buffers and drivers. The I/O model is difficult to obtain due to the IP protection and limited information. We proposed to use the X-parameter to model the IC interconnect system. Based on the PHD formalism, X-parameter models provide an accurate frequency-domain method under large-signal operating points to characterize their nonlinear behaviors. Starting from modeling the CMOS inverter, the whole link modeling primarily based on X-parameter for the pulse digital signals was presented. I/O modeling can also be investigated by the proposed new method to understand the impedance effects at high speed serial links. It is the first complete examination of the X-parameter to IC interconnect SI analysis. The nonlinear I/O property represented by IBIS models is also investigated to model its impact to IC packaging EMI. Statistical analysis is proposed to provide insightful results on random bit patterns.published_or_final_version
Electrical and Electronic Engineering
Doctoral
Doctor of Philosophy
23
Senthinathan, Ramesh 1961. "ELECTRICAL CHARACTERISTICS OF INTEGRATED CIRCUIT PACKAGES." Thesis, The University of Arizona, 1987. http://hdl.handle.net/10150/276425.
24
Marinins, Aleksandrs. "Polymer Components for Photonic Integrated Circuits." Doctoral thesis, KTH, Skolan för teknikvetenskap (SCI), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-219556.
Abstract:
Optical polymers are a subject of research and industry implementation for many decades. Optical polymers are inexpensive, easy to process and flexible enough to meet a broad range of application-specific requirements. These advantages allow a development of cost-efficient polymer photonic integrated circuits for on-chip optical communications. However, low refractive index contrast between core and cladding limits light confinement in a core and, consequently, integrated polymer device miniaturization. Also, polymers lack active functionality like light emission, amplification, modulation, etc. In this work, we improved a performance of integrated polymer waveguides and demonstrated active waveguide devices. Also, we present novel Si QD/polymer optical materials. In the integrated device part, we demonstrate optical waveguides with enhanced performance. Decreased radiation losses in air-suspended curved waveguides allow low-loss bending with radii of only 15 µm, which is far better than >100 µm for typical polymer waveguides. Another study shows a positive effect of thermal treatment on acrylate waveguides. By heating higher than polymer glass transition temperature, surface roughness is reflown, minimizing scattering losses. This treatment method enhances microring resonator Q factor more than 2 times. We also fabricated and evaluated all-optical intensity modulator based on PMMA waveguides doped with Si QDs. We developed novel hybrid optical materials. Si QDs are encapsulated into PMMA and OSTE polymers. Obtained materials show stable photoluminescence with high quantum yield. We achieved the highest up to date ~65% QY for solid-state Si QD composites. Demonstrated materials are a step towards Si light sources and active devices. Integrated devices and materials presented in this work enhance the performance and expand functionality of polymer PICs. The components described here can also serve as building blocks for on-chip sensing applications, microfluidics, etc.QC 20171207
25
Lötter, Pierre. "Parameter extraction of superconducting integrated circuits /." Link to online version, 2006. http://hdl.handle.net/10019/569.
26
Smith, Nathan. "Substrate integrated waveguide circuits and systems." Thesis, McGill University, 2010. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=92388.
Abstract:
This thesis investigates substrate integrated waveguide (SIW) based interconnects, components, and systems. SIWs are high performance broadband interconnects with excellent immunity to electromagnetic interference and suitable for use in microwave and millimetre-wave electronics, as well as wideband systems. They are very low-cost in comparison to the classic milled metallic waveguides as they may be developed using inexpensive printed circuit board (PCB) fabrication techniques. In this thesis, the interconnect design is studied by investigating the modes supported by SIW using fullwave simulations. Also, SIW transitions, as well as miniaturization methods to decrease the waveguide footprint are evaluated. Next, a miniaturized Wilkinson SIW power divider is developed exhibiting excellent isolation of up to 40dB between its output ports. Another SIW component investigated in this thesis is an SIW cavity resonator. A circular SIW cavity resonator fed by a microstrip line and via probe through an opening on the top cavity wall is designed. The aperture on the top wall creates a radiating folded slot and measurements show a gain of 7.76dB for this cavity-backed antenna at 16.79GHz. The antenna exhibits a bandwidth of 250MHz (return loss > 10dB). With this resonator, a microwave oscillator is designed to produce a 10dBm tone. Measurements of the fabricated oscillator demonstrate a low phase noise of -82dBc/Hz. Finally, a new SIW component, i.e. tapered SIW reflector, is designed to counteract the dispersive behavior of an SIW interconnect near cutoff. Two dispersion equalization systems are implemented using either a circulator or a coupler to route the compensated reflected signal. The systems are tested when a 1Gbps pseudo-random binary signal is up-converted to 10.7GHz and launched into the SIW interconnect. Observation of the compensated output eye-diagrams reveals achievement of a lower distortion in the highly dispersive band just above the cutoff frequency.Cette thèse examine des interconnexions, des composantes et des systèmes basés sur des guides d'ondes intégrés au substrat (GIS). Les GIS sont des interconnexions de haute performance à large bande qui possèdent d'excellentes caractéristiques d'immunité contre les interférences électromagnétiques et qu'on pourrait utiliser dans des systèmes microondes et des circuits d'ondes millimétriques. Le coût des GIS est très faible comparativement à celui des guides d'ondes métalliques communs, car leur fabrication utilise des techniques peu coûteuses de production de cartes de circuits imprimés. Cette thèse étudie, au moyen de simulations à onde entière, le design de l'interconnexion et les modes supportés par le GIS. De plus, la thèse évalue les transitions des GIS ainsi que les méthodes de miniaturisation visant à diminuer l'empreinte du guide d'onde. Ensuite, la thèse expose le développement d'un répartiteur de puissance GIS Wilkinson qui possède d'excellentes propriétés isolantes allant jusqu'à 40dB entre les bornes de sortie. La thèse examine aussi une autre composante GIS: un résonateur à cavité GIS. La thèse décrit la conception d'un résonateur à cavité GIS qui est alimenté par une ligne microbande et une sonde passées par une aperture sur le mur supérieur de la cavité. L'aperture dans le mur supérieur crée une encoche plissée rayonnante, et des mesures ont révélé un gain de 7,76dB pour l'antenne adossée d'une cavité de 16,79 GHz. L'antenne possède une bande passante de 250MHz (perte de réflexion > 10dB). En plus de ce résonateur, un oscillateur micro-onde est conçu pour produire une tonalité de 10dBm. Les mesures de l'oscillateur fabriqué montrent un faible bruit de phase de -82dBc/Hz. Enfin, une nouvelle composante de GIS (un réflecteur effilé) est conçue pour compenser la caractéristique dispersive d'une interconnexion GIS près de la fréquence de coupure. Deux systèmes de correction de la disp
27
Ward, Elizabeth May. "Advanced technologies for optoelectronic integrated circuits." Thesis, Imperial College London, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.404887.
28
Alipour, Motaallem Seyed Payam. "Reconfigurable integrated photonic circuits on silicon." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51792.
Abstract:
Integrated optics as a platform for signal processing offers significant benefits such as large bandwidth, low loss, and a potentially high degree of reconfigurability. Silicon (Si) has unique advantages as a material platform for integration, as well as properties such as a strong thermo-optic mechanism that allows for the realization of highly reconfigurable photonic systems. Chapter 1 is devoted to the discussion of these advantages, and Chapter 2 provides the theoretical background for the analysis of integrated Si-photonic devices. The thermo-optic property of Si, while proving extremely useful in facilitating reconfiguration, can turn into a nuisance when there is a need for thermally stable devices on the photonic chip. Chapter 3 presents a technique for resolving this issue without relying on a dynamic temperature stabilization process. Temperature-insensitive (or “athermal”) Si microdisk resonators with low optical loss are realized by using a polymer overlayer whose thermo-optic property is opposite to that of Si, and TiO2 is introduced as an alternative to polymer to deal with potential CMOS-compatibility issues. Chapter 4 demonstrates an ultra-compact, low-loss, fully reconfigurable, and high-finesse integrated photonic filter implemented on a Si chip, which can be used for RF-photonic as well as purely optical signal processing purposes. A novel, thermally reconfigurable reflection suppressor is presented in Chapter 5 for on-chip feedback elimination which can be critical for mitigating spurious interferences and protecting lasers from disturbance. Chapter 6 demonstrates a novel device for on-chip control of optical fiber polarization. Chapter 7 deals with select issues in the implementation of Si integrated photonic circuits. Chapter 8 concludes the dissertation.
29
ITALO, ADRIANA MARIA RAPOSO. "ART & NATURE: PHILOSOPHICAL INTEGRATED CIRCUITS." PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO, 2004. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=5262@1.
Abstract:
CONSELHO NACIONAL DE DESENVOLVIMENTO CIENTÍFICO E TECNOLÓGICOMinha pesquisa tem por objetivo examinar a suposta distinção entre arte e natureza no interior de uma análise crítica da chamada crise de fundamentos. Isto é, a crise do projeto fundacionista moderno, a rejeição pós-moderna à metafísica em geral e à idéia de fundamento em particular, suas relações com as rupturas impostas pelas novas tecnologias e suas conseqüências na visão de mundo e de humanidade. Arte e natureza não constituem domínios fundamentalmente distintos, ou ainda, não há heterogeneidade ontológica entre aquilo que se faz por si mesmo (natureza) e aquilo que se fabrica (arte). Com efeito, a enorme dificuldade em determinar e definir precisamente a realidade designada pelo termo natureza levou ao reconhecimento de que a eficácia da idéia de natureza é proporcional à sua imprecisão. A quebra do Tabu do Natural, isto é, a suspensão da crença de que nada do que é tecnicamente fabricado pode igualar-se à essência dos trabalhos da natureza, significou um convite à reavaliação das fronteiras entre natural e artificial. Do cálculo ao algoritmo, e destes às tecnologias da informação e biotecnologias, metáforas transformaram-se em máquinas e ferramentas, e máquinas em potentes metáforas cujo valor heurístico apresenta-se, em última instância, na indiscernibilidade entre natureza e cultura. A tecnologia contemporânea revela e disponibiliza a realidade como artefato. Isto é, como arte e fato. Ars gratia artis.
The purpose of my research is to examine the presumed distinction between Art and Nature within a critical analysis of the so called crisis of foundations. I.e., the crisis of the foundationlist modern project, the post- modern rejection of metaphysics in general and of the idea of a foundation in particular, its relationships with the ruptures imposed by the new technologies and its consequences on the perception of the world and of humanity. Art and Nature do not constitute fundamentally different domains, or yet, there is no ontological heterogeneity between that which is self-made (Nature) and that which is manufactured (Art). In effect, the great difficulty in precisely determining and defining the reality referred to by the term nature has led to the acknowledgement of the fact that the efficacy of the idea of nature is proportional to its imprecision. The lifting up of the Taboo of the Natural, that is, the suspension in the belief that nothing which is technically manufactured can be put on a par to the essence of nature`s doings, was an invitation to a re-assessment of the frontiers between natural and artificial. From calculus to algorithms, and from these to information technology and biotechnology, metaphors transform themselves into machines and tools, and machines into powerful metaphors whose heuristic value lies, in last instance, in the indiscernibility between nature and culture. Contemporary technology reveals and makes reality available as an artifact - i.e. art and fact. Ars gratia artis.
30
Parish, Simon James. "Behavioural synthesis of analogue integrated circuits." Thesis, University of Birmingham, 2010. http://etheses.bham.ac.uk//id/eprint/549/.
Abstract:
Automatic synthesis of analogue circuits remains a very manually intensive task despite huge strides in the field of Electronic Design Automation (EDA) in recent decades. Genetic Algorithms (GAs) are biologically inspired search algorithms which have previously shown some promise in this field. Their ability to form the basis of a practically useful synthesis system is investigated. A GA-based experimental synthesis system is implemented, which employs a Genetic Programming (GP) style encoding scheme based on tree structures, and a novel fitness function based on pole-zero analysis. The system is capable of synthesising circuit topologies entirely from scratch, but can also utilise user-provided circuit knowledge of arbitrary detail and complexity. The system uses a SPICE-based circuit simulator as a circuit evaluator. Experimental results reveal a number of issues that adversely impact the ability of GAs to reliably synthesise practically useful analogue circuits. These include considerable resource requirements and a tendency for synthesised circuits to contain an unnecessarily large number of components. Most serious is the sensitivity of analogue circuits to changes in topology and/or sizing. GAs are shown to be currently ill-suited to the problem domain of analogue circuit synthesis. The problem of SPICE non-convergence on the GA is also considered.
31
Lim, Daihyun 1976. "Extracting secret keys from integrated circuits." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/18059.
Abstract:
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 117-119).
Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, various kinds of tampering methods have been devised to extract secret keys from widely fielded conditional access systems such as smartcards and ATMs. As a solution, Arbiter-based Physical Unclonable Functions (PUFs) are proposed. This technique exploits statistical delay variation of wires and transistors across integrated circuits (ICs) in the manufacturing processes to build a secret key unique to each IC. We fabricated Arbiter-based PUFs in custom silicon and investigated the identification based PUFs in custom silicon and investigated the identification capability, reliability, and security of this scheme. Experimental results and theoretical studies show that a sufficient amount of variation exists across ICs. This variation enables each IC to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage. Thus, arbiter-based PUFs are well-suited to build key-cards and membership cards that must be resistant to cloning attacks.
by Daihyun Lim.
S.M.
32
Hoang, Lan H. (Lan Hoang). "Improving mechanical reliability of integrated circuits." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/41344.
33
Mumtaz, Asim. "Power integrated circuits for photovoltaic applications." Thesis, University of Cambridge, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.616250.
34
Lam, S. C. K. "Gallium arsenide bit-serial integrated circuits." Thesis, University of Edinburgh, 1990. http://hdl.handle.net/1842/11027.
Abstract:
Bit-Serial architecture and Gallium Arsenide have essentially been mutually exclusive fields in the past. Digital Gallium Arsenide integrated circuits have increasingly adopted the conventional approach of bit-parallel structures that do not always suit the properties and problems of the technology. This thesis proposes an alternative by using a least significant bit first bit-serial architecture, and presents a group of 'cells' designed for signal processing applications. The main features of the cells include the extensive use of pseudo-dynamic latches for pipelining, modularity, and programmability. The logic circuits are mainly based on direct-coupled FET logic. They are also compatible with silicon ECL circuits. The target clock rates for these cells are 500MHz, at least ten times faster than previous silicon bit-serial circuits. The differences between GaAs and silicon technologies meant that the cells were designed from circuit level upwards. Further to these cells, a multi-level signaling scheme has been developed to substantially alleviate off-chip signaling. Synchonisation between signals are simplified, improving even further on the conventional bit-serial system, especially at the high bit-rates encountered in GaAs circuits. For on-chip signals, a single phase clock scheme has been developed for the GaAs cells, which maintains the low clock loading and high speed charactersitics of the pseudo-dynamic cells, while substantially simplifying clock distribution and generation. Two novel latch designs are proposed for this scheme. Test results available have already proved the concepts behind the two-phase clocking scheme, the latches, and the multi-level scheme. Further tests are taking place to establish their speed performance.
35
Lotter, Pierre. "Parameter extraction of superconducting integrated circuits." Thesis, Stellenbosch : University of Stellenbosch, 2006. http://hdl.handle.net/10019.1/1652.
Abstract:
Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006.Integrated circuits are expensive to manufacture and it is important to verify the correct operation of a circuit before fabrication. Efficient, though accurate, parameter extraction of post-layout designs are required for estimation of circuit success rates. This thesis discusses electrical netlist and fast parameter extraction techniques suited for both intraand inter-gate connections. This includes the use of extraction windows and look-up tables (LUTs) for accurate inductance and capacitance estimation. These techniques can readily be implemented in automated layout software where fast parameter extraction is required for timing analysis and gate placement.
36
Gohil, Nikhil N. "Design of DPA-Resistant Integrated Circuits." University of Cincinnati / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1516622822794541.
37
Figueiredo, Mónica Jorge Carvalho de. "Synchronisation in high-performance integrated circuits." Doctoral thesis, Universidade de Aveiro, 2012. http://hdl.handle.net/10773/8798.
Abstract:
Doutoramento em Engenharia ElectrotécnicaA distribui ção de um sinal relógio, com elevada precisão espacial (baixo skew) e temporal (baixo jitter ), em sistemas sí ncronos de alta velocidade tem-se revelado uma tarefa cada vez mais demorada e complexa devido ao escalonamento da tecnologia. Com a diminuição das dimensões dos dispositivos e a integração crescente de mais funcionalidades nos Circuitos Integrados (CIs), a precisão associada as transições do sinal de relógio tem sido cada vez mais afectada por varia ções de processo, tensão e temperatura. Esta tese aborda o problema da incerteza de rel ogio em CIs de alta velocidade, com o objetivo de determinar os limites do paradigma de desenho sí ncrono. Na prossecu ção deste objectivo principal, esta tese propõe quatro novos modelos de incerteza com âmbitos de aplicação diferentes. O primeiro modelo permite estimar a incerteza introduzida por um inversor est atico CMOS, com base em parâmetros simples e su cientemente gen éricos para que possa ser usado na previsão das limitações temporais de circuitos mais complexos, mesmo na fase inicial do projeto. O segundo modelo, permite estimar a incerteza em repetidores com liga ções RC e assim otimizar o dimensionamento da rede de distribui ção de relógio, com baixo esfor ço computacional. O terceiro modelo permite estimar a acumula ção de incerteza em cascatas de repetidores. Uma vez que este modelo tem em considera ção a correla ção entre fontes de ruí do, e especialmente util para promover t ecnicas de distribui ção de rel ogio e de alimentação que possam minimizar a acumulação de incerteza. O quarto modelo permite estimar a incerteza temporal em sistemas com m ultiplos dom ínios de sincronismo. Este modelo pode ser facilmente incorporado numa ferramenta autom atica para determinar a melhor topologia para uma determinada aplicação ou para avaliar a tolerância do sistema ao ru ído de alimentação. Finalmente, usando os modelos propostos, são discutidas as tendências da precisão de rel ogio. Conclui-se que os limites da precisão do rel ogio são, em ultima an alise, impostos por fontes de varia ção dinâmica que se preveem crescentes na actual l ogica de escalonamento dos dispositivos. Assim sendo, esta tese defende a procura de solu ções em outros ní veis de abstração, que não apenas o ní vel f sico, que possam contribuir para o aumento de desempenho dos CIs e que tenham um menor impacto nos pressupostos do paradigma de desenho sí ncrono.
Distributing a the clock simultaneously everywhere (low skew) and periodically everywhere (low jitter) in high-performance Integrated Circuits (ICs) has become an increasingly di cult and time-consuming task, due to technology scaling. As transistor dimensions shrink and more functionality is packed into an IC, clock precision becomes increasingly a ected by Process, Voltage and Temperature (PVT) variations. This thesis addresses the problem of clock uncertainty in high-performance ICs, in order to determine the limits of the synchronous design paradigm. In pursuit of this main goal, this thesis proposes four new uncertainty models, with di erent underlying principles and scopes. The rst model targets uncertainty in static CMOS inverters. The main advantage of this model is that it depends only on parameters that can easily be obtained. Thus, it can provide information on upcoming constraints very early in the design stage. The second model addresses uncertainty in repeaters with RC interconnects, allowing the designer to optimise the repeater's size and spacing, for a given uncertainty budget, with low computational e ort. The third model, can be used to predict jitter accumulation in cascaded repeaters, like clock trees or delay lines. Because it takes into consideration correlations among variability sources, it can also be useful to promote oorplan-based power and clock distribution design in order to minimise jitter accumulation. A fourth model is proposed to analyse uncertainty in systems with multiple synchronous domains. It can be easily incorporated in an automatic tool to determine the best topology for a given application or to evaluate the system's tolerance to power-supply noise. Finally, using the proposed models, this thesis discusses clock precision trends. Results show that limits in clock precision are ultimately imposed by dynamic uncertainty, which is expected to continue increasing with technology scaling. Therefore, it advocates the search for solutions at other abstraction levels, and not only at the physical level, that may increase system performance with a smaller impact on the assumptions behind the synchronous design paradigm.
38
Rodrigues, Carla Iolanda Costa. "Photonic integrated circuits for NG-EPON." Master's thesis, Universidade de Aveiro, 2016. http://hdl.handle.net/10773/22732.
Abstract:
Mestrado em Engenharia Electrónica e TelecomunicaçõesAlong with privacy and security, the growth of demand from the consumer for higher bandwidth presents one of the most important modern challenges in telecommunications infrastructures. The researchers were encouraged to nd not only e cient but also the economically viable solutions capable of meeting the growing needs of the consumer. Optical communications are the way that can accompany this growth. The Passive Optical Network (PON) is an architecture that shares the ber bandwidth among several users. There has been a constant study under this topic for the purpose of using all the ber abilities and to nd new solutions to keep the access network simple. Photonic Integrated Circuits (PICs) are a technology that emerged to help the complexity of the hardware that exists nowadays. It is a single chip capable of integrating numerous optical components, which leads to a reduced complexity, size and power consumption. These are the important characteristics that make the PICs a powerful tool to use in several applications. This dissertation presents a monolithic PIC transceiver in the context of Next Generation of Ethernet Passive Optical Network (NG-EPON) which aims to design and implement integrated optical circuits for future access networks. The transceiver architecture is able to be used as an Optical Network Unit (ONU) with a 4 channels approach for 100 Gb/s solutions. The present work contributed for the FUTPON project supported by P2020.
Em par com a privacidade e segurança, a crescente procura do consumidor por maiores larguras de banda apresenta um dos mais importantes desafios modernos das infraestruturas de telecomunicações. Esta procura incentiva assim a investigação de novas soluções não são eficientes, mas também economicamente viáveis, capazes de satisfazer as crescentes necessidades do consumidor. As comunicações óticas apresentam ser o meio apropriado para acompanhar este crescimento. A Rede Óptica Passiva (PON) e uma arquitectura usada para distribuição de fibra ótica ate ao consumidor final. Esta tecnologia permite dividir a largura de banda de uma única fibra por diferentes clientes. Tem havido um estudo constante no âmbito deste tópico para conseguir tirar máximo partido das capacidades da fibra e de modo a encontrar novas soluções para tornar este método mais simples. Os Circuitos Oticos Integrados (PIC) sao uma tecnologia que surge para ajudar na complexidade do hardware existente hoje em dia. Consiste num único chip capaz de integrar vários componentes óticos, o que leva a uma diminuição da complexidade, tamanho e redução do consumo de energia. Estas características fazem com que seja uma tecnologia vantajosa para uso em diferentes aplicações. O desenho e a implementação da arquitectura do transrecetor em formato PIC no contexto da Next Generation of Ethernet Passive Optical Network (NG-EPON), e o principal objectivo desta dissertação onde visa o desenvolvimento circuitos óticos integrados para redes oticas de acesso futuras. Esta arquitectura devera ser utilizada como Optical Network Unit (ONU) contendo 4 canais para atingir 100 Gb/s. Este trabalho contribuiu para o projecto FUTPON suportado pelo P2020.
39
Smuk, Jeffrey William Carleton University Dissertation Engineering Electrical. "Hybrid semiconductive/superconductive microwave integrated circuits." Ottawa, 1991.
40
Bernard, Martino. "Lightwave circuits for integrated Silicon Photonics." Doctoral thesis, Università degli studi di Trento, 2017. https://hdl.handle.net/11572/368818.
Abstract:
This thesis work covers scientific and technological advancements in integrated silicon photonics circuits aimed at developing an All-On-Chip device for quantum photonics experiments. The work has been carried out within the framework of project SiQuro, where the Silicon-On-Insulator platform is chosen to integrate all the components of an optical bench necessary for a quantum experiment into a single chip. The problem of generating photon pairs have been addressed by studying second order polarisation effects in strained silicon with the aim to realize a bright photon pairs source based on Spontaneous Down Conversion. The study revealed that processes other than the Pockels effect are responsible for the non-linearity coefficients previously measured, suggesting to look for other candidate processes for the generation of photon pairs, as third order non-linear processes. To provide with the bright coherent source necessary to enable non-linear processes the integration of a hybrid III-V-silicon mode-locked laser has also been studied. During this study, technological novelties have also been developed by modelling the wedge profile obtained during the wet etching of silicon glass materials to engineer 3D structures. In parallel, the physics of whispering gallery mode resonators, both in silicon and in silicon glass materials, have been addressed. Silicon nitride Ultra High-Quality resonators have been demonstrated by using a strip-loaded configuration, while relative tuning of resonant modes has been demonstrated in an all-optical experiment exploiting the thermo-optic effect.
This work represents a step forward in the study of the physics and applications of silicon-based lightwave circuits for integrated photonics.
41
Bernard, Martino. "Lightwave circuits for integrated Silicon Photonics." Doctoral thesis, University of Trento, 2017. http://eprints-phd.biblio.unitn.it/2067/1/Disclaimer_thesis_signed.pdf.
Abstract:
This thesis work covers scientific and technological advancements in integrated silicon photonics circuits aimed at developing an All-On-Chip device for quantum photonics experiments. The work has been carried out within the framework of project SiQuro, where the Silicon-On-Insulator platform is chosen to integrate all the components of an optical bench necessary for a quantum experiment into a single chip. The problem of generating photon pairs have been addressed by studying second order polarisation effects in strained silicon with the aim to realize a bright photon pairs source based on Spontaneous Down Conversion. The study revealed that processes other than the Pockels effect are responsible for the non-linearity coefficients previously measured, suggesting to look for other candidate processes for the generation of photon pairs, as third order non-linear processes. To provide with the bright coherent source necessary to enable non-linear processes the integration of a hybrid III-V-silicon mode-locked laser has also been studied. During this study, technological novelties have also been developed by modelling the wedge profile obtained during the wet etching of silicon glass materials to engineer 3D structures. In parallel, the physics of whispering gallery mode resonators, both in silicon and in silicon glass materials, have been addressed. Silicon nitride Ultra High-Quality resonators have been demonstrated by using a strip-loaded configuration, while relative tuning of resonant modes has been demonstrated in an all-optical experiment exploiting the thermo-optic effect.
This work represents a step forward in the study of the physics and applications of silicon-based lightwave circuits for integrated photonics.
42
Gope, Dipanjan. "Integral equation based fast electromagnetic solvers for circuit applications /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6116.
43
Hamanaka, Cristian Otsuka. "Projeto de circuitos para geração de tensão de referência em sistemas receptores/transmissores RF." Universidade de São Paulo, 2007. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-09012008-164614/.
Abstract:
Este trabalho consiste no projeto de uma Fonte de Tensão de Referência CMOS com coeficiente de temperatura inferior a 50 ppm/ºC. Esta fonte deve ser aplicada em receptores/transmissores de radio freqüência mas pode também ser utilizada em qualquer sistema analógico. A tecnologia utilizada foi a CMOS 0,35 µm da AMS (Austria Micro Systems) com quatro níveis de metal e dois de silício policristalino. A fonte de tensão implementada é do tipo Bandgap e utiliza dispositivos MOS em inversão fraca, um transistor bipolar parasitário e resistores de silício policristalino de alta resistividade. No circuito é produzida uma tensão PTAT (Proportional to Absolute Temperature) que somada a tensão base-emissor do transistor bipolar resulta numa tensão de saída independente da temperatura. O projeto e o desenho do layout desta fonte foram realizados. A partir do layout foram gerados netlists para simulações realizadas utilizando o software ELDO com o modelo MOS BSIM3v3, nas condições de operação típicas, worst speed e worst power. Através destas simulações verificou-se que o circuito atendia as especificações iniciais. O valor da tensão de saída, no entanto, apesar de estar próximo do valor desejado de 1,25 V, variou com as condições de simulação empregadas. Dois circuitos Bandgap diferentes foram enviados para fabricação: um circuito com resistores integrados (dimensões de 220 µm x 76 µm) e outro sem os resistores (dimensões de 190 µm x 36 µm). Este último permite, com o ajuste do valor dos resistores colocados externamente, modificar, se necessário, as condições de operação do circuito. Os circuitos foram caracterizados obtendo-se para o circuito com resistores integrados um coeficiente de temperatura inferior à 40 ppm/ºC, taxa de variação da saída com a tensão de alimentação próxima de 19 mV/V. O valor da tensão de saída a 50 ºC esteve entre 1,1835 V e 1,2559 V (1,25 V ± 67 mV). Para o circuito sem os resistores integrados, obteve-se um coeficiente de temperatura que chegou à 90 ppm/ºC, taxa de variação da saída com a tensão de alimentação inferior à 28 mV/V. O valor da tensão de saída a 50 ºC esteve entre 1,247 V e 1,2588 V (1,25 V ± 9 mV). A faixa de temperatura utilizada para as medidas foi de -30 ºC a 100 ºC. O consumo de corrente dos circuitos é de aproximadamente 14 µA e seu funcionamento é garantido para tensões de alimentação tão baixas quanto 1,8 V.This work consists in the design of a CMOS Voltage Reference Source with a temperature coefficient inferior to 50 ppm/ºC. This voltage source should be applied in radio frequency receptor/transmitter but can be also applied in any analog system. The technology employed in the design is the CMOS 0.35 µm from the AMS (Austria Micro Systems) with four metal levels and two poly-silicon levels. The implemented voltage source is of the Bandgap type and uses MOS devices in weak inversion, a parasitic bipolar transistor, and resistors made with high resistive poly-silicon. The circuit produces a PTAT (Proportional to Absolute Temperature) voltage that is added to the bipolar transistor base-emitter voltage to build an output voltage independent of temperature. The project and the drawing of the layout of the circuit had been carried out. The netlists of the circuit were generated from the layout and they were employed in simulations done with the software ELDO and the BSIM3v3 MOS model, in typical, worst speed, and worst power conditions. Through these simulations it was verified that the circuit reached the initial specifications. The value of the output voltage, however, although being next to the desired value of 1.25 V, varied with the employed simulation conditions. Two different Bandgap circuits had been sent to the foundry: a circuit with integrated resistors (dimensions of 220 µm x 76 µm) and another one without the resistors (dimensions of 190 µm x 36 µm). This last one allows, with the adjustment of external resistor values, modifying, if necessary, the operation conditions of the circuit. The circuits had been characterized and the circuit with integrated resistors has a temperature coefficient inferior to 40 ppm/ºC, an output variation rate with the power supply close to 19 mV/V. The output voltage value at 50 ºC is between 1.1835 V and 1.2559 V (1.25 V ± 67 mV). The circuit without the resistors has a temperature coefficient as high as 90 ppm/ºC, an output variation rate with the power supply inferior to 28 mV/V. The output voltage value at 50 ºC is between 1.247 V and 1.2588 V (1.25 V ± 9 mV). The temperature range used in the measurements was from -30 ºC to 100 ºC. The current consumption of the circuits is approximately of 14 µA, and they operate with power supply voltages as low as 1.8 V.
44
Rahimi, Kambiz. "Adaptive-delay sequential circuits /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5907.
45
Kantipudi, Kalyana R. "Minimizing N-detect tests for combinational circuits." Auburn, Ala., 2007. http://repo.lib.auburn.edu/2007%20Spring%20Theses/KANTIPUDI_KALYANA_27.pdf.
46
Ahmed, Mohammad Abrar. "Early Layout Design Exploration in TSV-based 3D Integrated Circuits." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3617.
Abstract:
Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage.
The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function.
The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance.
Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and blocks, as well as nets-to-TSVs assignment to obtain floorplans with minimized coupling noise. We also suggested diagonal TSV arrangement for larger TSV pitch and nonuniform pitch arrangement for reducing worst TSV-to-TSV coupling, thereby minimizing the coupling noise in the interconnects.
This thesis also focuses on more realistic evaluation and optimization of delay and power in TSV based 3D integrated circuits considering the interconnect density on individual device layers. The floorplanning tool uses TSV locations and delay, non-uniform interconnect density across multiple stacked device layers to assess and optimize the buffer count, delay, and interconnect power dissipation in a design. It is shown that the impact of non-uniform interconnect density, across the stacked device layers, should not be ignored, as its contribution to the performance of the 3D interconnects is consequential.
A wire capacitance-aware buffer insertion scheme is presented that determines the optimal distance between adjacent buffers on the individual device layers for nonuniform wire density between stacked device layers. The proposed approach also considers TSV location on a 3D wire to optimize the buffer insertion around TSVs. For 3D designs with uniform wire density across stacked device layers, we propose a TSV-aware buffer insertion approach that appropriately models the TSV RC delay impact on interconnect delay to determine the optimum interval between adjacent buffers for individual 3D nets. Moreover, our floorplanning tool help achieve 3D layouts with superior performance by incorporating the impact of nonuniform density on the delay, power and coupling noise in the interconnects during floorplanning.
47
Özkaramanli, Hüseyin Mehmet. "Distributed circuits in integrated circuits : signal integrity, crosstalk and delay in VLSI /." Thesis, Connect to Dissertations & Theses @ Tufts University, 1995.
Abstract:
Thesis (Ph.D.)--Tufts University, 1995.Submitted to the Dept. of Electrical Engineering. Includes bibliographical references (leaves 237-253). Access restricted to members of the Tufts University community. Also available via the World Wide Web;
48
Cronquist, Darren C. "Reconfigurable pipelined datapaths /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6988.
49
Hu, Fei. "Process variation-resistant dynamic power optimization of VLSI circuits." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Fall/Dissertation/HU_FEI_35.pdf.
50
Gore, Kapil Suhling J. C. Jaeger Richard C. "Vibration analysis of test chips with integrated piezoresistive stress sensors." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Summer/Theses/GORE_KAPIL_36.pdf.