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1
M, Thillai Rani, Rajkumar R, Sai Pradeep K.P, Jaishree M, and Rahul S.G. "Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits." ITM Web of Conferences 56 (2023): 01005. http://dx.doi.org/10.1051/itmconf/20235601005.
Abstract:
High-level synthesis (HLS) is utilized for high-performance and energy-efficient heterogeneous systems designing. HLS is assist in field-programmable gate array circuits designing where hardware implementations are refined and replaced in target device. However, the power-process-voltage-temperature-delay (PPVTD) variation in VLSI circuits undergoes many problems and reduced the performance. In order to address these problems, C4.5 with eXtreme Gradient Boosting Classification based High Level Synthesis (C4.5-XGBCHLS) Method is designed for afford better runtime adaptability (RA) with minimal error rate. VLSI circuits are designed using the behavioral input and results are measured at running condition. When VLSI circuit’s results get reduced, the language description of the circuit is considered as an input. Then, compilation process convert high level specification into Intermediate Representation (IR) in control/data flow graph (CDFG). CDFG computes data and control dependencies among operations. eXtreme Gradient Boosting (XGBoost) Classifier is exploited in C4.5-XGBCHLS method to classify the error causing functional unit (FU) with minimal error rate. XGBoost Classifier exploited C4.5 decision tree as base classifier to enhance classification of error causing FU in VLSI circuits. After that, FU gets allocated in place of error causing FU from functional library based on the design objectives and PPVTD variations. Finally, operation scheduling and binding process is executed for register transfer level (RTL) generation to form VLSI circuits with improved RA. The simulation results shows that the C4.5-XGBCHLS method enhances the performance of functional unit selection accuracy (FUSA) with minimal error rate (ER) and circuit adaptability time (CAT).
2
Patel, Ambresh, and Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, no. 01 (January 30, 2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.
Abstract:
The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits because it requires fewer transistors, has lower parasitic capacitance, is faster, and enables pipelinedsystem architecture with glitch-free circuits. It has, however, increased power dissipation. Both types of CMOS circuits withlow power dissipation overcome their own shortcomings.This paper discusses dynamic CMOS logic circuits and their structures. Various logics are also discussed and on the basisof the results obtained, logic which is best suited for designing CMOS logic circuit will be found out. The logic on the basisof structure layout and design which gives best results for high-speed VLSI circuits, is found out.
3
Iwai, Hiroshi, Kuniyuki Kakushima, and Hei Wong. "CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING." International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 43–81. http://dx.doi.org/10.1142/s0129156406003539.
Abstract:
The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.
4
Madhura, S. "A Review on Low Power VLSI Design Models in Various Circuits." Journal of Electronics and Informatics 4, no. 2 (July 8, 2022): 74–81. http://dx.doi.org/10.36548/jei.2022.2.002.
Abstract:
Low power design is one of the primary goals for any integrated circuits. Very Large-Scale Integration (VLSI) is a kind of Integrated Circuit (IC) that consists of hundreds and hundreds of transistor connection into a small chip. The communication and computer applications have grown very faster in the past decade due to the development of VLSI circuit design as microcontroller and microprocessors. However, still the research on VLSI are moving faster towards the scope of power and area minimization. The paper gives an overview about the recent methodologies that have been developed for the performance improvement of VLSI design and it shows the future directions of the areas that are to be concentrated on VLSI circuit design.
5
Im, James S., and Robert S. Sposili. "Crystalline Si Films for Integrated Active-Matrix Liquid-Crystal Displays." MRS Bulletin 21, no. 3 (March 1996): 39–48. http://dx.doi.org/10.1557/s0883769400036125.
Abstract:
The fabrication of thin-film-transistor (TFT) devices on a transparent substrate lies at the heart of active-matrix-liquid-crystal-display (AMLCD) technology. This is both good and bad. On one hand it is a difficult task to manufacture millions of intricate semiconductor devices reliably over such large display substrates. On the positive side, AMLCD technology can aspire to become much more than a “display” technology. The idea is as follows: It is possible for one to readily fabricate additional transistors to execute various electronic functions—those that would otherwise be handled by separate large-scale-integration (LSI) and very large-scale-integration (VLSI) circuits—on the periphery of the display. Since this can be done, in principle, with no—or a minimal number of—additional processing steps, substantial cost reduction is possible and significant value can be added to the final product.Doing so and doing it well can ultimately lead to “system-on-glass” products in which the entire electronic circuitry needed for a product is incorporated directly onto a glass substrate. This means that integrated active-matrix liquid-crystal displays (IAMLCDs) have the potential to bypass conventional Si-wafer-based products and may lead TFT technology to compete directly against Si-wafer-based monolithic integrated circuits.
6
Beck, Anthony, Franziska Obst, Mathias Busek, Stefan Grünzner, Philipp Mehner, Georgi Paschew, Dietmar Appelhans, Brigitte Voit, and Andreas Richter. "Hydrogel Patterns in Microfluidic Devices by Do-It-Yourself UV-Photolithography Suitable for Very Large-Scale Integration." Micromachines 11, no. 5 (May 2, 2020): 479. http://dx.doi.org/10.3390/mi11050479.
Abstract:
The interest in large-scale integrated (LSI) microfluidic systems that perform high-throughput biological and chemical laboratory investigations on a single chip is steadily growing. Such highly integrated Labs-on-a-Chip (LoC) provide fast analysis, high functionality, outstanding reproducibility at low cost per sample, and small demand of reagents. One LoC platform technology capable of LSI relies on specific intrinsically active polymers, the so-called stimuli-responsive hydrogels. Analogous to microelectronics, the active components of the chips can be realized by photolithographic micro-patterning of functional layers. The miniaturization potential and the integration degree of the microfluidic circuits depend on the capability of the photolithographic process to pattern hydrogel layers with high resolution, and they typically require expensive cleanroom equipment. Here, we propose, compare, and discuss a cost-efficient do-it-yourself (DIY) photolithographic set-up suitable to micro-pattern hydrogel-layers with a resolution as needed for very large-scale integrated (VLSI) microfluidics. The achievable structure dimensions are in the lower micrometer scale, down to a feature size of 20 µm with aspect ratios of 1:5 and maximum integration densities of 20,000 hydrogel patterns per cm². Furthermore, we demonstrate the effects of miniaturization on the efficiency of a hydrogel-based microreactor system by increasing the surface area to volume (SA:V) ratio of integrated bioactive hydrogels. We then determine and discuss a correlation between ultraviolet (UV) exposure time, cross-linking density of polymers, and the degree of immobilization of bioactive components.
7
Li, Jian, Robert Blewer, and J. W. Mayer. "Copper-Based Metallization for ULSI Applications." MRS Bulletin 18, no. 6 (June 1993): 18–21. http://dx.doi.org/10.1557/s088376940004728x.
Abstract:
Multilevel metallization of very large-scale integrated (VLSI) circuits has become an area of intense research interest as devices are scaled down in order to increase circuit density. As device dimensions approach the submicron regime, reliability becomes more of an issue. Metallization generally requires good conductivity, electromigration resistance, controllable contact performance, corrosion resistance, adherence, thermal stability, bondability, ability to be patterned into a desirable geometry, and economic feasibility.Aluminum and its alloys have been commonly used as the main metallization materials because they meet most of the metallization requirements for microelectronic devices. Aluminum, however, suffers from major limitations, such as elec-tromigration and stress-voiding induced open-circuit failure. For the development of ultralarge-scale integration (ULSI) for fast-switching-speed devices, the electrical resistivities of aluminum and its alloys are not low enough. As the minimum geometry is scaled down to one-quarter micron, aluminum and its alloys potentially will be replaced by other materials such as Cu, Au, or superconductors for on-chip interconnection.
8
Dove, Lewis. "Multi-Layer Ceramic Packaging for High Frequency Mixed-Signal VLSI ASICS." Journal of Microelectronics and Electronic Packaging 6, no. 1 (January 1, 2009): 38–41. http://dx.doi.org/10.4071/1551-4897-6.1.38.
Abstract:
Mixed-signal Application Specific Integrated Circuits (ASICs) have traditionally been used in test and measurement applications for a variety of functions such as data converters, pin electronics circuitry, drivers, and receivers. Over the past several years, the complexity, power density, and bandwidth of these chips has increased dramatically. This has necessitated dramatic changes in the way these chips have been packaged. As the chips have become true VLSI (Very Large Scale Integration) ICs, the number of I/Os have become too large to interconnect with wire bonds. Thus, it has become necessary to utilize flip chip interconnects. Also, the bandwidth of the high-speed signal paths and clocks has increased into the multi Gbit or GHz ranges. This requires the use of packages with good high-frequency performance which are designed using microwave circuit techniques to optimize signal integrity and to minimize signal crosstalk and noise.
9
Wong, C. P. "An Overview of Integrated Circuit Device Encapsulants." Journal of Electronic Packaging 111, no. 2 (June 1, 1989): 97–107. http://dx.doi.org/10.1115/1.3226528.
Abstract:
The rapid development of integrated circuit technology from small-scale integration (SSI) to very large scale integration (VLSI) has had great technological and economical impact on the electronics industry. The exponential growth of the number of components per IC chip, the exponential decrease of device dimensions, and the steady increase in IC chip size have imposed stringent requirements, not only on the IC physical design and fabrication, but also on IC encapsulants. This report addresses the purpose of encapsulation, encapsulation techniques, and a general overview of the application of inorganic and organic polymer materials as electronic device encapsulants.
10
Boychenko, Dmitry, Oleg Kalashnikov, Alexander Nikiforov, Anastasija Ulanova, Dmitry Bobrovsky, and Pavel Nekrasov. "Total ionizing dose effects and radiation testing of complex multifunctional VLSI devices." Facta universitatis - series: Electronics and Energetics 28, no. 1 (2015): 153–64. http://dx.doi.org/10.2298/fuee1501153b.
Abstract:
Total ionizing dose (TID) effects and radiation tests of complex multifunctional Very-large-scale integration (VLSI) integrated circuits (ICs) rise up some particularities as compared to conventional ?simple? ICs. The main difficulty is to organize informative and quick functional tests directly under irradiation. Functional tests approach specified for complex multifunctional VLSI devices is presented and the basic radiation test procedure is discussed in application to some typical examples.
11
IKEDA, SHOJI, HIDEO SATO, MICHIHIKO YAMANOUCHI, HUADONG GAN, KATSUYA MIURA, KOTARO MIZUNUMA, SHUN KANAI, et al. "RECENT PROGRESS OF PERPENDICULAR ANISOTROPY MAGNETIC TUNNEL JUNCTIONS FOR NONVOLATILE VLSI." SPIN 02, no. 03 (September 2012): 1240003. http://dx.doi.org/10.1142/s2010324712400036.
Abstract:
We review recent developments in magnetic tunnel junctions with perpendicular easy axis (p-MTJs) for nonvolatile very large scale integrated circuits (VLSIs). So far, a number of material systems such as rare-earth/transition metal alloys, L10-ordered ( Co, Fe )– Pt alloys, Co /( Pd, Pt ) multilayers, and ferromagnetic-alloy/oxide stacks have been proposed as electrodes in p-MTJs. Among them, p-MTJs with single or double ferromagnetic-alloy/oxide stacks, particularly CoFeB–MgO , were shown to have high potential to satisfy major requirements for integration.
12
Sun, Chongjun, and Chao Ding. "Study on Calibration Method for Testing During Burn In equipment of integrated circuits." Journal of Physics: Conference Series 2029, no. 1 (September 1, 2021): 012035. http://dx.doi.org/10.1088/1742-6596/2029/1/012035.
Abstract:
Abstract In order to implement Method 1015 of GJB 548B, TDBI(Testing During Burn In) technology of integrated circuit is widely used in the aging process of core VLSI(Very Large Scale Integration) which is included of FPGA, DSP, CPU and dedicated chips. Many models of TDBI equipment at home or abroad have been come into use. It is an important task to calibrate TDBI equipment in system level and ensure the traceability of its measurement value. At present, the calibration device of TDBI equipment has been successfully finalized and put into production, which has the advantages of convenient use and high cost performance. This paper mainly introduces the calibration method for TDBI equipment of integrated circuit from the aspects of the overall architecture design, signal adaptation design and calibration software design.
13
Rajaei, Ramin. "A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics." Journal of Circuits, Systems and Computers 27, no. 13 (August 3, 2018): 1850205. http://dx.doi.org/10.1142/s0218126618502055.
Abstract:
Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write operation over the previous MFFs. This magnetic-based logic circuit is based on the previous two-in-one (TIO) MTJ cell that presents the aforementioned attributes. Radiation-induced single event upset, as another reliability challenge, is also taken into consideration for the MFFs and another MFF robust against radiation effects is suggested and evaluated.
14
Murarka, S. P., J. Steigerwald, and R. J. Gutmann. "Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing." MRS Bulletin 18, no. 6 (June 1993): 46–51. http://dx.doi.org/10.1557/s0883769400047321.
Abstract:
Continuing advances in the fields of very-large-scale integration (VLSI), ultralarge-scale integration (ULSI), and gigascale integration (GSI), leading to the continuing development of smaller and smaller devices, have continually challenged the fields of materials, processes, and circuit designs. The existing metallization schemes for ohmic contacts, gate metal, and interconnections are inadequate for the ULSI and GSI era. An added concern is the reliability of aluminum and its alloys as the current carrier. Also, the higher resistivity of Al and its use in two-dimensional networks have been considered inadequate, since they lead to unacceptably high values of the so-called interconnection delay or RC delay, especially in microprocessors and application-specific integrated circuits (ICs). Here, R refers to the resistance of the interconnection and C to the total capacitance associated with the interlayer dielectric. For the fastest devices currently available and faster ones of the future, the RC delay must be reduced to such a level that the contribution of RC to switching delays (access time) becomes a small fraction of the total, which is a sum of the inherent device delay associated with the semiconductor, the device geometry and type, and the RC delay.
15
Chen, Xiangyu, Takeaki Yajima, Isao H. Inoue, and Tetsuya Iizuka. "An ultra-compact leaky integrate-and-fire neuron with long and tunable time constant utilizing pseudo resistors for spiking neural networks." Japanese Journal of Applied Physics 61, SC (February 18, 2022): SC1051. http://dx.doi.org/10.35848/1347-4065/ac43e4.
Abstract:
Abstract Spiking neural networks (SNNs) inspired by biological neurons enable a more realistic mimicry of the human brain. To realize SNNs similar to large-scale biological networks, neuron circuits with high area efficiency are essential. In this paper, we propose a compact leaky integrate-and-fire (LIF) neuron circuit with a long and tunable time constant, which consists of a capacitor and two pseudo resistors (PRs). The prototype chip was fabricated with TSMC 65 nm CMOS technology, and it occupies a die area of 1392 μm2. The fabricated LIF neuron has a power consumption of 6 μW and a leak time constant of up to 1.2 ms (the resistance of PR is up to 600 MΩ). In addition, the time constants are tunable by changing the bias voltage of PRs. Overall, this proposed neuron circuit facilitates the very-large-scale integration of adaptive SNNs, which is crucial for the implementation of bio-scale brain-inspired computing.
16
Chowdary, M. Kalpana, Rajasekhar Turaka, Bayan Alabduallah, Mudassir Khan, J. Chinna Babu, and Ajmeera Kiran. "Low-Power Very-Large-Scale Integration Implementation of Fault-Tolerant Parallel Real Fast Fourier Transform Architectures Using Error Correction Codes and Algorithm-Based Fault-Tolerant Techniques." Processes 11, no. 8 (August 8, 2023): 2389. http://dx.doi.org/10.3390/pr11082389.
Abstract:
As technology advances, electronic circuits are more vulnerable to errors. Soft errors are one among them that causes the degradation of a circuit’s reliability. In many applications, protecting critical modules is of main concern. One such module is Fast Fourier Transform (FFT). Real FFT (RFFT) is a memory-based FFT architecture. RFFT architecture can be optimized by its processing element through employing several types of adder and multipliers and an optimized memory usage. It has been seen that various blocks operate simultaneously in many applications. For the protection of parallel FFTs using conventional Error Correction Codes (ECCs), algorithmic-based fault tolerance (ABFT) techniques like Parseval checks and its combination are seen. In this brief, the protection schemes are applied to the single RAM-based parallel RFFTs and dual RAM-based parallel RFFTs. This work is implemented on platforms such as field programmable gate arrays (FPGAs) using Verilog HDL and on application-specific integrated circuit (ASIC) using a cadence encounter digital IC implementation tool. The synthesis results, including LUTs, slices registers, LUT–Flip-Flop pairs, and the frequency of two types of protected parallel RFFTs, are analyzed, along with the existing FFTs. The two proposed architectures with the combined protection scheme Parity-SOS-ECC present an 88% and 33% reduction in area overhead when compared to the existing parallel RFFTs. The performance metrics like area, power, delay, and power delay product (PDP) in an ASIC of 45 nm and 90 nm technology are evaluated, and the proposed single RAM-based parallel RFFTs architecture presents a 62.93% and 57.56% improvement of PDP in 45 nm technology and a 67.20% and 60.31% improvement of PDP in 90 nm technology compared to the dual RAM-based parallel RFFTs and the existing architecture, respectively.
17
Zhang, Ai Rong. "The Integration on Electrical Control Systems Based on Optimized Method." Advanced Materials Research 490-495 (March 2012): 2604–8. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2604.
Abstract:
Very large scale integration (VLSI) applications have improved control implementation performance. Indeed, an application specific integrated circuit (ASIC) solution can exploit efficiently specificities of the control algorithms that fixed hardware architecture cannot do. For example, parallel calculation cannot be included in a software solution based on sequential processing. In addition, ASIC can reduce wire and electromagnetic field interference by a fully system on a chip (SoC) integration. However, there are still two main drawbacks to an integrated circuit solution: design complexity and reuse difficulty. This is true even with programmable logic device (PLD) solutions. Conception aid developer (CAD) combined with hardware description languages (HDL) and VLSI design methodology have accelerated conception and reuse. Nevertheless, the main problem of integrated circuit design is to define the hardware architecture; this is particularly true for heterogeneous algorithm structures such as electrical controls.
18
Luo, Guozheng, Xiang Chen, and Shanshan Nong. "Net Clusting Based Low Complexity Coarsening Algorithm In k-way Hypergraph Partitioning." Journal of Physics: Conference Series 2245, no. 1 (April 1, 2022): 012019. http://dx.doi.org/10.1088/1742-6596/2245/1/012019.
Abstract:
Abstract With the increasing scale of integrated circuits, hypergraph partitioning is usually applied to Very Large Scale Integration (VLSI) circuit layout and other applications to reduce the computational complexity. However, if without properly coarsening, the hypergraph partitioning problem will become intractable along with the increase of the number of vertices. In this paper, we propose a coarsening algorithm in k-way hypergraph partitioning based on net clustering, where net clustering is used to obtain the initial set of vertices with higher internal similarity. Due to the property of nets connecting through vertices, the proposal can cluster the net by local search and discard unimportant vertices from net clusters to achieve high-quality solutions. The experimental results show that our proposal achieves a high quality of coarsening with lower complexity. Even as the number of partitions rises, the computation time reduction will obviously increase. In the case of setting the number of partitions as 8, our algorithm can achieve almost the same partitioning quality as traditional hMetis, but with a time consumption reduction of 50%.
19
Jayakumar, Ganesh, Per-Erik Hellström, and Mikael Östling. "Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application." Micromachines 9, no. 11 (October 25, 2018): 544. http://dx.doi.org/10.3390/mi9110544.
Abstract:
Silicon ribbons (SiRi) have been well-established as highly sensitive transducers for biosensing applications thanks to their high surface to volume ratio. However, selective and multiplexed detection of biomarkers remains a challenge. Further, very few attempts have been made to integrate SiRi with complementary-metal-oxide-semiconductor (CMOS) circuits to form a complete lab-on-chip (LOC). Integration of SiRi with CMOS will facilitate real time detection of the output signal and provide a compact small sized LOC. Here, we propose a novel pixel based SiRi device monolithically integrated with CMOS field-effect-transistors (FET) for real-time selective multiplexed detection. The SiRi pixels are fabricated on a silicon-on-insulator wafer using a top-down method. Each pixel houses a control FET, fluid-gate (FG) and SiRi sensor. The pixel is controlled by simultaneously applying frontgate (VG) and backgate voltage (VBG). The liquid potential can be monitored using the FG. We report the transfer characteristics (ID-VG) of N- and P-type SiRi pixels. Further, the ID-VG characteristics of the SiRis are studied at different VBG. The application of VBG to turn ON the SiRi modulates the subthreshold slope (SS) and threshold voltage (VTH) of the control FET. Particularly, N-type pixels cannot be turned OFF due to the control NFET operating in the strong inversion regime. This is due to large VBG (≥25 V) application to turn ON the SiRi sensor. Conversely, the P-type SiRi sensors do not require large VBG to switch ON. Thus, P-type pixels exhibit excellent ION/IOFF ≥ 106, SS of 70–80 mV/dec and VTH of 0.5 V. These promising results will empower the large-scale cost-efficient production of SiRi based LOC sensors.
20
Li, Peng, Shite Zhu, Wei Xi, Changbao Xu, Dandan Zheng, and Kai Huang. "Triple-Threshold Path-Based Static Power-Optimization Methodology (TPSPOM) for Designing SOC Applications Using 28 nm MTCMOS Technology." Applied Sciences 13, no. 6 (March 8, 2023): 3471. http://dx.doi.org/10.3390/app13063471.
Abstract:
The threshold voltage distribution technique is an effective way to reduce the static power consumption of integrated circuits. Several gate-level-based distribution algorithms have been proposed, but the optimization effect and run time still need further optimization when applied to very large-scale integration (VLSI) designs. This paper presents a triple-threshold path-based static power optimization methodology (TPSPOM) for low-power system-on-chip. This method obtains the path weights and cell weights from paths’ timing constraints and cells’ delay-to-power ratios, then uses them as indexes to distribute each cell to low-threshold voltage (LVT), standard-threshold voltage (SVT), or high-threshold voltage (HVT). The experimental results based on a 28 nm circuit containing 385,781 cells show that the TPSPOM method reduces static power consumption by 15.16% more than the critical-path aware power consumption optimization methodology (CAPCOM). At the same time, run time is reduced by 96.85%.
21
Nagabushanam, M., Skandan Srikanth, Rushita Mupalla, Sushmitha S. Kumar, and Swathi K. "Optimization of Power and Area Using VLSI Implementation of MAC Unit Based on Additive Multiply Module." International Journal of Electrical and Electronics Research 10, no. 4 (December 30, 2022): 1099–106. http://dx.doi.org/10.37391/ijeer.100455.
Abstract:
The development of Digital Signal Processors (DSPs), graphical systems, Field Programmable Gate Arrays (FPGAs)/ Application-Specific Integrated Circuits (ASICs), and multimedia systems all rely heavily on digital circuits. The need for high-precision fixed-point or floating-point multipliers suitable for Very Large-Scale Integration (VLSI) implementation in high-speed DSP applications is developing rapidly. An integral part of any digital system is the multiplier. In digital systems as well as signal processing, the adder and multiplier seem to be the fundamental arithmetic units. Problems arise when using a multiplier in the realms of area, power, complexity, and speed. This paper details a more efficient MAC (Multiply- Accumulate) multiplier that has been tuned for space usage. The proposed design is more efficient, takes up less room, and has lower latency than conventional designs. The performance of the Additive Multiply Module (AMM) multiplier is measured against that of existing multipliers, where it serves as a module in the MAC reducing area and delay.
22
Zhu, Ziran, Zhipeng Huang, Jianli Chen, and Longkun Guo. "Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles." Complexity 2021 (April 14, 2021): 1–12. http://dx.doi.org/10.1155/2021/8843271.
Abstract:
As one of the most important routing problems in the complex network within a very-large-scale integration (VLSI) circuit, bus routing has become much more challenging when witnessing the advanced technology node enters the deep nanometer era because all bus bits need to be routed with the same routing topology in the context. In particular, the nonuniform routing track configuration and obstacles bring the largest difficulty for maintaining the same topology for all bus bits. In this paper, we first present a track handling technique to unify the nonuniform routing track configuration with obstacles. Then, we formulate the topology-aware single bus routing as an unsplittable flow problem (UFP), which is integrated into a negotiation-based global routing to determine the desired routing regions for each bus. A topology-aware track assignment is also presented to allocate the tracks to each segment of buses under the guidance of the global routing result. Finally, a detailed routing scheme is proposed to connect the segments of each bus. We evaluate our routing result with the benchmark suite of the 2018 CAD Contest. Compared with the top-3 state-of-the-art methods, experimental results show that our proposed algorithm achieves the best overall score regarding specified time limitations.
23
MOHANA KANNAN, LOGANATHAN, and DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION." DYNA 96, no. 5 (September 1, 2021): 505–11. http://dx.doi.org/10.6036/10214.
Abstract:
Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit and image processing approach makes improved application availability. The design of high speed digital FIR filter is designed with various adders and multipliers. The incorporation of VLSI design and image processing techniques are used on biomedical imaging applications. The Enhanced FIR filter design utilized the hybrid adder and adaptive Vedic multiplier approaches for increasing the performance of VLSI part and the image processing results are taken from Matrix Laboratory tool. This proposed FIR filter design helps to perform the biomedical imaging techniques. The simulation result obtains the performance of enhanced FIR with area, delay and power; for biomedical imaging, Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) is obtained. Comparing with existing and proposed method, the proposed FIR filter for biomedical imaging application obtains the better result. Thus the design model states with various application availability of VLSI image processing approaches and it obtains the better performance results of both VLSI and image processing applications. Overall, the proposed system is designed by Xilinx ISE 14.5 and the synthesized result is done with ModelSim. Here the biomedical image performance is done by using MATLAB with the adaptation of 2018a. Keywords- Enhanced FIR filter; Adaptive vedic multiplier; Hybrid adder; Biomedical imaging; power delay product;
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N., Alivelu Manga. "Design of High-Speed Low Power Computational Blocks for DSP Processors." Revista Gestão Inovação e Tecnologias 11, no. 2 (June 5, 2021): 1419–29. http://dx.doi.org/10.47059/revistageintec.v11i2.1768.
Abstract:
In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary performance criteria for these signal processing operations are speed and power consumption. To lower the power consumption, there are techniques like Multi threshold (Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used which allows reduction in power, delay and area of digital circuits, while maintaining low complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder, Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The Simulation results shows that GDI based designs consume less power and delay also reduced compared to CMOS based designs.
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Cheng, Yi Lung, Yi Shiung Lu, and Tai Jung Chiu. "Comparative Study of Low Dielectric Constant Material Deposited Using Different Precursors." Advanced Materials Research 233-235 (May 2011): 2480–85. http://dx.doi.org/10.4028/www.scientific.net/amr.233-235.2480.
Abstract:
Two kinds of organosilicate precursors, trimethylsilane (3MS) and diethoxymethylsilane (DEMS), were used to produce low-k films by plasma-enhanced chemical vapor deposition (PECVD) in this work. The experimental results indicate that DEMS-based low-k films have superior electrical performance and better thermal stability as compared to 3MS-based low-k films. Therefore, DEMS-based films are the promising low-k materials which can be integrated in very large scale integration circuit as an inter-layer dielectric material.
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Ahmad, Afaq, Sabir Hussain, M. A. Raheem, Ahmed Al Maashri, Sayyid Samir Al Busaidi, and Medhat Awadalla. "ASIC vs FPGA based Implementations of Built-In Self-Test." International Journal of Advanced Natural Sciences and Engineering Researches 7, no. 6 (July 13, 2023): 14–20. http://dx.doi.org/10.59287/ijanser.942.
Abstract:
Linear Feedback Shift Registers (LFSRs) are play key role in testing of for Very Large Scale Integration (VLSI) Integrated Circuits (ICs) testing. Due to tremendous IC complex growth, testing of recent VLSI ICs technology have become more complicated. This led to develop a popular alternate viable solution in the form of Built-In Self-Test (BIST) technology as compared to Automatic Test Equipment (ATE). However, the challenges of BIST technology remain the subject of research. Furthermore, implementation of BIST’s LFSR on Application Specific Integrated Circuit (ASIC) versus Field Programmable Gate Array on (FPGA) platform is current area of research especially in context to power consumption. Hence, to make an informed choice between ASIC and FPGA for implementing BIST’s LFSR we focus on study of design of reconfigurable LFSR on ASIC versus FPGA platform. The Electronic Design Automation (EDA) tool, Cadence is used for implementing BIST’s LFSR on ASIC platform. Whereas, Hardware Description Language (HDL), Verilog is used to implement BIST’s LFSR on FPGA platform. During experimental methodology, maximum frequency, the critical path delay is investigated to assess the power dissipation. The functional and timing simulation models are used to verify the implemented reconfigurable BIST’s LFSR designs. The obtained results show that the performance, in terms of speed and power, of ASIC implementation is far better than traditional FPGA implementation.
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Rasheed, Israa Mohammed, and Hassan Jasim Motlak. "Performance parameters optimization of CMOS analog signal processing circuits based on smart algorithms." Bulletin of Electrical Engineering and Informatics 12, no. 1 (February 1, 2023): 149–57. http://dx.doi.org/10.11591/eei.v12i1.4128.
Abstract:
Designing ideal analogue circuits has become difficult due to extremely large-scale integration. The complementary metal oxide semiconductor (CMOS) analog integrated circuits (IC) could use an evolutionary method to figure out the size of each device. The CMOS operational transconductance amplifier (CMOS OTA) and the CMOS current conveyor second generation (CMOS CCII) are designed using advanced nanometer transistor technology (180 nm). Both CMOS OTA and CMOS CCII have high performance, such as a wide frequency, voltage gain, slew rate, and phase margin, to include very wide applications in signal processing, such as active filters and oscillators. The optimization approach is an iterative procedure that uses an optimization algorithm to change design variables until the optimal solution is identified. In this study, different sorts of algorithms the genetic algorithm (GA), particle swarm optimization (PSO), and cuckoo search (CS) are employed to boost and enhance the performance parameters. While decreasing the time required to develop a conventional operation amplifier's settling time. Some studies decrease the value of the power utilized at various frequencies. Others operate at extremely high frequencies, but their power consumption is greater than that of those operating at lower frequencies.
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NIRANJAN, VANDANA, ASHWANI KUMAR, and SHAIL BALA JAIN. "COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS." Journal of Circuits, Systems and Computers 23, no. 08 (June 18, 2014): 1450108. http://dx.doi.org/10.1142/s0218126614501084.
Abstract:
In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.
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Sun, Ben. "Interpretable machine learning in VLSI physical design." Applied and Computational Engineering 4, no. 1 (June 14, 2023): 13–19. http://dx.doi.org/10.54254/2755-2721/4/20230338.
Abstract:
Today's popularisation of portable devices largely depends on the progress in integrated circuits. Modern Very Large Scale Integration technology (VLSI) allows billions of transistors to be packed into the same chip. In the past years, digital design in VLSI has been developed compared to analogue design. The traditional method is hard to model the performance change in analogue or mixed-signal components caused by physical design. In the early 2000s, rapid advances in machine learning and computing power made analogue design automation possible. Despite their outstanding performance, the transparency issue has become significant. This paper introduces the history of VLSI physical design, which includes placement and routing in the early stages. The change that machine learning (ML) has made is mentioned in the third section. Analysis of the potential problem has been proposed, followed by a brief category of some well-known work in interpretable Machine Learning, which could be the primary direction for VLSI automation to be further popularised in the future.
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Eppili, Jaya, Sri B. Sai, Kumar P. Akshay, Kumar O. Hem, D. Sunil, and R. Rajesh. "VLSI implementation of Kogge-Stone Adder for low-power applications." i-manager's Journal on Digital Signal Processing 11, no. 1 (2023): 9. http://dx.doi.org/10.26634/jdp.11.1.19372.
Abstract:
The adder is a vital part of the Central Processing Unit (CPU) that can perform computational operations. It is used in digital components, mainly in the design of integrated circuits. Recent decades have seen a sharp rise in demand for mobile electronics, which has increased the need for highly efficient Very Large-Scale Integration (VLSI) structures. All operations must be computed using low-power, space-efficient designs that run faster. The Kogge-Stone adder (KSA) is an extension of the carry look-ahead adder which is used for performing fast addition in high-performance computing systems. This study compares the latency, space, and energy used by the Kogge-Stone Adder after development and implementation in Xilinx Vivado using Verilog to those of the Ripple Carry Adder (RCA) and Carry Lookahead Adder (CLA). The results show that the KSA has a decrease in power consumption as well as improvements in high speed and area compaction when compared to the RCA and CLA.
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Soref, Richard. "Applications of Silicon-Based Optoelectronics." MRS Bulletin 23, no. 4 (April 1998): 20–24. http://dx.doi.org/10.1557/s0883769400030220.
Abstract:
Silicon-based optoelectronics is a diversified technology that has grown steadily but not exponentially over the past decade. Some applications—such as smart-pixel signal processing and chip-to-chip optical interconnects—have enjoyed impressive growth, whereas other applications have remained quiescent. A few important applications such as optical diagnosis of leaky metal-oxide-semiconductor-field-effect-transistor circuits, have appeared suddenly. Over the years, research and development has unveiled some unique and significant aspects of Si-based optoelectronics. The main limitation of this technology is the lack of practical silicon light sources—Si lasers and efficient Si light-emitting devices (LEDs)—though investigators are “getting close” to the LED.Silicon-based optoelectronics refers to the integration of photonic and electronic components on a Si chip or wafer. The photonics adds value to the electronics, and the electronics offers low-cost mass-production benefits. The electronics includes complementary-metal-oxide semiconductors (CMOS), very large-scale integration (VLSI), bipolar CMOS, SiGe/Si heterojunction bipolar transistors, and heterostructure field-effect transistors. In this discussion, we will use a loose definition of optoelectronics that includes photonic and optoelectronic integrated circuits (PICs and OEICs), Si optical benches, and micro-optoelectromechanical (MOEM) platforms. Optoelectronic chips and platforms are subsystems of computer systems, communication networks, etc. Silicon substrates feature a superior native oxide, in addition to excellent thermal, mechanical, and economic properties. Silicon wafers “shine” as substrates for PICs and OEICs.
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NAKADA, KAZUKI, TETSUYA ASAI, and HATSUO HAYASHI. "ANALOG VLSI IMPLEMENTATION OF RESONATE-AND-FIRE NEURON." International Journal of Neural Systems 16, no. 06 (December 2006): 445–56. http://dx.doi.org/10.1142/s0129065706000846.
Abstract:
We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.
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Shanavas, I. Hameem, and R. K. Gnanamurthy. "Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm." Mathematical Problems in Engineering 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/809642.
Abstract:
In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.
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Sanadhya, Minakshi, Devendra Kumar Sharma, and Alfilh Raed Hameed Chyad. "Adiabatic technique based low power synchronous counter design." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 4 (August 1, 2023): 3770. http://dx.doi.org/10.11591/ijece.v13i4.pp3770-3777.
Abstract:
<p>The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in synchronous counters, and its high-power consumption impacts the overall effectiveness of the system. This paper calculates the power dissipation (PD), power delay product (PDP), and latency of the presented T flip-flop. To create a 2-bit synchronous counter based on the novel T flip-flops, a performance matrix such as PD, latency, and PDP is analyzed. The analysis is carried out at 100 and 10 MHz frequencies with varying temperatures and operating voltages. It is observed that the presented counter design has a lesser power requirement and PDP compared to the existing counter architectures. The proposed T-flip-flop design at the 45 nm technology node shows an improvement of 30%, 76%, and 85% in latency, PD, and PDP respectively to the 180 nm node at 10 MHz frequency. Similarly, the proposed counter at the 45 nm technology node shows 96% and 97% improvement in power dissipation, delay, and PDP respectively compared to the 180 nm at 10 MHz frequency.</p>
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Kumar, Umesh. "Vlsi Interconnection Modelling Using a Finite Element Approach." Active and Passive Electronic Components 18, no. 3 (1995): 179–202. http://dx.doi.org/10.1155/1995/97362.
Abstract:
In the last decade, an important shift has taken place in the design of hardware with the advent of smaller and denser integrated circuit packages. Analysis techniques are required to ensure the proper electrical functioning of this hardware. An efficient method is presented to model the parasitic capacitance of VLSI (very large scale integration) interconnections. It is valid for conductors in a stratified medium, which is considered to be a good approximation for theSi−SiO2system of which present day ICs are made. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a “spider” of edges. Here the method used [1] has very low complexity, as compared to other models used previously [2], and achieves a high degree of precision within the range of validity of the stratified medium.
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Balodi, Deepak, and Rahul Misra. "Low Power Differential and Ring Voltage Controlled Oscillator Architectures for High Frequency (L-Band) Phase Lock Loop Applications in 0.35 Complementary Metal Oxide Semi Conductor Process." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 11, no. 01 (July 25, 2019): 63–70. http://dx.doi.org/10.18090/samriddhi.v11i01.9.
Abstract:
The design of a high frequency (L Band), low power (2.75mW) Phase Lock Loops with a 350nm Complementary Metal Oxide Semi Conductor (CMOS) technology has been represented. The comparison of Current Starved Voltage Controlled Oscillator (CSVCO) and Differential pair VCO is performed and analyzed for low power and high frequency analysis respectively. Each component of Phase Lock Loop (PLL) is designed with 350nm CMOS technology in Design Architect Integrated Circuit Station by Mentor Graphics (Eldo-Net) as simulator. In this paper both the standard configurations have been simulated under the same environment and results are analyzed for two most important Very Large Scale Integration (VLSI)constraints, Speed (High frequency range) and Power consumption. The high speed and locking performance of the Differential pair VCO has been evaluated against the lower power consumption benefit of CSVCO.
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Yeh, Chung-Huang, and Jwu-E. Chen. "Unbalanced-Tests to the Improvement of Yield and Quality." Electronics 10, no. 23 (December 4, 2021): 3032. http://dx.doi.org/10.3390/electronics10233032.
Abstract:
An integrated-circuit testing model (DITM) is used to describe various factors that affect test yield during a test process. We used a probability distribution model to evaluate test yield and quality and introduced a threshold test and a guardband test. As a result of the development speed of the semiconductor manufacturing industry in the future being unpredictable, we use electrical properties of existing products and the current manufacturing technology to estimate future product-distribution trends. In the development of very-large-scale integration (VLSI) testing, the progress of testing technology is very slow. To improve product testing yield and quality, we change the test method and propose an unbalanced-test method, leading to improvements in test results. The calculation using our proposed model and data estimated by the product published by the IEEE International Roadmap for Devices and Systems (IRDS, 2017) proves that the proposed unbalanced-test method can greatly improve test yield and quality and achieve the goal of high-quality, near-zero-defect products.
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Laudis, Lalin L., and N. Ramadass. "A Lion’s Pride Inspired Algorithm for VLSI Floorplanning." Journal of Circuits, Systems and Computers 29, no. 01 (March 15, 2019): 2050003. http://dx.doi.org/10.1142/s0218126620500036.
Abstract:
The complexity of any integrated circuit pushes the researchers to optimize the various parameters in the design process. Usually, the Nondeterministic Polynomial problems in the design process of Very Large Scale Integration (VLSI) are considered as a Single Objective Optimization Problem (SOOP). However, due to the increasing demand for the multi-criterion optimization, researchers delve up on Multi-Objective Optimization methodologies to solve a problem with multiple objectives. Moreover, it is evident from the literature that biologically inspired algorithm works very well in optimizing a Multi-Objective Optimization Problem (MOOP). This paper proposes a new Lion’s pride inspired algorithm to solve any MOOP. The methodologies mimic the traits of a Lion which always strives to become the Pride Lion. The Algorithm was tested with VLSI floorplanning problem wherein the area and dead space are the objectives. The algorithm was also tested with several standard test problems. The tabulated results justify the ruggedness of the proposed algorithm in solving any MOOP.
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Smy, T., S. K. Dew, and M. J. Brett. "Simulation of Microstructure and Surface Profiles of Thin Films for VLSI Metallization." MRS Bulletin 20, no. 11 (November 1995): 65–69. http://dx.doi.org/10.1557/s0883769400045619.
Abstract:
A crucial step in the manufacture of very large-scale integration (VLSI) integrated circuits is the fabrication of reliable, low-resistance metal interconnects between semiconductor devices. The fabrication of these interconnects is generally performed by depositing a blanket metal film and then patterning it by lithographic and etching techniques. The primary means of depositing thin metal films for VLSI interconnects are sputtering and chemical vapor deposition (CVD).The creation of reliable interconnects is, however, complicated by a number of issues. In order to obtain low contact resistance, to inhibit reactions with the silicon, and to provide good adhesion to both Si and SiO2, contact, barrier, and adhesion layers are generally deposited prior to the deposition of the low-resistance metal film that forms the bulk of the interconnect. If these layers are to provide an effective barrier to diffusion of the interconnection metal to the silicon, they must be deposited in a uniform, homogeneous form. It is also necessary that the primary interconnect material have as high step coverage as is possible in order to reduce current crowding, local heating effects, and electromigration. Unfortunately, as VLSI circuit densities have increased, the fabrication of interconnects requires high aspect-ratio contact cuts, and relatively severe local topographies can result. These factors make it difficult to deposit films with good step and bottom coverage.In addition to these concerns with the film surface profile, another factor is becoming increasingly significant. Both sputtering and CVD produce thin films with characteristic microstructures. This microstructure consists of columns or grains separated by grain boundaries and voids.
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Krishna, T. Rama, T. Krishna Murthy, N. Vilasrao Sarode, P. Srilakshmi, and V. Geetha Sri. "Verilog HDL using LTE Implementation MAP Algorithm." International Journal of Innovative Research in Computer Science and Technology 10, no. 2 (March 30, 2022): 611–14. http://dx.doi.org/10.55524/ijircst.2022.10.2.115.
Abstract:
In many communication systems, turbo coding Techniques for Encoding and Decoding are employed to repair errors. As compared to other error correction codes, turbo codes provide great error correcting capabilities. For the implementation of the Turbo decoder, a Very Large Scale Integration (VLSI) architecture is suggested in this study. The Maximum-a-Posteriori (MAP) algorithm is employed at the decoder side, where soft-in-soft-out decoders, interleaves, and deinterleavers are all used. The usage of the MAP algorithm reduces the quantity of iterations necessary to decode the information bits being transferred. This research employs a system for the encoder component that consists of two recursive convolutional encoders and a pseudorandom interleaver on the encoder side. Tools from Octave and Xilinx Vivado are used for the Turbo encoding and decoding. The system is synthesised and implemented using a specialised integrated circuit.
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Qiao, Zhitong, Yan Han, Xiaoxia Han, Han Xu, Will X. Y. Li, Dong Song, Theodore W. Berger, and Ray C. C. Cheung. "ASIC Implementation of a Nonlinear Dynamical Model for Hippocampal Prosthesis." Neural Computation 30, no. 9 (September 2018): 2472–99. http://dx.doi.org/10.1162/neco_a_01107.
Abstract:
A hippocampal prosthesis is a very large scale integration (VLSI) biochip that needs to be implanted in the biological brain to solve a cognitive dysfunction. In this letter, we propose a novel low-complexity, small-area, and low-power programmable hippocampal neural network application-specific integrated circuit (ASIC) for a hippocampal prosthesis. It is based on the nonlinear dynamical model of the hippocampus: namely multi-input, multi-output (MIMO)–generalized Laguerre-Volterra model (GLVM). It can realize the real-time prediction of hippocampal neural activity. New hardware architecture, a storage space configuration scheme, low-power convolution, and gaussian random number generator modules are proposed. The ASIC is fabricated in 40 nm technology with a core area of 0.122 mm[Formula: see text] and test power of 84.4 [Formula: see text]W. Compared with the design based on the traditional architecture, experimental results show that the core area of the chip is reduced by 84.94% and the core power is reduced by 24.30%.
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Shacham-Diamand, Yosi. "The Reliability of Aluminum/Tungsten Technology for VLSI Applications." MRS Bulletin 20, no. 11 (November 1995): 78–82. http://dx.doi.org/10.1557/s0883769400045644.
Abstract:
Interconnects technology and back-end processing moved to the center stage of very large-scale integration (VLSI) technology in the mid-1980s. At that time, the critical dimensions dropped below 1 μm while the chip size and complexity increased to a level where interconnects were recognized to be a limiting factor. As dimensions decreased, the step coverage of sputtered aluminum inside contacts and via-contact holes decreased and alternative technologies were studied. The increasing cost of ownership (COO) of single-wafer Al sputtering processes also supported the search for alternative technologies, such as tungsten chemical vapor deposition (CVD) for via contacts and plugs (Figure 1). Only recently have all the W CVD process steps been optimized to lower cost without loss of reliability and/or performance. The development of cluster tool technology and multiwafer process modules also allowed reliable and cost-effective utilization of the W/Al technology.Tungsten technology for VLSI circuits became complementary to that of aluminum. Tungsten thin-film resistivity ρw = 7–8 μΩ cm is much higher than that of aluminum ρAl = 3–4 μΩ cm, introducing large W interconnect resistance-capacitance (RC) delays compared to Al. Therefore, tungsten is not favorable for high-speed global-interconnect schemes. However, tungsten is suitable for local interconnects where the impedance of the driving transistors is dominant and the RC interconnect delay is less significant. Tungsten is also suitable for contact filling, in which the via resistance is negligible. For these applications, tungsten became a dominant technology and was integrated with the aluminumalloy-based technology used for global interconnects.
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Sidorenko, V. P., V. D. Zhora, O. I. Radkevich, V. P. Grunyanska, Yu V. Prokofiev, Yu V. Tayakin, and T. M. Virozub. "Assembly technology and design features of microelectronic coordinate-sensitive detectors." Технология и конструирование в электронной аппаратуре, no. 1 (2018): 21–27. http://dx.doi.org/10.15222/tkea2018.1.21.
Abstract:
The design features and assembly technology of microelectronic coordinate-sensitive detectors of charged particles for spectroscopy are considered. The device is based on the specialized very-large-scale integration (VLSI) crystal manufactured using CMOS technology and containing a charge-sensitive matrix designed to detect isotope ions in a wide mass spectrum of the test substance. The range of concentrations measured by devices is also wide and ranges from 10–7 to 100%. The VLSI crystal is placed on a multilayer ceramic basis. The devices also contain a Hamamatsu micro-channel plate (MCP), electrodes that supply high voltage to integrated circuits (2.0 kV), a non-magnetic metal shield for protecting the device components, a connector and other structural elements. VLSI crystals are installed using the method of laying the microcircuits on a flexible aluminum — polyimide media. Such mounting method has a number of advantages over others. The VLSI crystals with project standards of 1 µm are designed for the possibility to create new generation of detectors, which can include either one or several crystals. The prototype version has been developed and it allows placing a bar of five ceramic-based crystals with a minimum gap of 100 µm between them. This design provides high reliability of products due to the usage of multilayer ceramic boards and due to progressive assembly methods used in the manufacturing of special-purpose microelectronic equipment, including the equipment resistant to special external factors.
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Satria, Brama Yoga, Munawar Agus Riyadi, and Muhammad Arfan. "PERANCANGAN MULTIPLIER SEKUENSIAL 8-BIT DENGAN TEKNOLOGI 180NM MENGGUNAKAN PERANGKAT LUNAK ELECTRIC." TRANSIENT 6, no. 3 (November 9, 2017): 476. http://dx.doi.org/10.14710/transient.6.3.476-482.
Abstract:
Very Large Scale Integration (VLSI) merupakan proses dari pembuatan sirkuit terpadu atau Integrated Circuit (IC) dengan cara menggabungkan ribuan rangkaian berbasis transistor ke dalam sebuah chip atau prosesor. Dengan adanya VLSI, ukuran dari devais elektronik berbasis transistor dapat dimampatkan agar menghemat area, biaya produksi, dan efek parasitik. Prosesor terdiri dari beberapa blok utama sebagai penunjang kerjanya, salah satu blok yang paling penting yaitu Arithmatic Logic Unit (ALU). Salah satu contoh dari ALU sendiri yaitu adalah multiplier. Multiplier sangat penting untuk banyak dasar proses dari sebuah prosesor. Tujuan dari penelitian ini adalah merancang sebuah multiplier sekuensial 8-bit dengan teknologi 180nm. Multiplier dirancang dengan menggabungkan blok-blok pembangun seperti blok counter, adder, shift register, dan lain-lainnya. Penelitian ini menggunakan perangkat lunak electric untuk mendesain layout dan perangkat lunak LT-Spice untuk menguji fungsional, delay, dan kinerja dari hasil ekstraksi layout. Hasil perancangan ini secara fungsional telah berjalan dengan baik. Multiplier yang dirancang memiliki layout sebesar 3.725.150 lambda2 dengan nilai delay sebesar 4,428ns. Selain itu, frekuensi maksimum yang digunakan untuk mendapatkan hasil yang benar dari multiplier sekuensial 8-bit yaitu 50MHz.
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Dong, Chen, Jinghui Chen, Wenzhong Guo, and Jian Zou. "A machine-learning-based hardware-Trojan detection approach for chips in the Internet of Things." International Journal of Distributed Sensor Networks 15, no. 12 (December 2019): 155014771988809. http://dx.doi.org/10.1177/1550147719888098.
Abstract:
With the development of the Internet of Things, smart devices are widely used. Hardware security is one key issue in the security of the Internet of Things. As the core component of the hardware, the integrated circuit must be taken seriously with its security. The pre-silicon detection methods do not require gold chips, are not affected by process noise, and are suitable for the safe detection of a very large-scale integration. Therefore, more and more researchers are paying attention to the pre-silicon detection method. In this study, we propose a machine-learning-based hardware-Trojan detection method at the gate level. First, we put forward new Trojan-net features. After that, we use the scoring mechanism of the eXtreme Gradient Boosting to set up a new effective feature set of 49 out of 56 features. Finally, the hardware-Trojan classifier was trained and detected based on the new feature set by the eXtreme Gradient Boosting algorithm, respectively. The experimental results show that the proposed method can obtain 89.84% average Recall, 86.75% average F-measure, and 99.83% average Accuracy, which is the best detection result among existing machine-learning-based hardware-Trojan detection methods.
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Manjunath, T. C., Deekshitha P., Pavithra G., Sindhu Sree M., Suhasini V.K., and K. N. Vijaykumar. "A Survey of the Different Intelligent Algorithms for the VLSI-Based Design Flows for Various Embedded Applications in Electronics Engineering." Journal of Embedded Systems and Processing 7, no. 3 (November 3, 2022): 14–17. http://dx.doi.org/10.46610/joesp.2022.v07i03.003.
Abstract:
The AI/ML applications and techniques that could be applied in VLSI design technology are briefly reviewed in this study. The integrated circuit (IC) industry will undoubtedly face challenges in the nano-meter regime related to the research and development of methods that could reduce design complexity brought on by increasing process variability and reducing the turnaround time of chip manufacture. The majority of the traditional methods utilized for these tasks involve manual labor, which requires time and resources. Contrarily, the unique learning strategies of artificial intelligence enable the design and testing of very large-scale integration (VLSI) to benefit from several innovative automated ways (AI). Artificial intelligence (AI) and machine learning (ML) algorithms use automated learning algorithms to reduce the time and effort needed to interpret and process data within and across different abstraction levels, enhancing IC yield and accelerating manufacturing turnaround. This article examines the formerly employed automated AI/ML methods for VLSI design and manufacture. The project that is the subject of this paper is a P.G. (M.Tech) student's technical seminar report, which is a component of the seminar that each student must deliver on any topic during the second semester of the PG program.
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Mai, Christian, Steffen Marschmeyer, Anna Peczek, Aleksandra Kroh, Josmy Jose, Sebastian Reiter, Inga Fischer, Christian Wenger, and Andreas Mai. "Integration Aspects of Plasmonic TiN-based Nano-Hole-Arrays on Ge Photodetectorsin a 200mm Wafer CMOS Compatible Silicon Technology." ECS Meeting Abstracts MA2022-02, no. 32 (October 9, 2022): 1174. http://dx.doi.org/10.1149/ma2022-02321174mtgabs.
Abstract:
During the last decade optical sensor technologies have attracted increased attention for various applications. Plasmon-based optical sensor concepts for the detection of refractive index changes that rely on propagating surface-plasmon polaritons at metal-dielectric interfaces or on localized plasmons in metallic nanostructures prove their potential for these application due to their fast detection speed, high specificity and sensitivities [1, 2]. Combining plasmonic structures directly with optoelectronic devices could enable a high level of integration, however, it represents a significant technological challenge to develop an on-chip solution for these concepts including the integration of sensor and detector components. Previous works demonstrated first approaches mainly for the integration of refractive index sensor components on wafer level [3, 4]. In [5] and [6] a proof-of-concept of a fully integrated on-chip solution with high sensitivities was presented, which can be easily combined with microfluidics [7] for potential applications in biosensing. In this concept, a nanohole array (NHA) was structured in a 100 nm thick aluminum layer on top of a vertical PIN germanium photodetector (GePD) with an intrinsic germanium sheet of 480 nm. This sensor concept relies on extraordinary optical transmission through the NHA [8]: Light transmission is only possible for narrow wavelength ranges determined by the NHA geometry which determine the transmission peaks at the resonance wavelength of the NHA. Thus, the NHA acts as a high quality wavelength filter. Due to the change in the refractive index, a material under test (MUT) contacting directly the surface of the NHA, provokes a shift of the wavelength maximum, which can be detected by measuring the photocurrent spectra of the GePD. While responsivities and sensitivities of (0 V) = 0.075 A/W and = 1200 nm/RIU could be attained in this proof-of-concept device [6, 7], the semiconductor device layers were deposited using molecular beam epitaxy (MBE). Furthermore the vertical PIN GePD was realized by a mesa procedure to enable large areas for top illuminated operations. These techniques are unsuitable for an industrial CMOS fabrication process with high throughput. Therefore, the development of a CMOS compatible technology process with low costs and high yields is an important step towards large-scale fabrication of this sensor concept. In this work we present the progress for the realization of a surface plasmon resonance (SPR) refractive index sensor in a 200 mm wafer Silicon based technology. One main challenge is the fabrication of a large area photodetector for top illuminated sensor devices. We developed a process, which is mainly based on the IHP electronic photonic integrated circuits (ePIC) technology [9]. This ePIC technology enables the production of waveguide coupled lateral PIN GePDs with high bandwidth and high responsivities [10]. However, these PDs are unsuitable for top illuminated applications because of their small germanium areas. Due to certain process conditions with respect to chemical mechanical polishing procedures there are limits for feasible large detector areas. Furthermore, large detector areas for lateral PIN GePDs would result in very low electric fields in the intrinsic zone where carriers are generated by photon absorption. Thus, very high voltages for reversed bias are necessary for sufficient carrier drifts. For the first time we have developed a modern detector design concept which is compatible to the IHP ePIC technology. This concept allows the realization of large area detectors of 1600µm² (40µm x 40µm) with optimized optical responsivities for top illuminated applications. The detector consists of several parallel connected lateral PIN GePDs. We designed different variations and varied Ge width and distance between neighboring GePDs in order to investigate process limits. The p- and n-doped regions were defined by dopant implantation using a photo resist mask. We used a finger-like design as implantation masks to enable one contact area for each p-doped and each n-doped region (Fig. 1). This contacting approach differs from the standard GePD offered in the IHP ePIC technology. We analyzed I-V characteristics in dependence of detector design and contacting scheme (Fig. 2). In addition, process adjustments for the optimization of the germanium quality were investigated to reduce dark currents and to improve optical responsivities (Fig.3). Titanium nitride (TiN) is very promising metallic alloy with respect to thickness homogeneity and low surface roughness. Therefore we used titanium nitride which was deposited by a sputtering process to develop plasmonic active NHA layers. Various process development runs were done to evaluate the NHA performance. Ellipsometry and atomic force microscope measurements were performed to characterize the quality of the TiN layer (Fig.4). Figure 1
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Deekshitha P, Pavithra G, Sindhu Sree M, and T.C.Manjunath. "AI/ML/DL Algorithms and Applications in VLSI Design Technology Process Flow – A Brief Review." international journal of engineering technology and management sciences 6, no. 6 (November 28, 2022): 329–32. http://dx.doi.org/10.46647/ijetms.2022.v06i06.057.
Abstract:
This paper gives a brief review of the AI/ML algorithms and applications that could be used in VLSI design technology. As the analysis and development of techniques that might lessen design complexity brought on by expanding process variability and shorten the turnaround time of chip manufacturing are clearly going to be a problem for the integrated circuit (IC) industry in the nanometre regime. The traditional approaches used for these activities are mostly manual, which takes time and resources. Contrarily, very large scale integration (VLSI) design and testing can take advantage of a variety of new automated ways thanks to the distinctive learning strategies of artificial intelligence (AI). Utilizing automated learning algorithms, AI and machine learning (ML) algorithms reduce the time and effort required to comprehend and process data within and across different abstraction levels, improving IC yield and speeding up production turnaround. This article examines the automated AI/ML methods for VLSI design and production that were previously used. The work presented in this paper is a technical seminar report of the P.G. (M.Tech) student, which is a part of the seminar that every student has to give w.r.t. any topic in the second semester of the PG programme.
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Flemming, Jeb, Kyle McWethy, Tim Mezel, Luis Chenoweth, and Carrie Schmidt. "Photosensitive Glass-Ceramics for Heterogeneous Integration." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000880–907. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_036.
Abstract:
The push for heterogeneous integration requires very unique material properties with respect to processing, material constants, and integration capabilities with other materials (such as copper, III–V, magnetics, etc.). Current common circuit board materials such as ceramics and laminates, as well as silicon substrates, suffer from a variety of limitations. For ceramics and laminates, these constraints include: (1) the inability to produce narrow line widths <100 m with narrow gaps between lines <100 m; (2) high surface roughness (on the order of 2μm RMS); (3) layer-to-layer misalignments; and (4) lack of high-quality integrated passives. For silicon, these constraints include: (1) high cost; (2) long design/production lead times; and (3) electrical properties of standard doped silicon are not suitable for millimeter-wave applications. A significant drawback of ceramics and laminates is that they cannot be 3D structured with micron-scale precision which is necessary for advanced interconnects for millimeter-wave IC packaging integration (e.g. transistor-to-board interconnects). These characteristics lead to devices with limited integration options, large footprints, and higher power consumption. To overcome the above limitations, 3D Glass Solutions (3DGS) has developed a photo-sensitive glass ceramics as a board-level system substrate. Compared to ceramics, laminates, and silicon, photo-sensitive glass ceramic materials offer higher interconnect densities, lower processing cost, better spatial resolution, as well as improved electrical properties for both RF and millimeter-wave frequencies. Photo-sensitive glass ceramics are ideal systems-level materials for heterogeneous integration programs as they overcome many of the limitations of legacy materials such as ceramics and laminates for broadband applications (DC – 100GHz). Furthermore, the advanced manufacturing ability of photo-sensitive glass ceramics enable a broad category of IP Blocks. The innovations of the 3DGS technology and research effort include:Low loss and low dispersion: photosensitive glass material has a measured loss tangent of 0.008 at GHz frequencies. Furthermore, the thick and highly-conductive metallization layers allow for low-loss transmission lines.High current and power handling: the metallization processes enable lines with a range of thicknesses (<50m) and widths (>2m), which result in both low resistive loss and high current handling. Additionally, the RF power handling is high due to the high breakdown voltage of glass (10kV/100m) and the possibility of coaxial line integration.Thermal management: high-density metal-filled via arrays generate up to 100W/mK thermal transfer in the 3DGS process and provide an additional thermal path for chips that are not mounted directly on a heterogeneous interface heat spreader.Built-in filtering: when a variety of chiplets with unknown design parameters and with signals of varying time constants are interconnected, EMI becomes a significant problem. The 3DGS approach allows for high-quality filtering, coupling and self-assessment functions to be directly integrated within the 2.5D interposer system as IPDs eliminating wire bonding and providing seamless integration with low loss.Scalability: the glass interconnect plane can be fabricated with footprints up to 40mm × 40mm with integrated air cavities for chip placement, through glass vias for I/Os and redistribution metal. In this presentation, 3DGS will present on three Heterogeneous Integration attributes: (1) design considerations, (2) integration of passive devices, and (3) millimeter wave integration. Design Considerations 3DGS is developing an IP Block library with 11 distinct categories. These categories include: (1) metal filled I/Os, (2) copper redistribution layers, (3) thermal management blocks, (4) cavities, (5) metal filled through glass structures, (6) phased array antenna, (7) conductor undercuts, (8) magnetic core devices, (9) capacitors, (10) inductors, and (11) grounding. While each of these unique IP Blocks contributes their own advantages for analog performance, they can all be integrated into a single chip. Integration of Passives Devices The foundation of the work done by 3DGS is on developing a volume manufacturing approach for high uniformity through glass vias (TGVs). All TGVs for I/O applications are 100% copper filled for low-loss, high power, electrical connections. Two major building blocks of 3DGS' Heterogeneous technology are High Quality Factor inductors and capacitors. 3DGS has developed a broad library of inductor components ranging from 0.5 – 200nH. Footprints are determined by inductance sizes but may be as small as 01005. Capacitors are built by placing two slots inside of the glass material, filling the slots with copper, and using the glass' natural Dk to form a capacitor. The benefit of these capacitors include high breakdown voltage (>1,000V), small footprint, high reliability, and Quality factors between 200–300. Inductors and capacitors can be integrated into a single monolithic RF package called an Integrated Passive Device (IPD). The benefits of the IPD include the elimination of RF losses associated with PCB Interconnects, long metal redistribution line lengths, bond pads, solder balls, and inconsistent assembly. This leads to the production of RF devices, capable of operating in the MHz – GHz frequency range with higher overall system Quality Factors, lower ripple, and lower losses. Furthermore, IPDs can be directly integrated into more complex System-in-Package (SiP) architectures. This approach has been used to build an RF ZigBee module in APEX® Glass [1]. The glass SiP module consisted of 35+ SMT components and was itself soldered to a PCB board. The full RF module was then subjected full complement of reliability tests and met the customer's stringent performance goals. Millimeter Wave Integration A major benefit of glass is the ability to produce low loss structures for millimeter wave applications. 3DGS has been designing and producing a variety of millimeter wave band pass filters with a variety of bandwidths ranging from 5–40%. These bandpass filters are compact, fully shielded and low loss (<2.0dB) with high attenuation (>50dB).
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Sharma, Himanshu, and Karmjit Singh Sandha. "Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects." Journal of Circuits, Systems and Computers 29, no. 12 (February 5, 2020): 2050185. http://dx.doi.org/10.1142/s0218126620501856.
Abstract:
Graphene nanoribbons are considered potentially suitable and have exhibited excellent results in on-chip interconnects. In order to evaluate the different circuit impedance parameters of multi-layer graphene nanoribbons (MLGNRs), an electrical equivalent single conductor (ESC) along with an analytical model is proposed. On the basis of an electrical model, the impact of intercalation doping on the performance of MLGNRs at 32, 22, and 16[Formula: see text]nm technology nodes is discussed in this paper. Moreover, it is also discussed that the increase in intercalation doping increases the Fermi energy of the layers of the MLGNR, which increases its overall conductivity. The fact that the variation in the Fermi energy will have a considerable impact on the parasitic parameters of the MLGNR interconnect at three different technology nodes (32, 22, and 16[Formula: see text]nm) for variable global lengths (500–2000[Formula: see text][Formula: see text]m) is also analyzed. To estimate and compare the performance in terms of delay and power delay product (PDP) of MLGNRs, the simulation program with integrated circuit emphasis (SPICE) simulation tool is used. The results also show that the increase in the Fermi energy improves the performance of MLGNRs in terms of delay and PDP at three different technology nodes. Furthermore, a comparative analysis of all three technology nodes is performed with the copper interconnect, and it is revealed that the MLGNR interconnect is considered to be a prominent material for the next-generation on-chip very-large-scale integration interconnects.