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1
Yang, Boyu. "Very Large-Scale Integration Circuit and Its Current Status Analysis." Highlights in Science, Engineering and Technology 71 (November 28, 2023): 421–27. http://dx.doi.org/10.54097/hset.v71i.14627.
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The development of Very Large Scale Integration (VLSI) has become very relevant to our lives, and although many of the technologies have matured, scientists are still actively exploring and innovating them. This article is a basic introduction to the composition and advanced technology of large-scale integrated circuits, focusing on transistors and the basic components it consists of, as well as the design of integrated circuits, manufacturing and measurement technology. Very Large Scale Integration Circuit, the transistor is the most basic component of the original, to the low-power CMOS tube is the most widely used, they form a logic gate and storage elements, to achieve a variety of basic functions of the circuit, while the circuit also exists to provide signal distribution and interconnection of the clock network, the optimization of the design of the contemporary research is also a hot spot. In recent years, the progress of the chip can not be separated from the development of new technologies, SOC technology, low-power technology and detection technology plays an important role in the promotion.
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M, Thillai Rani, Rajkumar R, Sai Pradeep K.P, Jaishree M, and Rahul S.G. "Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits." ITM Web of Conferences 56 (2023): 01005. http://dx.doi.org/10.1051/itmconf/20235601005.
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High-level synthesis (HLS) is utilized for high-performance and energy-efficient heterogeneous systems designing. HLS is assist in field-programmable gate array circuits designing where hardware implementations are refined and replaced in target device. However, the power-process-voltage-temperature-delay (PPVTD) variation in VLSI circuits undergoes many problems and reduced the performance. In order to address these problems, C4.5 with eXtreme Gradient Boosting Classification based High Level Synthesis (C4.5-XGBCHLS) Method is designed for afford better runtime adaptability (RA) with minimal error rate. VLSI circuits are designed using the behavioral input and results are measured at running condition. When VLSI circuit’s results get reduced, the language description of the circuit is considered as an input. Then, compilation process convert high level specification into Intermediate Representation (IR) in control/data flow graph (CDFG). CDFG computes data and control dependencies among operations. eXtreme Gradient Boosting (XGBoost) Classifier is exploited in C4.5-XGBCHLS method to classify the error causing functional unit (FU) with minimal error rate. XGBoost Classifier exploited C4.5 decision tree as base classifier to enhance classification of error causing FU in VLSI circuits. After that, FU gets allocated in place of error causing FU from functional library based on the design objectives and PPVTD variations. Finally, operation scheduling and binding process is executed for register transfer level (RTL) generation to form VLSI circuits with improved RA. The simulation results shows that the C4.5-XGBCHLS method enhances the performance of functional unit selection accuracy (FUSA) with minimal error rate (ER) and circuit adaptability time (CAT).
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Patel, Ambresh, and Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, no. 01 (January 30, 2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.
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The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits because it requires fewer transistors, has lower parasitic capacitance, is faster, and enables pipelinedsystem architecture with glitch-free circuits. It has, however, increased power dissipation. Both types of CMOS circuits withlow power dissipation overcome their own shortcomings.This paper discusses dynamic CMOS logic circuits and their structures. Various logics are also discussed and on the basisof the results obtained, logic which is best suited for designing CMOS logic circuit will be found out. The logic on the basisof structure layout and design which gives best results for high-speed VLSI circuits, is found out.
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Iwai, Hiroshi, Kuniyuki Kakushima, and Hei Wong. "CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING." International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 43–81. http://dx.doi.org/10.1142/s0129156406003539.
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The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.
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Madhura, S. "A Review on Low Power VLSI Design Models in Various Circuits." Journal of Electronics and Informatics 4, no. 2 (July 8, 2022): 74–81. http://dx.doi.org/10.36548/jei.2022.2.002.
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Low power design is one of the primary goals for any integrated circuits. Very Large-Scale Integration (VLSI) is a kind of Integrated Circuit (IC) that consists of hundreds and hundreds of transistor connection into a small chip. The communication and computer applications have grown very faster in the past decade due to the development of VLSI circuit design as microcontroller and microprocessors. However, still the research on VLSI are moving faster towards the scope of power and area minimization. The paper gives an overview about the recent methodologies that have been developed for the performance improvement of VLSI design and it shows the future directions of the areas that are to be concentrated on VLSI circuit design.
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Im, James S., and Robert S. Sposili. "Crystalline Si Films for Integrated Active-Matrix Liquid-Crystal Displays." MRS Bulletin 21, no. 3 (March 1996): 39–48. http://dx.doi.org/10.1557/s0883769400036125.
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The fabrication of thin-film-transistor (TFT) devices on a transparent substrate lies at the heart of active-matrix-liquid-crystal-display (AMLCD) technology. This is both good and bad. On one hand it is a difficult task to manufacture millions of intricate semiconductor devices reliably over such large display substrates. On the positive side, AMLCD technology can aspire to become much more than a “display” technology. The idea is as follows: It is possible for one to readily fabricate additional transistors to execute various electronic functions—those that would otherwise be handled by separate large-scale-integration (LSI) and very large-scale-integration (VLSI) circuits—on the periphery of the display. Since this can be done, in principle, with no—or a minimal number of—additional processing steps, substantial cost reduction is possible and significant value can be added to the final product.Doing so and doing it well can ultimately lead to “system-on-glass” products in which the entire electronic circuitry needed for a product is incorporated directly onto a glass substrate. This means that integrated active-matrix liquid-crystal displays (IAMLCDs) have the potential to bypass conventional Si-wafer-based products and may lead TFT technology to compete directly against Si-wafer-based monolithic integrated circuits.
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Beck, Anthony, Franziska Obst, Mathias Busek, Stefan Grünzner, Philipp Mehner, Georgi Paschew, Dietmar Appelhans, Brigitte Voit, and Andreas Richter. "Hydrogel Patterns in Microfluidic Devices by Do-It-Yourself UV-Photolithography Suitable for Very Large-Scale Integration." Micromachines 11, no. 5 (May 2, 2020): 479. http://dx.doi.org/10.3390/mi11050479.
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The interest in large-scale integrated (LSI) microfluidic systems that perform high-throughput biological and chemical laboratory investigations on a single chip is steadily growing. Such highly integrated Labs-on-a-Chip (LoC) provide fast analysis, high functionality, outstanding reproducibility at low cost per sample, and small demand of reagents. One LoC platform technology capable of LSI relies on specific intrinsically active polymers, the so-called stimuli-responsive hydrogels. Analogous to microelectronics, the active components of the chips can be realized by photolithographic micro-patterning of functional layers. The miniaturization potential and the integration degree of the microfluidic circuits depend on the capability of the photolithographic process to pattern hydrogel layers with high resolution, and they typically require expensive cleanroom equipment. Here, we propose, compare, and discuss a cost-efficient do-it-yourself (DIY) photolithographic set-up suitable to micro-pattern hydrogel-layers with a resolution as needed for very large-scale integrated (VLSI) microfluidics. The achievable structure dimensions are in the lower micrometer scale, down to a feature size of 20 µm with aspect ratios of 1:5 and maximum integration densities of 20,000 hydrogel patterns per cm². Furthermore, we demonstrate the effects of miniaturization on the efficiency of a hydrogel-based microreactor system by increasing the surface area to volume (SA:V) ratio of integrated bioactive hydrogels. We then determine and discuss a correlation between ultraviolet (UV) exposure time, cross-linking density of polymers, and the degree of immobilization of bioactive components.
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Siddesh, K. B., S. Roopa, Parveen B. A. Farzana, and T. Tanuja. "Design of duty cycle correction circuit using ASIC implementation for high speed communication." i-manager’s Journal on Electronics Engineering 13, no. 3 (2023): 33. http://dx.doi.org/10.26634/jele.13.3.19969.
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This research proposed an accurate Duty Cycle Correction (DCC) circuit for high-frequency systems with high measurement accuracy. It is a crucial component of Very Large Scale Integration (VLSI) circuits and is applied as a percentage of the measured average power of a modulated signal to obtain the signal power. This circuit uses two stages of correction, with the first stage performing course correction and the second stage performing fine corrections. This allows the power to be determined during the pulse given the measurement of the average power of a modulated signal with a known duty cycle. DCC have improved stability, correction range, and operating frequency compared with mixed-signal and all-digital DCCs. In this analysis, the duty cycle correction circuits and their significance in Application Specific Integrated Circuit (ASIC) design, along with typical implementation methods, are discussed.
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Li, Jian, Robert Blewer, and J. W. Mayer. "Copper-Based Metallization for ULSI Applications." MRS Bulletin 18, no. 6 (June 1993): 18–21. http://dx.doi.org/10.1557/s088376940004728x.
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Multilevel metallization of very large-scale integrated (VLSI) circuits has become an area of intense research interest as devices are scaled down in order to increase circuit density. As device dimensions approach the submicron regime, reliability becomes more of an issue. Metallization generally requires good conductivity, electromigration resistance, controllable contact performance, corrosion resistance, adherence, thermal stability, bondability, ability to be patterned into a desirable geometry, and economic feasibility.Aluminum and its alloys have been commonly used as the main metallization materials because they meet most of the metallization requirements for microelectronic devices. Aluminum, however, suffers from major limitations, such as elec-tromigration and stress-voiding induced open-circuit failure. For the development of ultralarge-scale integration (ULSI) for fast-switching-speed devices, the electrical resistivities of aluminum and its alloys are not low enough. As the minimum geometry is scaled down to one-quarter micron, aluminum and its alloys potentially will be replaced by other materials such as Cu, Au, or superconductors for on-chip interconnection.
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Dove, Lewis. "Multi-Layer Ceramic Packaging for High Frequency Mixed-Signal VLSI ASICS." Journal of Microelectronics and Electronic Packaging 6, no. 1 (January 1, 2009): 38–41. http://dx.doi.org/10.4071/1551-4897-6.1.38.
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Mixed-signal Application Specific Integrated Circuits (ASICs) have traditionally been used in test and measurement applications for a variety of functions such as data converters, pin electronics circuitry, drivers, and receivers. Over the past several years, the complexity, power density, and bandwidth of these chips has increased dramatically. This has necessitated dramatic changes in the way these chips have been packaged. As the chips have become true VLSI (Very Large Scale Integration) ICs, the number of I/Os have become too large to interconnect with wire bonds. Thus, it has become necessary to utilize flip chip interconnects. Also, the bandwidth of the high-speed signal paths and clocks has increased into the multi Gbit or GHz ranges. This requires the use of packages with good high-frequency performance which are designed using microwave circuit techniques to optimize signal integrity and to minimize signal crosstalk and noise.
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Boychenko, Dmitry, Oleg Kalashnikov, Alexander Nikiforov, Anastasija Ulanova, Dmitry Bobrovsky, and Pavel Nekrasov. "Total ionizing dose effects and radiation testing of complex multifunctional VLSI devices." Facta universitatis - series: Electronics and Energetics 28, no. 1 (2015): 153–64. http://dx.doi.org/10.2298/fuee1501153b.
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Total ionizing dose (TID) effects and radiation tests of complex multifunctional Very-large-scale integration (VLSI) integrated circuits (ICs) rise up some particularities as compared to conventional ?simple? ICs. The main difficulty is to organize informative and quick functional tests directly under irradiation. Functional tests approach specified for complex multifunctional VLSI devices is presented and the basic radiation test procedure is discussed in application to some typical examples.
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Wong, C. P. "An Overview of Integrated Circuit Device Encapsulants." Journal of Electronic Packaging 111, no. 2 (June 1, 1989): 97–107. http://dx.doi.org/10.1115/1.3226528.
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The rapid development of integrated circuit technology from small-scale integration (SSI) to very large scale integration (VLSI) has had great technological and economical impact on the electronics industry. The exponential growth of the number of components per IC chip, the exponential decrease of device dimensions, and the steady increase in IC chip size have imposed stringent requirements, not only on the IC physical design and fabrication, but also on IC encapsulants. This report addresses the purpose of encapsulation, encapsulation techniques, and a general overview of the application of inorganic and organic polymer materials as electronic device encapsulants.
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IKEDA, SHOJI, HIDEO SATO, MICHIHIKO YAMANOUCHI, HUADONG GAN, KATSUYA MIURA, KOTARO MIZUNUMA, SHUN KANAI, et al. "RECENT PROGRESS OF PERPENDICULAR ANISOTROPY MAGNETIC TUNNEL JUNCTIONS FOR NONVOLATILE VLSI." SPIN 02, no. 03 (September 2012): 1240003. http://dx.doi.org/10.1142/s2010324712400036.
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We review recent developments in magnetic tunnel junctions with perpendicular easy axis (p-MTJs) for nonvolatile very large scale integrated circuits (VLSIs). So far, a number of material systems such as rare-earth/transition metal alloys, L10-ordered ( Co, Fe )– Pt alloys, Co /( Pd, Pt ) multilayers, and ferromagnetic-alloy/oxide stacks have been proposed as electrodes in p-MTJs. Among them, p-MTJs with single or double ferromagnetic-alloy/oxide stacks, particularly CoFeB–MgO , were shown to have high potential to satisfy major requirements for integration.
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Rajaei, Ramin. "A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics." Journal of Circuits, Systems and Computers 27, no. 13 (August 3, 2018): 1850205. http://dx.doi.org/10.1142/s0218126618502055.
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Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write operation over the previous MFFs. This magnetic-based logic circuit is based on the previous two-in-one (TIO) MTJ cell that presents the aforementioned attributes. Radiation-induced single event upset, as another reliability challenge, is also taken into consideration for the MFFs and another MFF robust against radiation effects is suggested and evaluated.
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Sun, Chongjun, and Chao Ding. "Study on Calibration Method for Testing During Burn In equipment of integrated circuits." Journal of Physics: Conference Series 2029, no. 1 (September 1, 2021): 012035. http://dx.doi.org/10.1088/1742-6596/2029/1/012035.
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Abstract In order to implement Method 1015 of GJB 548B, TDBI(Testing During Burn In) technology of integrated circuit is widely used in the aging process of core VLSI(Very Large Scale Integration) which is included of FPGA, DSP, CPU and dedicated chips. Many models of TDBI equipment at home or abroad have been come into use. It is an important task to calibrate TDBI equipment in system level and ensure the traceability of its measurement value. At present, the calibration device of TDBI equipment has been successfully finalized and put into production, which has the advantages of convenient use and high cost performance. This paper mainly introduces the calibration method for TDBI equipment of integrated circuit from the aspects of the overall architecture design, signal adaptation design and calibration software design.
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Murarka, S. P., J. Steigerwald, and R. J. Gutmann. "Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing." MRS Bulletin 18, no. 6 (June 1993): 46–51. http://dx.doi.org/10.1557/s0883769400047321.
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Continuing advances in the fields of very-large-scale integration (VLSI), ultralarge-scale integration (ULSI), and gigascale integration (GSI), leading to the continuing development of smaller and smaller devices, have continually challenged the fields of materials, processes, and circuit designs. The existing metallization schemes for ohmic contacts, gate metal, and interconnections are inadequate for the ULSI and GSI era. An added concern is the reliability of aluminum and its alloys as the current carrier. Also, the higher resistivity of Al and its use in two-dimensional networks have been considered inadequate, since they lead to unacceptably high values of the so-called interconnection delay or RC delay, especially in microprocessors and application-specific integrated circuits (ICs). Here, R refers to the resistance of the interconnection and C to the total capacitance associated with the interlayer dielectric. For the fastest devices currently available and faster ones of the future, the RC delay must be reduced to such a level that the contribution of RC to switching delays (access time) becomes a small fraction of the total, which is a sum of the inherent device delay associated with the semiconductor, the device geometry and type, and the RC delay.
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Chen, Xiangyu, Takeaki Yajima, Isao H. Inoue, and Tetsuya Iizuka. "An ultra-compact leaky integrate-and-fire neuron with long and tunable time constant utilizing pseudo resistors for spiking neural networks." Japanese Journal of Applied Physics 61, SC (February 18, 2022): SC1051. http://dx.doi.org/10.35848/1347-4065/ac43e4.
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Abstract Spiking neural networks (SNNs) inspired by biological neurons enable a more realistic mimicry of the human brain. To realize SNNs similar to large-scale biological networks, neuron circuits with high area efficiency are essential. In this paper, we propose a compact leaky integrate-and-fire (LIF) neuron circuit with a long and tunable time constant, which consists of a capacitor and two pseudo resistors (PRs). The prototype chip was fabricated with TSMC 65 nm CMOS technology, and it occupies a die area of 1392 μm2. The fabricated LIF neuron has a power consumption of 6 μW and a leak time constant of up to 1.2 ms (the resistance of PR is up to 600 MΩ). In addition, the time constants are tunable by changing the bias voltage of PRs. Overall, this proposed neuron circuit facilitates the very-large-scale integration of adaptive SNNs, which is crucial for the implementation of bio-scale brain-inspired computing.
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Chowdary, M. Kalpana, Rajasekhar Turaka, Bayan Alabduallah, Mudassir Khan, J. Chinna Babu, and Ajmeera Kiran. "Low-Power Very-Large-Scale Integration Implementation of Fault-Tolerant Parallel Real Fast Fourier Transform Architectures Using Error Correction Codes and Algorithm-Based Fault-Tolerant Techniques." Processes 11, no. 8 (August 8, 2023): 2389. http://dx.doi.org/10.3390/pr11082389.
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As technology advances, electronic circuits are more vulnerable to errors. Soft errors are one among them that causes the degradation of a circuit’s reliability. In many applications, protecting critical modules is of main concern. One such module is Fast Fourier Transform (FFT). Real FFT (RFFT) is a memory-based FFT architecture. RFFT architecture can be optimized by its processing element through employing several types of adder and multipliers and an optimized memory usage. It has been seen that various blocks operate simultaneously in many applications. For the protection of parallel FFTs using conventional Error Correction Codes (ECCs), algorithmic-based fault tolerance (ABFT) techniques like Parseval checks and its combination are seen. In this brief, the protection schemes are applied to the single RAM-based parallel RFFTs and dual RAM-based parallel RFFTs. This work is implemented on platforms such as field programmable gate arrays (FPGAs) using Verilog HDL and on application-specific integrated circuit (ASIC) using a cadence encounter digital IC implementation tool. The synthesis results, including LUTs, slices registers, LUT–Flip-Flop pairs, and the frequency of two types of protected parallel RFFTs, are analyzed, along with the existing FFTs. The two proposed architectures with the combined protection scheme Parity-SOS-ECC present an 88% and 33% reduction in area overhead when compared to the existing parallel RFFTs. The performance metrics like area, power, delay, and power delay product (PDP) in an ASIC of 45 nm and 90 nm technology are evaluated, and the proposed single RAM-based parallel RFFTs architecture presents a 62.93% and 57.56% improvement of PDP in 45 nm technology and a 67.20% and 60.31% improvement of PDP in 90 nm technology compared to the dual RAM-based parallel RFFTs and the existing architecture, respectively.
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Zhang, Ai Rong. "The Integration on Electrical Control Systems Based on Optimized Method." Advanced Materials Research 490-495 (March 2012): 2604–8. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2604.
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Very large scale integration (VLSI) applications have improved control implementation performance. Indeed, an application specific integrated circuit (ASIC) solution can exploit efficiently specificities of the control algorithms that fixed hardware architecture cannot do. For example, parallel calculation cannot be included in a software solution based on sequential processing. In addition, ASIC can reduce wire and electromagnetic field interference by a fully system on a chip (SoC) integration. However, there are still two main drawbacks to an integrated circuit solution: design complexity and reuse difficulty. This is true even with programmable logic device (PLD) solutions. Conception aid developer (CAD) combined with hardware description languages (HDL) and VLSI design methodology have accelerated conception and reuse. Nevertheless, the main problem of integrated circuit design is to define the hardware architecture; this is particularly true for heterogeneous algorithm structures such as electrical controls.
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Shan, Tianchang. "Advancements in VLSI low-power design: Strategies and optimization techniques." Applied and Computational Engineering 41, no. 1 (February 22, 2024): 22–28. http://dx.doi.org/10.54254/2755-2721/41/20230706.
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As production technology advances, integrated circuits are increasing in size, leading to a corresponding rise in power consumption if not properly optimized. Consequently, the optimization of integrated circuit power consumption has gained paramount significance. This paper provides an overview of the theoretical and research developments in Very Large Scale Integration (VLSI) low-power design. Initially, the paper delves into the components of VLSI power consumption, elucidating the origins of various power consumption types and the factors influencing their magnitude. Subsequently, existing power reduction technologies are examined, including transistor-level optimization, gate-level optimization, and system-level power optimization. The principles, applicable power consumption types, as well as their respective advantages and drawbacks are analysed. The paper also introduces methods for evaluating VLSI power consumption and summarizes the characteristics, advantages, and disadvantages of high-level power estimation and low-level power estimation. Ultimately, it underscores the importance of considering multiple power optimization strategies during VLSI design and discusses research approaches for achieving low power consumption. This comprehensive exploration contributes to the enhancement and optimization of VLSI design efforts.
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Luo, Guozheng, Xiang Chen, and Shanshan Nong. "Net Clusting Based Low Complexity Coarsening Algorithm In k-way Hypergraph Partitioning." Journal of Physics: Conference Series 2245, no. 1 (April 1, 2022): 012019. http://dx.doi.org/10.1088/1742-6596/2245/1/012019.
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Abstract With the increasing scale of integrated circuits, hypergraph partitioning is usually applied to Very Large Scale Integration (VLSI) circuit layout and other applications to reduce the computational complexity. However, if without properly coarsening, the hypergraph partitioning problem will become intractable along with the increase of the number of vertices. In this paper, we propose a coarsening algorithm in k-way hypergraph partitioning based on net clustering, where net clustering is used to obtain the initial set of vertices with higher internal similarity. Due to the property of nets connecting through vertices, the proposal can cluster the net by local search and discard unimportant vertices from net clusters to achieve high-quality solutions. The experimental results show that our proposal achieves a high quality of coarsening with lower complexity. Even as the number of partitions rises, the computation time reduction will obviously increase. In the case of setting the number of partitions as 8, our algorithm can achieve almost the same partitioning quality as traditional hMetis, but with a time consumption reduction of 50%.
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Jayakumar, Ganesh, Per-Erik Hellström, and Mikael Östling. "Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application." Micromachines 9, no. 11 (October 25, 2018): 544. http://dx.doi.org/10.3390/mi9110544.
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Silicon ribbons (SiRi) have been well-established as highly sensitive transducers for biosensing applications thanks to their high surface to volume ratio. However, selective and multiplexed detection of biomarkers remains a challenge. Further, very few attempts have been made to integrate SiRi with complementary-metal-oxide-semiconductor (CMOS) circuits to form a complete lab-on-chip (LOC). Integration of SiRi with CMOS will facilitate real time detection of the output signal and provide a compact small sized LOC. Here, we propose a novel pixel based SiRi device monolithically integrated with CMOS field-effect-transistors (FET) for real-time selective multiplexed detection. The SiRi pixels are fabricated on a silicon-on-insulator wafer using a top-down method. Each pixel houses a control FET, fluid-gate (FG) and SiRi sensor. The pixel is controlled by simultaneously applying frontgate (VG) and backgate voltage (VBG). The liquid potential can be monitored using the FG. We report the transfer characteristics (ID-VG) of N- and P-type SiRi pixels. Further, the ID-VG characteristics of the SiRis are studied at different VBG. The application of VBG to turn ON the SiRi modulates the subthreshold slope (SS) and threshold voltage (VTH) of the control FET. Particularly, N-type pixels cannot be turned OFF due to the control NFET operating in the strong inversion regime. This is due to large VBG (≥25 V) application to turn ON the SiRi sensor. Conversely, the P-type SiRi sensors do not require large VBG to switch ON. Thus, P-type pixels exhibit excellent ION/IOFF ≥ 106, SS of 70–80 mV/dec and VTH of 0.5 V. These promising results will empower the large-scale cost-efficient production of SiRi based LOC sensors.
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Li, Peng, Shite Zhu, Wei Xi, Changbao Xu, Dandan Zheng, and Kai Huang. "Triple-Threshold Path-Based Static Power-Optimization Methodology (TPSPOM) for Designing SOC Applications Using 28 nm MTCMOS Technology." Applied Sciences 13, no. 6 (March 8, 2023): 3471. http://dx.doi.org/10.3390/app13063471.
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The threshold voltage distribution technique is an effective way to reduce the static power consumption of integrated circuits. Several gate-level-based distribution algorithms have been proposed, but the optimization effect and run time still need further optimization when applied to very large-scale integration (VLSI) designs. This paper presents a triple-threshold path-based static power optimization methodology (TPSPOM) for low-power system-on-chip. This method obtains the path weights and cell weights from paths’ timing constraints and cells’ delay-to-power ratios, then uses them as indexes to distribute each cell to low-threshold voltage (LVT), standard-threshold voltage (SVT), or high-threshold voltage (HVT). The experimental results based on a 28 nm circuit containing 385,781 cells show that the TPSPOM method reduces static power consumption by 15.16% more than the critical-path aware power consumption optimization methodology (CAPCOM). At the same time, run time is reduced by 96.85%.
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Nagabushanam, M., Skandan Srikanth, Rushita Mupalla, Sushmitha S. Kumar, and Swathi K. "Optimization of Power and Area Using VLSI Implementation of MAC Unit Based on Additive Multiply Module." International Journal of Electrical and Electronics Research 10, no. 4 (December 30, 2022): 1099–106. http://dx.doi.org/10.37391/ijeer.100455.
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The development of Digital Signal Processors (DSPs), graphical systems, Field Programmable Gate Arrays (FPGAs)/ Application-Specific Integrated Circuits (ASICs), and multimedia systems all rely heavily on digital circuits. The need for high-precision fixed-point or floating-point multipliers suitable for Very Large-Scale Integration (VLSI) implementation in high-speed DSP applications is developing rapidly. An integral part of any digital system is the multiplier. In digital systems as well as signal processing, the adder and multiplier seem to be the fundamental arithmetic units. Problems arise when using a multiplier in the realms of area, power, complexity, and speed. This paper details a more efficient MAC (Multiply- Accumulate) multiplier that has been tuned for space usage. The proposed design is more efficient, takes up less room, and has lower latency than conventional designs. The performance of the Additive Multiply Module (AMM) multiplier is measured against that of existing multipliers, where it serves as a module in the MAC reducing area and delay.
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Nagarajan, Sridevi, and Prasanna Kumar Mahadeviah. "On-chip based power estimation for CMOS VLSI circuits using support vector machine." Indonesian Journal of Electrical Engineering and Computer Science 35, no. 2 (August 1, 2024): 804. http://dx.doi.org/10.11591/ijeecs.v35.i2.pp804-811.
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Power estimation has a major impact on the reliability of very-large-scale integration (VLSI) circuits. As a results power estimation is highly needed in VLSI circuits at the early stages. One of the evident challenges in integrated circuit (IC) industry is development and investigation of techniques for the reduction of design complexity due to the growing process variations and reduction of chip manufacturing turnaround time. Under these conditions, the higher design levels of average power estimation before the chip manufacturing process is highly essential for the calculation of power budget and to take the necessary steps for the reduction of power consumption. Over the years, most of the approaches were designed to estimate the power usage, however, most of the conventional techniques are time consuming, resource-intensive and largely manual. Machine learning techniques have received much attention in many of the engineering applications and are capable for modelling the complex systems through historical data. Hence, in this work on chip-based power estimation for complementary metal-oxide-semiconductor (CMOS) VLSI using support-vector machine (SVM) is presented to estimate the power. The SVM is employed to estimate the usage of power at runtime. The performance of this model is evaluated in terms of Power usage, delay, data accuracy and error rate.
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N., Alivelu Manga. "Design of High-Speed Low Power Computational Blocks for DSP Processors." Revista Gestão Inovação e Tecnologias 11, no. 2 (June 5, 2021): 1419–29. http://dx.doi.org/10.47059/revistageintec.v11i2.1768.
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In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary performance criteria for these signal processing operations are speed and power consumption. To lower the power consumption, there are techniques like Multi threshold (Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used which allows reduction in power, delay and area of digital circuits, while maintaining low complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder, Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The Simulation results shows that GDI based designs consume less power and delay also reduced compared to CMOS based designs.
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Zhu, Ziran, Zhipeng Huang, Jianli Chen, and Longkun Guo. "Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles." Complexity 2021 (April 14, 2021): 1–12. http://dx.doi.org/10.1155/2021/8843271.
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As one of the most important routing problems in the complex network within a very-large-scale integration (VLSI) circuit, bus routing has become much more challenging when witnessing the advanced technology node enters the deep nanometer era because all bus bits need to be routed with the same routing topology in the context. In particular, the nonuniform routing track configuration and obstacles bring the largest difficulty for maintaining the same topology for all bus bits. In this paper, we first present a track handling technique to unify the nonuniform routing track configuration with obstacles. Then, we formulate the topology-aware single bus routing as an unsplittable flow problem (UFP), which is integrated into a negotiation-based global routing to determine the desired routing regions for each bus. A topology-aware track assignment is also presented to allocate the tracks to each segment of buses under the guidance of the global routing result. Finally, a detailed routing scheme is proposed to connect the segments of each bus. We evaluate our routing result with the benchmark suite of the 2018 CAD Contest. Compared with the top-3 state-of-the-art methods, experimental results show that our proposed algorithm achieves the best overall score regarding specified time limitations.
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MOHANA KANNAN, LOGANATHAN, and DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION." DYNA 96, no. 5 (September 1, 2021): 505–11. http://dx.doi.org/10.6036/10214.
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Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit and image processing approach makes improved application availability. The design of high speed digital FIR filter is designed with various adders and multipliers. The incorporation of VLSI design and image processing techniques are used on biomedical imaging applications. The Enhanced FIR filter design utilized the hybrid adder and adaptive Vedic multiplier approaches for increasing the performance of VLSI part and the image processing results are taken from Matrix Laboratory tool. This proposed FIR filter design helps to perform the biomedical imaging techniques. The simulation result obtains the performance of enhanced FIR with area, delay and power; for biomedical imaging, Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) is obtained. Comparing with existing and proposed method, the proposed FIR filter for biomedical imaging application obtains the better result. Thus the design model states with various application availability of VLSI image processing approaches and it obtains the better performance results of both VLSI and image processing applications. Overall, the proposed system is designed by Xilinx ISE 14.5 and the synthesized result is done with ModelSim. Here the biomedical image performance is done by using MATLAB with the adaptation of 2018a. Keywords- Enhanced FIR filter; Adaptive vedic multiplier; Hybrid adder; Biomedical imaging; power delay product;
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Meher, Sukanya S., M. Eren Çelik, Jushya Ravi, Amol Inamdar, and Deepnarayan Gupta. "An Integrated Approach towards VLSI Implementation of SFQ Logic using Standard Cell Library and Commercial Tool Suite." Journal of Physics: Conference Series 2776, no. 1 (June 1, 2024): 012007. http://dx.doi.org/10.1088/1742-6596/2776/1/012007.
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Abstract The semiconductor industry seeks energy-efficient alternatives as Moore’s law nears its limits. The Single Flux Quantum (SFQ) integrated circuits (ICs) using thousands of niobium Josephson junctions (JJs) and operating at 4 K show great promise for digital computing circuits at high speed (>20 GHz) and low power (a few nW per junction). The leading logic families are Rapid Single Flux Quantum (RSFQ), and its energy-efficient variant (ERSFQ). IARPA’s SuperTools program aims to develop integrated design tools for superconductor electronics, targeting SFQ and Adiabatic Quantum-Flux-Parametron (AQFP) logic families. This paper presents a passive transmission line (PTL) based standard cell library for SFQ logic, designed with Synopsys Electronic Design Automation (EDA) software tools for MIT-LL 100μA/μm2 SFQ5ee fab node. The dual RSFQ/ERSFQ standard cell library facilitates seamless integration of SFQ RTL-to-GDS design flow with Synopsys Fusion Compiler, an automated design tool. The SFQ RTL-to-GDS flow entails logic synthesis, checking, placement, clock synthesis, and routing. Row-based placement for library cells and H-tree clock tree structures are employed. Fusion Compiler’s effectiveness is validated with Hypres designs such as finite impulse response (FIR) filters, scalable multiply-accumulate (MAC) units, and memory arrays, comparing single and dual clocking schemes. The synergy between Hypres and Synopsys achieves a milestone by demonstrating the design of a digital superconducting circuit with over 10 million JJs, facilitated by a fully automated design tool for the first time. Challenges in very large-scale SFQ scaling are also discussed.
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Cheng, Yi Lung, Yi Shiung Lu, and Tai Jung Chiu. "Comparative Study of Low Dielectric Constant Material Deposited Using Different Precursors." Advanced Materials Research 233-235 (May 2011): 2480–85. http://dx.doi.org/10.4028/www.scientific.net/amr.233-235.2480.
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Two kinds of organosilicate precursors, trimethylsilane (3MS) and diethoxymethylsilane (DEMS), were used to produce low-k films by plasma-enhanced chemical vapor deposition (PECVD) in this work. The experimental results indicate that DEMS-based low-k films have superior electrical performance and better thermal stability as compared to 3MS-based low-k films. Therefore, DEMS-based films are the promising low-k materials which can be integrated in very large scale integration circuit as an inter-layer dielectric material.
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Dharanika, T., J. Jaya, and E. Nandakumar. "Design of Fostered Power Terahertz VLSI Testing Using Deep Neural Network and Embrace User Intent Optimization." Journal of Nanoelectronics and Optoelectronics 19, no. 7 (July 1, 2024): 724–36. http://dx.doi.org/10.1166/jno.2024.3619.
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VLSI (Very Large-Scale Integration) testing is a crucial step in ensuring the reliability and functionality of integrated circuits. However, conventional testing methods often lack the ability to address user-specific requirements, resulting in suboptimal outcomes. Terahertz technology offers unique capabilities for non-destructive testing, yet its integration with VLSI testing methodologies remains limited. Additionally, the neglect of user preferences in testing processes poses a challenge to tailoring testing procedures to specific user needs. This research presents a novel approach for fostered power terahertz VLSI testing, integrating deep neural networks (DNNs) and user intent optimization principles. The proposed framework comprises three main components: terahertz signal processing, deep neural network-based feature extraction, and user intent optimization. Terahertz signals are analyzed using deep neural networks trained on labeled datasets, while user intent optimization algorithms dynamically adjust testing parameters based on user feedback. Comparative analysis with traditional testing methods reveals superior testing coverage and accuracy achieved through the integration of Terahertz Technology (TZT), deep neural networks, and user intent optimization. Our approach demonstrated a significant improvement in reliability, with values ranging from 92.5% to 95.8%, depending on the specific testing scenario and dataset used for evaluation. The accuracy achieved by our methodology surpassed existing technologies by a substantial margin. Across various experiments, accuracy values ranged from 87.3% to 91.6%, indicating a consistent improvement over baseline methods.
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Ahmad, Afaq, Sabir Hussain, M. A. Raheem, Ahmed Al Maashri, Sayyid Samir Al Busaidi, and Medhat Awadalla. "ASIC vs FPGA based Implementations of Built-In Self-Test." International Journal of Advanced Natural Sciences and Engineering Researches 7, no. 6 (July 13, 2023): 14–20. http://dx.doi.org/10.59287/ijanser.942.
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Linear Feedback Shift Registers (LFSRs) are play key role in testing of for Very Large Scale Integration (VLSI) Integrated Circuits (ICs) testing. Due to tremendous IC complex growth, testing of recent VLSI ICs technology have become more complicated. This led to develop a popular alternate viable solution in the form of Built-In Self-Test (BIST) technology as compared to Automatic Test Equipment (ATE). However, the challenges of BIST technology remain the subject of research. Furthermore, implementation of BIST’s LFSR on Application Specific Integrated Circuit (ASIC) versus Field Programmable Gate Array on (FPGA) platform is current area of research especially in context to power consumption. Hence, to make an informed choice between ASIC and FPGA for implementing BIST’s LFSR we focus on study of design of reconfigurable LFSR on ASIC versus FPGA platform. The Electronic Design Automation (EDA) tool, Cadence is used for implementing BIST’s LFSR on ASIC platform. Whereas, Hardware Description Language (HDL), Verilog is used to implement BIST’s LFSR on FPGA platform. During experimental methodology, maximum frequency, the critical path delay is investigated to assess the power dissipation. The functional and timing simulation models are used to verify the implemented reconfigurable BIST’s LFSR designs. The obtained results show that the performance, in terms of speed and power, of ASIC implementation is far better than traditional FPGA implementation.
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Rasheed, Israa Mohammed, and Hassan Jasim Motlak. "Performance parameters optimization of CMOS analog signal processing circuits based on smart algorithms." Bulletin of Electrical Engineering and Informatics 12, no. 1 (February 1, 2023): 149–57. http://dx.doi.org/10.11591/eei.v12i1.4128.
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Designing ideal analogue circuits has become difficult due to extremely large-scale integration. The complementary metal oxide semiconductor (CMOS) analog integrated circuits (IC) could use an evolutionary method to figure out the size of each device. The CMOS operational transconductance amplifier (CMOS OTA) and the CMOS current conveyor second generation (CMOS CCII) are designed using advanced nanometer transistor technology (180 nm). Both CMOS OTA and CMOS CCII have high performance, such as a wide frequency, voltage gain, slew rate, and phase margin, to include very wide applications in signal processing, such as active filters and oscillators. The optimization approach is an iterative procedure that uses an optimization algorithm to change design variables until the optimal solution is identified. In this study, different sorts of algorithms the genetic algorithm (GA), particle swarm optimization (PSO), and cuckoo search (CS) are employed to boost and enhance the performance parameters. While decreasing the time required to develop a conventional operation amplifier's settling time. Some studies decrease the value of the power utilized at various frequencies. Others operate at extremely high frequencies, but their power consumption is greater than that of those operating at lower frequencies.
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NIRANJAN, VANDANA, ASHWANI KUMAR, and SHAIL BALA JAIN. "COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS." Journal of Circuits, Systems and Computers 23, no. 08 (June 18, 2014): 1450108. http://dx.doi.org/10.1142/s0218126614501084.
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In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.
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Sun, Ben. "Interpretable machine learning in VLSI physical design." Applied and Computational Engineering 4, no. 1 (June 14, 2023): 13–19. http://dx.doi.org/10.54254/2755-2721/4/20230338.
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Today's popularisation of portable devices largely depends on the progress in integrated circuits. Modern Very Large Scale Integration technology (VLSI) allows billions of transistors to be packed into the same chip. In the past years, digital design in VLSI has been developed compared to analogue design. The traditional method is hard to model the performance change in analogue or mixed-signal components caused by physical design. In the early 2000s, rapid advances in machine learning and computing power made analogue design automation possible. Despite their outstanding performance, the transparency issue has become significant. This paper introduces the history of VLSI physical design, which includes placement and routing in the early stages. The change that machine learning (ML) has made is mentioned in the third section. Analysis of the potential problem has been proposed, followed by a brief category of some well-known work in interpretable Machine Learning, which could be the primary direction for VLSI automation to be further popularised in the future.
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Eppili, Jaya, Sri B. Sai, Kumar P. Akshay, Kumar O. Hem, D. Sunil, and R. Rajesh. "VLSI implementation of Kogge-Stone Adder for low-power applications." i-manager's Journal on Digital Signal Processing 11, no. 1 (2023): 9. http://dx.doi.org/10.26634/jdp.11.1.19372.
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The adder is a vital part of the Central Processing Unit (CPU) that can perform computational operations. It is used in digital components, mainly in the design of integrated circuits. Recent decades have seen a sharp rise in demand for mobile electronics, which has increased the need for highly efficient Very Large-Scale Integration (VLSI) structures. All operations must be computed using low-power, space-efficient designs that run faster. The Kogge-Stone adder (KSA) is an extension of the carry look-ahead adder which is used for performing fast addition in high-performance computing systems. This study compares the latency, space, and energy used by the Kogge-Stone Adder after development and implementation in Xilinx Vivado using Verilog to those of the Ripple Carry Adder (RCA) and Carry Lookahead Adder (CLA). The results show that the KSA has a decrease in power consumption as well as improvements in high speed and area compaction when compared to the RCA and CLA.
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Soref, Richard. "Applications of Silicon-Based Optoelectronics." MRS Bulletin 23, no. 4 (April 1998): 20–24. http://dx.doi.org/10.1557/s0883769400030220.
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Silicon-based optoelectronics is a diversified technology that has grown steadily but not exponentially over the past decade. Some applications—such as smart-pixel signal processing and chip-to-chip optical interconnects—have enjoyed impressive growth, whereas other applications have remained quiescent. A few important applications such as optical diagnosis of leaky metal-oxide-semiconductor-field-effect-transistor circuits, have appeared suddenly. Over the years, research and development has unveiled some unique and significant aspects of Si-based optoelectronics. The main limitation of this technology is the lack of practical silicon light sources—Si lasers and efficient Si light-emitting devices (LEDs)—though investigators are “getting close” to the LED.Silicon-based optoelectronics refers to the integration of photonic and electronic components on a Si chip or wafer. The photonics adds value to the electronics, and the electronics offers low-cost mass-production benefits. The electronics includes complementary-metal-oxide semiconductors (CMOS), very large-scale integration (VLSI), bipolar CMOS, SiGe/Si heterojunction bipolar transistors, and heterostructure field-effect transistors. In this discussion, we will use a loose definition of optoelectronics that includes photonic and optoelectronic integrated circuits (PICs and OEICs), Si optical benches, and micro-optoelectromechanical (MOEM) platforms. Optoelectronic chips and platforms are subsystems of computer systems, communication networks, etc. Silicon substrates feature a superior native oxide, in addition to excellent thermal, mechanical, and economic properties. Silicon wafers “shine” as substrates for PICs and OEICs.
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Yadav, Vishal, and Brij Bihari Tiwari. "Design and analysis of low power sense amplifier for static random access memory." Indonesian Journal of Electrical Engineering and Computer Science 35, no. 3 (September 1, 2024): 1447. http://dx.doi.org/10.11591/ijeecs.v35.i3.pp1447-1455.
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<p>Today’s era is a digital world where each and every section of the society is experiencing and encountering with semiconductor chips. In very large-scale integration (VLSI) circuits the design of static random-access memory (SRAM) plays a crucial role in ensuring both low-power consumption and high-speed performance. The sense amplifiers (SA) are integral parts for information accessing storage in SRAM IC design. This paper introduces a dual voltage latch sense amplifier (DVLSA) for SRAM integrated circuits (IC). The comparative analyses of various SA are studied and then design a low-power SA through the implementation of energy-efficient technique. Further, we have elucidated the causes of delay and power dissipation in different SA with useful solutions and performance evaluation is conducted by comparing the proposed design with existing SA reported in the literature. The performance parameters such as power 1.604 uw, energy 470.50 fJ, delay 80.04 ps, and current 5.406 are scrutinized to assess the efficiency of the designs. The cell outcomes have been validated with cadence tool on 180 nm technology and operate at 1.8 V. The proposed design, namely, DVLSA demonstrates minimal energy consumption and low power dissipation, making it a promising advancement in SRAM IC technology.</p>
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Shanavas, I. Hameem, and R. K. Gnanamurthy. "Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm." Mathematical Problems in Engineering 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/809642.
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In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.
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NAKADA, KAZUKI, TETSUYA ASAI, and HATSUO HAYASHI. "ANALOG VLSI IMPLEMENTATION OF RESONATE-AND-FIRE NEURON." International Journal of Neural Systems 16, no. 06 (December 2006): 445–56. http://dx.doi.org/10.1142/s0129065706000846.
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We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.
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Akita, Junichi. "Open-source, multi-layer LSI design & fabrication framework for distributed IP development and education." International Journal of Innovative Research and Scientific Studies 6, no. 4 (September 22, 2023): 936–45. http://dx.doi.org/10.53894/ijirss.v6i4.2102.
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Continuous development of Large Scale Integration (LSI) technologies based on Moore's law results in highly developed LSI technologies, as well as very high costs in design and fabrication and high design complexity. This fact prevents various users from contributing to the activities of designing LSIs, fabricating LSIs, and developing Intellectual Properties (IPs). On the other hand, the trend towards open-source has been attracting attention to overcome these problems and extend the potential of LSI technologies. The purpose of this research is to develop an open-source LSI design framework aimed at connecting various layers of LSI knowledge. Its methodology is composed of two parts. One is the development of the LSI design flow using existing open-source EDA tools and their related glue software. The other is the open-source, NDA-free PDK (process design kit) used in designing LSIs. The process of developing and constructing Large Scale Integrated (LSI) circuits within this framework is conducted and assessed. From these trials, the effect of enhancing educational effectiveness on LSI design is indicated. These trials enhanced the contributors’ interest and motivation to understand the details of computer systems and their relation to LSIs. It is also indicated that this framework is effective in enhancing rapid IP development as well as its importance as an educational aspect of open-source software.
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Sanadhya, Minakshi, Devendra Kumar Sharma, and Alfilh Raed Hameed Chyad. "Adiabatic technique based low power synchronous counter design." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 4 (August 1, 2023): 3770. http://dx.doi.org/10.11591/ijece.v13i4.pp3770-3777.
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<p>The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in synchronous counters, and its high-power consumption impacts the overall effectiveness of the system. This paper calculates the power dissipation (PD), power delay product (PDP), and latency of the presented T flip-flop. To create a 2-bit synchronous counter based on the novel T flip-flops, a performance matrix such as PD, latency, and PDP is analyzed. The analysis is carried out at 100 and 10 MHz frequencies with varying temperatures and operating voltages. It is observed that the presented counter design has a lesser power requirement and PDP compared to the existing counter architectures. The proposed T-flip-flop design at the 45 nm technology node shows an improvement of 30%, 76%, and 85% in latency, PD, and PDP respectively to the 180 nm node at 10 MHz frequency. Similarly, the proposed counter at the 45 nm technology node shows 96% and 97% improvement in power dissipation, delay, and PDP respectively compared to the 180 nm at 10 MHz frequency.</p>
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Huang, Chen‐Wei, Shing‐Kwong Wong, Yi‐Xiang Gao, and Xin Wang. "13‐1: A Lightweight Inference Network‐based Algorithm for Low‐Light Image Brightness Adjustment." SID Symposium Digest of Technical Papers 55, S1 (April 2024): 121–24. http://dx.doi.org/10.1002/sdtp.17014.
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Low‐light images pose a challenge due to their compressed dynamic range, often resulting in loss of detail. To address this, enhancement techniques are evolving, aiming to better represent these images on modern displays. In this paper, we propose a novel algorithm that utilizes two cascaded neural networks to adjust image illumination effectively. Our approach begins with the first architecture, which employs 2D separable convolutional layers, ReLU, and sigmoid functions to extract essential features from RGB images. Subsequently, the second architecture, a U‐ shaped network, hierarchically adjusts image illumination, particularly in low‐light conditions. A significant contribution of our method lies in its ability to process low‐illumination images efficiently using a simpler, lightweight neural network architecture. This characteristic is crucial for its implementation in application‐specific integrated circuits for edge devices, as it reduces the number of trainable parameters, thus facilitating integer inference. We validate our approach using the widely used LOw‐Light (LOL) dataset, containing 500 pairs of low‐light and normal‐light images. Through experimentation, we demonstrate the efficacy of our method in adjusting brightness. Furthermore, we discuss the feasibility of hardware implementation, particularly emphasizing the suitability for designing very large‐ scale integration circuits on System‐on‐Chip (SOC) platforms. This is made possible by leveraging integer‐based matrix operations and implementing appropriate data rounding techniques to handle overflow computations effectively.
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Yu, Shenglu, Shimin Du, and Chang Yang. "A Deep Reinforcement Learning Floorplanning Algorithm Based on Sequence Pairs." Applied Sciences 14, no. 7 (March 29, 2024): 2905. http://dx.doi.org/10.3390/app14072905.
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In integrated circuit (IC) design, floorplanning is an important stage in obtaining the floorplan of the circuit to be designed. Floorplanning determines the performance, size, yield, and reliability of very large-scale integration circuit (VLSI) ICs. The results obtained in this step are necessary for the subsequent continuous processes of chip design. From a computational perspective, VLSI floorplanning is an NP-hard problem, making it difficult to be efficiently solved by classical optimization techniques. In this paper, we propose a deep reinforcement learning floorplanning algorithm based on sequence pairs (SP) to address the placement problem. Reinforcement learning utilizes an agent to explore the search space in sequence pairs to find the optimal solution. Experimental results on the international standard test circuit benchmarks, MCNC and GSRC, demonstrate that the proposed deep reinforcement learning floorplanning algorithm based on sequence pairs can produce a superior solution.
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Fujino, Masahisa, Yuuki Araga, Hiroshi Nakagawa, Katsuya Kikuchi, and Noboru Miyata. "(Invited) Direct Bonding and Its Interface for High-Density Integration of Superconducting Qubits." ECS Meeting Abstracts MA2023-02, no. 33 (December 22, 2023): 1620. http://dx.doi.org/10.1149/ma2023-02331620mtgabs.
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Superconducting qubits are one of the intensive approaches to fabricate quantum computing (QC). Qubits can be manufactured by the current Si-based semiconductor manufacturing processes. However, circuits should be superconducting material such as Nb (Tc=9.29 K), Al (Tc=1.18 K), Pb (Tc=7.2 K), In (Tc=3.4 K) , etc. In current technology, qubits are arranged in planar geometry in a chip, and each qubit should wire to control and read signal lines in the same plane. When a large number of qubits are integrated, these wires would be too constrained, and several problems would be actualized, such as wiring for qubits located at the chip center, crosstalk among wiring, and so on. The signal integrity for the QC devices is much better to have qubits at short distances from the control circuitry. Therefore, 3D wiring is required for a large-scale qubit integration. 3D integration of qubits with interposer chips by flip-chip bonding is the proof-of-concept of the large-scale qubit integration. The 3D integration approaches for qubit- based devices are the same as conventional electronic devices, including the through silicon via (TSV) process for interposers and micro bump flip-chip bonding. However, they use superconducting metals instead of copper and other non-superconducting materials. Most flip-chip microbump bonding processes require thermal compression at over 170 °C. Superconducting elements are easily degraded by heat. Consequently, we apply surface activated bonding (SAB) to a superconducting metal as a low-temperature bonding process for superconducting circuits. The test element group (TEG) for the current-voltage (I-V) measurement of the bonded interface was bonded by SAB method, and at the Nb SAB interface layer is a 2- to 3-nm-thick amorphous layer and the layer consist of Si-rich interfacial layer compared to the Nb bulk area. The bonding specimens were activated on jigs made of Si during the bonding process; then the Si sputtered by FAB was redeposited on the bonding surfaces. Furthermore, the bonded specimen was wired using Al wire to a chip carrier with a stage installed into a 0.3-K cryostat. As a result, the Tc of this path is 9.3 K, which is very similar to that of Nb bulk (9.2 K). However, a small step of the Tc at 9.1-9.4 K was also observed. (Fig.1) [1] In this study, we discuss the superconducting interface of direct bonded Nb-Nb by Tc, and also the interfacial structure measured by polarized neutron reflectometry (PNR). The results show clear spin asymmetry in the superconducting state, as splitting is observed in the fringes of the parallel neutron (neutron spins parallel to the external magnetic field 0.1 T) reflection R+ and the antiparallel (neutron spins antiparallel to it) reflection R−, where the latter has become larger. This well-known effect is related to the flux penetration in the superconducting state. Therefore, unique information about the superconducting state of the buried thin film can be measured by using the polarized neutron beam. For this project the major advantage of PNR will be to characterize the superconducting state at the deeply buried Nb interfaces, sandwiched between the two substrate wafers, which would be infeasible using alternate techniques. [1] M. Fujino, et. al., J. Appl. Phys., 133, 015301, 2023 Figure 1
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Kumar, Umesh. "Vlsi Interconnection Modelling Using a Finite Element Approach." Active and Passive Electronic Components 18, no. 3 (1995): 179–202. http://dx.doi.org/10.1155/1995/97362.
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In the last decade, an important shift has taken place in the design of hardware with the advent of smaller and denser integrated circuit packages. Analysis techniques are required to ensure the proper electrical functioning of this hardware. An efficient method is presented to model the parasitic capacitance of VLSI (very large scale integration) interconnections. It is valid for conductors in a stratified medium, which is considered to be a good approximation for theSi−SiO2system of which present day ICs are made. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a “spider” of edges. Here the method used [1] has very low complexity, as compared to other models used previously [2], and achieves a high degree of precision within the range of validity of the stratified medium.
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Balodi, Deepak, and Rahul Misra. "Low Power Differential and Ring Voltage Controlled Oscillator Architectures for High Frequency (L-Band) Phase Lock Loop Applications in 0.35 Complementary Metal Oxide Semi Conductor Process." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 11, no. 01 (July 25, 2019): 63–70. http://dx.doi.org/10.18090/samriddhi.v11i01.9.
Full textAbstract:
The design of a high frequency (L Band), low power (2.75mW) Phase Lock Loops with a 350nm Complementary Metal Oxide Semi Conductor (CMOS) technology has been represented. The comparison of Current Starved Voltage Controlled Oscillator (CSVCO) and Differential pair VCO is performed and analyzed for low power and high frequency analysis respectively. Each component of Phase Lock Loop (PLL) is designed with 350nm CMOS technology in Design Architect Integrated Circuit Station by Mentor Graphics (Eldo-Net) as simulator. In this paper both the standard configurations have been simulated under the same environment and results are analyzed for two most important Very Large Scale Integration (VLSI)constraints, Speed (High frequency range) and Power consumption. The high speed and locking performance of the Differential pair VCO has been evaluated against the lower power consumption benefit of CSVCO.
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Yeh, Chung-Huang, and Jwu-E. Chen. "Unbalanced-Tests to the Improvement of Yield and Quality." Electronics 10, no. 23 (December 4, 2021): 3032. http://dx.doi.org/10.3390/electronics10233032.
Full textAbstract:
An integrated-circuit testing model (DITM) is used to describe various factors that affect test yield during a test process. We used a probability distribution model to evaluate test yield and quality and introduced a threshold test and a guardband test. As a result of the development speed of the semiconductor manufacturing industry in the future being unpredictable, we use electrical properties of existing products and the current manufacturing technology to estimate future product-distribution trends. In the development of very-large-scale integration (VLSI) testing, the progress of testing technology is very slow. To improve product testing yield and quality, we change the test method and propose an unbalanced-test method, leading to improvements in test results. The calculation using our proposed model and data estimated by the product published by the IEEE International Roadmap for Devices and Systems (IRDS, 2017) proves that the proposed unbalanced-test method can greatly improve test yield and quality and achieve the goal of high-quality, near-zero-defect products.
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Laudis, Lalin L., and N. Ramadass. "A Lion’s Pride Inspired Algorithm for VLSI Floorplanning." Journal of Circuits, Systems and Computers 29, no. 01 (March 15, 2019): 2050003. http://dx.doi.org/10.1142/s0218126620500036.
Full textAbstract:
The complexity of any integrated circuit pushes the researchers to optimize the various parameters in the design process. Usually, the Nondeterministic Polynomial problems in the design process of Very Large Scale Integration (VLSI) are considered as a Single Objective Optimization Problem (SOOP). However, due to the increasing demand for the multi-criterion optimization, researchers delve up on Multi-Objective Optimization methodologies to solve a problem with multiple objectives. Moreover, it is evident from the literature that biologically inspired algorithm works very well in optimizing a Multi-Objective Optimization Problem (MOOP). This paper proposes a new Lion’s pride inspired algorithm to solve any MOOP. The methodologies mimic the traits of a Lion which always strives to become the Pride Lion. The Algorithm was tested with VLSI floorplanning problem wherein the area and dead space are the objectives. The algorithm was also tested with several standard test problems. The tabulated results justify the ruggedness of the proposed algorithm in solving any MOOP.
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Smy, T., S. K. Dew, and M. J. Brett. "Simulation of Microstructure and Surface Profiles of Thin Films for VLSI Metallization." MRS Bulletin 20, no. 11 (November 1995): 65–69. http://dx.doi.org/10.1557/s0883769400045619.
Full textAbstract:
A crucial step in the manufacture of very large-scale integration (VLSI) integrated circuits is the fabrication of reliable, low-resistance metal interconnects between semiconductor devices. The fabrication of these interconnects is generally performed by depositing a blanket metal film and then patterning it by lithographic and etching techniques. The primary means of depositing thin metal films for VLSI interconnects are sputtering and chemical vapor deposition (CVD).The creation of reliable interconnects is, however, complicated by a number of issues. In order to obtain low contact resistance, to inhibit reactions with the silicon, and to provide good adhesion to both Si and SiO2, contact, barrier, and adhesion layers are generally deposited prior to the deposition of the low-resistance metal film that forms the bulk of the interconnect. If these layers are to provide an effective barrier to diffusion of the interconnection metal to the silicon, they must be deposited in a uniform, homogeneous form. It is also necessary that the primary interconnect material have as high step coverage as is possible in order to reduce current crowding, local heating effects, and electromigration. Unfortunately, as VLSI circuit densities have increased, the fabrication of interconnects requires high aspect-ratio contact cuts, and relatively severe local topographies can result. These factors make it difficult to deposit films with good step and bottom coverage.In addition to these concerns with the film surface profile, another factor is becoming increasingly significant. Both sputtering and CVD produce thin films with characteristic microstructures. This microstructure consists of columns or grains separated by grain boundaries and voids.