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1
Ivanov, André. "Dynamic testibility measures and their use in ATPG." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63324.
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Draier, Benny. "Test vector generation and compaction for easily testable PLAs." Thesis, McGill University, 1988. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63970.
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Kim, Kwanghyun. "An expert system for self-testable hardware design." Diss., Virginia Polytechnic Institute and State University, 1989. http://hdl.handle.net/10919/54216.
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BIDES (A BIST Design Expert System) is an expert system for incorporating BIST into a digital circuit described with VHDL. BIDES modifies a circuit to produce a self-testable circuit by inserting BIST hardware such as pseudorandom pattern generators and signature analysis registers. In inserting BIST hardware, BIDES not only makes a circuit self-testable, but also incorporates the appropriate type of BIST structure so that a set of user-specified constraints on hardware overhead and testing time can be satisfied. This flexibility comes from the formulation of the BIST design problem as a search problem. A satisfactory BIST structure is explored through an iterative process of evaluation and regeneration of BIST structure. The process of regeneration is performed by a problem solving technique called hierarchical planning. In order to apply a hierarchical planning technique, we introduce an abstraction hierarchy in BIST design. Using the abstraction hierarchy, the knowledge of the BIST design process is represented with several operators defined on the abstraction levels. This type of knowledge representation in conjunction with hierarchical planning led to an easy implementation of the system and results in an easily modifiable system.
In this dissertation, we also study a BIST scheme called cascade testing. ln cascade testing, a signature analysis register is used concurrently as a test pattern generator in order to reduce the overall testing time by improving testing parallelism. The characteristics of the patterns generated by the signature analysis register are investigated through analysis as well as experiments. lt is shown that the patterns generated by signature analysis registers are rarely repeated when the number of patterns generated is relatively small compared to the number of all possible patterns. It is also shown that the patterns generated by signature analysis registers are almost random. Therefore, signature analysis registers can be used effectively as pseudorandom pattern generators. The practicality of cascade testing is investigated by fault simulation experiments using an example circuit.Ph. D.
4
Panda, Uma R. "An efficient single-latch scan-design scheme/." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63266.
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Venkatesan, Raguraman. "Multilevel interconnect architectures for gigascale integration (GSI)." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/13370.
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Chen, Ing-yi 1962. "Efficient reconfiguration by degradation in defect-tolerant VLSI arrays." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277195.
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This thesis addresses the problem of constructing a flawless subarray from a defective VLSI/WSI array consists of identical cells such as memory cells or processors. In contrast to the redundancy approach in which some cells are dedicated as spares, all the cells in the degradation approach are treated in a uniform way. Each cell can be either fault-free or defective and a subarray which contains no faulty cell is derived under constraints of switching and routing mechanisms. Although extensive literatures exist concerning spare allocation and reconfiguration in arrays with redundancy, little research has been published on optimal reconfiguration in a degradable array. A systematic method based on graph theoretic models is developed to deal with the problem. The complexities of reconfiguration are analyzed for schemes using different switching mechanisms. Efficient heuristic algorithms are presented to determine a target subarray from the defective host array.
7
高雲龍 and Wan-lung Ko. "A new optimization model for VLSI placement." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1998. http://hub.hku.hk/bib/B29812938.
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Bishop, Gregory Raymond H. ""On stochastic modelling of very large scale integrated circuits : an investigation into the timing behaviour of microelectronic systems" /." Title page, contents and abstract only, 1993. http://web4.library.adelaide.edu.au/theses/09PH/09phb6222.pdf.
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Whipple, Thomas Driggs 1961. "Design and implementation of an integrated VLSI packaging support software environment." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277105.
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An interactive software shell has been developed which integrates several packaging simulation tools developed at the University of Arizona which are used to analyze electro-magnetic coupling between interconnects in an integrated circuit. This software shell uses experimental frames to manage this simulation process. Through the experimental frames, the model descriptions and the model inputs are separated, and input data is verified for correctness. This model/input separation allows several model variations to be tested based on several input variations. The results of these simulations are then analyzed and displayed graphically. Further work for the software shell is discussed. This tool provides a user-friendly, efficient method for performing coupled-line analyses in interconnect systems.
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Haddadin, Baker. "Time domain space mapping optimization of digital interconnect circuits." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=116004.
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Microwave circuit design including the design of Interconnect circuits are proving to be a very hard and complex process where the use of CAD tools is becoming more essential to the reduction in design time and in providing more accurate results. Space mapping methods, the relatively new and very efficient way of optimization which are used in microwave filters and structures will be investigated in this thesis and applied to the time domain optimization of digital interconnects. The main advantage is that the optimization is driven using simpler models called coarse models that would approximate the more complex fine model of the real system, which provide a better insight to the problem and at the same time reduce the optimization time. The results are always mapped back to the real system and a relation/mapping is found between both systems which would help the convergence time. In this thesis, we study the optimization of interconnects where we build certain practical error functions to evaluate performance in the time domain. The space mapping method is formulated to avoid problems found in the original formulation where we apply some necessary modifications to the Trust Region Aggressive Space Mapping TRASM for it to be applicable to the design process in time domain. This new method modified TRASM or MTRASM is then evaluated and tested on multiple circuits with different configuration and the results are compared to the results obtained from TRASM.
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Boudreault, Yves 1959. "Design of a VLSI convolver for a robot vision system." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=65342.
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袁志勤 and Chi-kan Yuen. "A double-track greedy algorithm for VLSI channel routing." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1997. http://hub.hku.hk/bib/B31220241.
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Dickinson, Alex. "Complexity management and modelling of VLSI systems." Title page, contents and abstract only, 1988. http://web4.library.adelaide.edu.au/theses/09PH/09phd553.pdf.
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Kim, Kwanghyun. "An interactive design rule checker for integrated circuit layout." Thesis, Virginia Polytechnic Institute and State University, 1985. http://hdl.handle.net/10919/50034.
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An implementation of an interactive design rule checker is described in this thesis. Corner-based design rule checking algorithm is used for the implementation. Due to the locality of checking mechanism of the corner-based algorithm, it is suitable for hierarchical and interactive local design rule checking. It also allows the various design rules to be specified very easily.
Interactive operations are devised so that the design rule checker can be invoked from inside the layout editor. All the information about the violation, such as position, type of violation, and symbol definition name are provided in an interactive manner. In order to give full freedom to the user to choose the scope of checking, three options, "Flattening", "Unflattening" and "User-defined window" are implemented in creating the database to be checked. The "User-defined window" option allows hierarchical design rule checking on a design which contains global rectangles. Using these three options, very efficient hierarchical checking can be performed.Master of Science
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Morton, Shannon V. "Fast asynchronous VSLI circuit design techniques and their application to microprocessor design /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09phm891.pdf.
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Bagchi, Tanuj. "An Efficient Hybrid Heuristic and Probabilistic Model for the Gate Matrix Layout Problem in VLSI Design." Thesis, University of North Texas, 1993. https://digital.library.unt.edu/ark:/67531/metadc500878/.
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In this thesis, the gate matrix layout problem in VLSI design is considered where the goal is to minimize the number of tracks required to layout a given circuit and a taxonomy of approaches to its solution is presented. An efficient hybrid heuristic is also proposed for this combinatorial optimization problem, which is based on the combination of probabilistic hill-climbing technique and greedy method. This heuristic is tested experimentally with respect to four existing algorithms. As test cases, five benchmark problems from the literature as well as randomly generated problem instances are considered. The experimental results show that the proposed hybrid algorithm, on the average, performs better than other heuristics in terms of the required computation time and/or the quality of solution. Due to the computation-intensive nature of the problem, an exact solution within reasonable time limits is impossible. So, it is difficult to judge the effectiveness of any heuristic in terms of the quality of solution (number of tracks required). A probabilistic model of the gate matrix layout problem that computes the expected number of tracks from the given input parameters, is useful to this respect. Such a probabilistic model is proposed in this thesis, and its performance is experimentally evaluated.
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Park, Hoon. "Formal Modeling and Verification of Delay-Insensitive Circuits." PDXScholar, 2015. https://pdxscholar.library.pdx.edu/open_access_etds/2639.
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Einstein's relativity theory tells us that the notion of simultaneity can only be approximated for events distributed over space. As a result, the use of asynchronous techniques is unavoidable in systems larger than a certain physical size. Traditional design techniques that use global clocks face this barrier of scale already within the space of a modern microprocessor chip. The most common response by the chip industry for overcoming this barrier is to use Globally Asynchronous Locally Synchronous (GALS) design techniques. The circuits investigated in this thesis can be viewed as examples of GALS design. To make such designs trustworthy it is necessary to model formally the relative signal delays and timing requirements that make these designs work correctly. With trustworthy asynchrony one can build reliable, large, and scalable systems, and exploit the lower power and higher speed features of asynchrony.
This research presents ARCtimer, a framework for modeling, generating, verifying, and enforcing timing constraints for individual self-timed handshake components that use bounded-bundled-data handshake protocols. The constraints guarantee that the component's gate-level circuit implementation obeys the component's handshake protocol specification. Because the handshake protocols are delay insensitive, self-timed systems built using ARCtimer-verified components can be made delay insensitive. Any delay sensitivity inside a component is detected and repaired by ARCtimer. In short: by carefully considering time locally, we can ignore time globally.
ARCtimer applies early in the design process as part of building a library of verified components for later system use. The library also stores static timing analysis (STA) code to validate and enforce the component's constraints in any self-timed system built using the library. The library descriptions of a handshake component's circuit, protocol, timing constraints, and STA code are robust to circuit modifications applied later in the design process by technology mapping or layout tools.
New contributions of ARCtimer include:
1. Upfront modeling on a component by component basis to reduce the validation effort required to
(a) reimplement components in different technologies,
(b) assemble components into systems, and
(c) guarantee system-level timing closure.
2. Modeling of bounded-bundled-data timing constraints that permit the control signals to lead or lag behind data signals to optimize system timing.
18
Moon, Gyo Sik. "An Algorithm for the PLA Equivalence Problem." Thesis, University of North Texas, 1995. https://digital.library.unt.edu/ark:/67531/metadc278922/.
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The Programmable Logic Array (PLA) has been widely used in the design of VLSI circuits and systems because of its regularity, flexibility, and simplicity. The equivalence problem is typically to verify that the final description of a circuit is functionally equivalent to its initial description. Verifying the functional equivalence of two descriptions is equivalent to proving their logical equivalence. This problem of pure logic is essential to circuit design. The most widely used technique to solve the problem is based on Binary Decision Diagram or BDD, proposed by Bryant in 1986. Unfortunately, BDD requires too much time and space to represent moderately large circuits for equivalence testing. We design and implement a new algorithm called the Cover-Merge Algorithm for the equivalence problem based on a divide-and-conquer strategy using the concept of cover and a derivational method. We prove that the algorithm is sound and complete. Because of the NP-completeness of the problem, we emphasize simplifications to reduce the search space or to avoid redundant computations. Simplification techniques are incorporated into the algorithm as an essential part to speed up the the derivation process. Two different sets of heuristics are developed for two opposite goals: one for the proof of equivalence and the other for its disproof. Experiments on a large scale of data have shown that big speed-ups can be achieved by prioritizing the heuristics and by choosing the most favorable one at each iteration of the Algorithm. Results are compared with those for BDD on standard benchmark problems as well as on random PLAs to perform an unbiased way of testing algorithms. It has been shown that the Cover-Merge Algorithm outperforms BDD in nearly all problem instances in terms of time and space. The algorithm has demonstrated fairly stabilized and practical performances especially for big PLAs under a wide range of conditions, while BDD shows poor performance because of its memory greedy representation scheme without adequate simplification.
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Nain, Rajeev Kumar. "Floorplan Design and Yield Enhancement of 3-D Integrated Circuits." PDXScholar, 2011. https://pdxscholar.library.pdx.edu/open_access_etds/2810.
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We have developed a placement-aware 3-D floorplanning algorithm that enables additional wirelength reduction by planning for 3-D placement of logic gates in selected circuit modules during the floorplanning stage. Thus it also bridges the existing gap between 3-D floorplanning and 3-D placement. To reduce the solution space of 3-D floorplanning which is known to be an NP-hard problem, we derive a set of feasibility conditions on the topological representation of a floorplan. In addition, we have designed a fast module packing algorithm that satisfies a set of constraints for placement-aware 3-D floorplanning. Furthermore, we have designed an efficient evolutionary algorithm that is used in the proposed 3-D floorplanning algorithm for multi-objective combinatorial optimization. Our results show that the proposed placement-aware 3-D floorplanning algorithm is very fast, and it reduces the system level total wirelength by 9.8% compared to existing state-of-the-art floorplanning tools that do not plan for 3-D placement of floorplanning modules.
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Johnson, Timothy E. "MOSSTAT An interactive static rule checker for MOS VLSI designs." Full text open access at:, 1986. http://content.ohsu.edu/u?/etd,109.
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Cooke, Bradly James. "S-parameter VLSI transmission line analysis." Diss., The University of Arizona, 1989. http://hdl.handle.net/10150/184876.
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This dissertation investigates the implementation of S-parameter based network techniques for the analysis of multiconductor, high speed VLSI integrated circuit and packaging interconnects. The S-parameters can be derived from three categories of input parameters: (1) lossy quasi-static R,L,C and G, (2) lossy frequency dependent (dispersive) R,L,C,G and (3) the propagation constants, Γ, the characteristic impedance, Z(c) and the conductor eigencurrents, I, derived from full wave analysis. The S-parameter network techniques developed allow for: the analysis of periodic waveform excitation, the incorporation of externally measured or calculated scattering parameter data and large system analysis through macro decomposition. The inclusion of non-linear terminations has also been developed.
22
Appleton, Samuel Scott. "Performance-directed design of asynchronous VLSI systems /." Title page, contents and abstract only, 1997. http://web4.library.adelaide.edu.au/theses/09PH/09pha651.pdf.
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Ale, Anil Kumar. "Comparison and Evaluation of Existing Analog Circuit Simulator using Sigma-Delta Modulator." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5422/.
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In the world of VLSI (very large scale integration) technology, there are many different types of circuit simulators that are used to design and predict the circuit behavior before actual fabrication of the circuit. In this thesis, I compared and evaluated existing circuit simulators by considering standard benchmark circuits. The circuit simulators which I evaluated and explored are Ngspice, Tclspice, Winspice (open source) and Spectre® (commercial). I also tested standard benchmarks using these circuit simulators and compared their outputs. The simulators are evaluated using design metrics in order to quantify their performance and identify efficient circuit simulators. In addition, I designed a sigma-delta modulator and its individual components using the analog behavioral language Verilog-A. Initially, I performed simulations of individual components of the sigma-delta modulator and later of the whole system. Finally, CMOS (complementary metal-oxide semiconductor) transistor-level circuits were designed for the differential amplifier, operational amplifier and comparator of the modulator.
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Battina, Brahmasree. "An Interactive Framework for Teaching Fundamentals of Digital Logic Design and VLSI Design." Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc799495/.
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Integrated Circuits (ICs) have a broad range of applications in healthcare, military, consumer electronics etc. The acronym VLSI stands for Very Large Scale Integration and is a process of making ICs by placing millions of transistors on a single chip. Because of advancements in VLSI design technologies, ICs are getting smaller, faster in speed and more efficient, making personal devices handy, and with more features. In this thesis work an interactive framework is designed in which the fundamental concepts of digital logic design and VLSI design such as logic gates, MOS transistors, combinational and sequential logic circuits, and memory are presented in a simple, interactive and user friendly way to create interest in students towards engineering fields, especially Electrical Engineering and Computer Engineering. Most of the concepts are explained in this framework by taking the examples which we see in our daily lives. Some of the critical design concerns such as power and performance are presented in an interactive way to make sure that students can understand these significant concepts in an easy and user friendly way.
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Ryu, Kyeong Keol. "Automated Bus Generation for Multi-processor SoC Design." Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5076.
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In the design of a multi-processor System-on-a-Chip (SoC), the bus architecture typically comes to the forefront because the system performance is not dependent only on the speed of the Processing Elements (PEs) but also on the bus architecture in the system. An efficient bus architecture with effective arbitration for reducing contention on the bus plays an important role in maximizing performance. Therefore, among many issues of multi-processor SoC research, we focus on two issues related to the bus architecture in this dissertation. One issue is how to quickly and easily design an efficient bus architecture for an SoC. The second issue is how to quickly explore the design space across performance influencing factors to achieve a high performance bus system.
The objective of this research is to provide a Computer-Aided Design (CAD) tool with which the user can quickly explore System-on-a-Chip (SoC) bus design space in search of a high performance SoC bus system. From a straightforward description of the numbers and types of Processing Elements (PEs), non-PEs, memories and buses (including, for example, the address and data bus widths of the buses and memories), our Bus Synthesis tool, called BusSynth, generates a Register-Transfer Level (RTL) Verilog Hardware Description Language (HDL) description of the specified bus system. The user can utilize this RTL Verilog in bus-accurate simulations to more quickly arrive at an efficient bus architecture for a multi-processor SoC.
The methodology we propose gives designers a great benefit in fast design space exploration of bus systems across a variety of performance influencing factors such as bus types, PE types and software programming styles (e.g., pipelined parallel fashion or functional parallel fashion). We also show that BusSynth can efficiently generate bus systems in a matter of seconds as opposed to weeks of design effort to integrate together each system component by hand. Moreover, unlike the previous related work, BusSynth can support a wide variety of PEs, memory types and bus architectures (including a hybrid bus architecture) in search of a high performance SoC.
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Zhang, Mingyang 1981. "Macromodeling and simulation of linear components characterized by measured parameters." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=112589.
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Recently, microelectronics designs have reached extremely high operating frequencies as well as very small die and package sizes. This has made signal integrity an important bottleneck in the design process, and resulted in the inclusion of signal integrity simulation in the computer aided design flow. However, such simulations are often difficult because in many cases it is impossible to derive analytical models for certain passive elements, and the only available data are frequency-domain measurements or full-wave simulations. Furthermore, at such high frequencies these components are distributed in nature and require a large number of poles to be properly characterized. Simple lumped equivalent circuits are therefore difficult to obtain, and more systematic approaches are required. In this thesis we study the Vector Fitting techniques for obtaining such equivalent model and propose a more streamlined approach for preserving passivity while maintaining accuracy.
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Nugent, Steven Paul. "A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC)." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6885.
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Future opportunities for gigascale integration will be governed by a hierarchy of theoretical and practical limits that can be codified as follows: fundamental, material, device, circuit, and system. An exponential increase in on-chip integration is driving System-on-Chip (SoC) methodologies as a dominant design solution for gigascale ICs. Therefore, a second generation generic systems simulator (GENESYS) is developed to address a need for rapid assessment of technology/architecture tradeoffs for multi-billion transistor SoCs while maintaining the depth of core modeling codified in the hierarchy of limits. A newly developed system methodology incorporates a hiearchical block-based model, a dual interconnect distribution for both local and global interconnects, a generic on-chip bus model, and cell placement algorithms. A comparison of simulation results for five commercial SoC implementations shows increased accuracy in predicting die size, clock frequency, and total power dissipation. ITRS projections for future technology requirments are applied with results indicating that increasing static power dissipation is a key impediment to making continued improvements in chip performance. Additionally, simulations of a generic chip multi-processor architecture utilizing several interconnect schemes shows that the most promising candidate for the future of on-chip global interconnect networks will be hierarchical bus structures providing a high degree of connectivity while maintaining high operating frequencies.
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Yang, Yun Ju 1980. "Impacto de técnicas de redução do consumo de energia no projeto de SoCs Multimedia." [s.n.], 2011. http://repositorio.unicamp.br/jspui/handle/REPOSIP/275743.
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Orientador: Guido Costa Souza de AraújoDissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação
Made available in DSpace on 2018-08-19T00:08:02Z (GMT). No. of bitstreams: 1 Yang_YunJu_M.pdf: 3101962 bytes, checksum: 3711cbf9c4db60e5d2938d566db0d87c (MD5) Previous issue date: 2011
Resumo: A indústria de semicondutores sempre enfrentou fortes demandas em resolver problema de dissipação de calor e reduzir o consumo de energia em dispositivos. Esta tendência tem sido intensificada nos últimos anos com o movimento de sustentabilidade ambiental. A concepção correta de um sistema eletrônico de baixo consumo de energia é um problema de vários níveis de complexidade e exige estratégias sistemáticas na sua construção. Fora disso, a adoção de qualquer técnica de redução de energia sempre está vinculada com objetivos especiais e provoca alguns impactos no projeto. Apesar dos projetistas conheçam bem os impactos de forma qualitativa, as detalhes quantitativas ainda são incógnitas ou apenas mantidas dentro do 'know-how' das empresas. Neste trabalho, de acordo com resultados experimentais baseado num plataforma de SoC1 industrial, tentamos quantificar os impactos derivados do uso de técnicas de redução de consumo de energia. Nos concentramos em relacionar o fator de redução de energia de cada técnica aos impactos em termo de área, desempenho, esforço de implementação e verificação. Na ausência desse tipo de dados, que relacionam o esforço de engenharia com as metas de consumo de energia, incertezas e atrasos serão frequentes no cronograma de projeto. Esperamos que este tipo de orientações possam ajudar/guiar os arquitetos de projeto em selecionar as técnicas adequadas para reduzir o consumo de energia dentro do alcance de orçamento e cronograma de projeto
Abstract: The semiconductor industry has always faced strong demands to solve the problem of heat dissipation and reduce the power consumption in electronic devices. This trend has been increased in recent years with the action of environmental sustainability. The correct conception of an electronic system for low power consumption is an issue with multiple levels of complexities and requires systematic approaches in its construction. However, the adoption of any technique for reducing the power consumption is always linked with some specific goals and causes some impacts on the project. Although the designers know well that these impacts can affect the design in a quality aspect, the quantitative details are still unkown or just be kept inside the company's know-how. In this work, according to the experimental results based on an industrial SoC2 platform, we try to quantify the impacts of the use of low power techniques. We will relate the power reduction factor of each technique to the impact in terms of area, performance, implementation and verification effort. In the absence of such data, which relates the engineering effort to the goals of power consumption, uncertainties and delays are frequent. We hope that such guidelines can help/guide the project architects in selecting the appropriate techniques to reduce the power consumption within the limit of budget and project schedule
Mestrado
Ciência da Computação
Mestre em Ciência da Computação
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Goshi, Sudheer. "Digital Fabric." PDXScholar, 2012. https://pdxscholar.library.pdx.edu/open_access_etds/115.
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Continuing advances with VLSI have enabled engineers to build high performance computer systems to solve complex problems. The real-world problems and tasks like pattern recognition, speech recognition, etc. still remain elusive to the most advanced computer systems today. Many advances in the science of computer design and technology are coming together to enable the creation of the next-generation computing machines to solve real-world problems, which the human brain does with ease. One such engineering advance is the field of neuromorphic engineering, which tries to establish closer links to biology and help us investigate the problem of designing better computing machines. A chip built with the principles of neuromorphic engineering is called as neuromorphic chip. Neuromorphic chip aims to solve real-world problems. As the complexity of the problem increases, the computation capability of these chips can become a limitation. In order to improve the performance and accomplish a complex task in the real-world, many such chips need to be integrated into a system. Hence, efficiency of such a system depends on effective inter-chip communication. Here, the work presented aims at building a message-passing network (Digital Fabric) simulator, that integrates many such chips. Each chip represents a binary event-based unit called spiking analog cortical module. The inter-chip communication protocol employed here is called as Address Event Representation. Here, the Digital Fabric is built in three revisions, with different architectures being considered in each revision. The complexity is increased at each iteration stage. The experiments performed in each revision test the performance of such configuration systems and results proves to lay a foundation for further studies. In the future, building a high level simulation model will assist in scaling and evaluating various network topologies.
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Inampudi, Sivateja. "Teaching Fundamentals of Digital Logic Design and VLSI Design Using Computational Textiles." Thesis, University of North Texas, 2014. https://digital.library.unt.edu/ark:/67531/metadc699874/.
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This thesis presents teaching fundamentals of digital logic design and VLSI design for freshmen and even for high school students using e-textiles. This easily grabs attention of students as it is creative and interesting. Using e-textiles to project these concepts would be easily understood by students at young age. This involves stitching electronic circuits on a fabric using basic components like LEDs, push buttons and so on. The functioning of these circuits is programmed in Lilypad Arduino. By using this method, students get exposed to basic electronic concepts at early stage which eventually develops interest towards engineering field.
31
Rockliff, John E. (John Edward). "The implementation of testability strategies in a VLSI circuit." 1986. http://web4.library.adelaide.edu.au/theses/09ENS/09ensr683.pdf.
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"Design and test for timing uncertainty in VLSI circuits." 2012. http://library.cuhk.edu.hk/record=b5549444.
Full textAbstract:
由於特徵尺寸不斷縮小，集成電路在生產過程中的工藝偏差在運行環境中溫度和電壓等參數的波動以及在使用過程中的老化等效應越來越嚴重，導致芯片的時序行為出現很大的不確定性。多數情況下，芯片的關鍵路徑會不時出現時序錯誤。加入更多的時序餘量不是一種很好的解決方案，因為這種保守的設計方法會抵消工藝進步帶來的性能上的好處。這就為設計一個時序可靠的系統提出了極大的挑戰，其中的一些關鍵問題包括：(一)如何有效地分配有限的功率預算去優化那些正爆炸式增加的關鍵路徑的時序性能；(二)如何產生能夠捕捉準確的最壞情況時延的高品質測試向量；(三)為了能夠取得更好的功耗和性能上的平衡，我們將不得不允許芯片在使用過程中出現一些頻率很低的時序錯誤。隨之而來的問題是如何做到在線的檢錯和糾錯。為了解決上述問題，我們首先發明了一種新的技術用於識別所謂的虛假路徑，該方法使我們能夠發現比傳統方法更多的虛假路徑。當將所提取的虛假路徑集成到靜態時序分析工具里以後，我們可以得到更為準確的時序分析結果，同時也能節省本來用於優化這些路徑的成本。接著，考慮到現有的延時自動向量生成(ATPG) 方法會產生功能模式下無法出現的測試向量，這種向量可能會造成測試過程中在被激活的路徑周圍出現過多(或過少)的電源噪聲(PSN) ，從而導致測試過度或者測試不足情況。為此，我們提出了一種新的偽功能ATPG工具。通過同時考慮功能約束以及電路的物理佈局信息，我們使用類似ATPG 的算法產生狀態跳變使其能最大化已激活的路徑周圍的PSN影響。最後，基於近似電路的原理，我們提出了一種新的在線原位校正技術，即InTimeFix，用於糾正時序錯誤。由於實現近似電路的綜合僅需要簡單的電路結構分析，因此該技術能夠很容易的擴展到大型電路設計上去。
With technology scaling, integrated circuits (ICs) suffer from increasing process, voltage, and temperature (PVT) variations and aging effects. In most cases, these reliability threats manifest themselves as timing errors on speed-paths (i.e., critical or near-critical paths) of the circuit. Embedding a large design guard band to prevent timing errors to occur is not an attractive solution, since this conservative design methodology diminishes the benefit of technology scaling. This creates several challenges on build a reliable systems, and the key problems include (i) how to optimize circuit’s timing performance with limited power budget for explosively increased potential speed-paths; (ii) how to generate high quality delay test pattern to capture ICs’ accurate worst-case delay; (iii) to have better power and performance tradeoff, we have to accept some infrequent timing errors in circuit’s the usage phase. Therefore, the question is how to achieve online timing error resilience.
To address the above issues, we first develop a novel technique to identify so-called false paths, which facilitate us to find much more false paths than conventional methods. By integrating our identified false paths into static timing analysis tool, we are able to achieve more accurate timing information and also save the cost used to optimize false paths. Then, due to the fact that existing delay automated test pattern generation (ATPG) methods may generate test patterns that are functionally-unreachable, and such patterns may incur excessive (or limited) power supply noise (PSN) on sensitized paths in test mode, thus leading to over-testing or under-testing of the circuits, we propose a novel pseudo-functional ATPG tool. By taking both circuit layout information and functional constrains into account, we use ATPG like algorithm to justify transitions that pose the maximized functional PSN effects on sensitized critical paths. Finally, we propose a novel in-situ correction technique to mask timing errors, namely InTimeFix, by introducing redundant approximation circuit with more timing slack for speed-paths into the design. The synthesis of the approximation circuit relies on simple structural analysis of the original circuit, which is easily scalable to large IC designs.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Yuan, Feng.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2012.
Includes bibliographical references (leaves 88-100).
Abstract also in Chinese.
Abstract --- p.i
Acknowledgement --- p.iv
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Challenges to Solve Timing Uncertainty Problem --- p.2
Chapter 1.2 --- Contributions and Thesis Outline --- p.5
Chapter 2 --- Background --- p.7
Chapter 2.1 --- Sources of Timing Uncertainty --- p.7
Chapter 2.1.1 --- Process Variation --- p.7
Chapter 2.1.2 --- Runtime Environment Fluctuation --- p.9
Chapter 2.1.3 --- Aging Effect --- p.10
Chapter 2.2 --- Technical Flow to Solve Timing Uncertainty Problem --- p.10
Chapter 2.3 --- False Path --- p.12
Chapter 2.3.1 --- Path Sensitization Criteria --- p.12
Chapter 2.3.2 --- False Path Aware Timing Analysis --- p.13
Chapter 2.4 --- Manufacturing Testing --- p.14
Chapter 2.4.1 --- Functional Testing vs. Structural Testing --- p.14
Chapter 2.4.2 --- Scan-Based DfT --- p.15
Chapter 2.4.3 --- Pseudo-Functional Testing --- p.17
Chapter 2.5 --- Timing Error Tolerance --- p.19
Chapter 2.5.1 --- Timing Error Detection --- p.19
Chapter 2.5.2 --- Timing Error Recover --- p.20
Chapter 3 --- Timing-Independent False Path Identification --- p.23
Chapter 3.1 --- Introduction --- p.23
Chapter 3.2 --- Preliminaries and Motivation --- p.26
Chapter 3.2.1 --- Motivation --- p.27
Chapter 3.3 --- False Path Examination Considering Illegal States --- p.28
Chapter 3.3.1 --- Path Sensitization Criterion --- p.28
Chapter 3.3.2 --- Path-Aware Illegal State Identification --- p.30
Chapter 3.3.3 --- Proposed Examination Procedure --- p.31
Chapter 3.4 --- False Path Identification --- p.32
Chapter 3.4.1 --- Overall Flow --- p.34
Chapter 3.4.2 --- Static Implication Learning --- p.35
Chapter 3.4.3 --- Suspicious Node Extraction --- p.36
Chapter 3.4.4 --- S-Frontier Propagation --- p.37
Chapter 3.5 --- Experimental Results --- p.38
Chapter 3.6 --- Conclusion and Future Work --- p.42
Chapter 4 --- PSN Aware Pseudo-Functional Delay Testing --- p.43
Chapter 4.1 --- Introduction --- p.43
Chapter 4.2 --- Preliminaries and Motivation --- p.45
Chapter 4.2.1 --- Motivation --- p.46
Chapter 4.3 --- Proposed Methodology --- p.48
Chapter 4.4 --- Maximizing PSN Effects under Functional Constraints --- p.50
Chapter 4.4.1 --- Pseudo-Functional Relevant Transitions Generation --- p.51
Chapter 4.5 --- Experimental Results --- p.59
Chapter 4.5.1 --- Experimental Setup --- p.59
Chapter 4.5.2 --- Results and Discussion --- p.60
Chapter 4.6 --- Conclusion --- p.64
Chapter 5 --- In-Situ Timing Error Masking in Logic Circuits --- p.65
Chapter 5.1 --- Introduction --- p.65
Chapter 5.2 --- Prior Work and Motivation --- p.67
Chapter 5.3 --- In-Situ Timing Error Masking with Approximate Logic --- p.69
Chapter 5.3.1 --- Equivalent Circuit Construction with Approximate Logic --- p.70
Chapter 5.3.2 --- Timing Error Masking with Approximate Logic --- p.72
Chapter 5.4 --- Cost-Efficient Synthesis for InTimeFix --- p.75
Chapter 5.4.1 --- Overall Flow --- p.76
Chapter 5.4.2 --- Prime Critical Segment Extraction --- p.77
Chapter 5.4.3 --- Prime Critical Segment Merging --- p.79
Chapter 5.5 --- Experimental Results --- p.81
Chapter 5.5.1 --- Experimental Setup --- p.81
Chapter 5.5.2 --- Results and Discussion --- p.82
Chapter 5.6 --- Conclusion --- p.85
Chapter 6 --- Conclusion and Future Work --- p.86
Bibliography --- p.100
33
Ramalingam, Anand 1979. "Analysis techniques for nanometer digital integrated circuits." Thesis, 2007. http://hdl.handle.net/2152/3661.
Full textAbstract:
As technology has scaled into nanometer regime, manufacturing variations have emerged as a major limiter of performance (timing) in VLSI circuits. Issues related to timing are addressed in the first part of the dissertation. Statistical Static Timing Analysis (SSTA) has been proposed to perform full-chip analysis of timing under uncertainty such as manufacturing variations. In this dissertation, we propose an efficient sparse-matrix framework for a path-based SSTA. In addition to an efficient framework for doing timing analysis, to improve the accuracy of the timing analysis one needs to address the accuracy of: waveform modeling, and gate delay modeling. We propose a technique based on Singular Value Decomposition (SVD) that accurately models the waveform in a timing analyzer. To improve the gate delay modeling, we propose a closed form expression based on the centroid of power dissipation. This new metric is inspired by our key observation that the Sakurai-Newton (SN) delay metric can be viewed as the centroid of current. In addition to accurately analyzing the timing of a chip, improving timing is another major concern. One way to improve timing is to scale down the threshold voltage (Vth). But scaling down increases the subthreshold leakage current exponentially. Sleep transistors have been proposed to reduce leakage current while maintaining performance. We propose a path-based algorithm to size the sleep transistor to reduce leakage while maintaining the required performance. In the second part of dissertation we address power grid and thermal issues that arise due to the scaling of integrated circuits. In the case of power grid simulation, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The transistor is modeled as a switch in series with an RC and the switch itself is modeled behaviorally. This model allows more accurate prediction of voltage drop compared to the current source model. In the case of thermal simulation, we address the issue of ignoring the nonlinearity of thermal conductivity in silicon. We found that ignoring the nonlinearity of thermal conductivity may lead to a temperature profile that is off by 10° C.
34
Lai, Minghorng. "New algorithms for physical design of VLSI circuits." 2002. http://wwwlib.umi.com/cr/utexas/fullcit?p3099471.
Full text
35
Choi, Youngmoon. "Parallel prefix adder design." Thesis, 2004. http://hdl.handle.net/2152/1300.
Full text
36
"An incremental alternation placement algorithm for macrocell array design." Chinese University of Hong Kong, 1990. http://library.cuhk.edu.hk/record=b5886910.
Full textAbstract:
by Tsz Shing Cheung.Thesis (M.Phil.)--Chinese University of Hong Kong, 1990.
Includes bibliographical references.
Chapter Section 1 --- Introduction --- p.2
Chapter 1.1 --- The Affinity Clustering Phase --- p.2
Chapter 1.2 --- The Alteration Phase --- p.3
Chapter 1.3 --- Floorplan of Macrocell Array --- p.3
Chapter 1.4 --- Chip Model --- p.4
Chapter 1.4.1 --- Location Representation --- p.4
Chapter 1.4.2 --- Interconnection Length Estimation --- p.6
Chapter 1.5 --- Cost Function Evaluation --- p.6
Chapter 1.5.1 --- Net-length Calculation --- p.6
Chapter 1.5.2 --- Net-length Estimated by Half of the Perimeter of Bounding Box --- p.7
Chapter 1.6 --- Thesis Layout --- p.8
Chapter Section 2 --- Reviews of Partitioning and Placement Methods --- p.9
Chapter 2.1 --- Partitioning Methods --- p.9
Chapter 2.1.1 --- Direct Method --- p.10
Chapter 2.1.2 --- Group Migration Method --- p.10
Chapter 2.1.3 --- Metric Allocation Methods --- p.10
Chapter 2.1.4 --- Simulated Annealing --- p.11
Chapter 2.2 --- Placement Methods --- p.12
Chapter 2.2.1 --- Min-cut Methods --- p.13
Chapter 2.2.2 --- Affinity Clustering Methods --- p.13
Chapter 2.2.3 --- Other Placement Methods --- p.16
Chapter Section 3 --- Algorithm --- p.17
Chapter 3.1 --- The Affinity Clustering Phase --- p.18
Chapter 3.1.1 --- Construction of Connection Lists --- p.18
Chapter 3.1.2 --- Primary Grouping --- p.21
Chapter 3.1.3 --- Element Appendage to Existing Groups --- p.23
Chapter 3.1.4 --- Loose Appendage of Ungrouped Elements --- p.25
Chapter 3.1.5 --- Single Element Groups Formation --- p.26
Chapter 3.2 --- The Alteration Phase --- p.27
Chapter 3.2.1 --- Element Assignment to a Group --- p.29
Chapter 3.2.2 --- Empty Space Searching --- p.30
Chapter 3.2.3 --- Determination of Direction of Element Allocation --- p.31
Chapter 3.2.3.1 --- Cross-cut Direction of Allocation --- p.32
Chapter 3.2.3.2 --- Dynamic Determination of Path Based on Size Functions --- p.34
Chapter 3.2.3.2.1 --- Segmentation of Cross-cut --- p.35
Chapter 3.2.3.2.2 --- Partial Optimization of Segments --- p.36
Chapter 3.2.3.2.3 --- Dynamic Linking of Segments --- p.38
Chapter 3.2.4 --- Element Allocation --- p.39
Chapter Section 4 --- Implementation --- p.41
Chapter 4.1 --- The System Row --- p.41
Chapter 4.1.1 --- The Affinity Clustering Phase --- p.43
Chapter 4.1.2 --- The Alteration Phase --- p.44
Chapter 4.2 --- Data Structures --- p.47
Chapter 4.2.1 --- Insertion of Elements to a Linked List --- p.54
Chapter 4.2.2 --- Dynamic Linking of Segments --- p.56
Chapter 4.2.3 --- Advantages of the Dynamic Data Structure --- p.59
Chapter 4.3 --- Data Manipulation and File Management --- p.60
Chapter 4.3.1 --- The Connection Lists and the Group List --- p.60
Chapter 4.3.2 --- Description on Programs and Data Files --- p.62
Chapter 4.3.2.1 --- The Affinity Clustering Phase --- p.63
Chapter 4.3.2.2 --- The Alteration Phase --- p.64
Chapter Section 5 --- Results --- p.70
Chapter 5.1 --- Results on Affinity Clustering Phase --- p.84
Chapter 5.2 --- Details of Affinity Clustering Procedure on Ckt. 2 and Ckt. 5 --- p.92
Chapter 5.3 --- Results on Alteration Phase --- p.97
Chapter 5.4 --- Details of Alteration Procedure on Ckt. 2 and Ckt. 5 --- p.101
Chapter Section 6 --- Discussion --- p.107
Chapter 6.1 --- Computation Time of the Algorithm --- p.107
Chapter 6.2 --- Alternative Methods on the Determination of Propagation Path --- p.110
Chapter 6.2.1 --- Method 1 --- p.110
Chapter 6.2.2 --- Method 2 --- p.111
Chapter 6.2.3 --- Method 3 --- p.114
Chapter 6.2.4 --- Comparison on Execution Time of the Four Methods --- p.117
Chapter 6.3 --- Wiring Optimization --- p.118
Chapter 6.3.1 --- Data Structure --- p.119
Chapter 6.3.2 --- Overlapping and Separate Bounding Boxes --- p.120
Chapter 6.4 --- Generalization of the Data Structure --- p.122
Chapter 6.4.1 --- Cell Types --- p.123
Chapter 6.4.2 --- Adhesive Attributes --- p.124
Chapter 6.4.3 --- Blocks Representation --- p.124
Chapter 6.4.4 --- Critical Path Adjustment --- p.125
Chapter 6.4.5 --- Total Interconnection Length Estimation --- p.129
Chapter 6.5 --- A New Placement Algorithm --- p.130
Chapter 6.6 --- An Alternative Method on Element Allocation --- p.132
Chapter Section 7 --- Conclusion --- p.136
Chapter Section 8 --- References --- p.138
Chapter Section 9 --- Appendix I --- p.142
Chapter 9.1 --- Definition of the Problem --- p.142
Chapter 9.2 --- The Simulated Annealing Algorithm --- p.142
Chapter 9.3 --- Example Circuit --- p.143
Chapter 9.4 --- Performance Indices and Energy Value --- p.144
Chapter 9.4.1 --- Total Interconnection Length --- p.144
Chapter 9.4.2 --- Delay on Critical Paths --- p.144
Chapter 9.4.3 --- Skew in Input-to-Output Delays --- p.146
Chapter 9.4.4 --- Energy Value --- p.146
Chapter 9.5 --- The Simulation Program --- p.146
Chapter 9.5.1 --- "The ""function"" Subroutines" --- p.147
Chapter 9.5.1.1 --- alise --- p.147
Chapter 9.5.1.2 --- max delay --- p.147
Chapter 9.5.1.3 --- replace --- p.147
Chapter 9.5.1.4 --- total length --- p.147
Chapter 9.5.2 --- "The ""procedure"" Subroutines" --- p.148
Chapter 9.5.2.1 --- init_weight --- p.148
Chapter 9.5.2.2 --- inverse --- p.148
Chapter 9.5.2.3 --- initial --- p.148
Chapter 9.5.2.4 --- shuffle --- p.148
Chapter 9.5.3 --- The Main Program --- p.148
Chapter 9.6 --- Results and Discussion --- p.149
Chapter 9.7 --- Summary --- p.156
Chapter 9.8 --- References --- p.156
Chapter Section 10 --- Appendix II --- p.157
37
Croix, John Francis 1963. "Cell and interconnect timing analysis using waveforms." 2002. http://hdl.handle.net/2152/11193.
Full text
38
Luo, Tao Ph D. "Nanometer VLSI placement and optimization for multi-objective design closure." Thesis, 2007. http://hdl.handle.net/2152/3688.
Full text
39
Ren, Haoxing. "Incremental placement for modern VLSI design closure." Thesis, 2006. http://hdl.handle.net/2152/2626.
Full text
40
"A novel asynchronous cell library for self-timed system design." Chinese University of Hong Kong, 1995. http://library.cuhk.edu.hk/record=b5888603.
Full textAbstract:
by Eva Yuk-Wah Pang.Thesis (M.Phil.)--Chinese University of Hong Kong, 1995.
Includes bibliographical references (leaves 88-89).
ACKNOWLEDGEMETS
ABSTRACT
LIST OF FIGURES
LIST OF TABLES
Chapter CHAPTER1 --- INTRODUCTION
Chapter 1.1 --- Motivation --- p.1-1
Chapter 1.1.1 --- Problems with Synchronous Systems --- p.1-1
Chapter 1.1.2 --- The Advantages of Self-timed Systems --- p.1-2
Chapter 1.1.3 --- Self-Timed Cell Library --- p.1-3
Chapter 1.2 --- Overview of the Thesis --- p.1-5
Chapter CHAPTER2 --- BACKGROUND
Chapter 2.1 --- Introduction --- p.2-1
Chapter 2.2 --- Models for Asynchronous System --- p.2-2
Chapter 2.2.1 --- Huffman model --- p.2-2
Chapter 2.2.2 --- Muller model --- p.2-4
Chapter 2.3 --- Self-timed System --- p.2-5
Chapter 2.3.1 --- Definitions and Assumptions --- p.2-6
Chapter 2.4 --- Design Methodologies --- p.2-8
Chapter 2.4.1 --- Differential Logic Structure Design Methodology --- p.2-9
Chapter 2.4.1.1 --- Data Path --- p.2-9
Chapter 2.4.1.2 --- Control Path --- p.2-10
Chapter 2.4.2 --- Micropipeline Design Methodology --- p.2-12
Chapter 2.4.2.1 --- Data Path --- p.2-12
Chapter 2.4.2.2 --- Control Path --- p.2-13
Chapter CHAPTER3 --- SELF-TIMED CELL LIBRARY
Chapter 3.1 --- Introduction --- p.3-1
Chapter 3.2 --- Muller C element --- p.3-1
Chapter 3.3 --- Differential Cascode Voltage Switch Logic Circuits --- p.3-6
Chapter 3.3.1 --- INVERTER --- p.3-8
Chapter 3.3.2 --- "AND, OR, NAND, NOR" --- p.3-8
Chapter 3.3.3 --- "XOR, XNOR" --- p.3-10
Chapter 3.4 --- Latches --- p.3-11
Chapter 3.4.1 --- Precharged Latch --- p.3-12
Chapter 3.4.2 --- Capture and Pass Latch --- p.3-12
Chapter 3.5 --- Delay Elements --- p.3-13
Chapter 3.6 --- Discussion --- p.3-15
Chapter CHAPTER4 --- THE CHARACTERISTICS OF SELF-TIMED CELL LIBRARY
Chapter 4.1 --- Introduction --- p.4-1
Chapter 4.2 --- The Simulation Characteristics --- p.4-2
Chapter 4.2.1 --- HSPICE program --- p.4-2
Chapter 4.2.2 --- Characterization Information and Datasheet terms --- p.4-5
Chapter 4.2.3 --- Characterization values --- p.4-6
Chapter 4.3 --- The Experimental Analysis --- p.4-6
Chapter 4.4 --- Experimental Result and Discussion --- p.4-9
Chapter 4.4.1 --- Experimental Result --- p.4-9
Chapter 4.4.2 --- Comparison of the characteristics of C-elements --- p.4-12
Chapter 4.4.3 --- Comparison of simulation with experimental results --- p.4-13
Chapter 4.4.4 --- Properties of DCVSL gate --- p.4-14
Chapter 4.4.5 --- The Characteristics of Delay elements --- p.4-15
Chapter 4.5 --- CAD Features on Cadence --- p.4-16
Chapter CHAPTER5 --- DESIGN EXAMPLE: SELF-TIMED MATRIX MULTIPLIER
Chapter 5.1 --- Introduction --- p.5-1
Chapter 5.2 --- A Matrix Multiplier using DCVSL structure --- p.5-2
Chapter 5.2.1 --- Structure --- p.5-2
Chapter 5.2.2 --- Handshaking Control Circuit --- p.5-3
Chapter 5.2.2.1 --- Handshaking Control Circuit of Pipeline --- p.5-4
Chapter 5.2.2.2 --- Handshaking Control Circuit of Feedback Path --- p.5-8
Chapter 5.3 --- A Matrix Multiplier using Micropipeline Structure --- p.5-10
Chapter 5.3.1 --- Structure --- p.5-10
Chapter 5.3.2 --- Control Circuit --- p.5-12
Chapter 5.4 --- Experimental Result --- p.5-13
Chapter 5.4.1 --- The Matrix Multiplier using DCVSL structure --- p.5-13
Chapter 5.4.2 --- The Matrix Multiplier using Micropipeline structure --- p.5-16
Chapter 5.5 --- Comparison of DCVSL structure and Micropipeline structure --- p.5-18
Chapter CHAPTER6 --- CONCLUSION
Chapter 6.1 --- Achievement --- p.6-1
Chapter 6.1.1 --- Self-timed Cell Library --- p.6-1
Chapter 6.1.2 --- Self-timed System Design simplification --- p.6-2
Chapter 6.1.3 --- Area and Speed --- p.6-3
Chapter 6.1.4 --- Applications --- p.6-4
Chapter 6.2 --- Future work --- p.6-6
Chapter 6.2.1 --- Interface with synthesis tools --- p.6-6
Chapter 6.2.2 --- Mixed Circuit Design --- p.6-6
REFERENCES
APPENDICES
41
"Scalability and interconnection issues in floorplan design and floorplan representations." 2001. http://library.cuhk.edu.hk/record=b5890773.
Full textAbstract:
Yuen Wing-seung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.
Includes bibliographical references (leaves [116]-[122]).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgments --- p.iii
List of Figures --- p.viii
List of Tables --- p.xii
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivations and Aims --- p.1
Chapter 1.2 --- Contributions --- p.3
Chapter 1.3 --- Dissertation Overview --- p.4
Chapter 2 --- Physical Design and Floorplanning in VLSI Circuits --- p.6
Chapter 2.1 --- VLSI Design Flow --- p.6
Chapter 2.2 --- Floorplan Design --- p.8
Chapter 2.2.1 --- Problem Formulation --- p.9
Chapter 2.2.2 --- Types of Floorplan --- p.10
Chapter 3 --- Floorplanning Representations --- p.12
Chapter 3.1 --- Polish Expression(PE) [WL86] --- p.12
Chapter 3.2 --- Bounded-Sliceline-Grid(BSG) [NFMK96] --- p.14
Chapter 3.3 --- Sequence Pair(SP) [MFNK95] --- p.17
Chapter 3.4 --- O-tree(OT) [GCY99] --- p.19
Chapter 3.5 --- B*-tree(BT) [CCWW00] --- p.21
Chapter 3.6 --- Corner Block List(CBL) [HHC+00] --- p.22
Chapter 4 --- Optimization Technique in Floorplan Design --- p.27
Chapter 4.1 --- General Optimization Methods --- p.27
Chapter 4.1.1 --- Simulated Annealing --- p.27
Chapter 4.1.2 --- Genetic Algorithm --- p.29
Chapter 4.1.3 --- Integer Programming Method --- p.31
Chapter 4.2 --- Shape Optimization --- p.33
Chapter 4.2.1 --- Shape Curve --- p.33
Chapter 4.2.2 --- Lagrangian Relaxation --- p.34
Chapter 5 --- Literature Review on Interconnect Driven Floorplanning --- p.37
Chapter 5.1 --- Placement Constraint in Floorplan Design --- p.37
Chapter 5.1.1 --- Boundary Constraints --- p.37
Chapter 5.1.2 --- Pre-placed Constraints --- p.39
Chapter 5.1.3 --- Range Constraints --- p.41
Chapter 5.1.4 --- Symmetry Constraints --- p.42
Chapter 5.2 --- Timing Analysis Method --- p.43
Chapter 5.3 --- Buffer Block Planning and Congestion Control --- p.45
Chapter 5.3.1 --- Buffer Block Planning --- p.45
Chapter 5.3.2 --- Congestion Control --- p.50
Chapter 6 --- Clustering Constraint in Floorplan Design --- p.53
Chapter 6.1 --- Problem Definition --- p.53
Chapter 6.2 --- Overview --- p.54
Chapter 6.3 --- Locating Neighboring Modules --- p.56
Chapter 6.4 --- Constraint Satisfaction --- p.62
Chapter 6.5 --- Multi-clustering Extension --- p.64
Chapter 6.6 --- Cost Function --- p.64
Chapter 6.7 --- Experimental Results --- p.65
Chapter 7 --- Interconnect Driven Multilevel Floorplanning Approach --- p.69
Chapter 7.1 --- Multilevel Partitioning --- p.69
Chapter 7.1.1 --- Coarsening Phase --- p.70
Chapter 7.1.2 --- Refinement Phase --- p.70
Chapter 7.2 --- Overview of Multilevel Floorplanner --- p.72
Chapter 7.3 --- Clustering Phase --- p.73
Chapter 7.3.1 --- Clustering Methods --- p.73
Chapter 7.3.2 --- Area Ratio Constraints --- p.75
Chapter 7.3.3 --- Clustering Velocity --- p.76
Chapter 7.4 --- Refinement Phase --- p.77
Chapter 7.4.1 --- Temperature Control --- p.79
Chapter 7.4.2 --- Cost Function --- p.80
Chapter 7.4.3 --- Handling Shape Flexibility --- p.80
Chapter 7.5 --- Experimental Results --- p.81
Chapter 7.5.1 --- Data Set Generation --- p.82
Chapter 7.5.2 --- Temperature Control --- p.82
Chapter 7.5.3 --- Packing Results --- p.83
Chapter 8 --- Study of Non-slicing Floorplan Representations --- p.89
Chapter 8.1 --- Analysis of Different Floorplan Representations --- p.89
Chapter 8.1.1 --- Complexity --- p.90
Chapter 8.1.2 --- Types of Floorplans --- p.92
Chapter 8.2 --- T-junction Orientation Property --- p.97
Chapter 8.3 --- Twin Binary Tree Representation for Mosaic Floorplan --- p.103
Chapter 8.3.1 --- Previous work --- p.103
Chapter 8.3.2 --- Twin Binary Tree Construction --- p.105
Chapter 8.3.3 --- Floorplan Construction --- p.109
Chapter 9 --- Conclusion --- p.114
Chapter 9.1 --- Summary --- p.114
Bibliography --- p.116
Chapter A --- Clustering Constraint Data Set --- p.123
Chapter A.1 --- ami33 --- p.123
Chapter A.1.1 --- One cluster --- p.123
Chapter A.1.2 --- Multi-cluster --- p.123
Chapter A.2 --- ami49 --- p.124
Chapter A.2.1 --- One cluster --- p.124
Chapter A.2.2 --- Multi-cluster --- p.124
Chapter A.3 --- playout --- p.124
Chapter A.3.1 --- One cluster --- p.124
Chapter A.3.2 --- Multi-cluster --- p.125
Chapter B --- Multilevel Data Set --- p.126
Chapter B.l --- data_100 --- p.126
Chapter B.2 --- data_200 --- p.127
Chapter B.3 --- data_300 --- p.129
Chapter B.4 --- data_400 --- p.131
Chapter B.5 --- data_500 --- p.133
42
Rajaram, Anand Kumar. "Synthesis of variation tolerant clock distribution networks." 2008. http://hdl.handle.net/2152/18098.
Full textAbstract:
In the sub-65nm VLSI technology, the variation effects like manufacturing variation, power supply noise and temperature variation become very significant. As one of the most vital components in any synchronous VLSI chip, the Clock Distribution Network (CDN) is especially sensitive to these variations. The unwanted clock skews caused by the variation effects consume increasing proportion of the clock cycle, thereby limiting chip performance and yield. Thus, making the clock network variation-tolerant is a key objective in the chip designs of today. In this dissertation, we propose several techniques that can be used to synthesize variation-tolerant clock networks. Our contributions can be broadly classified into following four categories: (i) Efficient algorithms for synthesizing link based non-tree clock networks. (ii) A methodology for synthesizing a balanced, variation tolerant, buffered clock network with cross-links. (iii) A comprehensive framework for planning, synthesis and optimization of clock mesh networks. (iv) A chip-level clock tree synthesis technique to address issues unique to hierarchical System-On-a-Chip (SOC) designs that are becoming more and more frequent today. Depending on the performance requirements and resource constraints of a given chip, the above techniques can be used separately or in combination to synthesize a variation tolerant clock network.text
43
"Reticle floorplanning and voltage island partitioning." 2006. http://library.cuhk.edu.hk/record=b5892947.
Full textAbstract:
Ching Lap Sze.Thesis (M.Phil.)--Chinese University of Hong Kong, 2006.
Includes bibliographical references (leaves 69-71).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgement --- p.iv
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Shuttle Mask --- p.2
Chapter 1.2 --- Voltage Island --- p.6
Chapter 1.3 --- Structure of the Thesis --- p.8
Chapter 2 --- Literature Review on Shuttle Mask Floorplanning --- p.9
Chapter 2.1 --- Introduction --- p.9
Chapter 2.1.1 --- Problem formulation --- p.10
Chapter 2.2 --- Slicing Floorplan --- p.10
Chapter 2.3 --- General Floorplan --- p.11
Chapter 2.3.1 --- Conflict Graph Approaches --- p.11
Chapter 2.3.2 --- Integer Linear Programming Approaches --- p.14
Chapter 2.4 --- Grid Packing --- p.15
Chapter 2.4.1 --- "(α,β,γ)-restricted Grid Approach" --- p.15
Chapter 2.4.2 --- Branch and Bound Searching Approach --- p.17
Chapter 3 --- Shuttle Mask Floorplanning --- p.18
Chapter 3.1 --- Problem Description --- p.18
Chapter 3.2 --- An Overview --- p.20
Chapter 3.3 --- Modified α-Restricted Grid --- p.21
Chapter 3.4 --- Branch and Bound Algorithm --- p.23
Chapter 3.4.1 --- Feasibility Check --- p.25
Chapter 3.5 --- Dicing Plan --- p.30
Chapter 3.6 --- Experimental Result --- p.30
Chapter 4 --- Literature Review on Voltage Island Partitioning --- p.36
Chapter 4.1 --- Introduction --- p.36
Chapter 4.1.1 --- Problem Definition --- p.36
Chapter 4.2 --- Dynamic Programming --- p.38
Chapter 4.2.1 --- Problem Definition --- p.38
Chapter 4.2.2 --- Algorithm Overview --- p.38
Chapter 4.2.3 --- Size Reduction --- p.39
Chapter 4.2.4 --- Approximate Voltage-Partitioning --- p.40
Chapter 4.3 --- Quad-tree Approach --- p.41
Chapter 5 --- Voltage Island Partitioning --- p.44
Chapter 5.1 --- Introduction --- p.44
Chapter 5.2 --- Problem Formulation --- p.45
Chapter 5.3 --- Methodology --- p.46
Chapter 5.3.1 --- Coarsening and Graph Construction --- p.47
Chapter 5.3.2 --- Tree Construction --- p.49
Chapter 5.3.3 --- Optimal Tree Partitioning --- p.50
Chapter 5.3.4 --- Tree Refinement --- p.52
Chapter 5.3.5 --- Solution Legalization --- p.53
Chapter 5.3.6 --- Time Complexity --- p.54
Chapter 5.4 --- Direct Method --- p.55
Chapter 5.4.1 --- Dual Grid-partitioning Problem (DGPP) --- p.56
Chapter 5.4.2 --- Time Complexity --- p.58
Chapter 5.5 --- Experimental Results --- p.59
Chapter 6 --- Conclusion --- p.66
Bibliography --- p.69
44
Xu, Gang 1974. "Layout optimization algorithms vor VLSI design and manufacturing." Thesis, 2007. http://hdl.handle.net/2152/3362.
Full textAbstract:
As the feature size of the transistor shrinks into nanometer scale, it becomes a grand challenge for semiconductor manufacturers to achieve good manufacturability of integrated circuits cost-effectively. In this dissertation, we aim at layout optimization algorithms from both manufacturing and design perspectives to address problems in this grand challenge. Our work covers three topics in this research area: a redundant via enhanced maze routing algorithm for yield improvement, a shuttle mask floorplanner, and optimization of post-CMP topography variation. Existing methods for redundant via insertion are all post-layout optimizations that insert redundant vias after detailed routing. In the first part of this dissertation, we propose the first routing algorithm that conducts redundant via insertion during detailed routing. Our routing problem is formulated as a maze routing with redundant via constraints and transformed into a multiple constraint shortest path problem, and then solved by Lagrangian relaxation technique. Experimental results show that our algorithm can find routing solutions with remarkably higher rate of redundant via insertion than conventional maze routing. Shuttle mask is an economical method to share the soaring mask cost by placing different chips on the same mask. Shuttle mask floorplanning is a key step to pack these chips according to certain objectives and constraints related to mask manufacturing and cost. In the second part of this dissertation, we develop a simulated annealing based floorplanner that can optimize these objectives and meet the constraints simultaneously. Chemical-mechanical polishing (CMP) is a crucial manufacturing step to planarize wafer surface. Minimum post-CMP topography variation is preferred to control the defocus in lithography process. In the third of this dissertation, we present several studies on optimization of the variation. First, we enhance the shuttle mask floorplanner to minimize the post-CMP topography variation. Then we study the following singleblock positioning problem: given a shuttle mask floorplan, how to determine a movable block's optimal position with respect to post-CMP topography variation. We propose a fast incremental algorithm achieving 6x to 9x speedup. Finally, we formulate a novel CMP dummy fill problem that targets at minimizing the height variance, which is key to reduce the image distortion by defocus. Experimental results show that with the new formulation, we can significantly reduce the height variance without sacrificing the height spread much.
45
"Optimal geometric design of VLSI interconnect networks by simulated annealing." Chinese University of Hong Kong, 1995. http://library.cuhk.edu.hk/record=b5888582.
Full textAbstract:
by Sau-yuen Wong.Thesis (M.Phil.)--Chinese University of Hong Kong, 1995.
Includes bibliographical references (leaves 77-82).
Acknowledgement --- p.i
Abstract --- p.ii
List of Tables --- p.ii
List of Figures --- p.iv
Chapter 1 --- Introduction --- p.1
Chapter 2 --- Review of Previous Work --- p.4
Chapter 2.1 --- Optimization of Delay and Layout Design --- p.4
Chapter 2.2 --- Simulated Annealing --- p.8
Chapter 3 --- Definition of Circuit Model --- p.12
Chapter 4 --- Evaluation of Delay --- p.16
Chapter 4.1 --- RC-tree and Elmore Delay --- p.16
Chapter 4.2 --- Exponential Decayed Polynomial Function --- p.17
Chapter 4.3 --- Two-pole Approximation --- p.18
Chapter 4.4 --- AWE and Adopted Delay Model --- p.19
Chapter 5 --- Delay Minimization by Simulated Annealing --- p.28
Chapter 5.1 --- Cost Function --- p.28
Chapter 5.2 --- Neighbor Moves --- p.30
Chapter 5.2.1 --- Logical models --- p.31
Chapter 5.2.2 --- Discretization of Solution Space --- p.32
Chapter 5.2.3 --- Valid Configurations --- p.35
Chapter 5.2.4 --- Valid Moves --- p.39
Chapter 5.2.5 --- Modification to the Newly Generated Graph --- p.41
Chapter 5.2.6 --- Access to Neighbor configuration --- p.43
Chapter 5.2.7 --- Reduction of Solution Space --- p.45
Chapter 5.2.8 --- Correctness of the Algorithm --- p.48
Chapter 5.2.9 --- Completeness of the Algorithm --- p.49
Chapter 6 --- Experimental result --- p.56
Chapter 6.1 --- Optimization of Overall Performance --- p.58
Chapter 6.2 --- Optimization on Individual Delay --- p.70
Chapter 7 --- Conclusion --- p.74
A --- p.76
Bibliography
46
Noonan, J. A. (John Anthony). "Investigations into methods and analysis of computer aided design of VLSI circuits." 1986. http://web4.library.adelaide.edu.au/theses/09ENS/09ensn817.pdf.
Full text
47
"Clock routing for high performance microprocessor designs." 2011. http://library.cuhk.edu.hk/record=b5894819.
Full textAbstract:
Tian, Haitong.Chinese abstract is on unnumbered page.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2011.
Includes bibliographical references (p. 65-74).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgement --- p.iii
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivations --- p.1
Chapter 1.2 --- Our Contributions --- p.2
Chapter 1.3 --- Organization of the Thesis --- p.3
Chapter 2 --- Background Study --- p.4
Chapter 2.1 --- Traditional Clock Routing Problem --- p.4
Chapter 2.2 --- Tree-Based Clock Routing Algorithms --- p.5
Chapter 2.2.1 --- Clock Routing Using H-tree --- p.5
Chapter 2.2.2 --- Method of Means and Medians(MMM) --- p.6
Chapter 2.2.3 --- Geometric Matching Algorithm (GMA) --- p.8
Chapter 2.2.4 --- Exact Zero-Skew Algorithm --- p.9
Chapter 2.2.5 --- Deferred Merge Embedding (DME) --- p.10
Chapter 2.2.6 --- Boundary Merging and Embedding (BME) Algorithm --- p.14
Chapter 2.2.7 --- Planar Clock Routing Algorithm --- p.17
Chapter 2.2.8 --- Useful-skew Tree Algorithm --- p.18
Chapter 2.3 --- Non-Tree Clock Distribution Networks --- p.19
Chapter 2.3.1 --- Grid (Mesh) Structure --- p.20
Chapter 2.3.2 --- Spine Structure --- p.20
Chapter 2.3.3 --- Hybrid Structure --- p.21
Chapter 2.4 --- Post-grid Clock Routing Problem --- p.22
Chapter 2.5 --- Limitations of the Previous Work --- p.24
Chapter 3 --- Post-Grid Clock Routing Problem --- p.26
Chapter 3.1 --- Introduction --- p.26
Chapter 3.2 --- Problem Definition --- p.27
Chapter 3.3 --- Our Approach --- p.30
Chapter 3.3.1 --- Delay-driven Path Expansion Algorithm --- p.31
Chapter 3.3.2 --- Pre-processing to Connect Critical ports --- p.34
Chapter 3.3.3 --- Post-processing to Reduce Capacitance --- p.36
Chapter 3.4 --- Experimental Results --- p.39
Chapter 3.4.1 --- Experiment Setup --- p.39
Chapter 3.4.2 --- Validations of the Delay and Slew Estimation --- p.39
Chapter 3.4.3 --- Comparisons with the Tree Grow (TG) Approach --- p.41
Chapter 3.4.4 --- Lowest Achievable Delays --- p.42
Chapter 3.4.5 --- Simulation Results --- p.42
Chapter 4 --- Non-tree Based Post-Grid Clock Routing Problem --- p.44
Chapter 4.1 --- Introduction --- p.44
Chapter 4.2 --- Handling Ports with Large Load Capacitances --- p.46
Chapter 4.2.1 --- Problem Ports Identification --- p.47
Chapter 4.2.2 --- Non-Tree Construction --- p.47
Chapter 4.2.3 --- Wire Link Selection --- p.48
Chapter 4.3 --- Path Expansion in Non-tree Algorithm --- p.51
Chapter 4.4 --- Limitations of the Non-tree Algorithm --- p.51
Chapter 4.5 --- Experimental Results --- p.51
Chapter 4.5.1 --- Experiment Setup --- p.51
Chapter 4.5.2 --- Validations of the Delay and Slew Estimation --- p.52
Chapter 4.5.3 --- Lowest Achievable Delays --- p.53
Chapter 4.5.4 --- Results on New Benchmarks --- p.53
Chapter 4.5.5 --- Simulation Results --- p.55
Chapter 5 --- Efficient Partitioning-based Extension --- p.57
Chapter 5.1 --- Introduction --- p.57
Chapter 5.2 --- Partition-based Extension --- p.58
Chapter 5.3 --- Experimental Results --- p.61
Chapter 5.3.1 --- Experiment Setup --- p.61
Chapter 5.3.2 --- Running Time Improvement with Partitioning Technique --- p.61
Chapter 6 --- Conclusion --- p.63
Bibliography --- p.65
48
"Obstacle-avoiding rectilinear Steiner tree." 2009. http://library.cuhk.edu.hk/record=b5894012.
Full textAbstract:
Li, Liang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.
Includes bibliographical references (leaves 57-61).
Abstract also in Chinese.
Abstract --- p.i
Acknowledgement --- p.iv
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Background --- p.1
Chapter 1.1.1 --- Partitioning --- p.1
Chapter 1.1.2 --- Floorplanning and Placement --- p.2
Chapter 1.1.3 --- Routing --- p.2
Chapter 1.1.4 --- Compaction --- p.3
Chapter 1.2 --- Motivations --- p.3
Chapter 1.3 --- Problem Formulation --- p.4
Chapter 1.3.1 --- Properties of OARSMT --- p.4
Chapter 1.4 --- Progress on the Problem --- p.4
Chapter 1.5 --- Contributions --- p.5
Chapter 1.6 --- Thesis Organization --- p.6
Chapter 2 --- Literature Review on OARSMT --- p.8
Chapter 2.1 --- Introduction --- p.8
Chapter 2.2 --- Previous Methods --- p.9
Chapter 2.2.1 --- OARSMT --- p.9
Chapter 2.2.2 --- Shortest Path Problem with Blockages --- p.13
Chapter 2.2.3 --- OARSMT with Delay Minimization --- p.14
Chapter 2.2.4 --- OARSMT with Worst Negative Slack Maximization --- p.14
Chapter 2.3 --- Comparison --- p.15
Chapter 3 --- Heuristic Method --- p.17
Chapter 3.1 --- Introduction --- p.17
Chapter 3.2 --- Our Approach --- p.18
Chapter 3.2.1 --- Handling of Multi-pin Nets --- p.18
Chapter 3.2.2 --- Propagation --- p.20
Chapter 3.2.3 --- Backtrack --- p.23
Chapter 3.2.4 --- Finding MST --- p.26
Chapter 3.2.5 --- Local Refinement Scheme --- p.26
Chapter 3.3 --- Experimental Results --- p.28
Chapter 3.4 --- Summary --- p.28
Chapter 4 --- Exact Method --- p.32
Chapter 4.1 --- Introduction --- p.32
Chapter 4.2 --- Review on GeoSteiner --- p.33
Chapter 4.3 --- Overview of our Approach --- p.33
Chapter 4.4 --- FST with Virtual Pins --- p.34
Chapter 4.4.1 --- Definition of FST --- p.34
Chapter 4.4.2 --- Notations --- p.36
Chapter 4.4.3 --- Properties of FST with Virtual Pins --- p.36
Chapter 4.5 --- Generation of FST with Virtual Pins --- p.46
Chapter 4.5.1 --- Generation of FST with Two Pins --- p.46
Chapter 4.5.2 --- Generation of FST with 3 or More Pins --- p.48
Chapter 4.6 --- Concatenation of FSTs with Virtual Pins --- p.50
Chapter 4.7 --- Experimental Results --- p.52
Chapter 4.8 --- Summary --- p.53
Chapter 5 --- Conclusion --- p.55
Bibliography --- p.61
49
"Delay driven multi-way circuit partitioning." 2003. http://library.cuhk.edu.hk/record=b5891508.
Full textAbstract:
Wong Sze Hon.Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.
Includes bibliographical references (leaves 88-91).
Abstracts in English and Chinese.
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Preliminaries --- p.1
Chapter 1.2 --- Motivations --- p.1
Chapter 1.3 --- Contributions --- p.3
Chapter 1.4 --- Organization of the Thesis --- p.4
Chapter 2 --- VLSI Physical Design Automation --- p.5
Chapter 2.1 --- Preliminaries --- p.5
Chapter 2.2 --- VLSI Design Cycle [1] --- p.6
Chapter 2.2.1 --- System Specification --- p.6
Chapter 2.2.2 --- Architectural Design --- p.6
Chapter 2.2.3 --- Functional Design --- p.6
Chapter 2.2.4 --- Logic Design --- p.8
Chapter 2.2.5 --- Circuit Design --- p.8
Chapter 2.2.6 --- Physical Design --- p.8
Chapter 2.2.7 --- Fabrication --- p.8
Chapter 2.2.8 --- Packaging and Testing --- p.9
Chapter 2.3 --- Physical Design Cycle [1] --- p.9
Chapter 2.3.1 --- Partitioning --- p.9
Chapter 2.3.2 --- Floorplanning and Placement --- p.11
Chapter 2.3.3 --- Routing --- p.11
Chapter 2.3.4 --- Compaction --- p.12
Chapter 2.3.5 --- Extraction and Verification --- p.12
Chapter 2.4 --- Chapter Summary --- p.12
Chapter 3 --- Recent Approaches on Circuit Partitioning --- p.14
Chapter 3.1 --- Preliminaries --- p.14
Chapter 3.2 --- Circuit Representation --- p.15
Chapter 3.3 --- Delay Modelling --- p.16
Chapter 3.4 --- Partitioning Objectives --- p.19
Chapter 3.4.1 --- Interconnections between Partitions --- p.19
Chapter 3.4.2 --- Delay Minimization --- p.19
Chapter 3.4.3 --- Area and Number of Partitions --- p.20
Chapter 3.5 --- Partitioning Algorithms --- p.20
Chapter 3.5.1 --- Cut-size Driven Partitioning Algorithm --- p.21
Chapter 3.5.2 --- Delay Driven Partitioning Algorithm --- p.32
Chapter 3.5.3 --- Acyclic Circuit Partitioning Algorithm --- p.33
Chapter 4 --- Clustering Based Acyclic Multi-way Partitioning --- p.38
Chapter 4.1 --- Preliminaries --- p.38
Chapter 4.2 --- Previous Works on Clustering Based Partitioning --- p.39
Chapter 4.2.1 --- Multilevel Circuit Partitioning [2] --- p.40
Chapter 4.2.2 --- Cluster-Oriented Iterative-Improvement Partitioner [3] --- p.42
Chapter 4.2.3 --- Section Summary --- p.44
Chapter 4.3 --- Problem Formulation --- p.45
Chapter 4.4 --- Clustering Based Acyclic Multi-Way Partitioning --- p.46
Chapter 4.5 --- Modified Fan-out Free Cone Decomposition --- p.47
Chapter 4.6 --- Clustering Phase --- p.48
Chapter 4.7 --- Partitioning Phase --- p.51
Chapter 4.8 --- The Acyclic Constraint --- p.52
Chapter 4.9 --- Experimental Results --- p.57
Chapter 4.10 --- Chapter Summary --- p.58
Chapter 5 --- Network Flow Based Multi-way Partitioning --- p.61
Chapter 5.1 --- Preliminaries --- p.61
Chapter 5.2 --- Notations and Definitions --- p.62
Chapter 5.3 --- Net Modelling --- p.63
Chapter 5.4 --- Previous Works on Network Flow Based Partitioning --- p.64
Chapter 5.4.1 --- Network Flow Based Min-Cut Balanced Partitioning [4] --- p.65
Chapter 5.4.2 --- Network Flow Based Circuit Partitioning for Time-multiplexed FPGAs [5] --- p.66
Chapter 5.5 --- Proposed Net Modelling --- p.70
Chapter 5.6 --- Partitioning Properties Based on the Proposed Net Modelling --- p.73
Chapter 5.7 --- Partitioning Step --- p.75
Chapter 5.8 --- Constrained FM Post Processing Step --- p.79
Chapter 5.9 --- Experiment Results --- p.81
Chapter 6 --- Conclusion --- p.86
Bibliography --- p.88
50
"VLSI implementation of discrete cosine transform using a new asynchronous pipelined architecture." 2002. http://library.cuhk.edu.hk/record=b5891233.
Full textAbstract:
Lee Chi-wai.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.
Includes bibliographical references (leaves 191-196).
Abstracts in English and Chinese.
Abstract of this thesis entitled: --- p.i
摘要 --- p.iii
Acknowledgements --- p.v
Table of Contents --- p.vii
List of Tables --- p.x
List of Figures --- p.xi
Chapter Chapter1 --- Introduction --- p.1
Chapter 1.1 --- Synchronous Design --- p.1
Chapter 1.2 --- Asynchronous Design --- p.2
Chapter 1.3 --- Discrete Cosine Transform --- p.4
Chapter 1.4 --- Motivation --- p.5
Chapter 1.5 --- Organization of the Thesis --- p.6
Chapter Chapter2 --- Asynchronous Design Methodology --- p.7
Chapter 2.1 --- Overview --- p.7
Chapter 2.2 --- Background --- p.8
Chapter 2.3 --- Past Designs --- p.10
Chapter 2.4 --- Micropipeline --- p.12
Chapter 2.5 --- New Asynchronous Architecture --- p.15
Chapter Chapter3 --- DCT/IDCT Processor Design Methodology --- p.24
Chapter 3.1 --- Overview --- p.24
Chapter 3.2 --- Hardware Architecture --- p.25
Chapter 3.3 --- DCT Algorithm --- p.26
Chapter 3.4 --- Used Architecture and DCT Algorithm --- p.30
Chapter 3.4.1 --- Implementation on Programmable DSP Processor --- p.31
Chapter 3.4.2 --- Implementation on Dedicated Processor --- p.33
Chapter Chapter4 --- New Techniques for Operating Dynamic Logic in Low Frequency --- p.36
Chapter 4.1 --- Overview --- p.36
Chapter 4.2 --- Background --- p.37
Chapter 4.3 --- Traditional Technique --- p.39
Chapter 4.4 --- New Technique - Refresh Control Circuit --- p.40
Chapter 4.4.1 --- Principle --- p.41
Chapter 4.4.2 --- Voltage Sensor --- p.42
Chapter 4.4.3 --- Ring Oscillator --- p.43
Chapter 4.4.4 --- "Counter, Latch and Comparator" --- p.46
Chapter 4.4.5 --- Recalibrate Circuit --- p.47
Chapter 4.4.6 --- Operation Monitoring Circuit --- p.48
Chapter 4.4.7 --- Overall Circuit --- p.48
Chapter Chapter5 --- DCT Implementation on Programmable DSP Processor --- p.51
Chapter 5.1 --- Overview --- p.51
Chapter 5.2 --- Processor Architecture --- p.52
Chapter 5.2.1 --- Arithmetic Unit --- p.53
Chapter 5.2.2 --- Switching Network --- p.56
Chapter 5.2.3 --- FIFO Memory --- p.59
Chapter 5.2.4 --- Instruction Memory --- p.60
Chapter 5.3 --- Programming --- p.62
Chapter 5.4 --- DCT Implementation --- p.63
Chapter Chapter6 --- DCT Implementation on Dedicated DCT Processor --- p.66
Chapter 6.1 --- Overview --- p.66
Chapter 6.2 --- DCT Chip Architecture --- p.67
Chapter 6.2.1 --- ID DCT Core --- p.68
Chapter 6.2.1.1 --- Core Architecture --- p.74
Chapter 6.2.1.2 --- Flow of Operation --- p.76
Chapter 6.2.1.3 --- Data Replicator --- p.79
Chapter 6.2.1.4 --- DCT Coefficients Memory --- p.80
Chapter 6.2.2 --- Combination of IDCT to 1D DCT core --- p.82
Chapter 6.2.3 --- Accuracy --- p.85
Chapter 6.3 --- Transpose Memory --- p.87
Chapter 6.3.1 --- Architecture --- p.89
Chapter 6.3.2 --- Address Generator --- p.91
Chapter 6.3.3 --- RAM Block --- p.94
Chapter Chapter7 --- Results and Discussions --- p.97
Chapter 7.1 --- Overview --- p.97
Chapter 7.2 --- Refresh Control Circuit --- p.97
Chapter 7.2.1 --- Implementation Results and Performance --- p.97
Chapter 7.2.2 --- Discussion --- p.100
Chapter 7.3 --- Programmable DSP Processor --- p.102
Chapter 7.3.1 --- Implementation Results and Performance --- p.102
Chapter 7.3.2 --- Discussion --- p.104
Chapter 7.4 --- ID DCT/IDCT Core --- p.107
Chapter 7.4.1 --- Simulation Results --- p.107
Chapter 7.4.2 --- Measurement Results --- p.109
Chapter 7.4.3 --- Discussion --- p.113
Chapter 7.5 --- Transpose Memory --- p.122
Chapter 7.5.1 --- Simulated Results --- p.122
Chapter 7.5.2 --- Measurement Results --- p.123
Chapter 7.5.3 --- Discussion --- p.126
Chapter Chapter8 --- Conclusions --- p.130
Appendix --- p.133
Operations of switches in DCT implementation of programmable DSP processor --- p.133
C Program for evaluating the error in DCT/IDCT core --- p.135
Pin Assignments of the Programmable DSP Processor Chip --- p.142
Pin Assignments of the 1D DCT/IDCT Core Chip --- p.144
Pin Assignments of the Transpose Memory Chip --- p.147
Chip microphotograph of the 1D DCT/IDCT core --- p.150
Chip Microphotograph of the Transpose Memory --- p.151
Measured Waveforms of 1D DCT/IDCT Chip --- p.152
Measured Waveforms of Transpose Memory Chip --- p.156
Schematics of Refresh Control Circuit --- p.158
Schematics of Programmable DSP Processor --- p.164
Schematics of 1D DCT/IDCT Core --- p.180
Schematics of Transpose Memory --- p.187
References --- p.191
Design Libraries - CD-ROM --- p.197