Books on the topic 'Integrated circuits Very large scale integration Design and construction Testing'

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1

Jakubowski, Andrzej. Diagnostic measurements in LSI/VLSI integrated circuits production. Singapore: World Scientific, 1991.

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2

Jha, Niraj K. Testing and reliable design of CMOS circuits. Boston: Kluwer Academic Publishers, 1990.

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3

Mazumder, Pinaki. Genetic algorithms for VLSI design, layout & test automation. Upper Saddle River, NJ: Prentice Hall PTR, 1999.

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4

International Symposium on Quality Electronic Design (3rd 2002 San Jose, Calif.). International Symposium on Quality Electronic Design: Proceedings : 18-21 March, 2002, San Jose, California. Los Alamitos, California: IEEE Computer Society, 2002.

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5

International Symposium on Quality Electronic Design (2nd 2001 San Jose, Calif.). International Symposium on Quality Electronic Design: Proceedings, 26-28 March, 2001, San Jose, California. Los Alamitos, Calif: IEEE Computer Society, 2001.

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6

International Symposium on Quality Electronic Design (6th 2005 San Jose, Calif.). 6th International Symposium on Quality Electronic Design: Proceedings : March 21-23, 2005, San Jose, California. Los Alamitos, Calif: IEEE Computer Society, 2005.

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7

International Symposium on Quality Electronic Design (7th 2006 San Jose, Calif.). 7th International Symposium on Quality Electronic Design: ISQED 2006, proceedings : 27-29 March 2006, San Jose, California. Los Alamitos, Calif: IEEE Computer Society, 2006.

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8

International, Symposium on Quality Electronic Design (9th 2008 San Jose Calif ). Ninth International Symposium on Quality Electronic Design: ISQED 2008 : proceedings : San Jose, California : 17-19 March 2008. Los Alamitos, Calif: IEEE Computer Society, 2008.

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9

International, Symposium on Quality Electronic Design (8th 2007 San Jose Calif ). 8th International Symposium on Quality Electronic Design: ISQED 2007 : proceedings : San Jose, California : 26-28 March. Los Alamitos, Calif: IEEE Computer Society, 2007.

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10

Fanucci, Luca. An experimental approach to CDMA and interference mitigation: From system architecture to hardware testing through VLSI design. New York: Springer, 2011.

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11

I͡Armolik, V. N. Self-testing VLSI design. Amsterdam: Elsevier, 1993.

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12

Vai, M. Michael. VLSI design. Boca Raton, FL: CRC Press, 2001.

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13

Tsui, Frank F. LSI/VLSI testability design. New York: McGraw-Hill, 1987.

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14

Balkır, Sina. Analog VLSI design automation. Boca Raton, Fla: CRC Press, 2003.

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15

David, Harris. Skew-tolerant circuit design. San Francisco: Morgan Kaufmann Publishers, 2001.

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16

Geiger, Randall L. VLSI design techniques for analog and digital circuits. New York: McGraw, 1990.

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17

Geiger, Randall L. VLSI design techniques for analog and digital circuits. New York: McGraw-Hill Pub. Co., 1990.

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18

Bakoglu, H. B. Circuits, interconnections, and packaging for VLSI. Reading, Mass: Addison-Wesley Pub. Co., 1990.

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19

Hsu, Chi-Ping. Signal routing in integrated circuit layout. Ann Arbor, Mich: UMI Research Press, 1986.

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20

Kahng, Andrew B. On optimal interconnections for VLSI. Boston: Kluwer Academic Publishers, 1995.

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21

Sechen, Carl. VLSI placement and global routing using simulated annealing. Boston: Kluwer Academic Publishers, 1988.

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22

Hollis, Ernest E. Design of VLSI gate array ICs. Englewood Cliffs, NJ: Prentice-Hall, 1987.

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23

Pucknell, Douglas A. Basic VLSI design: Systems and circuits. 2nd ed. New York: Prentice-Hall, 1988.

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24

Peeters, A. Single-rail handshake circuits. Eindhoven, the Netherlands: A. Peeters, 1996.

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25

Kundu, Sandip. Nanoscale CMOS VLSI circuits: Design for manufacturability. New York: McGraw-Hill, 2010.

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26

Weste, Neil H. E. CMOS VLSI design: A circuits and systems perspective. 4th ed. Boston: Addison Wesley, 2011.

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27

Hsu, Yu-chin. Floor planning and global routing in an automated chip design system. Urbana, Ill. (1304 W. Springfield Ave., Urbana 61801-2987): Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1987.

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28

Beerel, Peter A. A designer's guide to VLSI. New York: Cambridge University Press, 2010.

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29

Beerel, Peter A. A Designer's Guide to VLSI Devices. New York: Cambridge University Press, 2010.

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30

Beerel, Peter A. A Designer's Guide to Asynchronous VLSI. New York: Cambridge University Press, 2010.

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31

Uyemura, John P. Chip design for submicron VLSI: CMOS layout and simulation. Toronto: Thomson/Nelson, 2006.

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32

Uyemura, John P. Chip design for submicron VLSI: CMOS layout and simulation. Ottawa: Thomson, 2004.

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33

IEEE, VLSI Test Symposium (1992 Atlantic City N. J. ). Digest of papers: 1992 IEEE VLSLI Test Conference 10th anniversary, April 7-9, 1992, Bally's Park Place Casino Hotel, Atlantic City, New Jersey, USA : design, test, and appliction--ASICs and systems-on-a-chip. [New York]: Institute of Electrical and Electronics Engineers, 1992.

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34

Price, T. E. Introduction to VLSI technology. New York: Prentice Hall, 1994.

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35

Kraśniewski, Andrzej. Projektowanie samotestowalnych układów cyfrowych wielkiej skali integracji. Warszawa: Wydawnictwa Politechniki Warszawskiej, 1989.

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36

Horne, Douglas F. Microcircuit production technology. Bristol [Avon]: A. Hilger, 1986.

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37

Rubin, Steven. Computer aids for VLSI design. Reading, Mass: Addison-Wesley, 1987.

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38

Walker, Duncan Moore Henry. Yield simulation for integrated circuits. Boston: Kluwer Academic Publishers, 1987.

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39

Attia, John Okyere. PSPICE and MATLAB for electronics: An integrated appraoch. Boca Raton, Fla: CRC Press, 2002.

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40

Cheng, Kwang-Ting. Unified methods for VLSI simulation and test generation. Boston: Kluwer Academic Publishers, 1989.

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41

Brackenbury, Linda E. M. Design of VLSI systems -: A practical introduction. London: Macmillan, 1987.

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42

Wolf, Wayne Hendrix. Modern VLSI design: IP-based design. 4th ed. Upper Saddle River, NJ: Prentice Hall, 2008.

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43

Wolf, Wayne Hendrix. Modern VLSI design: System-onchip design. 3rd ed. Upper Saddle River, NJ: Prentice Hall PTR, 2002.

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44

Pucknell, Douglas A. Basic VLSI design. 3rd ed. Sydney: Prentice Hall, 1994.

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45

Wolf, Wayne Hendrix. Modern VLSI design: System-on-chip design. 3rd ed. Upper Saddle River, N.J: Prentice Hall PTR, 2002.

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46

NASA Symposium on VLSI Design (3rd 1991 University of Idaho). 3rd NASA Symposium on VLSI Design: University of Idaho, Moscow, Idaho, October 30-31, 1991. [Moscow, Idaho: The University, 1991.

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47

International Symposium on Physical Design (1999 Monterey, Calif.). Proceedings, 1999 International Symposium on Physical Design: ISPD-99 : Monterey, CA, April 12-14, 1999. New York: Association for Computing Machinery, 1999.

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48

NASA Symposium on VLSI Design (4th 1992 University of Idaho). 4th NASA Symposium on VLSI Design: University of Idaho, Moscow, Idaho, October 29-30, 1992. [Moscow, Idaho: The University, 1992.

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49

Idaho), NASA SERC 1990 Symposium on VLSI Design (1st 1990 University of. NASA SERC 1990 Symposium on VLSI Design: University of Idaho, Moscow, Idaho, January 24, 1990. [Moscow: The University, 1990.

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50

Edinburgh Workshop on VLSI (1985). Formal aspects of VLSI design: Proceedings of the 1985 Edinburgh Workshop on VLSI, Edinburgh, Scotland, U.K. Edited by Milne George J. 1952- and Subrahmanyam P. A. Amsterdam: North Holland, 1986.

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