Academic literature on the topic 'Integrated circuits Very large scale integration Design and construction Mathematical models'

Recently, microelectronics designs have reached extremely high operating frequencies as well as very small die and package sizes. This has made signal integrity an important bottleneck in the design process, and resulted in the inclusion of signal integrity simulation in the computer aided design flow. However, such simulations are often difficult because in many cases it is impossible to derive analytical models for certain passive elements, and the only available data are frequency-domain measurements or full-wave simulations. Furthermore, at such high frequencies these components are distributed in nature and require a large number of poles to be properly characterized. Simple lumped equivalent circuits are therefore difficult to obtain, and more systematic approaches are required. In this thesis we study the Vector Fitting techniques for obtaining such equivalent model and propose a more streamlined approach for preserving passivity while maintaining accuracy.

Bibliography: leaves 255-280
viii, 280 leaves : ill ; 30 cm.
Title page, contents and abstract only. The complete thesis in print form is available from the University Library.
Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1992

Yuen Wing-seung.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.
Includes bibliographical references (leaves [116]-[122]).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgments --- p.iii
List of Figures --- p.viii
List of Tables --- p.xii
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivations and Aims --- p.1
Chapter 1.2 --- Contributions --- p.3
Chapter 1.3 --- Dissertation Overview --- p.4
Chapter 2 --- Physical Design and Floorplanning in VLSI Circuits --- p.6
Chapter 2.1 --- VLSI Design Flow --- p.6
Chapter 2.2 --- Floorplan Design --- p.8
Chapter 2.2.1 --- Problem Formulation --- p.9
Chapter 2.2.2 --- Types of Floorplan --- p.10
Chapter 3 --- Floorplanning Representations --- p.12
Chapter 3.1 --- Polish Expression(PE) [WL86] --- p.12
Chapter 3.2 --- Bounded-Sliceline-Grid(BSG) [NFMK96] --- p.14
Chapter 3.3 --- Sequence Pair(SP) [MFNK95] --- p.17
Chapter 3.4 --- O-tree(OT) [GCY99] --- p.19
Chapter 3.5 --- B*-tree(BT) [CCWW00] --- p.21
Chapter 3.6 --- Corner Block List(CBL) [HHC+00] --- p.22
Chapter 4 --- Optimization Technique in Floorplan Design --- p.27
Chapter 4.1 --- General Optimization Methods --- p.27
Chapter 4.1.1 --- Simulated Annealing --- p.27
Chapter 4.1.2 --- Genetic Algorithm --- p.29
Chapter 4.1.3 --- Integer Programming Method --- p.31
Chapter 4.2 --- Shape Optimization --- p.33
Chapter 4.2.1 --- Shape Curve --- p.33
Chapter 4.2.2 --- Lagrangian Relaxation --- p.34
Chapter 5 --- Literature Review on Interconnect Driven Floorplanning --- p.37
Chapter 5.1 --- Placement Constraint in Floorplan Design --- p.37
Chapter 5.1.1 --- Boundary Constraints --- p.37
Chapter 5.1.2 --- Pre-placed Constraints --- p.39
Chapter 5.1.3 --- Range Constraints --- p.41
Chapter 5.1.4 --- Symmetry Constraints --- p.42
Chapter 5.2 --- Timing Analysis Method --- p.43
Chapter 5.3 --- Buffer Block Planning and Congestion Control --- p.45
Chapter 5.3.1 --- Buffer Block Planning --- p.45
Chapter 5.3.2 --- Congestion Control --- p.50
Chapter 6 --- Clustering Constraint in Floorplan Design --- p.53
Chapter 6.1 --- Problem Definition --- p.53
Chapter 6.2 --- Overview --- p.54
Chapter 6.3 --- Locating Neighboring Modules --- p.56
Chapter 6.4 --- Constraint Satisfaction --- p.62
Chapter 6.5 --- Multi-clustering Extension --- p.64
Chapter 6.6 --- Cost Function --- p.64
Chapter 6.7 --- Experimental Results --- p.65
Chapter 7 --- Interconnect Driven Multilevel Floorplanning Approach --- p.69
Chapter 7.1 --- Multilevel Partitioning --- p.69
Chapter 7.1.1 --- Coarsening Phase --- p.70
Chapter 7.1.2 --- Refinement Phase --- p.70
Chapter 7.2 --- Overview of Multilevel Floorplanner --- p.72
Chapter 7.3 --- Clustering Phase --- p.73
Chapter 7.3.1 --- Clustering Methods --- p.73
Chapter 7.3.2 --- Area Ratio Constraints --- p.75
Chapter 7.3.3 --- Clustering Velocity --- p.76
Chapter 7.4 --- Refinement Phase --- p.77
Chapter 7.4.1 --- Temperature Control --- p.79
Chapter 7.4.2 --- Cost Function --- p.80
Chapter 7.4.3 --- Handling Shape Flexibility --- p.80
Chapter 7.5 --- Experimental Results --- p.81
Chapter 7.5.1 --- Data Set Generation --- p.82
Chapter 7.5.2 --- Temperature Control --- p.82
Chapter 7.5.3 --- Packing Results --- p.83
Chapter 8 --- Study of Non-slicing Floorplan Representations --- p.89
Chapter 8.1 --- Analysis of Different Floorplan Representations --- p.89
Chapter 8.1.1 --- Complexity --- p.90
Chapter 8.1.2 --- Types of Floorplans --- p.92
Chapter 8.2 --- T-junction Orientation Property --- p.97
Chapter 8.3 --- Twin Binary Tree Representation for Mosaic Floorplan --- p.103
Chapter 8.3.1 --- Previous work --- p.103
Chapter 8.3.2 --- Twin Binary Tree Construction --- p.105
Chapter 8.3.3 --- Floorplan Construction --- p.109
Chapter 9 --- Conclusion --- p.114
Chapter 9.1 --- Summary --- p.114
Bibliography --- p.116
Chapter A --- Clustering Constraint Data Set --- p.123
Chapter A.1 --- ami33 --- p.123
Chapter A.1.1 --- One cluster --- p.123
Chapter A.1.2 --- Multi-cluster --- p.123
Chapter A.2 --- ami49 --- p.124
Chapter A.2.1 --- One cluster --- p.124
Chapter A.2.2 --- Multi-cluster --- p.124
Chapter A.3 --- playout --- p.124
Chapter A.3.1 --- One cluster --- p.124
Chapter A.3.2 --- Multi-cluster --- p.125
Chapter B --- Multilevel Data Set --- p.126
Chapter B.l --- data_100 --- p.126
Chapter B.2 --- data_200 --- p.127
Chapter B.3 --- data_300 --- p.129
Chapter B.4 --- data_400 --- p.131
Chapter B.5 --- data_500 --- p.133

by Lam Shiu-chung.
Thesis (M.Phil.)--Chinese University of Hong Kong, 1999.
Includes bibliographical references (leaves 107-113).
Abstracts in English and Chinese.
List of Figures --- p.v
List of Tables --- p.vii
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Task Scheduling Problem and Lower Bound --- p.3
Chapter 1.3 --- Organization of the Thesis --- p.4
Chapter 2 --- Teamwork-Task Scheduling Problem --- p.5
Chapter 2.1 --- Problem Statement and Notations --- p.5
Chapter 2.2 --- Classification of Scheduling --- p.7
Chapter 2.3 --- Computational Complexity --- p.9
Chapter 2.4 --- Literature Review --- p.12
Chapter 2.4.1 --- Unrelated Machines Scheduling Environment --- p.12
Chapter 2.4.2 --- Multiprocessors Scheduling Problem --- p.13
Chapter 2.4.3 --- Search Algorithms --- p.14
Chapter 2.4.4 --- Lower Bounds --- p.15
Chapter 2.5 --- Summary --- p.17
Chapter 3 --- Fundamentals of Genetic Algorithms --- p.18
Chapter 3.1 --- Initial Inspiration --- p.18
Chapter 3.2 --- An Elementary Genetic Algorithm --- p.20
Chapter 3.2.1 --- "Genes, Chromosomes and Representations" --- p.20
Chapter 3.2.2 --- Population Pool --- p.22
Chapter 3.2.3 --- Evaluation Module --- p.22
Chapter 3.2.4 --- Reproduction Module --- p.22
Chapter 3.2.5 --- Genetic Operators: Crossover and Mutation --- p.23
Chapter 3.2.6 --- Parameters --- p.24
Chapter 3.3 --- A Brief Note to the Background Theory --- p.25
Chapter 3.4 --- Key Factors for the Success --- p.27
Chapter 4 --- Tasks Scheduling using Genetic Algorithms --- p.28
Chapter 4.1 --- Details of Scheduling Problem --- p.28
Chapter 4.2 --- Chromosome Coding --- p.32
Chapter 4.2.1 --- Job Priority Sequence --- p.33
Chapter 4.2.2 --- Engineer Priority Sequence --- p.33
Chapter 4.2.3 --- An Example Chromosome Interpretation --- p.34
Chapter 4.3 --- Fitness Evaluation --- p.37
Chapter 4.4 --- Parent Selection --- p.38
Chapter 4.5 --- Genetic Operators and Reproduction --- p.40
Chapter 4.5.1 --- Job Priority Crossover (JOB-CRX) --- p.40
Chapter 4.5.2 --- Job Priority Mutation (JOB-MUT) --- p.40
Chapter 4.5.3 --- Engineer Priority Mutation (ENG-MUT) --- p.42
Chapter 4.5.4 --- Reproduction: New Population --- p.42
Chapter 4.6 --- Replacement Strategy --- p.43
Chapter 4.7 --- The Complete Genetic Algorithm --- p.44
Chapter 5 --- Lower Bound on Optimal Makespan --- p.46
Chapter 5.1 --- Introduction --- p.46
Chapter 5.2 --- Definitions and Assumptions --- p.48
Chapter 5.2.1 --- Task Graph --- p.48
Chapter 5.2.2 --- Graph Partitioning --- p.49
Chapter 5.2.3 --- Activity and Load Density --- p.51
Chapter 5.2.4 --- Assumptions --- p.52
Chapter 5.3 --- Concepts of Lower Bound on the Minimal Time (LBMT) --- p.53
Chapter 5.3.1 --- Previous Bound (LBMTF) --- p.53
Chapter 5.3.2 --- Bound in other form --- p.54
Chapter 5.3.3 --- Improved Bound (LBMTJR） --- p.56
Chapter 5.4 --- Lower bound: Task graph reconstruction + LBMTJR --- p.59
Chapter 5.4.1 --- Problem reduction and Assumptions --- p.60
Chapter 5.4.2 --- Scenario I --- p.61
Chapter 5.4.3 --- Scenario II --- p.63
Chapter 5.4.4 --- An Example --- p.67
Chapter 6 --- Computational Results and Discussions --- p.73
Chapter 6.1 --- Parameterization of the GA --- p.73
Chapter 6.2 --- Computational Results --- p.75
Chapter 6.3 --- Performance Evaluation --- p.81
Chapter 6.3.1 --- Solution Quality --- p.81
Chapter 6.3.2 --- Computational Complexity --- p.86
Chapter 6.4 --- Effects of Machines Eligibility --- p.88
Chapter 6.5 --- Future Direction --- p.90
Chapter 7 --- Conclusion --- p.92
Chapter A --- Tasks data of problem sets in section 6.2 --- p.94
Chapter A.l --- Problem 1: 19 tasks --- p.95
Chapter A.2 --- Problem 2: 21 tasks --- p.97
Chapter A.3 --- Problem 3: 19 tasks --- p.99
Chapter A.4 --- Problem 4: 23 tasks --- p.101
Chapter A.5 --- Problem 5: 27 tasks --- p.104
Bibliography --- p.107

This thesis describes the implementation of a VLSI motion detector based on the Template model. Analog circuits are used to facilitate the differentiation and digital modules are used for storing the data, communication and processing.
Thesis (M.Eng.Sc.) -- University of Adelaide, Dept. of Electrical and Electronic Engineering, 1994