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Relevant bibliographies by topics / Integrated circuits Very large scale integration

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Academic literature on the topic 'Integrated circuits Very large scale integration'

Author: Grafiati

Published: 4 June 2021

Last updated: 30 July 2024

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Journal articles on the topic "Integrated circuits Very large scale integration"

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Yang, Boyu. "Very Large-Scale Integration Circuit and Its Current Status Analysis." Highlights in Science, Engineering and Technology 71 (November 28, 2023): 421–27. http://dx.doi.org/10.54097/hset.v71i.14627.

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The development of Very Large Scale Integration (VLSI) has become very relevant to our lives, and although many of the technologies have matured, scientists are still actively exploring and innovating them. This article is a basic introduction to the composition and advanced technology of large-scale integrated circuits, focusing on transistors and the basic components it consists of, as well as the design of integrated circuits, manufacturing and measurement technology. Very Large Scale Integration Circuit, the transistor is the most basic component of the original, to the low-power CMOS tube is the most widely used, they form a logic gate and storage elements, to achieve a variety of basic functions of the circuit, while the circuit also exists to provide signal distribution and interconnection of the clock network, the optimization of the design of the contemporary research is also a hot spot. In recent years, the progress of the chip can not be separated from the development of new technologies, SOC technology, low-power technology and detection technology plays an important role in the promotion.

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M, Thillai Rani, Rajkumar R, Sai Pradeep K.P, Jaishree M, and Rahul S.G. "Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits." ITM Web of Conferences 56 (2023): 01005. http://dx.doi.org/10.1051/itmconf/20235601005.

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High-level synthesis (HLS) is utilized for high-performance and energy-efficient heterogeneous systems designing. HLS is assist in field-programmable gate array circuits designing where hardware implementations are refined and replaced in target device. However, the power-process-voltage-temperature-delay (PPVTD) variation in VLSI circuits undergoes many problems and reduced the performance. In order to address these problems, C4.5 with eXtreme Gradient Boosting Classification based High Level Synthesis (C4.5-XGBCHLS) Method is designed for afford better runtime adaptability (RA) with minimal error rate. VLSI circuits are designed using the behavioral input and results are measured at running condition. When VLSI circuit’s results get reduced, the language description of the circuit is considered as an input. Then, compilation process convert high level specification into Intermediate Representation (IR) in control/data flow graph (CDFG). CDFG computes data and control dependencies among operations. eXtreme Gradient Boosting (XGBoost) Classifier is exploited in C4.5-XGBCHLS method to classify the error causing functional unit (FU) with minimal error rate. XGBoost Classifier exploited C4.5 decision tree as base classifier to enhance classification of error causing FU in VLSI circuits. After that, FU gets allocated in place of error causing FU from functional library based on the design objectives and PPVTD variations. Finally, operation scheduling and binding process is executed for register transfer level (RTL) generation to form VLSI circuits with improved RA. The simulation results shows that the C4.5-XGBCHLS method enhances the performance of functional unit selection accuracy (FUSA) with minimal error rate (ER) and circuit adaptability time (CAT).

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Patel, Ambresh, and Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, no. 01 (January 30, 2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.

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The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits because it requires fewer transistors, has lower parasitic capacitance, is faster, and enables pipelinedsystem architecture with glitch-free circuits. It has, however, increased power dissipation. Both types of CMOS circuits withlow power dissipation overcome their own shortcomings.This paper discusses dynamic CMOS logic circuits and their structures. Various logics are also discussed and on the basisof the results obtained, logic which is best suited for designing CMOS logic circuit will be found out. The logic on the basisof structure layout and design which gives best results for high-speed VLSI circuits, is found out.

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Iwai, Hiroshi, Kuniyuki Kakushima, and Hei Wong. "CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING." International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 43–81. http://dx.doi.org/10.1142/s0129156406003539.

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The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.

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Madhura, S. "A Review on Low Power VLSI Design Models in Various Circuits." Journal of Electronics and Informatics 4, no. 2 (July 8, 2022): 74–81. http://dx.doi.org/10.36548/jei.2022.2.002.

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Low power design is one of the primary goals for any integrated circuits. Very Large-Scale Integration (VLSI) is a kind of Integrated Circuit (IC) that consists of hundreds and hundreds of transistor connection into a small chip. The communication and computer applications have grown very faster in the past decade due to the development of VLSI circuit design as microcontroller and microprocessors. However, still the research on VLSI are moving faster towards the scope of power and area minimization. The paper gives an overview about the recent methodologies that have been developed for the performance improvement of VLSI design and it shows the future directions of the areas that are to be concentrated on VLSI circuit design.

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Im, James S., and Robert S. Sposili. "Crystalline Si Films for Integrated Active-Matrix Liquid-Crystal Displays." MRS Bulletin 21, no. 3 (March 1996): 39–48. http://dx.doi.org/10.1557/s0883769400036125.

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The fabrication of thin-film-transistor (TFT) devices on a transparent substrate lies at the heart of active-matrix-liquid-crystal-display (AMLCD) technology. This is both good and bad. On one hand it is a difficult task to manufacture millions of intricate semiconductor devices reliably over such large display substrates. On the positive side, AMLCD technology can aspire to become much more than a “display” technology. The idea is as follows: It is possible for one to readily fabricate additional transistors to execute various electronic functions—those that would otherwise be handled by separate large-scale-integration (LSI) and very large-scale-integration (VLSI) circuits—on the periphery of the display. Since this can be done, in principle, with no—or a minimal number of—additional processing steps, substantial cost reduction is possible and significant value can be added to the final product.Doing so and doing it well can ultimately lead to “system-on-glass” products in which the entire electronic circuitry needed for a product is incorporated directly onto a glass substrate. This means that integrated active-matrix liquid-crystal displays (IAMLCDs) have the potential to bypass conventional Si-wafer-based products and may lead TFT technology to compete directly against Si-wafer-based monolithic integrated circuits.

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Beck, Anthony, Franziska Obst, Mathias Busek, Stefan Grünzner, Philipp Mehner, Georgi Paschew, Dietmar Appelhans, Brigitte Voit, and Andreas Richter. "Hydrogel Patterns in Microfluidic Devices by Do-It-Yourself UV-Photolithography Suitable for Very Large-Scale Integration." Micromachines 11, no. 5 (May 2, 2020): 479. http://dx.doi.org/10.3390/mi11050479.

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The interest in large-scale integrated (LSI) microfluidic systems that perform high-throughput biological and chemical laboratory investigations on a single chip is steadily growing. Such highly integrated Labs-on-a-Chip (LoC) provide fast analysis, high functionality, outstanding reproducibility at low cost per sample, and small demand of reagents. One LoC platform technology capable of LSI relies on specific intrinsically active polymers, the so-called stimuli-responsive hydrogels. Analogous to microelectronics, the active components of the chips can be realized by photolithographic micro-patterning of functional layers. The miniaturization potential and the integration degree of the microfluidic circuits depend on the capability of the photolithographic process to pattern hydrogel layers with high resolution, and they typically require expensive cleanroom equipment. Here, we propose, compare, and discuss a cost-efficient do-it-yourself (DIY) photolithographic set-up suitable to micro-pattern hydrogel-layers with a resolution as needed for very large-scale integrated (VLSI) microfluidics. The achievable structure dimensions are in the lower micrometer scale, down to a feature size of 20 µm with aspect ratios of 1:5 and maximum integration densities of 20,000 hydrogel patterns per cm². Furthermore, we demonstrate the effects of miniaturization on the efficiency of a hydrogel-based microreactor system by increasing the surface area to volume (SA:V) ratio of integrated bioactive hydrogels. We then determine and discuss a correlation between ultraviolet (UV) exposure time, cross-linking density of polymers, and the degree of immobilization of bioactive components.

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Siddesh, K. B., S. Roopa, Parveen B. A. Farzana, and T. Tanuja. "Design of duty cycle correction circuit using ASIC implementation for high speed communication." i-manager’s Journal on Electronics Engineering 13, no. 3 (2023): 33. http://dx.doi.org/10.26634/jele.13.3.19969.

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This research proposed an accurate Duty Cycle Correction (DCC) circuit for high-frequency systems with high measurement accuracy. It is a crucial component of Very Large Scale Integration (VLSI) circuits and is applied as a percentage of the measured average power of a modulated signal to obtain the signal power. This circuit uses two stages of correction, with the first stage performing course correction and the second stage performing fine corrections. This allows the power to be determined during the pulse given the measurement of the average power of a modulated signal with a known duty cycle. DCC have improved stability, correction range, and operating frequency compared with mixed-signal and all-digital DCCs. In this analysis, the duty cycle correction circuits and their significance in Application Specific Integrated Circuit (ASIC) design, along with typical implementation methods, are discussed.

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Li, Jian, Robert Blewer, and J. W. Mayer. "Copper-Based Metallization for ULSI Applications." MRS Bulletin 18, no. 6 (June 1993): 18–21. http://dx.doi.org/10.1557/s088376940004728x.

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Multilevel metallization of very large-scale integrated (VLSI) circuits has become an area of intense research interest as devices are scaled down in order to increase circuit density. As device dimensions approach the submicron regime, reliability becomes more of an issue. Metallization generally requires good conductivity, electromigration resistance, controllable contact performance, corrosion resistance, adherence, thermal stability, bondability, ability to be patterned into a desirable geometry, and economic feasibility.Aluminum and its alloys have been commonly used as the main metallization materials because they meet most of the metallization requirements for microelectronic devices. Aluminum, however, suffers from major limitations, such as elec-tromigration and stress-voiding induced open-circuit failure. For the development of ultralarge-scale integration (ULSI) for fast-switching-speed devices, the electrical resistivities of aluminum and its alloys are not low enough. As the minimum geometry is scaled down to one-quarter micron, aluminum and its alloys potentially will be replaced by other materials such as Cu, Au, or superconductors for on-chip interconnection.

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Dove, Lewis. "Multi-Layer Ceramic Packaging for High Frequency Mixed-Signal VLSI ASICS." Journal of Microelectronics and Electronic Packaging 6, no. 1 (January 1, 2009): 38–41. http://dx.doi.org/10.4071/1551-4897-6.1.38.

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Mixed-signal Application Specific Integrated Circuits (ASICs) have traditionally been used in test and measurement applications for a variety of functions such as data converters, pin electronics circuitry, drivers, and receivers. Over the past several years, the complexity, power density, and bandwidth of these chips has increased dramatically. This has necessitated dramatic changes in the way these chips have been packaged. As the chips have become true VLSI (Very Large Scale Integration) ICs, the number of I/Os have become too large to interconnect with wire bonds. Thus, it has become necessary to utilize flip chip interconnects. Also, the bandwidth of the high-speed signal paths and clocks has increased into the multi Gbit or GHz ranges. This requires the use of packages with good high-frequency performance which are designed using microwave circuit techniques to optimize signal integrity and to minimize signal crosstalk and noise.

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Dissertations / Theses on the topic "Integrated circuits Very large scale integration"

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Hong, Won-kook. "Single layer routing : mapping topological to geometric solutions." Thesis, McGill University, 1986. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66030.

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Matsumori, Barry Alan. "QUALIFICATION RESEARCH FOR RELIABLE, CUSTOM LSI/VLSI ELECTRONICS." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275313.

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Jafar, Mutaz 1960. "THERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGING." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276959.

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Voranantakul, Suwan 1962. "CONDUCTIVE AND INDUCTIVE CROSSTALK COUPLING IN VLSI PACKAGES." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/277037.

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Dagenais, Michel R. "Timing analysis for MOSFETS, an integrated approach." Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=75459.

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Timing and electrical verification is an essential part of the design of VLSI digital MOS circuits. It consists of determining the maximum operating frequency of a circuit, and verifying that the circuit will always produce the expected logical behavior at or under this frequency. This complex task requires considerable computer and human resources.
The classical simulation approach cannot be used to insure the timing and electrical correctness of the large circuits that are now being designed. The huge number of possible states in large circuits renders this method impractical. Worst-case analysis tools alleviate the problem by restricting the analysis to a limited set of states which correspond to the worst-case operating conditions. However, existing worst-case analysis tools for MOS circuits present several problems. Their accuracy is inherently limited since they use a switch-level model. Also, these procedures have a high computational complexity because they resort to path enumeration to find the latest path in each transistor group. Finally, they lack the ability to analyze circuits with arbitrarily complex clocking schemes.
In this text, a new procedure for circuit-level timing analysis is presented. Because it works at electronic circuit level, the procedure can detect electrical errors, and attains an accuracy that is impossible to attain by other means. Efficient algorithms, based on graph theory, have been developed to partition the circuits in a novel way, and to recognize series and parallel combinations. This enables the efficient computation of worst-case, earliest and latest, waveforms in the circuit, using specially designed algorithms. The new procedure extracts automatically the timing requirements from these waveforms and can compute the clocking parameters, including the maximum clock frequency, for arbitrarily complex clocking schemes.
A computer program was written to demonstrate the effectiveness of the new procedure and algorithms developed. It has been used to determine the clocking parameters of circuits using different clocking schemes. The accuracy obtained on these parameters is around 5 to 10% when compared with circuit-level simulations. The analysis time grows linearly with the circuit size and is approximately 0.5s per transistor, on a microVAX II computer. This makes the program suitable for VLSI circuits.

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Liu, Yansong. "Passivity checking and enforcement in VLSI model reduction exercise." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B41290690.

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Hong, Seong-Kwan. "Performance driven analog layout compiler." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/15037.

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Davis, Jeffrey Alan. "A hierarchy of interconnect limits and opportunities for gigascale integration (GSI)." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15803.

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Anbalagan, Pranav. "Limitations and opportunities for wire length prediction in gigascale integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/22670.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007.
Committee Chair: Dr. Jeff Davis; Committee Member: Dr. James D. Meindl; Committee Member: Dr. Paul Kohl; Committee Member: Dr. Scott Wills; Committee Member: Dr. Sung Kyu Lim.

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Ivanov, André. "Dynamic testibility measures and their use in ATPG." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63324.

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Books on the topic "Integrated circuits Very large scale integration"

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Fco, López José, Pavlidis Dimitris, Montiel-Nelson Juan A, and Society of Photo-optical Instrumentation Engineers., eds. VLSI circuits and systems. Bellingham, Wash. : SPIE: SPIE, 2003.

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1948-, Fuchs Henry, ed. 1985 Chapel Hill Conference on Very Large Scale Integration. [Rockville, Md.]: Computer Science Press, 1985.

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name, No. VLSI circuits and systems: 19-21 May 2003, Maspalomas, Gran Canaria, Spain. Bellingham, WA: SPIE, 2003.

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Churiwala, Sanjay. Principles of VLSI RTL design: A practical guide. New York: Springer, 2011.

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Wanhammar, Lars. DSP integrated circuits. San Diego, Calif: Academic, 1998.

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Riesgo, Teresa, Eduardo de la Torre, and Leandro Soares Indrusiak. VLSI circuits and systems IV: 4-6 May 2009, Dresden, Germany. Edited by SPIE Europe, VDE/VDI-Gesellschaft für Mikroelektronik, Mikro- und Feinwerktechnik, and SPIE (Society). Bellingham, Wash: SPIE, 2009.

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Riesgo, Teresa. VLSI circuits and systems V: 18-20 April 2011, Prague, Czech Republic. Edited by SPIE (Society). Bellingham, Wash: SPIE, 2011.

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Dillinger, Thomas E. VLSI engineering. Englewood Cliffs, N.J: Prentice-Hall, 1988.

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B, Glendinning William, and Helbert John N, eds. Handbook of VLSI microlithography: Principles, technology, and applications. Park Ridge, N.J., U.S.A: Noyes Publications, 1991.

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David, Harris. Skew-tolerant circuit design. San Francisco: Morgan Kaufmann Publishers, 2001.

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Book chapters on the topic "Integrated circuits Very large scale integration"

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Maly, Wojciech. "Feasibility of Large Area Integrated Circuits." In Wafer Scale Integration, 31–56. Boston, MA: Springer US, 1989. http://dx.doi.org/10.1007/978-1-4613-1621-3_2.

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Ghate, P. B. "Metallization for Very Large-Scale Integrated Circuits." In Handbook of Advanced Semiconductor Technology and Computer Systems, 181–228. Dordrecht: Springer Netherlands, 1988. http://dx.doi.org/10.1007/978-94-011-7056-7_6.

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Rachmuth, Guy, and Chi-Sang Poon. "In-Silico Model of NMDA and Non-NMDA Receptor Activities Using Analog Very-Large-Scale Integrated Circuits." In Advances in Experimental Medicine and Biology, 171–75. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/0-387-27023-x_26.

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Gebregiorgis, Anteneh, Rajendra Bishnoi, and Mehdi B. Tahoori. "Reliability Analysis and Mitigation of Near-Threshold Voltage (NTC) Caches." In Dependable Embedded Systems, 303–34. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_13.

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AbstractNear-threshold computing (NTC) has significant role in reducing the energy consumption of modern very large-scale integrated circuits designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the utmost NTC benefits. This chapter presents a comprehensive cross-layer reliability analysis framework to assess the effect of soft error, aging, and process variation in the operation of near-threshold voltage caches. The objective is to quantify the reliability of different SRAM designs, evaluate voltage scaling potential of caches, and to find a reliability-performance optimal cache organization for an NTC microprocessor. In this chapter, the soft error rate (SER) and static noise margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit, and architecture-level analysis.

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Capmany, José, and Daniel Pérez. "Practical Implementation of Programmable Photonic Circuits." In Programmable Integrated Photonics, 178–226. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198844402.003.0006.

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In covering the fundamentals and ideal implementation of integrated multi-port interferometers and waveguide meshes, we saw that solutions with larger integration density of programmable unit cells enables the synthesis of more complex circuits. However, photonic integrated circuits (PICs) generally suffer from design and fabrication errors and other non-ideal working conditions, which compromises performance and scalability. In addition, PICs require the development of two additional tiers (electronic hardware and software) to allow their programmability, optimisation and (re)configuration. This chapter introduces basic practical considerations of programmable PIC design and reviews experimental demonstrations of both multi-port interferometers and waveguide mesh arrangements. It analyses the main error sources and their impact on circuit performance and investigates the most challenging evolution obstacles for very large-scale programmable PICs. It introduces an analytical method for arbitrary waveguide mesh analysis. Finally, it presents a general architecture for the control subsystem and introduces the software framework and main algorithms.

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Lee, Chang Yeol. "Transistor Degradations in Very Large-Scale-Integrated CMOS Technologies." In Very-Large-Scale Integration. InTech, 2018. http://dx.doi.org/10.5772/intechopen.68825.

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Zaidi, Muhaned, Ian Grout, and Abu Khari A’ain. "Operational Amplifier Design in CMOS at Low-Voltage for Sensor Input Front-End Circuits in VLSI Devices." In Very-Large-Scale Integration. InTech, 2018. http://dx.doi.org/10.5772/intechopen.68815.

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Kiran B., Raghu N., and Manjunatha K. N. "VLSI Implementation of a High-Speed Pipeline A/D Converter." In Role of 6G Wireless Networks in AI and Blockchain-Based Applications, 112–30. IGI Global, 2023. http://dx.doi.org/10.4018/978-1-6684-5376-6.ch005.

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In very large-scale-integrated (VLSI) design, a challenge is to increase the speed without compromising the power consumption in an analog and mixed mode signal circuit. This research work is carried out to design a 12-bit pipeline A/D converter (ADC) of 400MS/s sampling rate to meet the high computing requirements. The design is focused to determine high speed and resolution in pipeline ADC to cater different applications. The main advantages of pipeline method are simple to implement, more flexible to improve the speed, and makes layout design simple. A proposed technique holds sample and hold circuit (S/H), multiplying DAC, comparator, and operational transconductance amplifier (OTA) to design the pipeline ADC architecture. OTA is used to convert differential input voltage into current with the help of a switched capacitor integrator module.

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Möschwitzer, Albrecht. "Physical design considerations." In Semiconductor devices, circuits, and systems, 321–41. Oxford University PressOxford, 1991. http://dx.doi.org/10.1093/oso/9780198593744.003.0005.

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Abstract There are many layout design styles, the choice of which depends on the type and size of the IC. Basically we have two main classes of I Cs: standard integrated circuits (SI Cs); and application-specific integrated circuits (ASICs). TTL, CMȮS, and ECL SSI and MSI circuits containing several kinds of logic gates and macrocells (registers, counters etc., see chapter 3) belong to the class of SICs. Standard large-scale integration (LSI) and (VLSI) circuits are microprocessors and semiconductor memories (see the memory chip in Fig. 5.2). The main features of standard integrated circuits are: support of a wide range of applications; high-volume production; and low price.

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Lee, Joseph Ya-min, and Benjamin Chihming Lai. "The electrical properties of high-dielectric-constant and ferroelectric thin films for very large scale integration circuits." In Handbook of Thin Films, 1–98. Elsevier, 2002. http://dx.doi.org/10.1016/b978-012512908-4/50037-0.

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Conference papers on the topic "Integrated circuits Very large scale integration"

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Gunti, Nagendra Babu, Aman Khatri, and Karthikeyan Lingasubramanian. "Realizing a security aware triple modular redundancy scheme for robust integrated circuits." In 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2014. http://dx.doi.org/10.1109/vlsi-soc.2014.7004183.

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Chusseau, Laurent, Rachid Omarouayache, Jeremy Raoult, Sylvie Jarrix, Philippe Maurine, Karim Tobich, Alexandre Bover, et al. "Electromagnetic analysis, deciphering and reverse engineering of integrated circuits (E-MATA HARI)." In 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2014. http://dx.doi.org/10.1109/vlsi-soc.2014.7004189.

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Michailidis, Anastasios, Thomas Noulis, and Kostas Siozios. "Linear and Periodic State Integrated Circuits Noise Simulation Benchmarking." In 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2022. http://dx.doi.org/10.1109/vlsi-soc54400.2022.9939575.

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Xiang, Dong, Gang Liu, Krishnendu Chakrabarty, and Hideo Fujiwara. "Thermal-aware test scheduling for NOC-based 3D integrated circuits." In 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2013. http://dx.doi.org/10.1109/vlsi-soc.2013.6673257.

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Brik, Adil, Lioua Labrak, Laurent Carrel, Ian O'Connor, and Ramy Iskander. "Fast extraction of predictive models for integrated circuits using n-performance Pareto fronts." In 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2019. http://dx.doi.org/10.1109/vlsi-soc.2019.8920305.

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Livramento, Vinícius Dos Santos, and José Luís Güntzel. "Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits." In XXX Concurso de Teses e Dissertações da SBC. Sociedade Brasileira de Computação - SBC, 2017. http://dx.doi.org/10.5753/ctd.2017.3465.

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The evolution of CMOS technology made possible integrated circuits with billions of transistors assembled into a single silicon chip, giving rise to the jargon Very-Large-Scale Integration (VLSI). VLSI circuits span a wide range class of applications, including Application Specific Circuits and Systems-On-Chip. The latter are responsible for fueling the consumer electronics market, especially in the segment of smartphones and tablets, which are responsible for pushing hardware performance requirements every new generation. The required clock frequency affects the performance of a VLSI circuit and induces timing constraints that must be properly handled by synthesis tools. This thesis focuses on techniques for timing closure of cellbased VLSI circuits, i.e. techniques able to iteratively reduce the number of timing violations until the synthesis of the synchronous digital system reaches the specified target frequency.

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Ozaktas, Haldun M., Adolf W. Lohmann, and Hakan Urey. "Scaling of diffractive and refractive lenses for optical computing and interconnections." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1993. http://dx.doi.org/10.1364/oam.1993.mkk.3.

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Discussion of scaling of integrated circuit features and their effect on system parameters such as power dissipation, speed, chip area etc. have contributed useful insights to the understanding of the trends and limits in very large scale integration.

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Krishnamoorthy, A. V., J. E. Ford, K. W. Goossen, J. A. Walker, A. L. Lentine, L. A. D’Asaro, S. P. Hui, et al. "Implementation of a Photonic Page Buffer Based on GaAs MQW Modulators Bonded Directly over Active Silicon VLSI Circuits." In Optical Computing. Washington, D.C.: Optica Publishing Group, 1995. http://dx.doi.org/10.1364/optcomp.1995.pd2.

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The tremendous progress in high performance Very-Large Scale Integrated circuit (VLSI) technology has made possible the incorporation of several million transistors onto a single silicon chip with on-chip clock rates of 200 MegaHertz (MHz). By the end of decade, the integration density for silicon Complementary Metal Oxide Semiconductor (CMOS) is expected to be over 20 million transistors and the projected on-chip clock rate is 500 MHz. This enormous bandwidth that will be available for computation and switching on a silicon integrated circuit will create a huge bottleneck for Input and Output (I/O) to the VLSI circuit. Technologies that are being developed at AT&T Bell Laboratories, now exist for attaching GaAs Multiple Quantum Well (MQW) photodetectors and light-modulators onto a prefabricated silicon integrated circuit using a well-established hybrid flip-chip bonding technique followed by substrate removal of the GaAs chip to allow surface-normal operation of the optical modulators at 850nm [1]. From a systems point of view, the demands made of optoelectronic integration method are (i) that the silicon integrated circuit be state-of-the-art, (ii) the circuit be unaffected by the integration process, (iii) that the design and optimization of the circuit proceed independently of the placement and bonding to the optical I/O. The first two goals have been achieved in reference 1, and this technique has been effectively applied to simple switching nodes for a smart-pixel based photonic switch in reference 2. In this paper we further achieve the third goal by demonstrating for the first time that modulators can be bonded directly above active submicron CMOS transistors (figure 1), and by applying the technique to the demonstration of a high-density 2Kbit first-in first-out (Fifo) page buffer circuit.

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Clymer, Bradley D. "Surface-relief grating structures for photodetectors for optical interconnects in VLSI." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1988. http://dx.doi.org/10.1364/oam.1988.fx3.

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The miniaturization of integrated circuit elements and the expansion of chip sizes leading to very large-scale integration (VLSI) and wafer scale integration (WSI) have created a situation in which the speed of information processing for modern computing systems has become limited by communication delays rather than gate propagation delays for logic devices. The data communication limitation on processing speed has led to considerable interest in new methods for interconnection at nearly every level of computer hierarchy. While many researchers have proposed optical solutions to interconnection and communication problems at the chip, board, and backplane levels, the integration of fast photodetectors within a chip package has yet to be accomplished. The development of such devices is crucial to the feasibility of optical interconnection at hierarchical levels below the backplane connection.

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Yano, Kazuo, Tomoaki Akitomi, Koji Ara, Junichiro Watanabe, Satomi Tsuji, Nobuo Sato, Miki Hayakawa, and Norihiko Moriwaki. "Profiting from IoT: The key is very-large-scale happiness integration." In 2015 Symposium on VLSI Circuits. IEEE, 2015. http://dx.doi.org/10.1109/vlsic.2015.7231287.

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Reports on the topic "Integrated circuits Very large scale integration"

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Clark, Kay E. VLSI/VHSIC (Very Large Scale Integrated/Very High Speed Integrated Circuits) Package Test Development. Fort Belvoir, VA: Defense Technical Information Center, December 1986. http://dx.doi.org/10.21236/ada182360.

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Cohen, Seymour. Quality Procedures for VLSI/VHSIC (Very Large Scale Integrated and Very High Speed Integrated Circuits) Type Devices. Fort Belvoir, VA: Defense Technical Information Center, November 1985. http://dx.doi.org/10.21236/ada164885.

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Collier, Wiehrs L. VLSI (Very Large Scale Integrated Circuits) Implementation of a Quantized Sinusoid Filter Algorithm and Its Use to Compute the Discrete Fourier Transform. Fort Belvoir, VA: Defense Technical Information Center, March 1986. http://dx.doi.org/10.21236/ada168605.

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Hertel, Thomas, David Hummels, Maros Ivanic, and Roman Keeney. How Confident Can We Be in CGE-Based Assessments of Free Trade Agreements? GTAP Working Paper, June 2003. http://dx.doi.org/10.21642/gtap.wp26.

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With the proliferation of Free Trade Agreements (FTAs) over the past decade, demand for quantitative analysis of their likely impacts has surged. The main quantitative tool for performing such analysis is Computable General Equilibrium (CGE) modeling. Yet these models have been widely criticized for performing poorly (Kehoe, 2002) and having weak econometric foundations (McKitrick, 1998; Jorgenson, 1984). FTA results have been shown to be particularly sensitive to the trade elasticities, with small trade elasticities generating large terms of trade effects and relatively modest efficiency gains, whereas large trade elasticities lead to the opposite result. Critics are understandably wary of results being determined largely by the authors’ choice of trade elasticities. Where do these trade elasticities come from? CGE modelers typically draw these elasticities from econometric work that uses time series price variation to identify an elasticity of substitution between domestic goods and composite imports (Alaouze, 1977; Alaouze, et al., 1977; Stern et al., 1976; Gallaway, McDaniel and Rivera, 2003). This approach has three problems: the use of point estimates as “truth”, the magnitude of the point estimates, and estimating the relevant elasticity. First, modelers take point estimates drawn from the econometric literature, while ignoring the precision of these estimates. As we will make clear below, the confidence one has in various CGE conclusions depends critically on the size of the confidence interval around parameter estimates. Standard “robustness checks” such as systematically raising or lowering the substitution parameters does not properly address this problem because it ignores information about which parameters we know with some precision and which we do not. A second problem with most existing studies derives from the use of import price series to identify home vs. foreign substitution, for example, tends to systematically understate the true elasticity. This is because these estimates take price variation as exogenous when estimating the import demand functions, and ignore quality variation. When quality is high, import demand and prices will be jointly high. This biases estimated elasticities toward zero. A related point is that the fixed-weight import price series used by most authors are theoretically inappropriate for estimating the elasticities of interest. CGE modelers generally examine a nested utility structure, with domestic production substitution for a CES composite import bundle. The appropriate price series is then the corresponding CES price index among foreign varieties. Constructing such an index requires knowledge of the elasticity of substitution among foreign varieties (see below). By using a fixed-weight import price series, previous estimates place too much weight on high foreign prices, and too small a weight on low foreign prices. In other words, they overstate the degree of price variation that exists, relative to a CES price index. Reconciling small trade volume movements with large import price series movements requires a small elasticity of substitution. This problem, and that of unmeasured quality variation, helps explain why typical estimated elasticities are very small. The third problem with the existing literature is that estimates taken from other researchers’ studies typically employ different levels of aggregation, and exploit different sources of price variation, from what policy modelers have in mind. Employment of elasticities in experiments ill-matched to their original estimation can be problematic. For example, estimates may be calculated at a higher or lower level of aggregation than the level of analysis than the modeler wants to examine. Estimating substitutability across sources for paddy rice gives one a quite different answer than estimates that look at agriculture as a whole. When analyzing Free Trade Agreements, the principle policy experiment is a change in relative prices among foreign suppliers caused by lowering tariffs within the FTA. Understanding the substitution this will induce across those suppliers is critical to gauging the FTA’s real effects. Using home v. foreign elasticities rather than elasticities of substitution among imports supplied from different countries may be quite misleading. Moreover, these “sourcing” elasticities are critical for constructing composite import price series to appropriate estimate home v. foreign substitutability. In summary, the history of estimating the substitution elasticities governing trade flows in CGE models has been checkered at best. Clearly there is a need for improved econometric estimation of these trade elasticities that is well-integrated into the CGE modeling framework. This paper provides such estimation and integration, and has several significant merits. First, we choose our experiment carefully. Our CGE analysis focuses on the prospective Free Trade Agreement of the Americas (FTAA) currently under negotiation. This is one of the most important FTAs currently “in play” in international negotiations. It also fits nicely with the source data used to estimate the trade elasticities, which is largely based on imports into North and South America. Our assessment is done in a perfectly competitive, comparative static setting in order to emphasize the role of the trade elasticities in determining the conventional gains/losses from such an FTA. This type of model is still widely used by government agencies for the evaluation of such agreements. Extensions to incorporate imperfect competition are straightforward, but involve the introduction of additional parameters (markups, extent of unexploited scale economies) as well as structural assumptions (entry/no-entry, nature of inter-firm rivalry) that introduce further uncertainty. Since our focus is on the effects of a PTA we estimate elasticities of substitution across multiple foreign supply sources. We do not use cross-exporter variation in prices or tariffs alone. Exporter price series exhibit a high degree of multicolinearity, and in any case, would be subject to unmeasured quality variation as described previously. Similarly, tariff variation by itself is typically unhelpful because by their very nature, Most Favored Nation (MFN) tariffs are non-discriminatory in nature, affecting all suppliers in the same way. Tariff preferences, where they exist, are often difficult to measure – sometimes being confounded by quantitative barriers, restrictive rules of origin, and other restrictions. Instead we employ a unique methodology and data set drawing on not only tariffs, but also bilateral transportation costs for goods traded internationally (Hummels, 1999). Transportation costs vary much more widely than do tariffs, allowing much more precise estimation of the trade elasticities that are central to CGE analysis of FTAs. We have highly disaggregated commodity trade flow data, and are therefore able to provide estimates that precisely match the commodity aggregation scheme employed in the subsequent CGE model. We follow the GTAP Version 5.0 aggregation scheme which includes 42 merchandise trade commodities covering food products, natural resources and manufactured goods. With the exception of two primary commodities that are not traded, we are able to estimate trade elasticities for all merchandise commodities that are significantly different form zero at the 95% confidence level. Rather than producing point estimates of the resulting welfare, export and employment effects, we report confidence intervals instead. These are based on repeated solution of the model, drawing from a distribution of trade elasticity estimates constructed based on the econometrically estimated standard errors. There is now a long history of CGE studies based on SSA: Systematic Sensitivity Analysis (Harrison and Vinod, 1992; Wigle, 1991; Pagon and Shannon, 1987) Ho

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