Relevant bibliographies by topics / Integer-N phase-locked loop

Academic literature on the topic 'Integer-N phase-locked loop'

Author: Grafiati
Published: 10 December 2022
Last updated: 29 January 2023

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Contents

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Integer-N phase-locked loop.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Integer-N phase-locked loop"

1

Kuan, Ting-Kuei, and Shen-Iuan Liu. "A Loop Gain Optimization Technique for Integer-$N$ TDC-Based Phase-Locked Loops." IEEE Transactions on Circuits and Systems I: Regular Papers 62, no. 7 (July 2015): 1873–82. http://dx.doi.org/10.1109/tcsi.2015.2423793.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Wu, Jian-Ming, Stephen Chou, Simon Cimin Li, and Cheng-Yu Ho. "Comparing phase noise of integer-N phase-locked loop of voltage-controlled and digitally controlled oscillators." Microwave and Optical Technology Letters 56, no. 10 (July 22, 2014): 2226–28. http://dx.doi.org/10.1002/mop.28559.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Sumi, Yasuaki, Shigeki Obote, Yutaka Fukui, Kazutoshi Tsuda, and Kouichi Syoubu. "A New Fractional-N PLL Frequency Synthesizer." Journal of Circuits, Systems and Computers 07, no. 05 (October 1997): 395–405. http://dx.doi.org/10.1142/s0218126697000292.

Full text
Abstract:
Recently, the speedup of lock up time is required in the Phase Locked Loop (PLL) frequency synthesizer. The fractional-N method is one of the most important techniques among the speedup methods proposed hitherto. The fractional-N programmable divider can divide not only an integer step but also a fractional one. However, the phase detector always generates the phase error pulse in every period of reference frequency and the elimination of this phase error pulse seems to be difficult. In this paper, a new fractional-N programmable divider is proposed. In this divider, the width of phase error pulse is decreased by introducing the new division ratio (N + 1/2) besides N and (N + 1). Then, the width of maximum phase error pulse in the new fractional-N programmable divider is less than or equal to half of that of the conventional one.
APA, Harvard, Vancouver, ISO, and other styles
4

Kazeminia, Sarang, Khayrollah Hadidi, and Abdollah Khoei. "A Wide-Range Low-Jitter PLL Based on Fast-Response VCO and Simplified Straightforward Methodology of Loop Stabilization in Integer-N PLLs." Journal of Circuits, Systems and Computers 24, no. 07 (June 17, 2015): 1550104. http://dx.doi.org/10.1142/s0218126615501042.

Full text
Abstract:
A straightforward methodology of optimizing ring-oscillator phase-locked loops (PLLs) is organized for integer-N PLLs. Then, a brief 4-step design flow is concluded to implicitly quantize the loop components for optimized loop stability. Theoretical analysis confirms that the ratio of more than 20 is required for loop filter's capacitors to yield at least 65° degrees phase margin. A wide-range voltage controlled oscillator (VCO) is proposed which is continuously controlled through two fast and slow response paths. The fast-response path improves RMS jitter due to decreasing loop delay and the slower one is an adaptive bias tuning loop, utilized to reduce the power consumption at lower operating frequencies. The RMS jitter of around 2 ps and 0.35 ps at 250 MHz and 4 GHz operating frequencies are obtained, respectively, where the 1.8 V supply voltage is subjected to about 60 mV peak-to-peak noise and reference clock suffers from 12 ps peak-to-peak jitter. Power consumption is reduced from 12.6–4 mW at 250 MHz operating frequency when the adaptive bias scheme is applied. Furthermore, simulation results confirm 35% and 50% improvement in RMS and peak-to-peak jitter at 250 MHz operating frequency, respectively, when the ratio of capacitances is increased from 10 to 20 within the loop filter. The proposed PLL can be implemented in 170 μm × 250 μm active area in 0.18 μm CMOS process.
APA, Harvard, Vancouver, ISO, and other styles
5

Koithyar, Aravinda, and Telugu Kuppushetty Ramesh. "Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector." IET Circuits, Devices & Systems 14, no. 1 (January 2020): 60–65. http://dx.doi.org/10.1049/iet-cds.2019.0189.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Pandit, Vabya Kumar, Chitra Ramamurthy, Sourabh Basu, and Deepak V. Ingale. "Design and development of Ka-band carrier generator for IRS applications." International Journal of Microwave and Wireless Technologies 7, no. 6 (August 13, 2014): 637–44. http://dx.doi.org/10.1017/s175907871400107x.

Full text
Abstract:
A Ka-band carrier generator using phase-locked loop (PLL) frequency synthesizer is presented in this paper. The design uses integer-N PLL chip PE83336 as the important hardware support. The key idea of generating Ka-band frequency signal with low-phase noise is to generate a high-quality X-band frequency signal using PLL frequency synthesizer and employ a frequency multiplier to deliver the high-frequency output at the desired frequency band. Experimental measurements of the frequency synthesizer demonstrate the excellent performance, which is achieved with the Ka-band output with a frequency resolution of 5.7 MHz and phase noise better than −70 dBc/Hz at 1 kHz.
APA, Harvard, Vancouver, ISO, and other styles
7

Jin, Junting, Yuhua Jin, and Yebing Gan. "A 500 kHz to 150 MHz Multi-Output Clock Generator Using Analog PLL and Open-Loop Fractional Divider with 0.13 μm CMOS." Electronics 11, no. 15 (July 27, 2022): 2347. http://dx.doi.org/10.3390/electronics11152347.

Full text
Abstract:
Clocks are widely used in multimedia and electronic devices, and they usually have different frequency demands. This paper presents the design of a multi-output clock generator using an analog integer-N phase-locked loop (PLL) and open-loop fractional dividers. The PLL based on a three-stage ring voltage-controlled oscillator (VCO) is used to transform the lower frequency reference into a high-frequency intermediate clock (600 MHz–900 MHz). Then, relying on the open-loop fractional divider, a wide frequency range of 500 kHz to 150 MHz can be generated. Due to the open-loop control characteristic, the clock generator has instantaneous frequency switching capability. In addition, phase-adjusting circuits added to the divider greatly improved the jitter performance of the output clock; its RMS jitter is 5.2 ps. This work was conducted with 0.13 μm CMOS technology. The open-loop divider occupies an area of 0.032 mm2 and consumes 7.7 mW from a 1.2 V supply.
APA, Harvard, Vancouver, ISO, and other styles
8

Jo, Jongwan, David Kim, Arash Hejazi, YoungGun Pu, Yeonjae Jung, Hyungki Huh, Seokkee Kim, Joon-Mo Yoo, and Kang-Yoon Lee. "Low Phase-Noise, 2.4 and 5.8 GHz Dual-Band Frequency Synthesizer with Class-C VCO and Bias-Controlled Charge Pump for RF Wireless Charging System in 180 nm CMOS Process." Electronics 11, no. 7 (April 1, 2022): 1118. http://dx.doi.org/10.3390/electronics11071118.

Full text
Abstract:
This paper presents an integer-N phase-locked loop (PLL) for an RF wireless charging system. To improve the phase-noise characteristics under low power, a constant amplitude control class-C voltage-controlled oscillator (VCO) with a DC-DC converter, and a bias-controlled charge pump with a feedback loop are proposed. The frequency range of the VCO is 4.5–6.1 GHz, the target frequency of the proposed PLL is 2.4 and 5.8 GHz in the industry–science–medical band. It is designed with a same phase margin and bandwidth using one loop filter. The proposed PLL consumes less than 8 mW from a 1.8 V power supply with a settling time of fewer than 20 μs and an area of 1200 μm × 800 μm in the 180 nm CMOS process. For a carrier frequency offset of 1 MHz, the measured phase noise is −118.5 dBc/Hz at 2.4 GHz and −116.6 dBc/Hz at 5.8 GHz. Its FoM including the phase noise is −197 dB at 2.4 GHz and −202.8 GHz at 5.8 GHz, outperforming other PLLs designed in the 180 nm CMOS process.
APA, Harvard, Vancouver, ISO, and other styles
9

Trinh, Van-Son, Hyohyun Nam, Jeong-Moon Song, and Jung-Dong Park. "A 78.8–84 GHz Phase Locked Loop Synthesizer for a W-Band Frequency-Hopping FMCW Radar Transceiver in 65 nm CMOS." Sensors 22, no. 10 (May 10, 2022): 3626. http://dx.doi.org/10.3390/s22103626.

Full text
Abstract:
A W-band integer-N phase-locked loop (PLL) for a frequency hopping frequency modulation continuous wave (FMCW) radar is implemented in 65-nm CMOS technology. The cross-coupled voltage-controlled oscillator (VCO) was designed based on a systematic analysis of the VCO combined with its push-pull buffer to achieve high efficiency and high output power. To provide a frequency hopping functionality without any overhead in the implementation, the center frequency of the VCO is steeply controlled by the gate voltage of the buffer, which effectively modifies the susceptance of the VCO load. A stand-alone VCO with the proposed architecture is fabricated, and it achieves an output power of 13.5 dBm, a peak power efficiency of 9.6%, and a tuning range of 3.5%. The phase noise performance of the VCO is −92.6 dBc/Hz at 1-MHz and −106.1 dBc/Hz at 10 MHz offset. Consisting of a third-order loop filter and a divider chain with a total modulus of 48, the locking range of the implemented PLL with the cross-coupled VCO is recorded from 78.84 GHz to 84 GHz, and its phase noise is −85.2 dBc/Hz at 1-MHz offset.
APA, Harvard, Vancouver, ISO, and other styles
10

Sánchez-Azqueta, Carlos, Erick Guerrero, Cecilia Gimeno, and Santiago Celma. "A Reconfigurable Radio-Frequency Converter IC in 0.18 µm CMOS." Electronics 8, no. 10 (October 10, 2019): 1146. http://dx.doi.org/10.3390/electronics8101146.

Full text
Abstract:
This work presents a reconfigurable RF converter for DVB-T television applications using triple-play over GPON. The system takes the DVB-T input, a wavelength division multiplexing (WDM) signal with spectral inversion in the range from 47 M Hz –1000 M Hz , up-converts its frequency to the band-pass of a highly selective surface-acoustic wave (SAW) filter centered at 1 . 3 G Hz , and then down-converts it so that it is compatible with the antenna input of conventional television sets. The designed RF converter incorporates two pairs of frequency synthesizer and mixer, based, respectively, on an integer-N phase-locked loop (PLL) with two LC-tank VCOs with 128 coarse tuning bands in the range from 1.35 G Hz –2.7 G Hz , and a double-balanced Gilbert cell, modified for better impedance matching and improved linearity. It is fed with regulated supplies compensated in temperature and programmed by an I 2 C interface operating on five 16-bit registers. This work presents the experimental characterization of the whole system plus selected cells for stand-alone testing, which have been fabricated in a 0 . 18 m CMOS process.
APA, Harvard, Vancouver, ISO, and other styles

Dissertations / Theses on the topic "Integer-N phase-locked loop"

1

Tiagaraj, Sathya Narasimman. "Design of an Ultra-Low Phase Noise and Wide-Band Digital Phase Locked Loop for AWS and PCS Band Applications and CppSim Evaluation." The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1461262041.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Sharkia, Ahmad. "On the design of type-i integer-n phase-locked loops." Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/54504.

Full text
Abstract:
The phase-locked loop (PLL) is an essential building block of modern communication and computing systems. In a wireless communication system, a PLL is almost always used as the local oscillator (LO) that synthesizes the required frequency for data transmission and reception. In wireline and optical communication systems, PLL-based clock and data recovery (CDR) circuits are often employed for the extraction of the clock signal from the incoming data signal, and aligning the recovered clock edge with the incoming data for optimal bit-error rate (BER) performance. Furthermore, in microprocessor and field-programmable gate array (FPGA) systems, PLLs are typically used for clock generation. Although phase-locking is a very mature research topic, its continuous application in modern integrated circuits (ICs) and systems, requires continuous improvement in its performance, power consumption, and manufacturing costs. Analog Type-II PLLs are among the most widely used category of PLLs in CMOS (complementary-metal-oxide-semiconductor) ICs, mainly due to their robustness, superior performance and their well-established theory. However, analog Type-II PLLs require a large area in loop-filter (LF) and employ noisy and difficult-to-design charge-pumps (CPs). All-digital PLLs are also widely used, but they suffer from the strict jitter requirements on time-to-digital converters (TDCs). We propose a Type-I PLL that uses a small LF area, does not require bias-generation circuits or CP, and consumes low power. A pulse-width-modulated (PWM) voltage output from the phase-frequency detector (PFD) is fed to a simple RC single-pole LF. Two major limitations of conventional Type-I topologies – limited lock-range and large reference spur – are overcome by increasing the PFD gain with a combination of a voltage booster and a digital level shifter, and a sample-and-hold (S/H) envelope detector, respectively. Furthermore, a saturated-PFD (SPFD) is proposed to reduce cycle slipping and to further improve the lock-range and lock-time. A proof-of-concept prototype 2.2-to-2.8 GHz PLL occupies a core area of 0.12 mm² in 0.13-μm CMOS and achieves 490 fsrms random jitter, -103.4 dBc/Hz in-band phase-noise, -65 dBc reference spur, 2.5 μs worst-case lock-time while consuming 6.8 mW from a 1.2 V supply.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
APA, Harvard, Vancouver, ISO, and other styles
3

Wang, Jian-Xing, and 汪建興. "Design a Phase-Locked Loop Based Integer-N Frequency Synthesizer for 802.11b WLAN." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/85256795312159484228.

Full text
Abstract:
碩士
逢甲大學
電子工程所
92
ABSTRACT Design a 2.4 GHz CMOS Integer-N frequency synthesizer for 802.11b wireless communication system is described in this these. This frequency synthesizer consists of a off-chip VCO, a phase-frequency detector, a charge pump, a second-order loop filter, and dual-modulus frequency divider. This is realized by 0.35um 2P4M TSMC CMOS process. The operation frequency of divider can operate more than 2.4GHz. It was verified by h-spice software and total function was proved by Matlab Simulink software.
APA, Harvard, Vancouver, ISO, and other styles
4

Kamal, Noorfazila. "Reference spurs in an integer-N phase-locked loop : analysis, modelling and design." Thesis, 2013. http://hdl.handle.net/2440/80592.

Full text
Abstract:
The Phase-Locked Loop (PLL) is commonly used for frequency synthesis in RF transceivers. It can be implemented in two architectures, namely, fractional-N and integer- N. In this thesis, the integer-N architecture is chosen due to its suitability for frequency planning. Here, a PLL with a low noise output is important to ensure signal purity. There are two dominant noise sources in a PLL, namely, phase noise and periodic noise. In the integer-N PLL, periodic noise is also referred to as a reference spur, where the noise gives rise to multiple reference frequency offsets at the PLL output. Of these two noise sources, this thesis is focused on the analysis and suppression of reference spurs. It is because less work has been carried in the literature regarding spurs, and phase noise is better studied. The main factors underlying reference spurs are discussed. These factors are mainly from the charge pump and phase/frequency detector (PFD) circuit non-idealities, namely, PFD delay, charge pump current leakage, charge pump current mismatch, and rise and fall times characteristic of the charge pump current. Reference spur magnitude can be predicted via a transient analysis. The simulation is time consuming, as the reference spur magnitude can only be captured after the PLL in its locked state. Therefore, the simulation period has to be set long enough to ensure enough data can be obtained to read that state. In this thesis, a reference spur mathematical analysis is presented to accurately estimate the reference spur magnitude. In the analysis, all the circuit non-idealities that contribute to the reference spur are considered. Circuit parameters required in the mathematical analysis can be obtained from transistor level simulation for each circuit. As the simulation for each circuit can be carried out separately, a large amount of simulation time can be saved. The proposed mathematical analysis also can be used to determine the major contributing factor to the problem of reference spurs. The reference spur also can be estimated via behavioural modelling simulation. Behavioural modelling of the PLL using Simulink is presented in this thesis. Each PLL component is modelled separately, and circuit non-idealities contributing to the reference spur are included in the behavioural model. In addition to reference spur estimation, the PLL behavioural model also can be used to visualise the dynamic behaviour of the system. Results from the spur analysis show that a slight mismatch current in the charge pump helps to improve the reference spur performance. This thesis presents an analysis to determine an optimum charge pump current ratio for reference spur suppression, which is caused by the charge pump current mismatch and the switching delay. Further, a ratioed current charge pump circuit is proposed to replace the conventional charge pump circuit for a reference spur performance improvement. This spur suppression technique is implemented using a 180 nm SiGe BiCMOS technology for performance evaluation.
Thesis (Ph.D. )-- University of Adelaide, School of Electrical and Electronic Engineering, 2013
APA, Harvard, Vancouver, ISO, and other styles
5

Liao, Yu-Yu, and 廖佑予. "Design and Implementation of a CMOS Low Power Integer-N Cascaded Phase-Locked Loop for Implantable Medical SOCs." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/49048124277386257094.

Full text
Abstract:
碩士
國立交通大學
電子工程學系 電子研究所
101
In recent year, the implanted biomedical devices are got more and more attention in medical treatment. The Federal Communications Commission (FCC) announced the MICS (Medical Implant Communication Service) band for the implanted communication devices in 1999. In 2009, the band was broadened and renamed as MedRadio (Medical Device Radiocommunications Service) for diagnostic and therapeutic purposes. In this thesis, a low power integer-N cascaded phase locked loop (PLL) is presented to provide the carrier signal and clock signals for a SOC with MedRadio-band transceiver, ADC, DSP, and 13.56-MHz wireless power supply. In the proposed cascaded PLL, the first PLL provides the sampling clocks while the second PLL provides the carrier clock. Furthermore, the 13.56-MHz signal from the receiving coil of the wireless power transmission system is utilized as the input reference signal. Ring-based voltage controlled oscillator (VCO) is designed to minimize both power consumption and chip area. The chip is designed and implemented in TSMC 0.18-μm CMOS technology. According to the experimental results, the output of this PLL oscillates at 402.9MHz and exhibits phase noise of -79 dBc/Hz at 100 kHz offset. The result shows that the cascade structure work well, while only consume 0.28mW in the first PLL and 0.46mW in the second PLL with a 1.8V supply voltage. The die area is 0.525 mm2. The proposed cascaded PLL has low power dissipation, small chip area, and no off-chip components or crystal oscillator. It is suitable for the integration with implantable medical system-on-chips (SOCs). Finally, a discussion about poor jitter performance when turning on two PLL in the same time is made and the improvement is proposed.
APA, Harvard, Vancouver, ISO, and other styles
6

Chuang, Chih-Cheng, and 莊志成. "Implementations on X-Band CMOS Quadrature Voltage Controlled Oscillator, Integer-N Phase Locked Loop and GaN High Power and High Efficiency Voltage Controlled Oscillator." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/qkzg4v.

Full text
Abstract:
碩士
國立中央大學
電機工程學系
107
This thesis developed four local oscillator (LO) circuits for the signal source of X band and Ka band transceivers. The X-band LO was realized in tsmcTM 0.18 μm technology. The Ka-band LO was ikplemented in tsmcTM 90 nm technology. The X-band high power and high efficiency was realized in WINTM 0.25 μm GaN process. The developed LO circuits are listed as follow, A.Implementation on X-Band Quadrature Voltage Controlled Oscillator Using Cascode Coupling Technique The circuit improves the phase noise in traditional parallel coupling technique by using cascaded-coupling topology. After measurements, the operation frequency is from 9.27 to 10.12 GHz (i.e., 8.7% tuning range). The best phase noise is -115.2 dBc/Hz at 1-MHz offset. The output power including transmission loss is -4.78 dBm. Under 1.45-V supply voltage, the power consumption is 7.72 mW which is correspondent to an FoM of -185. The chip size includes all pads is 1.096 × 0.593 mm2. B.Implementation on X-Band Integer-N Phase Locked Loop (PLL) The functional circuit blocks of the designed PLL include a voltage controlled oscillator, a current mode logic divider, a differential to single buffer, a TSPC divider, a phase and frequency detector, a charge pump, and a loop filter. This thesis analyzes the behavior model of PLL. Meanwhile, we also analyze the issue of the differential-to-single buffer amplifier. The thesis adopts the phase and frequency detector with zero dead zone topology. The PLL is locked from 9.6 to 10.05 GHz when reference signal is 37.5 to 39.2578125 MHz. The division ratio is 256 and the total power consumption is 39.2 mW. The reference spur is as low as -45.7 dBc and phase noise is -93.7 dBc/Hz at 1-MHz offset. The chip size includes all pads is 1.035 × 0.809 mm2. C.Implementation on X-Band Tunable Feedback Type Voltage Controlled Oscillator The implementation on the VCO is realized in WINTM 0.25 μm GaN process under the constraint of the via-hole at source node that makes common source topology can be only adopted. Meanwhile, no varactor model is available. After measurements, the tuning frequency is from 9.348 to 9.46 GHz, and the output power including the transmission line loss and a 30-dB attenuator is 27.89 dBm. The best phase noise is -121.62 dBc/Hz at 1-MHz offset frequency. Under the 19-V supply voltage, the total power consumption is 2204 mW. The DC-to-RF conversion efficiency is 27.89%. The FoMp and FoMposc are -195.49 and -223.38, respectively. The chip size includes all pads is 2 × 1 mm2. D.Implementation on Ka-Band Integer-N Phase Locked Loop (PLL) The functional blocks of PLL include a VCO, an injection locked frequency divider, a current mode logic divider, a differential-to-single buffer, a TSPC divider, a phase and frequency detector, a charge pump, and a loop filter. The PLL is locked from 26.52 to 27.88 GHz when reference signal is 103.6 to 108.9 MHz. The division ratio is 256 and the total power consumption is 43.9 mW. The reference spur is -48.9 dBc and phase noise is -95.8 dBc/Hz at 1-MHz offset when PLL is locked. The chip size includes all pads is 1.015 × 0.972 mm2.
APA, Harvard, Vancouver, ISO, and other styles
7

Chan, Kai-Chun, and 詹凱鈞. "Implementations on C-band CMOS Low Phase Noise Class-C Voltage Controlled Oscillator, Transformer-coupled Quadrature Voltage Controlled Oscillator, C-band Integer-N Phase Locked Loop with Class-F Voltage Controlled Oscillator and X-band III-V Power Oscillators." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/5554um.

Full text
Abstract:
碩士
國立中央大學
電機工程學系
106
This thesis developed six local oscillator (LO) circuits for the signal sources of C band and X band transceivers. Three C band LOs were realized in tsmcTM CMOS processes. The X band high power LOs were realized in WINTM 0.25 m GaN and InGaAs pHEMT technologies. The developed LO circuits are listed as follow, A Implementations on C-band CMOS Local Oscillator Circuits I.Low Phase Noise Class-C Voltage Control Oscillator The Class-C oscillator has the features of low power consumption, high current efficiency and low phase noise. This thesis analyzed the phase noise performance of the traditional Colpitts oscillator and Class-C oscillator, repectively. Then, the author proposed a dynamic bias circuit to solve hard start-up problem of the Class-C oscillator. The designed oscillator consumed the dc power of 3.9 mW. The measured tuning range is 5.28 - 5.53 GHz (4.62 %). The lowest phase noise at 1-MHz offset frequency is -120.1 dBc/Hz which is correspondent to the FoM of -188.7. The chip size includes all pads is 0.671 × 0.909 mm2. II.Transformer Coupled Quadrature Voltage Control Oscillator The thesis introduced the requirements of the quadrature signal and how to generate the IQ signals by using transformer coupling technique. Meanwhile, the bi-model problem in IQ signal generation can be solved by this technique accordingly. The use of tail filter also improved the phase noise of quadrature oscillator. These IQ signals totally consumed the dc power of 21.6 mW. The tuning range of the circuit is from 5.23 to 5.73 GHz (9.1 %). The lowest phase noise at 1-MHz offset frequency is -119.75 dBc/Hz which is correspondent to a lowest FoM of -180.8. The chip size include all pads is 1.132 × 0.738 mm2. III.Integer-N Phase Locked Loop (PLL) with Class-F Voltage Controlled Oscillator The PLL adopted a Class-F VCO to improve the phase noise perforamnce. This thesis analyzed the mathematical model of the PLL and developed all functional block cicruits of the PLL. The PLL consumed the dc power of 32.5 mW. The phase noise at 10-kHz offset frequency as the PLL was locked is -95.4 dBc/Hz, and achieves a low frequency FoM of -192.3. The chip size include all pads is 0.887 × 1.077 mm2. B.Implementations on X-band III-V High Power Local Oscillator Circuits I.Clapp Power Oscillator The Clapp power oscillator circuit was realized in WINTM 0.25 m GaN high power process. Total power consumption of the circuit is 416 mW. The lowest phase noise at 1 MHz offset frequency is -118.02 dBc/Hz. The output power is 19.6 dBm. The DC-RF conversion efficiency is 21.9 %. The FoMPOSC, which adds output power and efficiency performance in the conventional FoM of oscillator, is -210.9. The chip size includes all pads is 1.5 × 1 mm2. II.Clapp Power Voltage Control Oscillator The Clapp power voltage control oscillator circuit was realized by 0.15 m InGaAs pHEMT technology. The GaAs equvilent diode was used as a varactor for the frequrncy tuning. The total power consumption is 20 mW. The tuning range is from 9.41 to 10.04 GHz (6.4 %). The lowest phase noise at 1 MHz offset frequency is -100.55 dBc/Hz. The highest output power is 7.7 dBm. The DC-R Fconversion efficiency is 35.6 %. The FoMPOSC is -202.4. The chip size included all pads is 1.5 × 1 mm2. III.Power Oscillator use Class-E Network The Class-E power oscillator was realized in 0.25 m GaN high power process. The phase noise was estimated according to the phase noise measured before. Since the circuit is still in the process, the design process and full EM simulation result is shown in this thesis. The expected total power consumption is 2.9 W. The lowest phase noise at 1 MHz offset frequency is estimated as -126.5 dBc/Hz. The highest output power is 30.5 dBm. The DC-RF efficiency 39.1 % was calculated. The FoMPOSC is -232.9. The chip size is 1.5 × 1 mm2.
APA, Harvard, Vancouver, ISO, and other styles
8

"A 1.5 V, 2.4 GHz monolithic CMOS sub-integer-N frequency synthesizer for WLAN application." Thesis, 2011. http://library.cuhk.edu.hk/record=b6075113.

Full text
Abstract:
This thesis presents the design of a 2.4 GHz sub-integer-N PLL for IEEE 802.llb/g WLAN applications. The proposed PLL not only acquires the advantages of the integer-N PLL, such as simple structure and good spurious performance, but also offers some benefits (for example, faster settling time and better phase noise performance) as in the fractional-N PLL design. In this design, a novel quadrature-input programmable fractional frequency divider provides fractional division ratio in steps of 0.5 by the phase-switching technique. Its key building block is a dual divide-by-4 injection-locked frequency divider (ILFD), which is realized by coupling two conventional divide-by-4 ILFDs. Two different coupling schemes are introduced, namely the cross-coupling type and coherent-coupling type. In both schemes, symmetric configuration is maintained and hence does not degrade the PLL output phase quadrature accuracy. Furthermore, the generated phase pattern for phase switching is uniquely defined, which simplifies the phase-switching circuitry and suppresses the possibility of incorrect frequency division due to glitches.
To demonstrate the feasibility of the two proposed coupling methodologies, two subinteger-N PLLs with different fractional frequency dividers have been fabricated in a 0.35 11m standard CMOS process. In design 1, the dual divide-by-4 ILFD in the fractional frequency divider is implemented with the cross-coupling scheme while the coherent-coupling scheme is used in design 2. The measured spurious tones of both designs are under -64 dBc and their measured phase noise at 1 MHz frequency offset is less than -115 dBc/Hz. The two proposed frequency synthesizers settle at approximately 32 us and their phase mismatches of the quadrature outputs are better than 38 dB (characterized by image rejection ratio). Moreover, both designs individually occupy a chip area as small as 0.70 mm2. At a supply of 1.5 V, the total power consumption for each design is below 24.1 mW.
Wireless local area networks (WLANs) are being extensively deployed since their introduction in the late 1990s. Low cost, high performance frequency synthesizers are indispensable in WLAN telecommunication systems. Meanwhile, integer-N phase-locked loop (PLL) architecture is commonly chosen due to its low circuit complexity and clean output spectrum with few spurs. However, designers have to face the tradeoffs between frequency resolution, phase noise performance and switching time. To solve the above dilemma, fractional-N PLL architecture is proposed, but fractional spurs emerge in the output spectrum, degrading the spectrum purity. Sub-integer-N PLL is thus a compromise between the integer-N and fractional-N PLL. Its structure is same as that of the integer-N while fractional division is achieved by a fractional frequency divider that is not relied on time-varying modulus control as in the fractional-N PLL.
Chang, Ka Fai.
Adviser: Kwok-Keung Cheng.
Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: .
Thesis (Ph.D.)--Chinese University of Hong Kong, 2011.
Includes bibliographical references (leaves 176-188).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract also in Chinese.
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "Integer-N phase-locked loop"

1

Choudhary, Vikas, and Krzysztof (Kris) Iniewski. "Phase-Locked Loop—Based Integer-N RF Synthesizer." In Wireless Technologies, 383–426. CRC Press, 2017. http://dx.doi.org/10.1201/9780849379970-16.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Choudhary, Vikas, and Krzysztof (Kris) Iniewski. "Phase-Locked Loop–Based Integer-N RF Synthesizer." In Wireless Technologies, 383–426. CRC Press, 2007. http://dx.doi.org/10.1201/9780849379970.ch14.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Integer-N phase-locked loop"

1

Liao, Te-Wen, Jun-Ren Su, and Chung-Chih Hung. "Low-spur technique for Integer-N phase-locked loop." In 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2012. http://dx.doi.org/10.1109/mwscas.2012.6292078.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Koithyar, Aravinda, and T. K. Ramesh. "Integer-N charge pump phase locked loop with reduced current mismatch." In 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET). IEEE, 2017. http://dx.doi.org/10.1109/wispnet.2017.8299840.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Rong, Chao, Susnata Mondal, L. Richard Carley, and Jeyanandh Paramesh. "A 60-GHz Digital Sub-Sampling Integer-N Phase-Locked Loop." In 2020 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS). IEEE, 2020. http://dx.doi.org/10.1109/wmcs49442.2020.9172416.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Teixeira, Rui Moutinho, and Jose Machado da Silva. "Design for Calibratability of a N-Integer Low-Frequency Phase-Locked Loop." In 2018 Conference on Design of Circuits and Integrated Systems (DCIS). IEEE, 2018. http://dx.doi.org/10.1109/dcis.2018.8681479.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Kamal, Noorfazila, Said Al-Sarawi, and Derek Abbott. "An accurate analytical spur model for an integer-N phase-locked loop." In 2012 4th International Conference on Intelligent & Advanced Systems (ICIAS). IEEE, 2012. http://dx.doi.org/10.1109/icias.2012.6306096.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Butryn, Igor, Krzysztof Siwiec, Jakub Kopanski, and Witold A. Pleskacz. "Integer-N phase locked loop for bluetooth receiver in CMOS 130 nm technology." In 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2016. http://dx.doi.org/10.1109/ddecs.2016.7482469.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Liao, Yu-Yu, Wei-Ming Chen, and Chung-Yu Wu. "A CMOS MedRadio-band low-power integer-N cascaded phase-locked loop for implantable medical SOCs." In 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS). IEEE, 2013. http://dx.doi.org/10.1109/biocas.2013.6679695.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Yi-Xiao Wang, Wei-Ming Chen, and Chung-Yu Wu. "A 65nm CMOS low-power MedRadio-band integer-N cascaded phase-locked loop for implantable medical systems." In 2014 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC). IEEE, 2014. http://dx.doi.org/10.1109/embc.2014.6943673.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Lei, Feiran, and Marvin H. White. "A low noise, inductor-less, integer-N RF synthesizer using phase-locked loop with reference injection (PLL-RI)." In 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2017. http://dx.doi.org/10.1109/mwscas.2017.8052934.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Biggio, Matteo, Federico Bizzarri, Angelo Brambilla, Giorgio Carlini, and Marco Storace. "Reliable and efficient phase noise simulation of mixed-mode integer-N Phase-Locked Loops." In 2013 European Conference on Circuit Theory and Design (ECCTD). IEEE, 2013. http://dx.doi.org/10.1109/ecctd.2013.6662284.

Full text
APA, Harvard, Vancouver, ISO, and other styles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography