Relevant bibliographies by topics / Instabilté de Vth

Academic literature on the topic 'Instabilté de Vth'

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Published: 7 July 2024
Last updated: 7 July 2024

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Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Journal articles on the topic "Instabilté de Vth":

1

Senzaki, Junji, Atsushi Shimozato, Kazutoshi Kojima, Shinsuke Harada, Keiko Ariyoshi, Takahito Kojima, Yasunori Tanaka, and Hajime Okumura. "Threshold Voltage Instability of SiC-MOSFETs on Various Crystal Faces." Materials Science Forum 778-780 (February 2014): 521–24. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.521.

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Threshold voltage (VTH) of SiC-MOSFETs on various crystal faces has been investigated systematically using the same bias-temperature-stress (BTS) conditions. In addition, dependences of gate-oxide-forming process on VTH instability is also discussed. Nitridation treatments such as N2O and NH3 post-oxidation annealing (POA) are effective in stabilization of VTH under both positive-and negative-BTS tests regardless of crystal face. On the other hand, serious VTH instability was confirmed in MOSFETs with gate oxide by pyrogenic oxidation followed by H2 POA.
2

Tadjer, Marko J., Karl D. Hobart, Eugene A. Imhoff, and Fritz J. Kub. "Temperature and Time Dependent Threshold Voltage Instability in 4H-SiC Power DMOSFET Devices." Materials Science Forum 600-603 (September 2008): 1147–50. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1147.

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Threshold voltage (Vth) was measured on 4H-SiC power DMOSFET devices as a function of temperature, gate stress, and gate stress time. Vth varied linearly with gate stress and gate stress time and inversely with temperature. This instability is explained with the trapping rate of channel electrons at or near the SiO2-SiC interface. Since the measurement scale of Vth is large in this case (it takes approx. 20 s to measure Vth), it is assumed that fast interface traps, i.e., ones closer to the interface, are already filled and do not contribute to the shift in Vth. Comparison with theoretical calculations shows the rate of carrier detrapping becomes higher with temperature and as a result the measured value of Vth approaches the theoretical value.
3

Sometani, Mitsuru, Dai Okamoto, Shinsuke Harada, Hitoshi Ishimori, Shinji Takasu, Tetsuo Hatakeyama, Manabu Takei, Yoshiyuki Yonezawa, Kenji Fukuda, and Hajime Okumura. "Exact Characterization of Threshold Voltage Instability in 4H-SiC MOSFETs by Non-Relaxation Method." Materials Science Forum 821-823 (June 2015): 685–88. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.685.

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In this work, we investigated the methods that measure the threshold voltage (Vth) instability without relaxation of the gate stress during the Vth measurement. We propose a non-relaxation method that demonstrates exact Vth shifts compared with conventional methods that are not as accurate. In the non-relaxation method, the constant gate-source voltage (Vgs) is continuously applied as a gate stress while the drain voltage (Vds) shift required to maintain a constant drain current (Id) is measured. Then, the Vds shift is converted to a Vth shift. The Vth shift values measured by the non-relaxation method are larger than those measured by the other methods, which means that the non-relaxation method can very accurately measure the Vth shift.
4

Na, Jeong-Hyeon, Jun-Hyeong Park, Won Park, Junhao Feng, Jun-Su Eun, Jinuk Lee, Sin-Hyung Lee, et al. "Dependence of Positive Bias Stress Instability on Threshold Voltage and Its Origin in Solution-Processed Aluminum-Doped Indium Oxide Thin-Film Transistors." Nanomaterials 14, no. 5 (March 4, 2024): 466. http://dx.doi.org/10.3390/nano14050466.

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The initial electrical characteristics and bias stabilities of thin-film transistors (TFTs) are vital factors regarding the practical use of electronic devices. In this study, the dependence of positive bias stress (PBS) instability on an initial threshold voltage (VTH) and its origin were analyzed by understanding the roles of slow and fast traps in solution-processed oxide TFTs. To control the initial VTH of oxide TFTs, the indium oxide (InOx) semiconductor was doped with aluminum (Al), which functioned as a carrier suppressor. The concentration of oxygen vacancies decreased as the Al doping concentration increased, causing a positive VTH shift in the InOx TFTs. The VTH shift (∆VTH) caused by PBS increased exponentially when VTH was increased, and a distinct tendency was observed as the gate bias stress increased due to a high vertical electric field in the oxide dielectric. In addition, the recovery behavior was analyzed to reveal the influence of fast and slow traps on ∆VTH by PBS. Results revealed that the effect of the slow trap increased as the VTH moved in the positive direction; this occured because the main electron trap location moved away from the interface as the Fermi level approached the conduction band minimum. Understanding the correlation between VTH and PBS instability can contribute to optimizing the fabrication of oxide TFT-based circuits for electronic applications.
5

Kutsuki, Katsuhiro, Sachiko Kawaji, Yukihiko Watanabe, Masatoshi Tsujimura, Toru Onishi, Hirokazu Fujiwara, Kensaku Yamamoto, and Takashi Kanemura. "Impact of Al Doping Concentration at Channel Region on Mobility and Threshold Voltage Instability in 4H-SiC Trench N-MOSFETs." Materials Science Forum 858 (May 2016): 607–10. http://dx.doi.org/10.4028/www.scientific.net/msf.858.607.

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The effect of Al doping concentration (NA) at channel regions ranging from 1.0×1017 to 4.0×1017 cm-3 on the effective channel mobility of electron (μeff) and the threshold voltage (Vth) instability under the positive bias-temperature-stress conditions has been investigated througu the use of trench-gate 4H-SiC MOSFETs with m-face (1-100) channel regions. It was found that μeff degraded with an increase in NA. On the other hand, the increase of NA enlarged the Vth instability. These results indicate that NA has a large impact not only on the Vth value but also on the channel resistance and reliability in 4H-SiC trench MOSFETs.
6

Senzaki, Junji, Atsushi Shimozato, Kozutoshi Kajima, Keiko Aryoshi, Takahito Kojima, Shinsuke Harada, Yasunori Tanaka, Hiroaki Himi, and Hajime Okumura. "Electrical Properties of MOS Structures on 4H-SiC (11-20) Face." Materials Science Forum 740-742 (January 2013): 621–24. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.621.

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Threshold voltage (VTH) instability, channel mobility and oxide reliability have been investigated for meta-oxide-semiconductor (MOS) structures on 4H-SiC (11-20) face using various gate oxidation procedures. Channel mobility of n-channel MOSFET with a gate oxide by pyrogenic oxidation is higher than that by dilute-DRY oxidation followed by a nitrous oxide (N2O) post-oxidation annealing (POA). On the other hand, oxide reliability for the pyrogenic oxides is poor compared with the dilute-DRY/N2O oxides. A Hydrogen POA is effective in an improvement of channel mobility for both oxides, but causes a harmful effect on VTH stability. Temperature dependence of VTH instability indicates that MOS structure grown by dilute-DRY followed by N2O POA is suitable for a practical use of SiC MOS power devices.
7

Kim, Sang Sub, Pyung Ho Choi, Do Hyun Baek, Jae Hyeong Lee, and Byoung Deog Choi. "Abnormal Threshold Voltage Shifts in P-Channel Low-Temperature Polycrystalline Silicon Thin Film Transistors Under Negative Bias Temperature Stress." Journal of Nanoscience and Nanotechnology 15, no. 10 (October 1, 2015): 7555–58. http://dx.doi.org/10.1166/jnn.2015.11167.

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In this research, we have investigated the instability of P-channel low-temperature polycrystalline silicon (poly-Si) thin-film transistors (LTPS TFTs) with double-layer SiO2/SiNX dielectrics. A negative gate bias temperature instability (NBTI) stress was applied and a turn-around behavior phenomenon was observed in the Threshold Voltage Shift (Vth). A positive threshold voltage shift occurs in the first stage, resulting from the negative charge trapping at the SiNX/SiO2 dielectric interface being dominant over the positive charge trapping at dielectric/Poly-Si interface. Following a stress time of 7000 s, the Vth switches to the negative voltage direction, which is “turn-around” behavior. In the second stage, the Vth moves from −1.63 V to −2 V, overwhelming the NBTI effect that results in the trapping of positive charges at the dielectric/Poly-Si interface states and generating grain-boundary trap states and oxide traps.
8

Okamoto, Mitsuo, Mitsuru Sometani, Shinsuke Harada, Hiroshi Yano, and Hajime Okumura. "Dynamic Characterization of the Threshold Voltage Instability under the Pulsed Gate Bias Stress in 4H-SiC MOSFET." Materials Science Forum 897 (May 2017): 549–52. http://dx.doi.org/10.4028/www.scientific.net/msf.897.549.

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The threshold voltage (Vth) instability of 4H-SiC MOSFETs was investigated using high-speed IV measurement instrument. DC stress measurement of wide time span ranging from 10-6 to 103 s without relaxation effect was conducted. The high-speed measurement allowed of dynamic ΔVth measurement under pulsed AC gate bias stress. We investigated effects of NO POA in gate oxidation process on the Vth instabilities.
9

Deb, Arkadeep, Jose Ortiz-Gonzalez, Mohamed Taha, Saeed Jahdi, Phillip Mawby, and Olayiwola Alatise. "Impact of Turn-Off Gate Voltage and Temperature on Threshold Voltage Instability in Pulsed Gate Voltage Stresses of SiC MOSFETs." Materials Science Forum 1091 (June 5, 2023): 61–66. http://dx.doi.org/10.4028/p-lidhbt.

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Bias temperature instability (BTI) in SiC MOSFETs has come under significant academic and industrial research. Threshold voltage (VTH) shift due to gate voltage stress has been demonstrated in several studies investigating gate oxide reliability in SiC MOSFETs. Results have shown positive.VTH shift occurs due to electron trapping (PBTI), and negative VTH shift occurs due to hole trapping (NBTI). In this paper, VTH shift is studied for unipolar and bipolar gate pulses with frequencies ranging from 1Hz to 100 kHz. The turn-OFF voltage for the unipolar VGS pulse is 0 V. In the case of the bipolar VGS pulses, two turn-OFF voltages are investigated, namely VGS-OFF = -3V and VGS-OFF= -5V. VTH shift is measured after 1000 seconds with recovery times in the range of 20 milliseconds, and preconditioning is performed before VTH measurement. These measurements have been performed at 25°C and 150°C on a commercially available SiC Planar MOSFET and a SiC Trench MOSFET. The results show that -3 V is enough for de-trapping sufficient electrons while -5V results in increased NBTI, which is accelerated by higher temperatures.
10

Rescher, Gerald, Gregor Pobegen, and Thomas Aichinger. "Impact of Nitric Oxide Post Oxidation Anneal on the Bias Temperature Instability and the On-Resistance of 4H-SiC nMOSFETs." Materials Science Forum 821-823 (June 2015): 709–12. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.709.

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We study the impact of different nitric oxide (NO) post oxidation annealing (POA) procedures on the on resistance Ron of n-channel MOSFETs and on the threshold voltage shift ∆Vth following positive bias temperature stress (PBTS). All samples were annealed in an NO containing atmosphere at various temperatures and times. A positive stress voltage of 30 V was chosen which corresponds to an electric field of about 4.3 MV/cm. The NO POA causes a decrease in overall ∆Vth for longer NO POA times and higher NO POA temperatures. As opposed to the change in ∆Vth, the device Ron increases with NO POA temperature and time.
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Journal articles

Dissertations / Theses on the topic "Instabilté de Vth":

1

Leurquin, Camille. "Etude des mécanismes de dégradation et Fiabilité dynamique des composants GaN sur Si." Electronic Thesis or Diss., Université Grenoble Alpes, 2024. http://www.theses.fr/2024GRALT025.

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Afin de contribuer de manière significative à la réduction de la consommation énergétique mondiale, le développement de convertisseurs d'énergie électrique reposant sur de nouveaux composants de puissance, tels que le GaN-sur-Si, est essentiel. Ces composants, plus compacts et plus efficaces, offrent des perspectives prometteuses. Les transistors de puissance MOS-HEMT (MOS channel High Electron Mobility Transistor) à base de GaN-sur-Si, développés au CEA-Leti, ciblent le marché des convertisseurs de puissance basse tension (< 900 V). Cette architecture a montré d'excellentes performances à la fois statiques et dynamiques. Cependant, les dégradations temporelles sous contraintes de grille et de drain, ainsi que les mécanismes de dégradation, demeurent encore peu connus. L'objectif de cette thèse est d'explorer les instabilités de la résistance à l'état passant RON et de la tension de seuil VTH de ces transistors, tant pendant qu'après des stress de plusieurs centaines de volts appliqués sur le drain du composant. Cette étude a été réalisée au moyen de techniques de caractérisation électrique innovantes spécialement conçues appelées HVBTI. Une part importante des travaux a été dédiée à l'identification des défauts à l'origine de ces dérives, ainsi qu'à la compréhension des mécanismes physiques sous-jacents impliqués dans ces dégradations. L'influence des couches épitaxiales et de l'architecture sur l'instabilité du VTH a été investiguée en profondeur. Bien que ces recherches aient considérablement enrichi notre compréhension des transistors GaN-sur-Si fabriqués au CEA-Leti, la compréhension des instabilités de RON et VTH reste encore à approfondir
To contribute significantly to the global reduction of energy consumption, it is essential to develop electrical energy converters based on new power components, such as GaN on Si. These more compact and efficient components offer promising prospects. MOS-HEMT (MOS channel High Electron Mobility Transistor) power transistors based on GaN-on-Si, developed at CEA-Leti, target the market for low-voltage power converters (< 900 V). This architecture has demonstrated excellent performance in both static and dynamic aspects. However, temporal degradations under gate and drain stresses, as well as the degradation mechanisms, remain relatively unknown. The objective of this thesis is to explore the instabilities of the on-state resistance RON and threshold voltage VTH of these transistors, both during and after stresses of several hundred volts applied to the component's drain. This study was conducted using specially designed innovative electrical characterization techniques called HVBTI. A significant portion of the work focused on identifying the defects causing these deviations and understanding the underlying physical mechanisms involved in these degradations. The influence of epitaxial layers and architecture on the instability of VTH has been thoroughly investigated. While these studies have significantly enriched our understanding of GaN-on-Si transistors manufactured at CEA-Leti, the comprehension of RON and VTH instabilities still requires further exploration
2

Denais, Mickael. "ETUDE DES PHENOMENES DE DEGRADATION DE TYPENEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI)DANS LES TRANSISTORS MOS SUBMICRONIQUES DESFILIERES CMOS AVANCEES." Phd thesis, Université de Provence - Aix-Marseille I, 2005. http://tel.archives-ouvertes.fr/tel-00011973.

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La miniaturisation croissante des circuits intégrés entraîne une augmentation de la complexité des procédés de
fabrication où chaque nouvelle étape peut influer la fiabilité du composant. Les fabricants de semi-conducteurs
doivent garantir un niveau de fiabilité excellent pour garantir les performances à long terme du produit final.
Pour cela il est nécessaire de caractériser et modéliser les différents mécanismes de défaillance au niveau du
transistor MOSFET. Ce travail de thèse porte spécifiquement sur les mécanismes de dégradation de type «
Negative Bias Temperature Instability» communément appelé NBTI.
Basé sur la génération d'états d'interface, la génération de charges fixes et de piégeage de trous dans l'oxyde, le
modèle de dégradation proposé permet de prédire les accélérations en température et en champ électrique,
d'anticiper les phénomènes de relaxation, tout en restant cohérent avec les caractères intrinsèques de chaque
défauts et les modifications des matériaux utilisés.
Ce travail de thèse ouvre le champ à de nouvelles techniques d'analyse basées sur l'optimisation des méthodes
de tests et d'extraction de paramètres dans les oxydes ultra minces en évitant les phénomènes de relaxation qui
rendent caduques les techniques conventionnelles. Ainsi, une nouvelle technique dite « à la volée » a été
développée, et permet d'associer à la fois la mesure et le stress accéléré à l'aide de trains d'impulsions
appropriés.
Finalement, une nouvelle méthodologie est développée pour tenir compte des conditions réelles de
fonctionnement des transistors, et une approche novatrice de compensation du NBTI est proposée pour des
circuits numériques et analogiques.
3

Wang, Xuguang Kwong Dim-Lee. "A novel high-K SONOS type non-volatile memory and NMOS HfO₂ Vth instability studies for gate electrode and interface threatment effects." 2005. http://repositories.lib.utexas.edu/bitstream/handle/2152/2089/wangx82253.pdf.

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4

Wang, Xuguang. "A novel high-K SONOS type non-volatile memory and NMOS HfO₂ Vth instability studies for gate electrode and interface threatment effects." Thesis, 2005. http://hdl.handle.net/2152/2089.

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Book chapters on the topic "Instabilté de Vth":

1

Goto, Shotaro, Shuichi Setoguchi, Kazuhisa Matsunaga, and Jiro Takata. "Overcoming the Photochemical Problem of Vitamin K in Topical Application." In Vitamin K - Recent Advances, New Perspectives and Applications for Human Health [Working Title]. IntechOpen, 2021. http://dx.doi.org/10.5772/intechopen.99310.

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Topical application of vitamin K is beneficial in the treatment of various skin pathologies. However, its delivery to the skin is hampered by the photo-instability and phototoxicity of vitamin K (quinone form). Indeed, topical use of vitamin K is regulated in Europe owing to the photosensitive properties of this molecule. Here, we discuss the suitability of ester derivatives of vitamin K hydroquinone (VKH), the active form of vitamin K, for topical applications. Notably, VKH derivatives have the potential to overcome the photo-instability and phototoxicity problem of vitamin K and act as VKH prodrugs, as demonstrated in HaCaT human keratinocytes. Thus, VKH prodrug is a promising strategy for topical application of vitamin K without the need for special protection from light.
2

Patterson, Caroline, and Derek Bell. "Thromboembolic Disease." In Oxford Textbook of Respiratory Critical Care, 397–402. Oxford University PressOxford, 2023. http://dx.doi.org/10.1093/med/9780198766438.003.0043.

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Abstract Summary Venous thromboembolism (VTE), both deep venous thrombosis (DVT) and pulmonary thromboembolism (PE), represent a significant and often under-recognized threat to the critically ill patient. Critically ill patients’ risk of VTE is influenced by their underlying co-morbidities, the pro-thrombotic effects of the acute illness, and the effects of organ support measures including immobility, sedation, and venous catheter placement. DVT can be readily diagnosed by bedside compression ultrasound, while PE is ideally diagnosed by computed tomography. Bedside echocardiography is insensitive for PE but may help risk stratification or identification of potential massive PE in the context of cardiovascular collapse. High-risk PE, defined by haemodynamic instability, should be managed with systemic thrombolysis and anticoagulation. In intermediate- and low-risk PE, the risk of bleeding outweighs any benefit from thrombolysis, and these patients should be managed with anticoagulation alone. Thromboprophylaxis is important in critically ill patients and needs careful management in the context of acute illness and renal failure.

Conference papers on the topic "Instabilté de Vth":

1

Zhang, J. F., Z. Ji, M. H. Chang, B. Kaczer, and G. Groeseneken. "Real Vth instability of pMOSFETs under practical operation conditions." In 2007 IEEE International Electron Devices Meeting - IEDM '07. IEEE, 2007. http://dx.doi.org/10.1109/iedm.2007.4419073.

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Shen, C., T. Yang, M. f. Li, G. Samudra, Y. c. Yeo, C. Zhu, S. Rustagi, M. Yu, and D. l. Kwong. "Fast Vth instability in HfO2 gate dielectric MOSFETs and Its impact on digital circuits." In 2006 IEEE International Reliability Physics Symposium Proceedings. IEEE, 2006. http://dx.doi.org/10.1109/relphy.2006.251308.

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3

Choi, Won Ho, Hoonki Kim, and Chris H. Kim. "Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs." In 2015 IEEE Custom Integrated Circuits Conference - CICC 2015. IEEE, 2015. http://dx.doi.org/10.1109/cicc.2015.7338417.

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Chen, Junting, Chengcai Wang, Jiali Jiang, and Mengyuan Hua. "Investigation of Time-Dependent VTH Instability Under Reverse-bias Stress in Schottky Gate p-GaN HEMT." In 2020 IEEE 9th International Power Electronics and Motion Control Conference (IPEMC2020-ECCE Asia). IEEE, 2020. http://dx.doi.org/10.1109/ipemc-ecceasia48364.2020.9367779.

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Thareja, Gaurav, Jack Lee, Aaron Voon-Yew Thean, Victor Vartanian, and Bich-Yen Nguyen. "NBTI Reliability of Strained SOI MOSFETs." In ISTFA 2006. ASM International, 2006. http://dx.doi.org/10.31399/asm.cp.istfa2006p0423.

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Abstract We investigated the degradation of device reliability due to Negative Bias Temperature Instability (NBTI) of PMOSFET on Strained Silicon on Insulator (S-SOI) substrates for the first time. The degradation has been found to be significantly higher for the S-SOI devices in comparison to SOI counterparts. Subsequent to a Constant Voltage Stress (CVS) during NBTI measurements, a negligible change in the subthreshold swing values was observed. Thus it is believed that generation of fixed charge is responsible for the observed BTI shift in threshold voltage (VTH) and transconductance (GM). Also higher BTI degradation was recorded for short channel devices.
6

Gurfinkel, M., J. Suehle, J. B. Bernstein, Y. Shapira, A. J. Lelis, D. Habersat, and N. Goldsman. "Ultra-Fast Measurements of VTH Instability in SiC MOSFETs due to Positive and Negative Constant Bias Stress." In 2006 IEEE International Integrated Reliability Workshop Final Report. IEEE, 2006. http://dx.doi.org/10.1109/irws.2006.305209.

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Choi, Woojin, Hojin Ryu, Namcheol Jeon, Minseong Lee, Neung-Hee Lee, Kwang-Seok Seo, and Ho-Young Cha. "Impacts of conduction band offset and border traps on Vth instability of gate recessed normally-off GaN MIS-HEMTs." In 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD). IEEE, 2014. http://dx.doi.org/10.1109/ispsd.2014.6856053.

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Yamamoto, Marcio, Joji Yamamoto, and Sotaro Masanobu. "Study on Riser System in Hang-Off Configuration for Deep-Sea Mining." In Offshore Technology Conference Asia. OTC, 2022. http://dx.doi.org/10.4043/31672-ms.

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Abstract For Deep Sea Mining (DSM), the current concept for the Vertical Transport System (VTS) has multiple lines for the return of water to the sea bottom. Such VTS resembles a drilling riser, which is a field-proven technology. Our objective is to compare a drilling riser with different boundary conditions, including hang-off configuration. Numerical simulation was calculated using commercial software for dynamic analysis of riser systems. The simulation included a 1, 500m long riser, sea current, irregular waves, and the platform motion calculated using Response Amplitude Operator. For the top tensioned configuration, the tensioning system is required to avoid the riser pipe's buckling and the Mathieu Instability at the bottom portion of the riser. On the other hand, the same phenomenon did not occur in the hang-off configuration. The LMRP and BOP attached to the bottom end kept the riser pipe tensioned during the whole simulation. Therefore, the hang-off configuration is an important alternative for DSM riser. Besides, a tensioning system shall be mandatory for VTS when supported or attached to the seafloor.
9

Cha, Soonyoung, Chang-Chih Chen, Taizhi Liu, and Linda S. Milor. "Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements." In 2014 IEEE 32nd VLSI Test Symposium (VTS). IEEE, 2014. http://dx.doi.org/10.1109/vts.2014.6818769.

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McGinnis, Pat, Dave Albert, Zhigang Song, Johns Oarethu, Phong Tran, John Sylvestri, Greg Hornicek, and Mike Tenney. "Residual EG Oxide in FinFET Analyses and Its Impact to Yield, Product Performance, and Transistor Reliability." In ISTFA 2019. ASM International, 2019. http://dx.doi.org/10.31399/asm.cp.istfa2019p0317.

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Abstract This paper describes an electrical and physical failure analysis methodology leading to a unique defect called residual EG oxide (shortened to REGO); which manifested in 14nm SOI high performance FinFET technology. Theoretically a REGO defect can be present anywhere and on any multiple Fin transistor, or any type of device (low Vt, Regular Vt or High Vt). Because of the quantum nature of the FinFET and REGO occurrence being primarily limited to single Fins, this defect does not impact large transistors with multiple FINs; moreover, REGO was found to only impact 3 Fin or less transistors. Since REGO can be present on any multi-FIN transistor the potential does exist for the defect to escape test screening. Subsequently a reliability BTI (Bias Temperature Instability) stress experiment by nanoprobing at contact level was designed to assess REGO’s potential reliability impact. The BTI stress results indicate that the REGO defect would not result in any additional reliability or performance degradation beyond model expectations.

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