Dissertations / Theses on the topic 'Input amplifier'
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Maruf, Md Hasan. "An Input Amplifier for Body-Channel Communication." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-89878.
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Body-channel communication (BCC) is based on the principle of electrical field data transmission attributable to capacitive coupling through the human body. It is gaining importance now a day in the scenario of human centric communication because it truly offers a natural means of interaction with the human body. Traditionally, near field communication (NFC) considers as a magnetic field coupling based on radio frequency identification (RFID) technology. The RFID technology also limits the definition of NFC and thus reduces the scope of a wide range of applications. In recent years BCC, after its first origin in 1995, regain importance with its valuable application in biomedical systems. Primarily, KAIST and Philips research groups demonstrate BCC in the context of biomedical remote patient health monitoring system. BCC transceiver mainly consists of two parts: one is digital baseband and the other is an analog front end (AFE). In this thesis, an analog front end receiver has presented to support the overall BCC. The receiver (Rx) architecture consists of cascaded preamplifier and Schmitt trigger. When the signals are coming from the human body, they are attenuated around 60 dB and gives weak signals in the range of mV. A high gain preamplifier stage needs to amplify these weak signals and make them as strong signals. The preamplifier single stage needs to cascade for the gain requirement. The single stage preamplifier, which is designed with ST65 nm technology, has an open loop gain of 24.01 dB and close loop gain of 19.43 dB. A flipped voltage follower (FVF) topology is used for designing this preamplifier to support the low supply voltage of 1 V because the topology supports low voltage, low noise and also low power consumption. The input-referred noise is 8.69 nV/sqrt(Hz) and the SNR at the input are 73.26 dB. The Schmitt trigger (comparator with hysteresis) is a bistable positive feedback circuit. It builds around two stage OTA with lead frequency compensation. The DC gain for this OTA is 26.94 dB with 1 V supply voltage. The corner analyzes and eye diagram as a performance matrix for the overall receiver are also included in this thesis work.
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Li, Wendi M. Eng Massachusetts Institute of Technology. "Wide common mode input operational amplifier with serially programmable output offset." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/61302.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 132-133).
Operational amplifiers continue to develop to meet modern demands on performance. This document describes an operational amplifier designed for a highly specific telecommunications application - to serve as the buffer between an I/Q demodulator and Gm-C filter. Requirements set forth by this application call for a wide common mode input range, stretching from ground to the positive supply, and a programmable output offset, offering up to ±25mV differentially from the output common mode. This programmable offset is implemented using two complementary current mode digital-to-analog converters (DACs) directly driving the input pins of the operational amplifier. The output offset is serially programmed with a three pin SPI interface. In addition to programming the offset DACs, the SPI interface is also designed to be able to program four additional parameters necessary for the function of the programmable Gm-C filter, into which the opamp will be integrated.
by Wendi Li.
M.Eng.
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Catravas, Palmyra E. (Palmyra Evangeline). "MIT 3.3 GHz relativistic klystron amplifier : experimental study of input cavity and beam characteristics." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/34063.
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Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (leaves 74-75).
by Palmyra E. Catravas.
M.S.
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Вербіцький, Дмитро Олегович. "Операційний підсилювач на супер-β транзисторах." Bachelor's thesis, КПІ ім. Ігоря Сікорського, 2020. https://ela.kpi.ua/handle/123456789/35116.
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Thesis is devoted to the operational amplifier on the super-β transistor. The aim of the work is to develop such an amplifier whose characteristics would exceed the characteristics of other amplifiers.
The paper compared different operational amplifiers, explained the advantage of the considered amplifier, considered different types and methods of forming this amplifier.
The total volume of the work is 62 pages, 24 illustrations, 3 tables, 25 links.
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Jurčík, Petr. "Automatizované pracoviště pro měření parametrů zesilovačů." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219316.
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The aim of this work is to create an automated workplace for measuring the basic parameters of audio amplifiers using a graphical programming environment LabVIEW. Subsequently, the functionality will be verified in practical measurements on the real amplifier.
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Sun, J. (Jia). "Speeding up the settling of switched-capacitor amplifier blocks in analog-to-digital converters." Doctoral thesis, Oulun yliopisto, 2019. http://urn.fi/urn:isbn:9789526223902.
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Abstract The goal of this dissertation was to study and model the settling transient response of switched-capacitor (SC) circuit, which is the most important building block of Analog-to-Digital converters (ADCs), and to improve the settling performance of the SC circuit implemented in ADC in CMOS technology. In the design of the SC circuit, there are common obstacles in obtaining a precise and fast settling with low power consumption. The main contribution of this thesis is to speed up different SC circuits without adding extra power consumption or to achieve the required settling precision with low power consumption. Two solutions to reduce the power consumption of SC integrators in sigma-delta (SD) ADCs were designed and verified by simulations. These implementations are based on the passive charge redistribution technique by injecting a precalculated open-loop charge in the output of the first integrator. The injected charge was implemented either by a continuous function of the input and feedback voltages or by quantizing to three levels. In both cases, the idea is to minimize the initial transient voltage in the input of the first OTA and hence bypass the slewing of the OTA. Another approach was proposed for the traditional SC residue circuit of the pipeline ADC, where a load capacitor is connected to the output during the evaluation phase. Here, a pre-charge of the load capacitance can be used. One proposed implementation is called the continuously controlled pre-charged technique. It pre-charges the load capacitor to the proper voltage during the previous phase, connects the pre-charged load capacitor to the output of the OTA during the evaluation phase, and hence pulls the charge sharing so that the initial input step of the OTA is instantaneously minimized. The other implementation called the minimal pre-charged method implemented for the SC residue circuit of the pipeline ADC is to simply pre-charge the load capacitor with the fixed existing voltage, minimized the spread of the initial input voltage. This proposed technique did not require any additional active componentsTiivistelmä Kytkettyihin kapasitansseihin (SC-tekniikka) perustuvat vahvistimet ovat CMOS-tekniikkaan perustuvien analogia-digitaalimuuntimien (AD-muunnin) tärkeimpiä osia. Tämän väitöstyön tavoitteena oli tutkia ja mallittaa SC-tekniikkaan perustuvien vahvistinpiirien asettumisaikaa, ja etsiä piiriteknisiä keinoja asettumisajan nopeuttamiseksi. SC-piirien suunnittelun suurimpia ongelmia on saavuttaa tarkka ja nopea asettuminen mahdollisimman pienellä tehonkulutuksella. Tämän työn päätuloksina on joukko keinoja, joilla voidaan nopeuttaa SC-kytkettyjen vahvistimien asettumista ilman että niiden tehonkulutusta lisätään, tai saavuttaa aiempi suorituskyky pienemmällä tehonkulutuksella. Menetelmät perustuvat siihen, että SC-piirin passiivista varausjakautumista ohjataan niin, että vahvistimen tulosolmussa oleva transientti minimoituu, jolloin vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelle, vaan sen asettuminen nopeutuu merkittävästi. Sigma-delta-tyyppiset AD-muuntimet koostuvat SC-integraattoreista, ja näiden asettumisen nopeuttamiseen kehitettiin ja varmennettiin simuloiden kaksi tapaa. Varauksen jakautumista autettiin syöttämällä erillisellä varauspumpulla transkonduktanssivahvistimen lähtösolmuun tietty, integraattorin tilasta ja tuloista riippuva varaus. Tällöin vahvistimen tulossa näkyvä alkutransientti pienenee, ja vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelleen, jolloin sen asettumisvirhe pienenee merkittävästi. Varausinjektio toteutettiin kahdella eri tavalla: laskemalla tarvittava varaus joko jatkuvana funktiona tulosignaaleista, tai approksimoimalla sitä muutamalla diskreetillä tasolla. Pipeline-tyyppisissä AD-muuntimissa peruslohko koostuu SC-kytketystä vahvistimesta, jonka kuormakapasitanssi on kytkettynä vahvistimen lähtöön asettumisen aikana. Tämän kapasitanssin esivaraaminen sopivasti tarjoaa hyvin yksinkertaisen keinon ohjata varausjakautumista niin, että vahvistimen tulossa oleva transientti saadaan minimoitua ja toiminta virtarajoitteisessa moodissa vältettyä. Tässäkin tapauksessa kehitettiin ja varmennettiin kaksi vaihtoehtoista toteutusta. Ensimmäisessä kuormakapasitanssin esivarausjännite lasketaan tulosuureiden jatkuvana funktiona erillisellä summausvahvistimella. Toisessa, hyvin minimalistisessa ratkaisussa esivaraukseen käytetään kolmea käytettävissä olevaa kiinteää jännitettä. Tämä menetelmä ei vaadi lainkaan ylimääräisiä aktiivikomponentteja
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Ізюмкин, Петро Ілліч. "Автономний канал електроміографа з WI-FI модулем для робототехнічних систем." Bachelor's thesis, КПІ ім. Ігоря Сікорського, 2020. https://ela.kpi.ua/handle/123456789/35930.
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Обсяг звіту становить 68 сторінок, міститься 42 ілюстрації, 6таблиць, 0 додатків. Загалом опрацьовано 34 джерела.
Впровадження роботехнічних комплексів в медичну практику і стимуляційних пристроїв визиває необхідність розробки пристроїв отримання керуючих сигналів.
Один з таких пристроїв є електроміограф, якій дозволяє ефективно оцінювати та аналізувати рухи кінцівок.
Для використання сигналу в якості керування, електроміограф повинен достатньо точно визначити зусилля м’яза і передати його у інформативному вигляді.
Дана розробка призначена отримання пристрою здібного зареєструвати, перетворити у більш інформативну форму і передати сигнал іншому приладу.
Мета ДР: Розробити і виготовити канал електроміографа з WI-FI модулем.
Задачі ДП:
– Розробити МТВ згідно чинних стандартів;
– Розробити принципові схеми елементів каналу;
– Спроектувати, виготовити та випробувати прототипThe volume of the report is 68 pages, contains 42 illustrations, 6 tables, 0 annexes. 34 references were used. The introduction of robotic systems in medical practice and stimulating devices necessitates the development of devices for receiving control signals. One such device is an electromyograph, which allows you to effectively assess and analyze the movements of the limbs. To use the signal as a control, the electromyograph must accurately determine the force of the muscle and transmit it in an informative way. This work is designed to solve this problem. Purpose: Develop and manufacture an electromyograph channel with a WI-FI module. Tasks: – Develop medical and technical requirements according to current standards; – Develop schematic diagrams of channel elements; – Design, fabricate and test a prototype
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Pisár, Peter. "Metody návrhu aktivních kmitočtových filtrů na základě pasivního RLC prototypu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218107.
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The aim of this diploma thesis is to design active frequency filters based on passive RLC prototype. Three methods of the design of active filters and active functional blocks of electronic circuits working in current or mixed mode are used to this purpose. These blocks allow to process electrical signals with frequencies up to low tens of megahertz. In addition they feature for instance with high slew rate and low supply voltage power. Active high-pass and low-pass 2nd order filters are designed using simulation of inductor by active subcircuit method. Grounded and subsequently floating synthetic inductor is made with the current conveyors in the first case and with the current operational amplifiers with single input and differential output in the second case. This method advantage is relatively simple design and disadvantage is great quantity of active functional blocks. Active filters based on passive frequency ladder 3rd order filter while only one floating inductor is connected, are designed with circuit equation method. In the first design differential input / output current followers are used and in the second case current-differencing buffered amplifiers are used. This method benefits by smaller active blocks number and disadvantage is more complex design of the active filter. Active filter based on passive prototype of low-pass 3rd order filter with two floating inductors is designed with Bruton transformation method. Final active filter uses current operational amplifiers with single input and differential output which together with other passive elements replace frequency depending negative resistor, which arise after previous Bruton transform. This method usage is advantageous if the design consists of larger quantity of inductors and less number of capacitors. High-pass 2nd order filter is simulated by tolerance and parametrical analyses. Physical realisation utilising current feedback operational amplifier which substitute commercially hardly accessible current conveyors is subsequently made. Measurements of constructed active filter show that additional modifications, which allow better amplitude frequency characteristics conformity, are necessary.
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Cupák, Jan. "Nízkofrekvenční zesilovač ve třídě D pro aktivní reproduktory." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219135.
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This master's thesis deals with design of D class audio final amplifier, which was output power 400 W for 4 ? load impedance. Designed audio amplifier is specifical for active speaker, which consists of satelite speakers and subwoofer. Further more it deals also with other functional blocks, e.g. balanced input preamplifier, active crossover and protection for safety running. Outcome of this work are schemes of each functional blocks of D class audio amplifier, whose functionality was verified by simulation. Thesis also contains full reference material including mechanical arrangement of functional blocks on printed connection board. The conclusion contains the measured parameters of function blocks of produced prototype and complete photographic documentation.
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Kaštánek, Martin. "Vstupní díl UHF přijímače s velmi nízkou spotřebou." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217183.
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The purpose of this work was to make a proposal for input parts of receiver for band 430 to 440 MHz. A model of chosen semiconductor triode BFP540 was created in simulation software. Possibilities how to decrease consumption of this semiconductor triode, keeping the profit, were investigated through the simulation.In compromise consumption, keeping the profit of the amplifier - an optimal operating point for this semiconductor triode UCE = 1,2 V and IC = 2 mA was found. It was tested through the testing wiring with noise microstrips conformity. Ascertained knowledge was used for construction of tuner for UHF receiver. An operating point of input amplifier of UHF receiver was owing to power supply amplifier forced for bigger effectiveness to UCE = 2,65 V and IC = 2,0 mA. Suppression of mirror frequency is provided with Helix filter of the third order, because of intermediate frequency 10,7 MHz. Mixing on intermediate frequency is made again by semiconductor triode BFP540. Selectivity of receiver is provided with intermediate frequency crystal filter 10,7 MHz with bandwidth 15 kHz. Designed input part enables reception of SSB, FM and digital types of modulation.Bandwidth intermediate frequency exit is adapted to this request To receive particular modulation , it is necessary to complete intermediate frequency signal way with appropriate intermediate frequency filter.
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Ramadan, Ashraf. "Active antennas with high input impedance low noise and highly linear amplifiers." [S.l. : s.n.], 2005. http://deposit.ddb.de/cgi-bin/dokserv?idn=975739174.
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Garner, Jason R. "Millimetre and sub-millimetre wave input couplers for gyrotron travelling wave amplifiers." Thesis, University of Strathclyde, 2018. http://digitool.lib.strath.ac.uk:80/R/?func=dbin-jump-full&object_id=29375.
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The input coupler is an important component for a microwave amplifier. A sidewall single-hole input coupler for a W-band gyrotron travelling-wave amplifier that operates at the frequency range of 90–100 GHz was designed and measured. Instead of using a cutoff waveguide, a broadband Bragg-type reflector with a small spread in phase was optimized for use as part of the input coupler. The minimum radius of the reflector was two times the size of a cutoff waveguide, which reduced the possibility for some of the beam electrons being collected in this section and lost to the amplifier interaction region. The design, simulation, construction and measurement of a W-band waveguide input coupler that used a backstop Bragg reflector that allowed for high electron beam transmission from a cusp electron beam source into a 3-fold helically corrugated interaction waveguide (HCIW) of a gyrotron travelling wave amplifier is presented. Experimental results are reported of a broadband, high power, gyrotron traveling wave amplifier (gyro-TWA) operating in the 75-110 GHz frequency band. The second harmonic cyclotron mode of a 55 keV, 1.5 A, axis-encircling electron beam was used to resonantly interact with a traveling TE21-like eigenwave, achieving broadband amplification. The gyro-TWA demonstrated a 3 dB gain bandwidth of at least 5.5 GHz in the experimental measurement with 9 GHz predicted for a wideband drive source with a measured unsaturated output power of 3.4 kW and gain of 36-38 dB. The inclusion of the Bragg reflector in the W-band waveguide input coupler enabled efficient (4.4%) beam-wave interaction to be achieved within the gyro-TWA. The design of 1) a T-junction fundamental mode rectangular to- circular waveguide input coupler, 2) a multiple-hole input coupler and 3) a higher order mode (HOM) input coupler for a low-terahertz gyrotron travelling wave amplifier were studied. The T-junction input coupler with a Bragg reflector and a multiple-hole directional coupler were optimized for operation between 360 and 384 GHz, the proposed bandwidth of a low THz gyro TWA. The T-junction coupler and the multiple-hole coupler achieved the respective bandwidths of 10% and 35%.A higher order mode (HOM) two-branch waveguide coupler based on the even distribution of incident power was designed to couple the rectangular TE10 mode to the circular TE61 mode. The optimised tapered waveguide input coupler achieved an operating frequency range of 359–385 GHz, equating to a bandwidth of 7%. A prototype waveguide coupler scaled to W-band (75–110 GHz) was manufactured. The vector network analyser measured return loss of the HOM coupler was shown to be < 10 dB at 90–96 GHz. A transmission and phase measurement is presented to analyse TE61 mode conversion in the HOM coupler.
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Vieira, Filipe Costa Beber. "Amplificador de Instrumentação em Modo Corrente com entrada e saída Rail-to-Rail." Universidade Federal de Santa Maria, 2009. http://repositorio.ufsm.br/handle/1/5347.
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This dissertation is aimed at the development of a current mode instrumentation amplifier (CMIA) with a high common mode input range. This characteristic is obtained due
to the rail-to-rail operational amplifiers (opamps). These opamps are built with rail-to-rail differential amplifiers as input stages, and with cascode-based output stages, which are able to copy its current by adding identical branches and connecting their gates without the voltage
degradation as the known CMIA topologies. The main contribution of this work is the development of a rail-to-rail current mode instrumentation amplifier, analyzing the pros and cons of this topology. The functionality of the proposed topology is shown through measured results of a manufactured integrated circuit. This first prototype, although it was operated in a large input common mode range, presented insufficient values of CMRR (Common Mode
Rejection Ratio) and VOS (Offset voltage). These two characteristics were studied and modeled, the instrumentation amplifier was re-designed, and simulated results demonstrate important improvements.Esta dissertação tem como objetivo o desenvolvimento de um amplificador de instrumentação em modo corrente com uma ampla faixa de entrada em modo comum. Esta característica é obtida graças ao emprego de estágios de amplificação rail-to-rail na entrada e a geração do sinal de saída através do espelhamento da corrente diretamente dos gates dos transistores do estágio ao invés da alternativa clássica, onde espelhos são ligados em série e degradam a excursão do sinal de saída. Com esta proposta, é possível a implementação de ampops com entrada e saída rail-to-rail. A principal contribuição deste trabalho é analisar as vantagens e desvantagens da utilização destas soluções na implementação de um amplificador de instrumentação com entrada rail-to-rail. A funcionalidade da topologia proposta é demonstrada através dos resultados medidos de um circuito integrado fabricado. Este primeiro protótipo, apesar do bom funcionamento em toda a faixa de entrada em modo comum, apresentou valores insatisfatórios de CMRR (Common Mode Rejection Ratio) e de VOS (Tensão de offset), o que levou a um aprofundamento no estudo e modelagem destas características. A partir disto, o circuito foi re-projetado e os resultados de simulação demonstram melhorias bastante significativas em suas características.
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Šnajdr, Václav. "Vysokofrekvenční a mezifrekvenční obvody krátkovlnné radiostanice." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217792.
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The study, description, design and implementation of selected blocks of multiband shortwave radio station are dealt with in the thesis. Focus is placed on the concept of multiband shortwave radio stations, with an emphasis on high frequency and intermediate frequency circuits. The first chapter is devoted to description of the transceiver block diagram which is designed as superheterodyne. The design of bandpass input filters, intermediate frequency crystal filters and output filters is described. Simulation results and the measured characteristics of the implemented functional blocks are presented. Furthermore, the amplifier circuits which maintain impedance matching of individual blocks are discussed. SSB signal generation in the transmitter part of radio station and final stage power amplification are depicted.
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Courty, Alexis. "Architecture d'amplificateur de puissance linéaire et à haut rendement en technologie GaN de type Doherty numérique." Thesis, Limoges, 2019. http://www.theses.fr/2019LIMO0067/document.
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Les fortes capacités actuelles et envisagées des futurs liens satellites de communication pour la 5G conduisent les signaux traités dans les charges utiles à présenter simultanément d'importantes variations d'amplitude (PAPR>10dB) et de très larges bandes passantes instantanées (BW>1GHz). A l'intérieur du sous-système d'émission hyperfréquence, le fonctionnement du module d'amplification de puissance se trouve très contraint par les formes d'ondes véhiculées, il se présente comme l'un des postes de consommation énergétique des plus importants, et ayant le plus d'impact sur l'intégrité du signal émis. Dans ce contexte, les fonctions dédiées au traitement numérique des signaux et couramment implémentées par le processeur numérique (telles que le filtrage, la canalisation, et éventuellement la démodulation et la régénération des signaux bande de base) embarquées dans les charges utiles, représentent une solution à fort potentiel qui permettrait de relâcher les contraintes reportées sur la fonction d'amplification de puissance afin de gérer au mieux la ressource électrique allouée. Ces travaux de thèse proposent d'étudier les potentialités d'amélioration du fonctionnement en rendement et linéarité d'un amplificateur de type Doherty à double entrée de gamme 20W en technologie GaN et fonctionnant en bande C. La combinaison des signaux de puissance sur la charge RF est optimisée par une distribution optimale des signaux en amplitude et phase à l'entrée par des moyens numériques de génération. Dans un premier temps une méthodologie de conception large bande d'un amplificateur Doherty est introduite et validée par la conception d'un démonstrateur en bande C. Dans un second temps, l'outil expérimental permettant l'extraction des lois optimales de distribution d'amplitude et de phase RF est présenté en détail, et la caractérisation expérimentale du dispositif en double entrée est réalisée puis comparée aux simulations. Finalement, en perspective à ces travaux, une étude préliminaire des potentialités de l'architecture Doherty à double entrée pour la gestion d’une désadaptation de la charge de sortie (gestion de TOS) est menée et des résultats sont mis en avantThe high capabilities of current and future 5G communication satellite links lead the processed signals in the payloads to simultaneously exhibit large amplitude variations (PAPR>10dB) and wide instantaneous bandwidths (BW>1GHz). Within the microwave transmission subsystem, the operation of the power amplification stage is highly constrained by the transmitted waveforms, it is one of the most energy-consuming module of the payload affecting as well the integrity of the transmitted signal. In this context, the functions dedicated to digital signal processing and currently implemented by the digital processor (such as filtering, channeling, and possibly the demodulation and regeneration of baseband signals) embedded in the payloads, represent a potential solution that would reduce the constraints reported on the power amplification function and help to manage the allocated power ressource. This work proposes a study on the capability of dual input power amplifier architectures in order to manage the efficiency-linearity trade-off over a wide bandwidth. This study is carried out on a 20W GaN Doherty demonstrator operating in C band. The combination of the output signals on the RF load is managed by an optimal amplitude and phase distribution that is digitally controlled at the input. Firstly, a wideband design methodology of Doherty amplifier is introduced and validated on a C band demonstrator. In a second time the experimental tool allowing the extraction of amplitude and phase input distributions is presented, the dual input characterization is achieved and compared with simulation results. Finally, in perspective of this work, a preliminary study of the capabilities of the digital Doherty for the management of an output load mismatch (VSWR management) is carried out and the results are put forward
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Wang, Lu. "A 256-input micro-electrode array with integrated cmos amplifiers for neural signal recording." Thesis, Boston University, 2013. https://hdl.handle.net/2144/11080.
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Thesis (Ph.D.)--Boston UniversityThe nervous system communicates and processes information through its basic structural units -- individual neurons (nerve cells). Neurons convey neural information via electrical and chemical signals, which makes electrophysiological recording techniques very important in the study of neurophysiology. Specifically, active microelectrode arrays (MEAs) with amplifiers integrated on the same substrate are used because they provide a very powerful neural electrical recording technique that can be directly interfaced to acute slices and cell cultures. 2D planer electrodes are typically used for recording from neural cultures in vitro, while in vivo recording in live animals invariably requires the use of 3D electrodes. I have designed an active MEA with neural amplifiers and 3D electrodes, all integrated on a single chip. The electrodes are commercially available 3D C4 (Controlled Collapse Chip Connect) flip-chip bonding solder balls that have a diameter of 100 µm and a pitch of 200 µm. An active MEA neural recording chip -- the Multiple-Input Neural Sensor (MINS) chip -- was designed and fabricated using the IBM BiCMOS 8HP 0.13 µm technology. The MINS IC has 256 input channels that are time-division multiplexed into two output pads. Each channel was designed to work at a 20 kHz frame rate with a total voltage gain of 60 dB per channel with an input-referred noise voltage of 5.3 µVrms over 10 Hz to 10 kHz. The entire MINS chip has an area of 4 x 4 mm^2 with 256 input C4s plus 20 wire-bond pads on two adjacent edges of the chip for power, control, and outputs. The fabricated MINS chips are wire-bonded to standard pin grid array (PGA), open-top PGA, and custom-designed printed circuit board (PCB) packages for electrical, in vitro, and in vivo testing, respectively. After process variation correction, the voltage gain of the 256 neural amplifiers, measured in vitro across several chips, has a mean value of 58.7 dB and a standard deviation of 0.37 dB. Measurements done with the electrical testing package demonstrate that the MINS IC has a flat frequency response from 0.05 Hz to 1.4 MHz, an input-referred noise voltage of 4.6 µVrms over 10 Hz to 10 kHz, an output voltage swing as large as 1.5 V peak-to-peak, and a total power consumption of 11.25 mW, or 43.9 µW per input channel.
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Ayad, Mohammed. "Etude et Conception d’amplificateurs DOHERTY GaN en technologie Quasi - MMIC en bande C." Thesis, Limoges, 2017. http://www.theses.fr/2017LIMO0027.
Full textAbstract:
Ce travail répond à un besoin industriel accru en termes d’amplification des signaux sur porteuses à enveloppes variables utilisés par les systèmes de télécommunications actuels. Ces signaux disposent d’un fort PAPR et d’une distribution statistique d’enveloppe centrée en-deçà de la valeur crête d’enveloppe. La raison pour laquelle les industriels télécoms requièrent alors des amplificateurs de très fortes puissances de sortie, robustes, fiables et ayant une dépense énergétique optimale le long de la dynamique d’enveloppe associée à un niveau de linéarité acceptable. Ce document expose les résultats d’étude et de réalisation de deux Amplificateurs de Puissance Doherty (APD) à haut rendement encapsulés en boîtiers plastiques QFN. Le premier est un amplificateur Doherty symétrique classique (APD-SE) et le second est un amplificateur à deux entrées RF (APD-DE). Ces démonstrateurs fonctionnant en bande C sont fondés sur l’utilisation de la technologie Quasi-MMIC associant des barrettes de puissance à base des transistors HEMTs AlGaN/GaN sur SiC à des circuits d’adaptation en technologie ULRC. L’approche Quasi-MMIC associée à la solution d’encapsulation plastique QFN permettant une meilleure gestion des comportements thermiques offre des performances électriques similaires à celles de la technologie MMIC avec des coûts et des cycles de fabrication très attractifs. Durant ces travaux, une nouvelle méthode d’évaluation des transistors dédiés à la conception d’amplificateurs Doherty a été développée et mise en oeuvre. L’utilisation intensive des simulations électromagnétiques 2.5D et 3D a permis de bien prendre en compte les effets de couplages entre les différents circuits dans l’environnement du boîtier QFN. Les résultats des tests des amplificateurs réalisés fonctionnant sur une bande de 1GHz ont permis de valider la méthode de conception et ont montré que les concepts avancés associés à l’approche Quasi-MMIC ainsi qu’à des technologies d’encapsulation plastique, peuvent générer des fonctions micro-ondes innovantes. Les caractérisations de l’APD-DE ont relevé l’intérêt inhérent à la préformation des signaux d’excitation et des points de polarisation de chaque étage de l’amplificateurThis work responds to an increased industrial need for on carrier signals with variable envelope amplification used by current telecommunications systems. These signals have a strong PAPR and an envelope statistical distribution centred below the envelope peak value, the reason why the telecom industrialists then require a robust and reliable high power amplifiers having an energy expenditure along of the envelope dynamics associated with an acceptable level of linearity. This document presents the results of the study and realization of two, high efficiency, Doherty Power Amplifiers (DPA) encapsulated in QFN plastic packages. The first is a conventional Doherty power Amplifier (DPA-SE) and the second is a dual-input Doherty power amplifier (DPA-DE). These C-band demonstrators are based on the use of Quasi-MMIC technology combining power bars based on the AlGaN/GaN transistors on SiC to matching circuits in ULRC technology. The Quasi-MMIC approach combined with Quasi-MMIC approach combined with QFN plastic package solution for better thermal behaviour management offers electrical performances similar to those of MMIC technology with very attractive coasts and manufacturing cycles. During this work, a new evaluation method for the transistors dedicated to the design of DPA was developed and implemented. The intensive use of 2.5D and 3D electromagnetic simulations made it possible to take into account the coupling effects existing between the different circuits in the QFN package environment. The results of the tests of the amplifiers realised and operating on 1GHz bandwidth validated the design method and showed that the advanced concepts associated with the Quasi-MMIC approach as well as plastic encapsulation technologies can generate innovative microwave functions. The characterizations of the DPA-DE have noted the interest inherent in the preformation of the excitation signals and the bias points of each stage of the amplifier
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Hudzik, Martin. "Návrh Rail-to-Rail proudového konvejoru v technologii CMOS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-242143.
Full textAbstract:
Master’s thesis deals with design of rail-to-rail second generation current conveyor in CMOS technology. Describes principles of function of different generations of current conveyors, as well as the basic principle of design of second generation current conveyor based on operational amplifier. Addresses circuit topology of input rail-to-rail stage and class AB output stage. The objective of this thesis is to design, characterize performance and create layout of second generation current conveyor with input common mode voltage rail-to-rail capability in ONSemi I3T25 technology.
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Marek, Pavel. "Měření přenosových a imitančních charakteristik aktivních obvodových prvků." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218000.
Full textAbstract:
This diploma work deals with active circuit elements and proposals of methods for measuring of some parameters of these elements. In the opening part the work deals with general classification of elements used in electronic circuits, ideal and real current sources and power supplies. Further there are stated basic parameters and characteristics presented by producers in a catalogue sheet for active elements MAX435, OPA660, AD844 and MAA741 element which already belongs to the history of IC. Main attention is paid to active circuit elements with current sources driven by CCCS (Current Controlled Current Source) and AD844 (high speed monolithic operational amplifier). In the work there is described a method for determining of selected parameters of active elements with CCCS. Examined parameters were frequency characteristics of current transfer, input impedance and output impedance. The proposed method was verified by a computer simulation on above mentioned active elements by means of PSpice software. Findings along with the description are summarized at the end of the work. In the closing part of the work there is undertaken a real measure of AD844 element based on the proposed method and the findings are compared with particular simulations. However, at first a flat connection board was made by means of EAGLE software and then the measure was performed on it.
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Al-Yasir, Yasir I. A., Ahmed M. Abdulkhaleq, Naser O. Parchin, I. T. Elfergani, J. Rodriguez, James M. Noras, Raed A. Abd-Alhameed, A. Rayit, and Rami Qahwaji. "Green and Highly Efficient MIMO Transceiver System for 5G Heterogenous Networks." IEEE, 2007. http://hdl.handle.net/10454/18574.
Full textAbstract:
YesThe paper presents the general requirements and an exemplary design of the RF front-end system that in today´s handset is a key consumer of power. The design is required to minimize the carbon footprint in mobile handsets devices, whilst facilitating cooperation, and providing the energy-efficient operation of multi-standards for 5G communications. It provides the basis of hardware solutions for RF front-end integration challenges and offers design features covering energy efficiency for power amplifiers (PAs), Internet of Things (IoT) controlled tunable filters and compact highly isolated multiple-input and multiple-output (MIMO) antennas. An optimum design requires synergetic collaboration between academic institutions and industry in order to satisfy the key requirements of sub-6 GHz energy-efficient 5G transceivers, incorporating energy efficiency, good linearity and the potential for low-cost manufacturing. A highly integrated RF transceiver was designed and implemented to transmit and receive a picture using compact MIMO antennas integrated with efficient tunable filters and high linearity PAs. The proposed system has achieved a bit error rate (BER) of less than 10-10 at a data rate of 600 Mb/s with a wireless communication distance of more than 1 meter and power dissipation of 18-20 mW using hybrid beamforming technology and 64-QAM modulation.
10.13039/100010665-H2020 Marie Skodowska Curie
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Al-Yasir, Yasir, Ahmed M. Abdulkhaleq, Naser O. Parchin, I. T. Elfergani, J. Rodriguez, James M. Noras, Raed A. Abd-Alhameed, A. Rayit, and Rami Qahwaji. "Green and Highly Efficient MIMO Transceiver System for 5G Heterogenous Networks." IEEE, 2021. http://hdl.handle.net/10454/18574.
Full textAbstract:
YesThe paper presents the general requirements and an exemplary design of the RF front-end system that in today´s handset is a key consumer of power. The design is required to minimize the carbon footprint in mobile handsets devices, whilst facilitating cooperation, and providing the energy-efficient operation of multi-standards for 5G communications. It provides the basis of hardware solutions for RF front-end integration challenges and offers design features covering energy efficiency for power amplifiers (PAs), Internet of Things (IoT) controlled tunable filters and compact highly isolated multiple-input and multiple-output (MIMO) antennas. An optimum design requires synergetic collaboration between academic institutions and industry in order to satisfy the key requirements of sub-6 GHz energy-efficient 5G transceivers, incorporating energy efficiency, good linearity and the potential for low-cost manufacturing. A highly integrated RF transceiver was designed and implemented to transmit and receive a picture using compact MIMO antennas integrated with efficient tunable filters and high linearity PAs. The proposed system has achieved a bit error rate (BER) of less than 10-10 at a data rate of 600 Mb/s with a wireless communication distance of more than 1 meter and power dissipation of 18-20 mW using hybrid beamforming technology and 64-QAM modulation.
10.13039/100010665-H2020 Marie Skodowska Curie
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Al-Yasir, Yasir, Ahmed M. Abdulkhaleq, Naser O. Parchin, Issa T. Elfergani, J. Rodriguez, James M. Noras, Raed A. Abd-Alhameed, A. Rayit, and Rami Qahwaji. "Green and Highly Efficient MIMO Transceiver System for 5G Heterogenous Networks." IEEE, 2021. http://hdl.handle.net/10454/18574.
Full textAbstract:
YesThe paper presents the general requirements and an exemplary design of the RF front-end system that in today´s handset is a key consumer of power. The design is required to minimize the carbon footprint in mobile handsets devices, whilst facilitating cooperation, and providing the energy-efficient operation of multi-standards for 5G communications. It provides the basis of hardware solutions for RF front-end integration challenges and offers design features covering energy efficiency for power amplifiers (PAs), Internet of Things (IoT) controlled tunable filters and compact highly isolated multiple-input and multiple-output (MIMO) antennas. An optimum design requires synergetic collaboration between academic institutions and industry in order to satisfy the key requirements of sub-6 GHz energy-efficient 5G transceivers, incorporating energy efficiency, good linearity and the potential for low-cost manufacturing. A highly integrated RF transceiver was designed and implemented to transmit and receive a picture using compact MIMO antennas integrated with efficient tunable filters and high linearity PAs. The proposed system has achieved a bit error rate (BER) of less than 10-10 at a data rate of 600 Mb/s with a wireless communication distance of more than 1 meter and power dissipation of 18-20 mW using hybrid beamforming technology and 64-QAM modulation.
10.13039/100010665-H2020 Marie Skodowska Curie
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HWA-YUAN, LIU, and 劉華元. "Digital Input Class-D Audio Amplifier Design." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/04894591351221180693.
Full textAbstract:
碩士中華技術學院
電子工程研究所碩士班
96
Abstract Due to power saving is current trend for portable electronic product and it is very import to design a system. Although audio amplifier design and application focus quality before,but people are leading concern for efficiency to use consumer product now. First, this master thesis introduce traditional audio amplifier structure and characteristic of Class A,B,AB, moreover, we compare with digital input audio amplifier Class D.we also detail various characteristics and advantage of Class D in the preceding chapter. The major content is discussed how to design a digital input modulator of Class D. We design this digital structure include gain control、3 stage filter、5 order 6 bits sigma-delta modulator and PWM. Per our analysis form actual measurement we have to observe if we achieve original opinion, or not? Maybe we can obtain a way to improve the defects further.
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Li, Chan-Chuan, and 李展權. "Built-In Self-Measurement for SRAM Sense Amplifier Input Signal." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/11187361891757021300.
Full textAbstract:
碩士國立清華大學
電機工程學系
93
Abstract The Static Random Access Memory (SRAM) is an important storage element for the embedded system and generally used today. The sense amplifier of SRAM is utilized to speed up the read operation so that it is a critical influence to the output. The input signals of the sense amplifier are very weak and determine if the sense process succeed or not so it is difficult to measure. We need an accurate and valid circuit to reach the goal. With it the measurement process is automatic and only the lower-end test machine is need. Besides, a new fault model IVDF (insufficient voltage difference fault) is proposed to model the behavior of SRAM cell. We can detect the faulty cell and locate it. The proposed circuit is simulated with 1-K-bit SRAM by using the UMC 0.18um 1P6M Mixed-signal CMOS process.
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Huang, Kuan Lin, and 黃冠霖. "Research of High Efficiency Doherty Power Amplifier with Adjustable Input Power Ratio of Main and Auxiliary Amplifiers." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/23158456783739496114.
Full text
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Sheng, Yi-Ming, and 盛以明. "A Measurement Unit for Input Signal Analysis of SRAM’s Sense Amplifier." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/27964862236796017556.
Full textAbstract:
碩士國立清華大學
電機工程學系
92
A Static Random Access Memory (SRAM) measurement unit is presented to sample the voltage signals of bit line pairs and to amplify the weak signal to higher voltage differential level. According to the measured result, the reliability analysis can be easily completed through curve fitting process. The proposed circuit is designed and simulated with a 1K-bit SRAM by using the UMC 0.18μm 1P6M CMOS process. The analyzed result can provide designers to verify/strengthen their memory circuit design.
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"Operational transconductance amplifier with a rail-to-rail constant transconductance input stage." 2002. http://library.cuhk.edu.hk/record=b5891100.
Full textAbstract:
Chan Shek-Hang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.
Includes bibliographical references (leaves 94-97).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgement --- p.iv
Table of Contents --- p.v
List of Figures --- p.ix
List of Tables --- p.xiii
Chapter Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Overview --- p.1
Chapter 1.2 --- Significance of the research --- p.2
Chapter 1.3 --- Objectives --- p.3
Chapter 1.4 --- Thesis outline --- p.4
Chapter Chapter 2 --- Background theory --- p.5
Chapter 2.1 --- Introduction --- p.5
Chapter 2.2 --- Electrical properties of MOS transistors --- p.5
Chapter 2.2.1 --- Strong inversion --- p.5
Chapter 2.2.2 --- Weak inversion --- p.6
Chapter 2.2.3 --- Moderate inversion --- p.8
Chapter 2.2.4 --- The transistors biased in this work --- p.8
Chapter 2.3 --- Rail-to-rail signals --- p.8
Chapter 2.4 --- Rail-to-rail operational amplifier --- p.10
Chapter 2.4.1 --- Rail-to-rail differential input pairs --- p.10
Chapter 2.4.1.1 --- Principle --- p.10
Chapter 2.4.1.2 --- Two stage operational amplifier --- p.13
Chapter 2.4.2 --- Folded-cascode gain stage --- p.14
Chapter 2.5 --- The nature of operational amplifier distortion --- p.16
Chapter 2.5.1 --- The total harmonic distortion --- p.17
Chapter Chapter 3 --- Constant transconductance rail-to-rail input stage --- p.20
Chapter 3.1 --- Introduction --- p.20
Chapter 3.2 --- Review of constant-gm input stage --- p.20
Chapter 3.2.1 --- Rail-to-rail input stages with current-based gm control --- p.20
Chapter 3.2.1.1 --- gm controlled by three-times current mirror --- p.21
Chapter 3.2.1.2 --- gm controlled by square root current control --- p.23
Chapter 3.2.1.3 --- gm controlled by using current switches only --- p.25
Chapter 3.2.2 --- Rail-to-rail input stages with voltage-based gm control --- p.28
Chapter 3.2.2.1 --- gm controlled by an ideal zener diode --- p.28
Chapter 3.2.2.2 --- gm controlled by two diodes --- p.30
Chapter 3.2.2.3 --- gm controlled by an electronic zener --- p.31
Chapter 3.3 --- Conclusion --- p.32
Chapter Chapter 4 --- Proposed constant transconductance rail-to-rail input stage --- p.34
Chapter 4.1 --- Introduction --- p.34
Chapter 4.2 --- Principle of the conventional input stage --- p.35
Chapter 4.2.1 --- Translinear circuit --- p.35
Chapter 4.3 --- Previous work --- p.36
Chapter 4.3.1 --- Input bias circuit --- p.36
Chapter 4.3.2 --- Weak inversion operation --- p.38
Chapter 4.3.3 --- Power up problem --- p.43
Chapter 4.4 --- Operational transconductance amplifier with proposed input biased stage --- p.47
Chapter 4.4.1 --- Proposed input biased stage architecture --- p.47
Chapter 4.4.2 --- Proposed input biased stage with 2 gm control circuits --- p.50
Chapter 4.4.3 --- OTA with proposed input biased stage --- p.51
Chapter Chapter 5 --- Simulation Results --- p.54
Chapter 5.1 --- Introduction --- p.54
Chapter 5.2 --- DC bias simulation --- p.54
Chapter 5.2.1 --- Total transconductance variation --- p.54
Chapter 5.2.2 --- Power consumption --- p.56
Chapter 5.3 --- AC simulation --- p.56
Chapter 5.3.1 --- Open-loop gain --- p.57
Chapter 5.3.2 --- Gain-bandwidth product --- p.59
Chapter 5.3.3 --- Phase margin --- p.59
Chapter 5.4 --- Transient simulation --- p.60
Chapter 5.4.1 --- Voltage follower --- p.60
Chapter 5.4.2 --- Total harmonic distortion --- p.62
Chapter 5.4.3 --- Step response --- p.65
Chapter 5.5 --- Conclusion --- p.67
Chapter Chapter 6 --- Layout Consideration --- p.68
Chapter 6.1 --- Introduction --- p.68
Chapter 6.2 --- Substrate tap --- p.68
Chapter 6.3 --- Input protection circuitry --- p.69
Chapter 6.4 --- Die micrographs of the OTA --- p.71
Chapter Chapter 7 --- Measurement Results --- p.74
Chapter 7.1 --- Introduction --- p.74
Chapter 7.2 --- DC bias measurement results --- p.74
Chapter 7.2.1 --- Total transconductance variation --- p.74
Chapter 7.2.2 --- Power consumption --- p.77
Chapter 7.3 --- AC measurement results --- p.78
Chapter 7.3.1 --- Open-loop gain --- p.78
Chapter 7.3.2 --- Gain-bandwidth product --- p.81
Chapter 7.3.3 --- Phase margin --- p.81
Chapter 7.4 --- Transient measurement result --- p.82
Chapter 7.4.1 --- Voltage follower --- p.82
Chapter 7.4.2 --- Total harmonic distortion --- p.85
Chapter 7.4.3 --- Step response --- p.87
Chapter 7.5 --- Conclusion --- p.88
Chapter Chapter 8 --- Conclusion --- p.90
Chapter 8.1 --- Contribution --- p.90
Chapter 8.2 --- Further development --- p.91
Chapter Chapter 9 --- Appendix --- p.92
Chapter Chapter 10 --- Bibliography --- p.94
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Wang, Huei-Chi, and 王惠琪. "Design of Current Mode Operational Amplifier with Differential Input and Differential Output." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/90020224361357870789.
Full textAbstract:
碩士淡江大學
電機工程學系
85
In the last few decades, the analogue designers more thought about processing signal by current mode signal. As the current mode circuit compares with the voltage mode circuit, the former proves to be two conceptual advantages: higher frequency capabilities and larger dynamic range. And the architecture of current mode circuit form, it is more convenient and direct to copy or operate the signal than the voltage mode. Such as the switch current filter in the recently developing. In this thesis, a new CMOS current operational amplifier (COA) with fully differential input and differential output is proposed and analyzed. The amplifier is implemented from a differential current mirror input transimpedance stage followed by a differential output transconductance gain stage. A differential mode design technique is proposed and used in the feedback circuit. The simulation results of the new COA are based upon the 0.5um CMOS process and ±1.5V supply voltage. The new COA exhibits an open-loop differential gain of 51.71dB with the gain-bandwidth product 314MHz and a settling time of 14ns. To design VLSI circuit in the recent, the mix mode circuit design is the future trend in order to cooperate with the digital process. So the low voltage, and low power analogue circuit design is indispensable. Specially in the mobile personal communication system. So in this paper, we first analysis the basis current cell circuits, e.g. low voltage current mirror. And we will discuss the property of the circuit, as follows describe: (a) bandwidth improvement (b) parasitic capacitor effect improvement (c) unit step function time response (d) temperature stability discussion (e) bias circuit and dynamic range discussion In the last, the applications of the COA in processing current signals are proven to be the counterpart of the traditional voltage mode operational amplifier (VOA). The current integrator and the current Biquad filter show their duality with voltage integrator and Biquad. In the domain of filter design, COA is proven to be applicable to MOS-C current filter as well as SC voltage filter. Thus this COA can be used to process the signals on chip.
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Fang, Wei-Hsien, and 方偉憲. "Low-Power Operational Amplifier with High-Gain Rail-to-Rail Input and Output Ranges." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/70004757408515675928.
Full textAbstract:
碩士淡江大學
電機工程學系碩士在職專班
98
A low-power high-gain CMOS operational amplifier with rail-to-rail input/output ranges is presented in this paper. A constant-gm controller is employed in the input stage to achieve an optimum bandwidth and settling response in a wide operational range. A differential-input single-output gain-boosting amplifier without common-mode feedback is applied to minimize the power consumption and increase the dc gain of opamp. The floating current sources are also introduced to the cascode stage to provide proper bias levels for the class AB output stage. The proposed opamp can load with a large capacitance or a small resistance loads without losing the gain and unity-gain bandwidth. It has been fabricated in a 0.35 μm 2P4M CMOS process. With a 50 pF of the output capacitance load, a 123dB of dc gain and a 1.52MHz of unity-gain frequency can be achieved in the proposed opamp. The total power dissipation is only 0.36 mW at a 3.3 V of supply voltage.
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pan, sheng-wen, and 潘聖文. "Low Power Rail-to-Rail Input Stage Operational Transconductance Amplifier for Biomedical System Application." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/62665708499160164958.
Full textAbstract:
碩士中原大學
電子工程研究所
97
The development of integrated circuit (IC) technologies for biomedical system applications has been widely used in recent years. Moreover, it has brought a considerable amount of portable and implantable biomedical equipment. In order to satisfy with ambulatory functions, low power and low voltage has been essential condition for the front-end circuit. Hence, as a basic analog building block, operational transconductance amplifier (OTA) has a limited voltage headroom due to the low battery-voltage characteristics, and it thereby needs rail-to-rail input signal swing to maximize the signal operational range. The paper present a low-power low-voltage rail-to-rail operational transconductance amplifier (OTA), which combined bulk-driven differential pair, PMOS differential pair, shunt down circuit and folded cascode load. Based on the proposed topology, the low voltage OTA with rail-to-rail input common-mode range is achieved. The scheme not only avoids leakage current of conventional bulk-driven circuit but also reduces power consumption. The simulated power consumption of the OTA is 23μW under conditions of 0.9V supply voltage in TSMC 0.35μm Mixed Signal 2P4M Polycide 3.3/5V technology.
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Chen, Chien-Lin, and 陳建霖. "Low Input Offset and Common Mode Voltage Amplifier Applied to LLC Synchronous Rectifier Controller." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/24290540197624275715.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
98
The requirements of the power converter efficiency are gradually increasing, therefore, the synchronous rectifier had been provided for LLC converter. The basic concept of synchronous rectifier is utilized a transistor switch to replace the traditional rectifying diode and a synchronous controller is required to control the transistor switch to work as a rectifying diode. Nonetheless, owing to the nonideal phenomena of the manufacture process, the comparator of the synchronous controller suffers an offset voltage which affects the signal from the LLC system. Therefore, the synchronous controller can not be turned off in time and the power conversion efficiency is decreased. In this thesis, a preamplifier with low input offset voltage and low common mode voltage is provided. Due to characteristic of the low input offset voltage, signal from LLC system will not be affected and can be amplified then transferred to the comparator. The characteristic of low common mode voltage ensures the preamplifier works.
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Lin, Ming-Dao, and 林明道. "A Novel Wide Band Low Noise Amplifier using Negative Resistance Input Matching for LTE Applications." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/15789984303620588983.
Full textAbstract:
碩士國立交通大學
電信工程研究所
102
In this thesis, a novel wide band low noise amplifier combined negative resistance with common gate structure for LTE applications are presented. The research focused on how to reduce the power consumption and noise figure, and using negative resistance to achieve the effect of input impedance matching. In the past, the design of low-noise amplifier used RLC feedback or lengthy inductance, capacitance in series and parallel to achieve broadband matching circuit at the input, however our circuit used fewer of components to increase the bandwidth. In our design, a common gate amplifier with negative resistance using the frequency independent of the transistor current is to replace the traditional architecture of passive inductor at input, and with the gm-boost technique to achieve low power and noise reduction effectively. The shunt peaking network at drain is drawn to further suppress the high-frequency noise and a low noise level is achieved. The proposed LNA is implemented by the TSMC 0.18-μm CMOS technology process, and measured by use of CIC instruments. The measured results are as follows: bandwidth of 0.5 ~ 3.7 GHz, input and output reflection loss are greater than -12 dB, the maximum power gain is 17.8 dB, the minimum noise figure is 3.3 dB, at 2.7 GHz, the P1dB gain compression point is -20 dBm, the IIP3 cut-off point is -10.3 dBm, the core circuit power consumption is 6.48 mW, and the overall layout area including the pads is 0.716 * 0.744 = 0.533 mm2.
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Hsu, Yuan-Wen, and 許媛雯. "Design of Low-Power High-Gain Operational Amplifier with Rail-to-Rail Input and Output Ranges." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/10397192373285911996.
Full textAbstract:
碩士淡江大學
電機工程學系碩士在職專班
102
This thesis presents an operational amplifier which function could meet the new requirement of nowadays. Following the improvement of VLSI (Very Large Scale Integrated Circuits) design and CMOS (Complementary Metal Oxide Semiconductor) process, the design of OPA (Operational Amplifier) has many choices for different applications and purposes. The new tendency of OPA applications would be high gain, low power consumption, rail-to-rail input/output range, better stability, better driving capability and low cost, etc., which would be the goal of this proposed OPA to be designed. The architecture of this proposed OPA includes 3 major stages: the first stage is the differential inputs stage combined with constant-gm controller; the second stage is the folded-cascode amplifier stage constructed of cascode, floating current source and gain boosting amplifiers; the third stage is the single-ended output stage consisted of a class AB push-pull amplifier. The goal of this OPA is to achieve that gain equals over 120dB, phase margin equals around 60°~63°, unity-gain frequency equals 1.5MHz, power consumption equals 0.37mW, the input/output range reaches the maximum, and the driving load is up to 50pF capacitor or lowest to 10kΩ resistor, etc. The fabrication of this proposed OPA is implemented by the 0.35μm 2P4M CMOS process of CIC (Chip Implementation Center). The final result of this OPA is that gain equals 123dB, phase margin 61.4°, unity-gain frequency 1.52MHz, power consumption equals 0.37mW, the input/output range reaches from 0V to 3.3V, and the driving load is stable up to 50pF capacitor or lowest to 10kΩ resistor.
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Huang, Chun-Jen, and 黃俊仁. "Design and Implementation of Low Voltage Rail-to-Rail CMOS Operational Amplifier Using Dual Differential Input Pairs." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/98438983359573886137.
Full textAbstract:
碩士輔仁大學
電子工程學系
92
In this work, we present three low-voltage CMOS amplifiers. The first amplifier with dual P-channel differential pairs, that combines a P-channel differential input pair and a level-shift P-channel differential input pair, obtain rail-to-rail signaling. Under 1 volts supply voltage, the input common mode range is 0.15~0.93V. The second amplifier with dual P-channel differential pairs and current driven bulk （C.D.B.）skill, that apply C.D.B. skill to reduce Vt of differential pairs , obtain rail-to-rail signaling. Under 1 volts supply voltage, the input common mode range is 0.02~0.98V. The third amplifier with dual N-channel differential pairs, that combines a N-channel differential input pair and a level-shift N-channel differential input pair, obtain rail-to-rail signaling. Under 1 volts supply voltage, the input common mode range is 0.01~0.97V. These 3 amplifiers are fabricated by TSMC 0.35um. The total chip size is 1476X927um2.
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Carvalho, João Pedro Leal Abalada De Matos. "Design of a Transimpedance Amplifier for an Optical Receiver." Master's thesis, 2017. http://hdl.handle.net/10362/34375.
Full textAbstract:
In today’s world, technology is so developed that it is possible to transmit huge amounts
of data in a short time.
In the experiments with high energy levels in laboratories carried out in CERN, it is
essential to have a method capable of carrying all this information and at the same time
of being tolerant to the radiation from these same experiments.
Optical fibres are currently the best method transmitting the data created by these
experiments. In order to receive the information from the optical fibre a Photodiode (PD)
is used to produce current from the light of the optical fibre. This current is however
small. It is necessary to use an amplifier which, in addition to amplifying the current
coming from the photodiode, also converts it into a voltage for the next phases of the
optical receiver.
These amplifiers are known as transimpedance amplifiers and are the critical part of
optical receivers since an high gain is required to amplify the current from the photodiode
and at the same time a high bandwidth to receive the hight data rate signals.
This thesis presents a complete analysis of these amplifiers, showing various types of
topologies and their pros and cons. In order to arrive at the amplifier with the desired
characteristics, this thesis uses mathematical equations that allow us to describe the
operation of the Transimpedance Amplifier (TIA) and to determine the optimal range
between the gain, the bandwidth and the noise of the amplifier (input referred noise).
All the theoretical expressions as well as the behaviour of the whole system was verified
using electrical simulations.
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Omoumi, Kevin Christopher. "Design of a High-Voltage, Differential Drive Bradbury-Nielsen Gate Amplifier with Ultra-High Slew Rate and Input Isolation." 2011. http://trace.tennessee.edu/utk_gradthes/901.
Full textAbstract:
To isolate and study various components of a nuclear reaction, elaborate equipment must be developed to aid in this process. This thesis presents the design and implementation of an ultra-high slew rate Bradbury-Nielsen gate driver circuit with high-voltage input isolation. This design will be used in a multi-pass time-of-flight isomer spectrometer and separator application integrated into an overall instrument called the Oak Ridge Isomer Spectrometer and Separator (ORISS). The output drive signals of this circuit are transmitted through a vacuum feed-through system to supply the necessary signals to the Bradbury-Nielsen gate contained within the vacuum. A differential driving signal with a 100-V magnitude and switching times on the order of nanoseconds is presented in this design. The “on time” of this signal is comparable to the amount of time required for it to transition states, creating complex design constraints. The implementation of this design is based on a 4-layer printed circuit board and the use of commercial off-the-shelf (COTS) components.
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Wu, Yi-lun, and 吳依倫. "A High Voltage Operational Amplifier with Rail-to-rail Input and Output Ranges and an 8:1 Analog High Voltage Multiplexer." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/u349mb.
Full textAbstract:
碩士國立中山大學
電機工程學系研究所
102
One of the key techniques of electric vehicles (EVs) is battery management systems, which demand the development of battery modules, the measurement circuits of batteries, and so on. This thesis investigates a high-voltage operational amplifier with rail-to-rail input and output ranges, and an 8:1 analog high-voltage multiplexer for the battery voltage measurement. This thesis proposes a high-voltage operational amplifier with rail-to-rail input and output ranges to meet the required amplifier for the aforementioned technology. It also carries out the signal transfer circuit design for battery management systems, such as subtractor, analog to digital converter. Since the input range of the design could be up to 30 V, and the output range is 0 ∼ 29.57 V, ADC with a high input range is no longer needed hereby. Although the dc gain is 41 dB, the gain error can be corrected by using low-bit ADCs. Finally, this design is expected for battery management systems to attain accurate SOC estimation . Another key circuit is the high-voltage multiplexer. This thesis proposes a 8:1 highvoltage analog multiplexer which can be used to measure the voltage of a single cell in a battery string. If the battery modules consists of eight batteries connected in series and the voltage of a battery cell is 2.5 V to 4.5 V, the input voltage range is 0 ∼ 36 V. To resolve the high input voltage problem, this thesis demonstrates a 8:1 high-voltage analog multiplexer, where the output voltage range is in line with SAR ADC input voltage range of 1.5 ∼ 3.5 V.
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Greenwell, Robert Lee. "Design of a 5-V compatible rail-to-rail input/output operational amplifier in 3.3-V SOI CMOS for wide temperature range operation." 2006. http://etd.utk.edu/2006/GreenwellRobert.pdf.
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Shih-HsiungChien and 簡士雄. "Low-Quiescent-Current Low-Distortion Analog-Input and High-Dynamic-Range Digital-Input Class-D Audio Amplifiers." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/9394d3.
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Leduc, Pascal. "Design of Adaptive Amplifiers with DC Varying Inputs." Thesis, 2012. http://spectrum.library.concordia.ca/974795/1/Leduc_MASc_S2013.pdf.
Full textAbstract:
Analog amplifiers are one of the most commonly used building blocks in electronic systems. Emerging circuit technologies create new systems and also new applications for signal amplification. A conventional amplifier operates at a fixed biasing point to transfer signals varying on a fixed DC level with a constant or variable gain. In some new systems, particularly those involving sensors, the DC component of a signal to be amplified can be variable, instead of fixed. The established design procedure is not applicable for such signals.
In this thesis, a design method for adaptive amplifiers is proposed. It is to design an amplifier that can adjust itself automatically to suit the DC level of the input voltage and the amplification gain is variable according to the input DC level. The amplifier is made to perform, from a small signal point view, a linear amplification with a fixed gain, but from a large signal point view, a nonlinear voltage transfer. The nonlinear character of its function makes the amplifier capable of operating with an input voltage of which the DC level can vary in a specified range and providing a gain adapting to the input DC level.
The proposed method has been used to design an amplifier for a voltage signal enhancement in a wide dynamic range current-to-voltage conversion circuit. The designed amplifier has four cascading stages, i.e., three simple common source amplifier stages and one source follower. The units are tuned to perform a nonlinear voltage transfer while keeping a local linearity. These units are combined to implement the characteristics needed for the signal enhancement. The circuit has been simulated and the results demonstrated that it is able to perform the required amplification of the signal varying on different DC levels with an input-dependent gain.
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Ming-Chang, Sun. "Design of Image-Reject CMOS Low-Noise Amplifiers with Novel Input-Matching Techniques." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2607200504192500.
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Sun, Ming-Chang, and 孫銘彰. "Design of Image-Reject CMOS Low-Noise Amplifiers with Novel Input-Matching Techniques." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/38706243386579534169.
Full textAbstract:
博士國立臺灣大學
電機工程學研究所
93
The design of radio frequency (RF) circuits using CMOS technology has gained many focuses in recent years. Many fantastic design techniques have been published in many literatures. Low noise amplifier (LNA) is one of the well-studied building block for RF circuits. However, the basic problem of input matching have been oversimplified or sometimes even ignored by common assumption. This makes the design of a high frequency LNA be time-consuming. In this dissertation, the difficulty of the input matching for cascode CMOS LNA is explored and a design methodology is proposed to achieve input matching in an explicit approach. In addition to the input matching problem, another design goal is the integration of image-reject (IR) filter for superheterodyne transceivers since the external band-pass filter prevents further integration for RF circuits. A new design technique for image-reject CMOS low-noise amplifiers (LNAs) is presented in this dissertation. In addition to the proposed input matching method, a passive notch filter with high image-reject ability is analyzed. This improved design technique uses a 4th-order symmetric T-coil notch filter to achieve image-reject function. Current reuse technique is adapted in the proposed technique to save power and to boost power gain. A 2.4 GHz image-reject LNA is designed with TSMC 0.18 μm CMOS process to demonstrate the potentially high image-reject ability of the proposed architecture. Simulation results using available foundry models show about 32 dB image rejection at 1.7 GHz. The power gain of the design is 19 dB and the total power consumption is about 4.6 mW at 1.5 V power supply.
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Taing, Yong. "Application of H[infinity] control for input signal disturbances within erbium-doped fiber amplifiers." 2005. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=370275&T=F.
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Ramadan, Ashraf [Verfasser]. "Active antennas with high input impedance low noise and highly linear amplifiers / by Ashraf Ramadan." 2005. http://d-nb.info/975739174/34.
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Brkovic, Milivoje Slobodan. "Switching converters with magnetic amplifiers as controllable switches : I: Soft-switching converters. II: Input current shaping." Thesis, 1994. https://thesis.library.caltech.edu/4783/1/Brkovic_ms_1994.pdf.
Full textAbstract:
Part I:
Novel soft-switching converters combine the functions of loss-less soft-switching for all switches and secondary side output voltage regulation at constant switching frequency. This was made possible by using magnetic amplifiers in series with the rectifier diodes in
the symmetrical topologies. The primary side switches are driven at constant frequency and near 50% duty ratio with small dead-time and the output voltage is regulated by pulse width modulation (PWM) control on the secondary side.
All three soft-switching topologies, half-bridge, full-bridge and push-pull, are analyzed. It was found that the multiple-output extension of these converter do not have some serious adverse effects inherent to their parent PWM converters with magnetic amplifier post-regulators.
Experimental results obtained on two different prototypes confirm the key advantages of the proposed soft-switching converters.
Part II:
Two classes of automatic current shapers are analyzed, with external and internal capacitive energy storage.
The Cuk converter with Integrated Magnetics when operated in DICM with external energy storage exhibits advantages over other automatic current shaper topologies. Unity power factor is provided automatically and by using "ripple steering" mechanism essentially zero input and output current ripples are obtained for all operating conditions. Consequently, the size of the magnetics can be significantly reduced even at very modest switching frequencies.
The requirement for fast output regulation implies that low-frequency energy is stored internally in the input current shaper. A new AC-to-DC converter which combines the functions of automatic current shaping, fast output voltage regulation, and loss-less soft-switching in a single converter is proposed. This was made possible through internal energy storage and discovery of the new modes of operation, which together, effectively decoupled the input boost-like part of the Cuk converter from its buck-like output. In order to keep the voltage stress on the switches low, the variable frequency control is required in addition to PWM control.
Another novel class of single stage AC-to-DC converters with unity power factor and fast output regulation is also proposed. These converters use a magnetic amplifier for the input current shaping, while the active switch is used for fast output regulation. By using
core material for magnetic amplifiers with high saturated permeability, and operating the input stage of the converter in DICM, the linear input inductance can be replaced by the saturated inductance of the magnetic amplifier. Thus, the magnetic amplifier combines the functions of a controllable switch and a linear inductor into a single device.
The proposed method of current shaping with magnetic amplifiers is extended to the full-bridge topologies with their input, boost-like stage operated in continuous conduction mode.
Experimental results obtained on different prototypes confirm advantages of the proposed topologies.
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Chen, Yung-Hung, and 陳永鴻. "Noise Improvement of Low Frequency and Low Power Dissipation Rail-To-Rail Differential Inpup Operational Amplifier IC Design." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/85124772732420524510.
Full textAbstract:
碩士國立清華大學
電子工程研究所
97
In this work, TSMC SiGe0.35μm technology is used to design a low noise analog integrated circuit. This work is called 「Noise Improvement of Low-frequency , Low-power Rail-To-Rail Differential Input Op-Amp」, and is simulated by H-SPICE. It uses BiCMOS technology replacing CMOS technology in the differential input stage to improve noise in Op-Amp circuits. Through simulation and comparison, the results show that noise in the BiCMOS rail-to-rail differential input Op-Amp is better than noise in CMOS rail-to-rail differential input Op-Amp. Finally, rail-to-rail instrumentation Amps are integrated by these two kinds of Op-Amp, and then they are simulated and compared again. The simulation and comparison results show that noise is significantly improved when using BiCMOS rail-to-rail differential input Op-Amps. In addition, this paper mentions the designed rail-to-rail instrumentation Amps could be applied as ECG Amplifier in the medical electronic. This paper also introduces what is ECG and ECG related electronics.
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Su, Chen-Feng, and 蘇宸鋒. "Universal biquadratic voltage-mode filter with three inputs and a single output using current feedback amplifiers." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/53975926912882855323.
Full textAbstract:
碩士中原大學
電機工程研究所
104
The purpose of the study was to develop universal voltage active filters by CFA (Current Feedback Amplifier). The thesis proposed the way of using the feature of active component to achieve matrix relationship. In this study, the active component of circuit structure was to use CFA to replace OPA, which has been used in the traditional circuit structure. Compared the difference between OPA and CFA, OPA have the problem that the Gain Bandwidth Product is a constant value. When the circuit structure is in high-gain status, it doesn’t have large bandwidth. On the contrary, CFA use the way of 「Current feedback」, which could offer high bandwidth and will not be affected by gain value. The design of the circuit was to use 1 MHz as its operating frequency, H-Spice for the circuit simulation, and with TSMC 0.35 um to execute the simulation and to verify the theory. Used the sensitivity characteristics of the component to maximize the circuit simulation and to make the output more precisely. In the end, hope the design of Universal filter in this study may be manufactured for integrated circuit in the future. This study could provide a good reference.
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TSAO, YU-TZU, and 曹佑慈. "Voltage-Mode Universal Biquadratic Filter With Four Inputs And One Output using Two Current Feedback Amplifiers." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/2rq5br.
Full textAbstract:
碩士中原大學
電子工程研究所
106
Since the development of active devices, current mode active devices have become the mainstream, which can effectively reduce costs and power consumption, and has a good gain bandwidth product and other advantages. The main research of this dissertation is a voltage-mode universal biquadratic filter that designed with current mode active elements. This article proposes a voltage mode universal biquadratic filter that uses two current feedback amplifiers, three resistors and two capacitors to complete a four-input, one-output voltage mode universal biquadratic filter. It is possible to complete six kinds (low-pass, high-pass, band-pass, inverting bandpass, notch, and all-pass) filters by changing the input voltage terminals and without changing the circuit structure or need one more active for inverting voltage input. The all-pass response that requires impedance matching condition. The circuit has a low output impedance, it is suitable for series connection and facilitates the formation of higher-order filters. Currently, current feedback amplifiers have been commercialized in IC AD844. To verify the correctness of the proposed circuit, the experiments and simulations are done. They are all in accordance with the theory.
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Παπαγεωργίου, Βασίλειος. "Τελεστικός ενισχυτής τάξης ΑΒ με μέγιστη μεταβολή τάσεων στην είσοδο." Thesis, 2010. http://hdl.handle.net/10889/6107.
Full textAbstract:
Η ανάγκη για εξοικονόμηση ενέργειας δεν θα μπορούσε να αφήσει ανεπηρέαστα τα ηλεκτρονικά κυκλώματα. Έτσι, κατά τον σχεδιασμό ενός σύγχρονου ηλεκτρονικού κυκλώματος γίνεται προσπάθεια για αύξηση της αποδοτικότητας διαχείρισης της ισχύος ώστε να μειωθεί η κατανάλωση και να αυξηθεί η αυτονομία. Ένα από τα πιο γνωστά κυκλώματα που συναντάται στις περισσότερες εφαρμογές της ηλεκτρονικής είτε πρόκειται για αναλογικές είτε για ψηφιακές, είναι αυτό του τελεστικού ενισχυτή. Προς, αυτήν την κατεύθυνση, διάφορες καινοτόμες τοπολογίες έχουν προταθεί για την σύγχρονη ενισχυτική βαθμίδα που σκοπό έχουν την μεγιστοποίηση της αποδοτικότητας διαχείρισης του σήματος, με την ελάχιστη κατανάλωση. Συνεπώς, ένας αποδοτικός τελεστικός ενισχυτής, εκτός από μεγάλο κέρδος σε μεγάλη περιοχή συχνοτήτων, θα πρέπει να παρέχει ταυτόχρονα την ικανότητα διαχείρισης σημάτων με το μέγιστο δυνατό εύρος και την δυνατότητα οδήγησης μεγάλων φορτίων. Κατά συνέπεια, νέες τεχνικές παρουσιάζονται για την διαχείριση του σήματος, τόσο στην είσοδο όσο και στην έξοδο κάτω από συνθήκες χαμηλής τροφοδοσίας.
Αυτή η εργασία έχει σαν αντικείμενο την μελέτη των βαθμίδων εισόδου τελεστικών ενισχυτών με εύρος rail-to-rail καθώς και των βαθμίδων εξόδου τάξεως ΑΒ. Μια rail-to-rail βαθμίδα εισόδου, μπορεί να διαχειριστεί την τάση τροφοδοσίας στο έπακρο δεχόμενη σήματα μεγάλου εύρους τάσεων, ενώ η βαθμίδα εξόδου έχει σαν κύριο πλεονέκτημα την γρηγορότερη οδήγηση μεγάλων φορτίων με ελαχιστοποίηση της παραμόρφωσης. Έτσι, στο πρώτο κεφάλαιο παρουσιάζονται οι βασικές αρχές που διέπουν τα κυκλώματα χαμηλής τροφοδοσίας και οι περιορισμοί που πρέπει να ληφθούν υπ’ όψιν κατά τον σχεδιασμό των κυκλωμάτων. Στο δεύτερο κεφάλαιο αυτής της εργασίας παρουσιάζονται οι βασικές αρχές λειτουργίας των rail-to-rail βαθμίδων εισόδου και οι βασικές τεχνικές υλοποίησής τους. Στο τρίτο κεφάλαιο παρουσιάζονται οι βασικές αρχές λειτουργίας των βαθμίδων εξόδου τάξεως ΑΒ με τις αντίστοιχες τεχνικές υλοποίησης.
Στα επόμενα κεφάλαια αυτού του συγγράμματος προτείνεται ένας νέος τελεστικός ενισχυτής ο οποίος αποτελείται από μια rail-to-rail βαθμίδα εισόδου και από μία βαθμίδα εξόδου τάξεως ΑΒ ενώ γίνεται χρήση 1V για την τάση τροφοδοσίας. Άλλο ένα πλεονέκτημα της προτεινόμενης αρχιτεκτονικής, είναι αυτό της δυνατότητας ρύθμισης των συνθηκών πόλωσης ώστε να διατηρείται η λειτουργικότητα του ενισχυτή αλλά και να προσαρμόζεται στις εκάστοτε ανάγκες της κάθε εφαρμογής. Πιο συγκεκριμένα ένα από τα πλεονεκτήματα αυτού του τελεστικού ενισχυτή, είναι η δυνατότητα ρύθμισης της διαγωγιμότητας της εισόδου με γραμμικό τρόπο μέσω μιας πηγής ρεύματος. Αντίστοιχα, επιλέγοντας μεγαλύτερο ρεύμα για την βαθμίδα εξόδου υπάρχει η δυνατότητα μείωσης της καθυστέρησης μετάδοσης του σήματος σε μεγάλα φορτία.A new technique for rail-to-rail input stage is proposed in this Letters. The proposed technique is based on the master-slave approach of complementary MOS transistor pairs. The input transconductance is linearly tunable over a large range and is almost constant for rail-to-rail common-mode range. The effectiveness of the proposed technique was verified by simulations using a standard 0.18μm CMOS process.