Relevant bibliographies by topics / In-memory-computing (IMC)

Academic literature on the topic 'In-memory-computing (IMC)'

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Published: 19 July 2023

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Journal articles on the topic "In-memory-computing (IMC)"

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Song, Soonbum, and Youngmin Kim. "Novel In-Memory Computing Adder Using 8+T SRAM." Electronics 11, no. 6 (March 16, 2022): 929. http://dx.doi.org/10.3390/electronics11060929.

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Von Neumann architecture-based computing systems are facing a von Neumann bottleneck owing to data transfer between separated memory and processor units. In-memory computing (IMC), on the other hand, reduces energy consumption and improves computing performance. This study explains an 8+T SRAM IMC circuit based on 8+T differential SRAM (8+T SRAM) and proposes 8+T SRAM-based IMC full adder (FA) and 8+T SRAM-based IMC approximate adder, which are based on the 8+T SRAM IMC circuit. The 8+T SRAM IMC circuit performs SRAM read and bitwise operations simultaneously and performs each logic operation parallelly. The proposed IMC FA and the proposed IMC approximate adder can be applied to a multi-bit adder. The two adders are based on the 8+T SRAM IMC circuit and thus read and compute simultaneously. In this study, the 8+T SRAM IMC circuit was applied to the adder, leveraging its ability to perform read and logic operations simultaneously. According to the performance in this study, the 8+T SRAM IMC circuit, proposed FA, proposed RCA, and proposed approximated adder are good candidates for IMC, which aims to reduce energy consumption and improve overall performance.
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Mannocci, P., M. Farronato, N. Lepri, L. Cattaneo, A. Glukhov, Z. Sun, and D. Ielmini. "In-memory computing with emerging memory devices: Status and outlook." APL Machine Learning 1, no. 1 (March 1, 2023): 010902. http://dx.doi.org/10.1063/5.0136403.

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In-memory computing (IMC) has emerged as a new computing paradigm able to alleviate or suppress the memory bottleneck, which is the major concern for energy efficiency and latency in modern digital computing. While the IMC concept is simple and promising, the details of its implementation cover a broad range of problems and solutions, including various memory technologies, circuit topologies, and programming/processing algorithms. This Perspective aims at providing an orientation map across the wide topic of IMC. First, the memory technologies will be presented, including both conventional complementary metal-oxide-semiconductor-based and emerging resistive/memristive devices. Then, circuit architectures will be considered, describing their aim and application. Circuits include both popular crosspoint arrays and other more advanced structures, such as closed-loop memory arrays and ternary content-addressable memory. The same circuit might serve completely different applications, e.g., a crosspoint array can be used for accelerating matrix-vector multiplication for forward propagation in a neural network and outer product for backpropagation training. The different algorithms and memory properties to enable such diversification of circuit functions will be discussed. Finally, the main challenges and opportunities for IMC will be presented.
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Sun, Zhaohui, Yang Feng, Peng Guo, Zheng Dong, Junyu Zhang, Jing Liu, Xuepeng Zhan, Jixuan Wu, and Jiezhi Chen. "Flash-based in-memory computing for stochastic computing in image edge detection." Journal of Semiconductors 44, no. 5 (May 1, 2023): 054101. http://dx.doi.org/10.1088/1674-4926/44/5/054101.

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Abstract The “memory wall” of traditional von Neumann computing systems severely restricts the efficiency of data-intensive task execution, while in-memory computing (IMC) architecture is a promising approach to breaking the bottleneck. Although variations and instability in ultra-scaled memory cells seriously degrade the calculation accuracy in IMC architectures, stochastic computing (SC) can compensate for these shortcomings due to its low sensitivity to cell disturbances. Furthermore, massive parallel computing can be processed to improve the speed and efficiency of the system. In this paper, by designing logic functions in NOR flash arrays, SC in IMC for the image edge detection is realized, demonstrating ultra-low computational complexity and power consumption (25.5 fJ/pixel at 2-bit sequence length). More impressively, the noise immunity is 6 times higher than that of the traditional binary method, showing good tolerances to cell variation and reliability degradation when implementing massive parallel computation in the array.
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Pedretti, Giacomo, and Daniele Ielmini. "In-Memory Computing with Resistive Memory Circuits: Status and Outlook." Electronics 10, no. 9 (April 30, 2021): 1063. http://dx.doi.org/10.3390/electronics10091063.

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In-memory computing (IMC) refers to non-von Neumann architectures where data are processed in situ within the memory by taking advantage of physical laws. Among the memory devices that have been considered for IMC, the resistive switching memory (RRAM), also known as memristor, is one of the most promising technologies due to its relatively easy integration and scaling. RRAM devices have been explored for both memory and IMC applications, such as neural network accelerators and neuromorphic processors. This work presents the status and outlook on the RRAM for analog computing, where the precision of the encoded coefficients, such as the synaptic weights of a neural network, is one of the key requirements. We show the experimental study of the cycle-to-cycle variation of set and reset processes for HfO2-based RRAM, which indicate that gate-controlled pulses present the least variation in conductance. Assuming a constant variation of conductance σG, we then evaluate and compare various mapping schemes, including multilevel, binary, unary, redundant and slicing techniques. We present analytical formulas for the standard deviation of the conductance and the maximum number of bits that still satisfies a given maximum error. Finally, we discuss RRAM performance for various analog computing tasks compared to other computational memory devices. RRAM appears as one of the most promising devices in terms of scaling, accuracy and low-current operation.
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Bansla, Neetu, and Rajneesh . "Future ERP: In-Memory Computing (IMC)Technology Infusion." Journal of Information Technology and Sciences 6, no. 3 (October 26, 2020): 17–21. http://dx.doi.org/10.46610/joits.2020.v06i03.003.

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Kim, Manho, Sung-Ho Kim, Hyuk-Jae Lee, and Chae-Eun Rhee. "Case Study on Integrated Architecture for In-Memory and In-Storage Computing." Electronics 10, no. 15 (July 21, 2021): 1750. http://dx.doi.org/10.3390/electronics10151750.

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Since the advent of computers, computing performance has been steadily increasing. Moreover, recent technologies are mostly based on massive data, and the development of artificial intelligence is accelerating it. Accordingly, various studies are being conducted to increase the performance and computing and data access, together reducing energy consumption. In-memory computing (IMC) and in-storage computing (ISC) are currently the most actively studied architectures to deal with the challenges of recent technologies. Since IMC performs operations in memory, there is a chance to overcome the memory bandwidth limit. ISC can reduce energy by using a low power processor inside storage without an expensive IO interface. To integrate the host CPU, IMC and ISC harmoniously, appropriate workload allocation that reflects the characteristics of the target application is required. In this paper, the energy and processing speed are evaluated according to the workload allocation and system conditions. The proof-of-concept prototyping system is implemented for the integrated architecture. The simulation results show that IMC improves the performance by 4.4 times and reduces total energy by 4.6 times over the baseline host CPU. ISC is confirmed to significantly contribute to energy reduction.
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Zhang, Jin, Zhiting Lin, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Qiang Zhao, and Junning Chen. "An 8T SRAM Array with Configurable Word Lines for In-Memory Computing Operation." Electronics 10, no. 3 (January 27, 2021): 300. http://dx.doi.org/10.3390/electronics10030300.

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In-memory computing (IMC) has been widely accepted to be an effective method to improve energy efficiency. To realize IMC, operands in static random-access memory (SRAM) are stored in columns, which contradicts SRAM write patterns and requires additional data movement. In this paper, an 8T SRAM array with configurable word lines is proposed, in where the operands are arranged in rows, following the traditional SRAM storage pattern, and therefore additional data movement is not required. The proposed structure supports three different computing modes. In the ternary multiplication mode, the reference voltage generation column is not required. The energy of computing is only 1.273 fJ/bit. In the unsigned multibit multiplication mode, discharge and charging paths are used to enlarge the voltage difference of the least significant bit. In the logic operation mode, different types of operations (e.g., IMP, OR, NOR, XNOR, and XOR) are achieved in a single cycle. The frequency of logic computing is up to 909 MHz.
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Xue, Wang, Liu, Lv, Wang, and Zeng. "An RISC-V Processor with Area-Efficient Memristor-Based In-Memory Computing for Hash Algorithm in Blockchain Applications." Micromachines 10, no. 8 (August 16, 2019): 541. http://dx.doi.org/10.3390/mi10080541.

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Blockchain technology is increasingly being used in Internet of things (IoT) devices for information security and data integrity. However, it is challenging to implement complex hash algorithms with limited resources in IoT devices owing to large energy consumption and a long processing time. This paper proposes an RISC-V processor with memristor-based in-memory computing (IMC) for blockchain technology in IoT applications. The IMC-adapted instructions were designed for the Keccak hash algorithm by virtue of the extendibility of the RISC-V instruction set architecture (ISA). Then, an RISC-V processor with area-efficient memristor-based IMC was developed based on an open-source core for IoT applications, Hummingbird E200. The general compiling policy with the data allocation method is also disclosed for the IMC implementation of the Keccak hash algorithm. An evaluation shows that >70% improvements in both performance and energy saving were achieved with limited area overhead after introducing IMC in the RISC-V processor.
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Krishnan, Gokul, Sumit K. Mandal, Manvitha Pannala, Chaitali Chakrabarti, Jae-Sun Seo, Umit Y. Ogras, and Yu Cao. "SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–24. http://dx.doi.org/10.1145/3476999.

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In-memory computing (IMC) on a monolithic chip for deep learning faces dramatic challenges on area, yield, and on-chip interconnection cost due to the ever-increasing model sizes. 2.5D integration or chiplet-based architectures interconnect multiple small chips (i.e., chiplets) to form a large computing system, presenting a feasible solution beyond a monolithic IMC architecture to accelerate large deep learning models. This paper presents a new benchmarking simulator, SIAM, to evaluate the performance of chiplet-based IMC architectures and explore the potential of such a paradigm shift in IMC architecture design. SIAM integrates device, circuit, architecture, network-on-chip (NoC), network-on-package (NoP), and DRAM access models to realize an end-to-end system. SIAM is scalable in its support of a wide range of deep neural networks (DNNs), customizable to various network structures and configurations, and capable of efficient design space exploration. We demonstrate the flexibility, scalability, and simulation speed of SIAM by benchmarking different state-of-the-art DNNs with CIFAR-10, CIFAR-100, and ImageNet datasets. We further calibrate the simulation results with a published silicon result, SIMBA. The chiplet-based IMC architecture obtained through SIAM shows 130 and 72 improvement in energy-efficiency for ResNet-50 on the ImageNet dataset compared to Nvidia V100 and T4 GPUs.
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Kiran Cherupally, Sai, Jian Meng, Adnan Siraj Rakin, Shihui Yin, Injune Yeo, Shimeng Yu, Deliang Fan, and Jae-Sun Seo. "Improving the accuracy and robustness of RRAM-based in-memory computing against RRAM hardware noise and adversarial attacks." Semiconductor Science and Technology 37, no. 3 (January 13, 2022): 034001. http://dx.doi.org/10.1088/1361-6641/ac461f.

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Abstract We present a novel deep neural network (DNN) training scheme and resistive RAM (RRAM) in-memory computing (IMC) hardware evaluation towards achieving high accuracy against RRAM device/array variations and enhanced robustness against adversarial input attacks. We present improved IMC inference accuracy results evaluated on state-of-the-art DNNs including ResNet-18, AlexNet, and VGG with binary, 2-bit, and 4-bit activation/weight precision for the CIFAR-10 dataset. These DNNs are evaluated with measured noise data obtained from three different RRAM-based IMC prototype chips. Across these various DNNs and IMC chip measurements, we show that our proposed hardware noise-aware DNN training consistently improves DNN inference accuracy for actual IMC hardware, up to 8% accuracy improvement for the CIFAR-10 dataset. We also analyze the impact of our proposed noise injection scheme on the adversarial robustness of ResNet-18 DNNs with 1-bit, 2-bit, and 4-bit activation/weight precision. Our results show up to 6% improvement in the robustness to black-box adversarial input attacks.
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Dissertations / Theses on the topic "In-memory-computing (IMC)"

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Ezzadeen, Mona. "Conception d'un circuit dédié au calcul dans la mémoire à base de technologie 3D innovante." Electronic Thesis or Diss., Aix-Marseille, 2022. http://theses.univ-amu.fr.lama.univ-amu.fr/221212_EZZADEEN_955e754k888gvxorp699jljcho_TH.pdf.

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Avec le développement de l'internet des objets et de l'intelligence artificielle, le "déluge de données" est une réalité, poussant au développement de systèmes de calcul efficaces énergétiquement. Dans ce contexte, en effectuant le calcul directement à l'intérieur ou à proximité des mémoires, le paradigme de l'in/near-memory-computing (I/NMC) semble être une voie prometteuse. En effet, les transferts de données entre les mémoires et les unités de calcul sont très énergivores. Cependant, les classiques mémoires Flash souffrent de problèmes de miniaturisation et ne semblent pas facilement adaptées à l'I/NMC. Ceci n'est pas le cas de nouvelles technologies mémoires émergentes comme les ReRAM. Ces dernières souffrent cependant d'une variabilité importante, et nécessitent l'utilisation d'un transistor d'accès par bit (1T1R) pour limiter les courants de fuite, dégradant ainsi leur densité. Dans cette thèse, nous nous proposons de résoudre ces deux défis. Tout d'abord, l'impact de la variabilité des ReRAM sur les opérations de lecture et de calcul en mémoire est étudié, et de nouvelles techniques de calculs booléens robustes et à faible impact surfacique sont développées. Dans le contexte des réseaux de neurones, de nouveaux accélérateurs neuromorphiques à base de ReRAM sont proposés et caractérisés, visant une bonne robustesse face à la variabilité, un bon parallélisme et une efficacité énergétique élevée. Dans un deuxième temps, pour résoudre les problèmes de densité d'intégration, une nouvelle technologie de cube mémoire 3D à base de ReRAM 1T1R est proposée, pouvant à la fois être utilisée en tant que mémoire de type NOR 3D dense qu'en tant qu'accélérateur pour l'I/NMC
With the advent of edge devices and artificial intelligence, the data deluge is a reality, making energy-efficient computing systems a must-have. Unfortunately, classical von Neumann architectures suffer from the high cost of data transfers between memories and processing units. At the same time, CMOS scaling seems more and more challenging and costly to afford, limiting the chips' performance due to power consumption issues.In this context, bringing the computation directly inside or near memories (I/NMC) seems an appealing solution. However, data-centric applications require an important amount of non-volatile storage, and modern Flash memories suffer from scaling issues and are not very suited for I/NMC. On the other hand, emerging memory technologies such as ReRAM present very appealing memory performances, good scalability, and interesting I/NMC features. However, they suffer from variability issues and from a degraded density integration if an access transistor per bitcell (1T1R) is used to limit the sneak-path currents. This thesis work aims to overcome these two challenges. First, the variability impact on read and I/NMC operations is assessed and new robust and low-overhead ReRAM-based boolean operations are proposed. In the context of neural networks, new ReRAM-based neuromorphic accelerators are developed and characterized, with an emphasis on good robustness against variability, good parallelism, and high energy efficiency. Second, to resolve the density integration issues, an ultra-dense 3D 1T1R ReRAM-based Cube and its architecture are proposed, which can be used as a 3D NOR memory as well as a low overhead and energy-efficient I/NMC accelerator
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Conference papers on the topic "In-memory-computing (IMC)"

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Li, Can, Daniel Belkin, Yunning Li, Peng Yan, Miao Hu, Ning Ge, Hao Jiang, et al. "In-Memory Computing with Memristor Arrays." In 2018 IEEE International Memory Workshop (IMW). IEEE, 2018. http://dx.doi.org/10.1109/imw.2018.8388838.

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Mayahinia, Mahta, Christopher Munch, and Mehdi B. Tahoori. "Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory." In 2021 IEEE International Test Conference (ITC). IEEE, 2021. http://dx.doi.org/10.1109/itc50571.2021.00036.

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"Invited Talk #9: Ferroelectric Capacitive Memory for Storage and In-memory Computing." In 2022 International Conference on IC Design and Technology (ICICDT). IEEE, 2022. http://dx.doi.org/10.1109/icicdt56182.2022.9933082.

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Luo, Yuan-Chun, Anni Lu, Jae Hur, Shaolan Li, and Shimeng Yu. "Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing." In 2021 IEEE International Memory Workshop (IMW). IEEE, 2021. http://dx.doi.org/10.1109/imw51353.2021.9439603.

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Lin, Yu-Hsuan, Po-Hao Tseng, Feng-Min Lee, Ming-Hsiu Lee, Chih-Chang Hsieh, Dai-Ying Lee, Keh-Chung Wang, and Chih-Yuan Lu. "NOR Flash-based Multilevel In-Memory-Searching Architecture for Approximate Computing." In 2022 IEEE International Memory Workshop (IMW). IEEE, 2022. http://dx.doi.org/10.1109/imw52921.2022.9779250.

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Yoda, Hiroaki, Yuichi Ohsawa, Yushi Kato, and Tomomi Yoda. "Proposal of A Nonvolatile XNOR Logic-Gate Using Voltage-Control Spintronics Memory Cells For In-Memory Computing." In 2020 IEEE International Memory Workshop (IMW). IEEE, 2020. http://dx.doi.org/10.1109/imw48823.2020.9108120.

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Halawani, Yasmin, Baker Mohammad, Mahmoud Al-Qutayri, and Said Al-Sarawi. "A Re-configurable Memristor Array Structure for In-Memory Computing Applications." In 2018 30th International Conference on Microelectronics (ICM). IEEE, 2018. http://dx.doi.org/10.1109/icm.2018.8704111.

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Nishimura, Takuto, Yuya Ichikawa, Akira Goda, Naoko Misawa, Chihiro Matsui, and Ken Takeuchi. "Stochastic Computing-based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of Non-volatile Memory Error and Defect Tolerance." In 2023 IEEE International Memory Workshop (IMW). IEEE, 2023. http://dx.doi.org/10.1109/imw56887.2023.10145982.

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Ziegler, Tobias, Leon Brackmann, Tyler Hennen, Christopher Bengel, Stephan Menzel, and Dirk J. Wouters. "Eliminating Capacitive Sneak Paths in Associative Capacitive Networks based on Complementary Resistive Switches for In-Memory Computing." In 2023 IEEE International Memory Workshop (IMW). IEEE, 2023. http://dx.doi.org/10.1109/imw56887.2023.10145947.

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Hsu, Po-Kai, and Shimeng Yu. "In-Memory 3D NAND Flash Hyperdimensional Computing Engine for Energy-Efficient SARS-CoV-2 Genome Sequencing." In 2022 IEEE International Memory Workshop (IMW). IEEE, 2022. http://dx.doi.org/10.1109/imw52921.2022.9779291.

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