Relevant bibliographies by topics / In-circuit debugging

Academic literature on the topic 'In-circuit debugging'

Author: Grafiati
Published: 30 May 2022
Last updated: 31 May 2022

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Journal articles on the topic "In-circuit debugging"

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Zhang, Ping, and Zuo Cheng Xing. "Design and Implementation of Debugging Structure in Full-Custom CPU." Advanced Materials Research 211-212 (February 2011): 861–65. http://dx.doi.org/10.4028/www.scientific.net/amr.211-212.861.

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With the development of integrated circuit technology, it is more and more difficult for debugging circuits. Generally, to achieve a powerful debugging capability of circuits is often at the expense of larger cost of hardware overhead .This paper propose a method of debugging structure designed in full-custom CPU based on scan-set testability methods and combed with the boundary-scan technology. This debugging structure can reduces much scan chains hardware overheads and is applicable to all general-purpose CPU chips. Moreover, it owns a powerful debugging capability which is observing and controlling the internal registers of circuits from JTAG port. This structure only increases the difficulty of the circuit logic design, but greatly decreases the cost of hardware.
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Li, Gao Zheng, Cheng Liu, Guo Hong Cao, and Nan Yu. "Design for Detection System of Landslides Based on SCM." Applied Mechanics and Materials 331 (July 2013): 622–25. http://dx.doi.org/10.4028/www.scientific.net/amm.331.622.

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In order to understand all data of landslides as much as possible, such as the time, place, scale and destructive power, a kind of Remote monitoring system of Landslides based on SCM was designed. The main function is for the purpose of dynamic monitoring of landslide timely and effectively. The main work include hardware design, software design and circuit debugging of the system. In the system, hardware design mainly consists of the analysis and design of landslides data acquisition module and data processing and control system module circuit; Software design is to refer to the compilations of various system modular program; Circuit debugging refers to the process of debugging the program running in the system to ensure that the department of the system can work normally.
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Liu, Xiangrong, Juan Suo, Juan Liu, Yan Gao, and Xiangxiang Zeng. "Molecular Logic Computation with Debugging Method." Journal of Nanomaterials 2015 (2015): 1–11. http://dx.doi.org/10.1155/2015/120365.

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Seesaw gate concept, which is based on a reversible DNA strand branch process, has been found to have the potential to be used in the construction of various computing devices. In this study, we consider constructing full adder and serial binary adder, using the new concept of seesaw gate. Our simulation of the full adder preformed properly as designed; however unexpected exception is noted in the simulation of the serial binary adder. To identify and address the exception, we propose a new method for debugging the molecular circuit. The main idea for this method is to add fan-outs to monitor the circuit in a reverse stepwise manner. These fan-outs are fluorescent signals that can obtain the real-time concentration of the target molecule. By analyzing the monitoring result, the exception can be identified and located. In this paper, examples of XOR and serial binary adder circuits are described to prove the practicability and validity of the molecular circuit debugging method.
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Kourfali, Alexandra, and Dirk Stroobandt. "In-Circuit Debugging with Dynamic Reconfiguration of FPGA Interconnects." ACM Transactions on Reconfigurable Technology and Systems 13, no. 1 (February 5, 2020): 1–29. http://dx.doi.org/10.1145/3375459.

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Huang, Kun, Li Hua Wang, and Xiao Jiang Hao. "The Measure and Control System Design for Temperature and Humidity in General Storeroom." Advanced Materials Research 710 (June 2013): 515–18. http://dx.doi.org/10.4028/www.scientific.net/amr.710.515.

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Based on the STC89C52 MCU as the core, this paper designs the measure and control system for temperature and humidity in general storeroom. The system includes two parts: hardware circuits design and software design. The hardware circuits include MCU smallest system, temperature and humidity signal acquisition circuit, keyboard circuit, LCD display circuit, control circuit and alarm circuit; the software includes main program and subroutines (temperature and humidity setting, acquisition, display and overrun processing, etc.). Through system function debugging, the system can realize the temperature and humidity information acquisition, display and control.
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Zhang, Ping, and Zuo Cheng Xing. "Design of Structure of Debugging Software in CPU Based on JTAG." Applied Mechanics and Materials 58-60 (June 2011): 1866–70. http://dx.doi.org/10.4028/www.scientific.net/amm.58-60.1866.

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It is important to own the capability of debugging application and system software and multitasking system in the design of microprocessor at present. In this paper, we proposed a debugging structure based on JTAG port and combined with boundary-scan technology and interrupt system, which can allow users to debug software procedure by the debugger which is connected to JTAG port. It is easy to form a standardized structure and applicable to all general-purpose CPU and only increases the difficulty of the circuit logic design.
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Yuan, Jin Song, Jian Zhang, and Yi Wang. "Applied Technology in Intelligent Home Furnishing Control System in Internet of Things Based on SCM Microcontroller and GSM." Applied Mechanics and Materials 540 (April 2014): 372–75. http://dx.doi.org/10.4028/www.scientific.net/amm.540.372.

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Main function of the intelligent home control system in internet of things is including the family equipment automatic control and home security. The applied technology of STC89C52 chip and the GSM module of TC35 modem are as the control core, temperature, humidity sensor for environmental information acquisition source, to create a smart Home Furnishing system. The applied technology content of experimental prototype includes the design of the system hardware and software debugging and controlling the writing and debugging. The results show that, the applied technology of circuit and software can finish the test basic functions.
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Wei, Chong Yu, Zu Ping Gu, and Shuai Huang. "The Application of an SD Card in Debugging an Embedded System." Advanced Materials Research 468-471 (February 2012): 1622–25. http://dx.doi.org/10.4028/www.scientific.net/amr.468-471.1622.

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In this paper, a new method using a Secure Digital Card in debugging an embedded system based on Android and its implementation are introduced. In debugging an embedded system, downloading image files to a RAM on a printed circuit board generally uses a net interface module and a server based on Trivial File Transfer Protocol (TFTP). Here a new method using an SD card is introduced. Compared with downloading by a TFTP server, the method is simple and inexpensive. In the paper, an SD card and its controller are introduced first. Then the designed circuit is presented. Third, two operation modes of the SD card, card identification and data transferring are analyzed in detail. Fourth, the structure of the FAT32 file system and the process for downloading image files into a RAM on board are shown.
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Fan, Han Bai, Xian Meng, and Jun Ma Hou. "Application and Debugging of All-Digital Frequency Synthesizer." Advanced Materials Research 989-994 (July 2014): 4058–61. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.4058.

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Presents the working principle of Integrated PLL chip Si4133, this paper presents the implementation of a 375MHz local oscillator for a super heterodyne transmitter/receiver by using Si4133.Using programming method to set the divider register Internal chip. In addition, this paper discuss the methods for decreases the phase noise. Debugging circuit using ICCAVR software , and show the debugging results. Facts show that the phase noise and spurious of the frequency synthesizer is low, and it is practical.
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Chen, Fulong, and Yunxiang Sun. "FPGA-based elastic in-circuit debugging for complex digital logic design." International Journal of Autonomous and Adaptive Communications Systems 10, no. 3 (2017): 303. http://dx.doi.org/10.1504/ijaacs.2017.086652.

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Dissertations / Theses on the topic "In-circuit debugging"

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Boulé, Marc. "Assertion-checker synthesis for hardware verification, in-circuit debugging and on-line monitoring." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=18754.

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Producing error-free circuits is of paramount importance in the semiconductor industry. Assertions are becoming an indispensable means of verifying the correctness of increasingly complex digital designs. Assertions model the proper behavior of a design, and are expressed in a high level language based on temporal logic. In dynamic verification, simulation is used to exercise a circuit in order to assess its behavior. For large designs, simulation times are often prohibitively excessive, and designs are instead emulated in hardware. Because of their high-level temporal operators, assertion statements do not lend themselves directly to hardware implementations such as emulation. This thesis introduces techniques and algorithms for generating resource-efficient circuit-level checkers from hardware assertion statements. These checkers are added to the source design, where they monitor the appropriate circuit signals to find faulty execution sequences. In this work, a finite automaton framework and a set of algorithms are developed and used extensively to create an intermediate representation of assertions. Implementing the large variety of temporal operators found in properties is also performed using specially designed rewrite rules. Checkers are circuit-level implementations of assertions, and thus allow assertions to be used in hardware emulation and simulation acceleration. The checkers are not only beneficial in pre-fabrication functional verification, but can also be used for debugging fabricated silicon, at speed, where timing issues are most prevalent. Using checkers beyond verification and silicon debug is also explored, by proposing the use of assertions and a checker generator to automate the design of certain types of circuits. A variety of enhancements are also introduced to improve the debugging process with assertion checkers. These enhancements range from additional observability and metric-reporting features, to behavioral modifications to the che
La production de circuits exempts d'erreurs est d'une importance capitale dans le domaine des semiconducteurs. Avec l'augmentation constante de la complexité des circuits numériques, la vérification matérielle basée sur les assertions devient indispensable. Les assertions modélisent le bon fonctionnement d'un circuit, et sont spécifiées à l'aide d'un langage faisant appel à la logique temporelle. En vérification dynamique, la simulation est utilisée afin d'analyser le comportement d'un circuit. Cependant, les temps de simulation deviennent trop longs pour de gros circuits et par conséquent, ces derniers sont souvent émulés de façon matérielle. Étant donné la présence d'opérateurs de logique temporelle de haut niveau, les assertions ne sont pas directement implantables de façon matérielle. Cette thèse présente les méthodes et les algorithmes nécessaires pour générer des circuits vérificateurs efficaces à partir des assertions. Ces vérificateurs se branchent au circuit à tester afin d'y observer les signaux, permettant ainsi de déceler un mauvais fonctionnement. Dans cet ouvrage, une série d'algorithmes ainsi qu'un modèle basé sur les automates finis sont développés et utilisés comme représentation intermédiaire pour les assertions. L'implémentation du vaste éventail d'opérateurs se fait aussi grâce à des règles de réécriture. En créant des circuits vérificateurs, les assertions peuvent dès lors être utilisés dans l'émulation matérielle et les accélérateurs de simulation. Les vérificateurs sont déjà fort utiles lors de la vérification préfabrication. Ces circuits peuvent aussi être utilisés lors de la vérification de circuits manufacturés où les problèmes de cadençage sont les plus réalistes. L'utilisation des vérificateurs est aussi applicable au-delà de la vérification et du déverminage post-fabrication, et peut servir pour la conception de circuits de haut niveau. Un ensemble d'extensi
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Зубков, О. В., І. В. Свид, О. С. Мальцев, and Л. Ф. Сайківська. "In-circuit Signal Analysis in the Development of Digital Devices in Vivado 2018." Thesis, Theoretical and Applied Aspects of Device Development on Microcontrollers and FPGAs, MC&FPGA-2019, 2019. https://doi.org/10.35598/mcfpga.2019.003.

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Considered the implementation of in-circuit analysis of logical signals in digital devices synthesized in Xilinx Field-Programmable Gate Array. Designed a digital control device streaming analog-to-digital converter. An analysis of the results of the analog-digital conversion was carried out and measures were taken to smooth out the false results of the conversion.
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Зубков, О. В., І. В. Свид, О. С. Мальцев, and Л. Ф. Сайківська. "In-circuit Signal Analysis in the Development of Digital Devices in Vivado 2018." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-003.

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Considered the implementation of in-circuit analysis of logical signals in digital devices synthesized in Xilinx Field-Programmable Gate Array. Designed a digital control device streaming analog-to-digital converter. An analysis of the results of the analog-digital conversion was carried out and measures were taken to smooth out the false results of the conversion.
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Slade, Anthony Lynn. "Designing, Debugging, and Deploying Configurable Computing Machine-based Applications Using Reconfigurable Computing Application Frameworks." Diss., CLICK HERE for online access, 2003. http://contentdm.lib.byu.edu/ETD/image/etd186.pdf.

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Conference papers on the topic "In-circuit debugging"

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Kourfali, Alexandra, and Dirk Stroobandt. "Superimposed in-circuit debugging for self-healing FPGA overlays." In 2018 IEEE 19th Latin-American Test Symposium (LATS). IEEE, 2018. http://dx.doi.org/10.1109/latw.2018.8349688.

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Goh, S. H., Wendy Lau, B. L. Yeoh, H. W. Ho, G. F. You, Hu Hao, Y. E. Koh, and Jeffrey Lam. "Debugging Phase-Locked Loop Failures in Integrated Circuit Products." In ISTFA 2014. ASM International, 2014. http://dx.doi.org/10.31399/asm.cp.istfa2014p0456.

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Abstract A phase-locked loop (PLL) is commonly used in integrated circuit devices for frequency control. In a finished product, it comprises of sub-building blocks operating in a closed-loop control system which do not have register readback or test access points for easy debugging. Failure analysis becomes a challenge. This paper demonstrates the inherent limitation of relying only on dynamic fault isolation techniques, in specific frequency mapping for PLL failure debug. A systematic debug approach that combines volume failure characterization on test, additional characterization using dynamic photon emission and design simulation is then presented. Results are obtained on a 28 nm node device.
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Nguyen, Binh, and Orlando Diaz. "Using Cross-Triggering in Oscilloscope for Debugging Multiphase Converter Circuit of Personal Computer (PC) Motherboard." In ISTFA 2008. ASM International, 2008. http://dx.doi.org/10.31399/asm.cp.istfa2008p0294.

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Abstract Analyzing a failure on multiphase converter circuit on PC motherboards presents significant challenges due to the high number of nodes and the timing relationship between them. Typically a standard 4-channel oscilloscope can not capture the necessary timing relationship to effectively analyze the whole circuit. This article presents a simple and low-cost solution that can effectively help the users overcome the challenges of debugging multiphase converter circuit of PC motherboards.
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Hofer, Birgit. "Removing Coincidental Correctness in Spectrum-Based Fault Localization for Circuit and Spreadsheet Debugging." In 2017 IEEE 28th International Symposium on Software Reliability Engineering: Workshops (ISSREW). IEEE, 2017. http://dx.doi.org/10.1109/issrew.2017.18.

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Huang, Pin Cheng, De Bin Lin, Jeng Hung Pan, Jackal Ma, James CC Chang, and Jian Chang Lin. "The Application of Circuit Debugging by Utilizing Pulse Function in Nano-Probing System." In 2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA). IEEE, 2020. http://dx.doi.org/10.1109/ipfa49335.2020.9261066.

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Zhao, Meng, Zhijing Liu, Zheng Liang, and Duan Zhou. "An On-Chip In-Circuit Emulation Architecture for Debugging an Asynchronous Java Accelerator." In 2009 International Conference on Computational Intelligence and Software Engineering. IEEE, 2009. http://dx.doi.org/10.1109/cise.2009.5363421.

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Yuan, Caiwen, Mehrdad Mahanpour, Hung-Jen Lin, and Gene Hill. "Application of Focused Ion Beam in Debug and Characterization of 0.13 µm Copper Interconnect Technology." In ISTFA 2002. ASM International, 2002. http://dx.doi.org/10.31399/asm.cp.istfa2002p0183.

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Abstract Focused Ion Beam (FIB) has been widely accepted in circuit modification and debugging of new chips and process technologies [1]. It has the advantages of rapid confirmation of design fixes and reducing the cost and time to build new masks. In this paper, we will describe the latest application of FIB to debugging Static Random Access Memory (SRAM) test chips processed on a dense copper metallization technology. Examples of finding leaky capacitors will be given. Individual transistors in the cell array have also been “fibbed” and characterization curves were measured. We compare the measurement with the SPICE simulation and discuss possible damage to the underlying transistors during FIB pad creation. Resistors in the periphery circuit were fibbed and measured with two and four point probes. Contact resistance was characterized and compared to that of Al interconnects. Example of finding problem vias with the help of cross-section and voltage contrast is given.
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Li, Susan X. "Performing Circuit Modification and Debugging Using Focused-Ion-Beam on Multi-Layered C4 Flip-Chip Devices." In ISTFA 1998. ASM International, 1998. http://dx.doi.org/10.31399/asm.cp.istfa1998p0067.

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Abstract The task of circuit repairing and debugging using a Focused-Ion-Beam system on multi-layered IC devices is often difficult and tedious, especially when desired or target metal nodes or layers are buried under other higher level or nontarget metal nodes or layers. As a result, not only are target nodes difficult to access, but also, undesired shorts are difficult to prevent. To further complicate the situation, as the number of metal layers increases, the lower level metal nodes become increasingly thinner, and the node population becomes increasingly denser. These conditions result in a decreased success rate utilizing the FIB and an increased turn-around time for design debugging. Besides significant improvement of the FIB equipment and tools, new techniques that can be used to overcome the difficulties encountered during FIB operations on multi-layered IC devices need to be utilized. In this paper, we will focus on discussion of some new techniques that can be used for FIB device modification work and device debugging on multi-layered IC devices, including C4 (controlled-collapse chip connection) flip-chip devices. Some recommendations and tips for using these techniques on complicated fib modification work will also be shared based on the author’s experience.
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Chen, Liang-Bi, Yung-Chih Liu, Chen-Hung Chen, Chung-Fu Kao, and Ing-Jer Huang. "Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor." In 13th Asia and South Pacific Design Automation Conference ASP-DAC 2008. IEEE, 2008. http://dx.doi.org/10.1109/aspdac.2008.4483923.

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Jurj, Sorin Liviu, Raul Rotar, Flavius Opritoiu, and Mircea Vladutiu. "Hybrid Testing of a Solar Tracking Equipment using In-Circuit Testing and JTAG Debugging Strategies." In 2021 IEEE International Conference on Environment and Electrical Engineering and 2021 IEEE Industrial and Commercial Power Systems Europe (EEEIC / I&CPS Europe). IEEE, 2021. http://dx.doi.org/10.1109/eeeic/icpseurope51590.2021.9584639.

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