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Academic literature on the topic 'Implantable chips'

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Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Implantable chips"

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Chiang, C. T., and C. Y. Wu. "Implantable neuromorphic vision chips." Electronics Letters 40, no. 6 (2004): 361. http://dx.doi.org/10.1049/el:20040269.

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Maguire, G. Q., and Ellen M. McGee. "Implantable Brain Chips? Time for Debate." Hastings Center Report 29, no. 1 (January 1999): 7. http://dx.doi.org/10.2307/3528533.

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Nabovati, Ghazal, and Mohammad Maymandi-Nejad. "Ultra-low power BPSK demodulator for bio-implantable chips." IEICE Electronics Express 7, no. 20 (2010): 1592–96. http://dx.doi.org/10.1587/elex.7.1592.

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Lee, Ah-Hyoung, Jihun Lee, Farah Laiwalla, Vincent Leung, Jiannan Huang, Arto Nurmikko, and Yoon-Kyu Song. "A Scalable and Low Stress Post-CMOS Processing Technique for Implantable Microsensors." Micromachines 11, no. 10 (October 5, 2020): 925. http://dx.doi.org/10.3390/mi11100925.

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Implantable active electronic microchips are being developed as multinode in-body sensors and actuators. There is a need to develop high throughput microfabrication techniques applicable to complementary metal–oxide–semiconductor (CMOS)-based silicon electronics in order to process bare dies from a foundry to physiologically compatible implant ensembles. Post-processing of a miniature CMOS chip by usual methods is challenging as the typically sub-mm size small dies are hard to handle and not readily compatible with the standard microfabrication, e.g., photolithography. Here, we present a soft material-based, low chemical and mechanical stress, scalable microchip post-CMOS processing method that enables photolithography and electron-beam deposition on hundreds of micrometers scale dies. The technique builds on the use of a polydimethylsiloxane (PDMS) carrier substrate, in which the CMOS chips were embedded and precisely aligned, thereby enabling batch post-processing without complication from additional micromachining or chip treatments. We have demonstrated our technique with 650 μm × 650 μm and 280 μm × 280 μm chips, designed for electrophysiological neural recording and microstimulation implants by monolithic integration of patterned gold and PEDOT:PSS electrodes on the chips and assessed their electrical properties. The functionality of the post-processed chips was verified in saline, and ex vivo experiments using wireless power and data link, to demonstrate the recording and stimulation performance of the microscale electrode interfaces.
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de Beeck, Maaike Op, John O'Callaghan, Karen Qian, Bishoy M. Morcos, Aleksandar Radisic, Karl Malachowski, M. F. Amira, and Chris Van Hoof. "Biocompatible encapsulation and interconnection technology for implantable electronic devices." International Symposium on Microelectronics 2012, no. 1 (January 1, 2012): 000215–24. http://dx.doi.org/10.4071/isom-2012-ta65.

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A biocompatible packaging process for implantable electronic systems is under development at imec, combining biocompatibility, hermeticity, extreme miniaturization and cost aspects. In a first phase of this packaging sequence, hermetic chip sealing is performed by encapsulating all chips to realize a bi-directional diffusion barrier preventing body fluids to leach into the package causing corrosion, and preventing IC materials such as Cu to diffuse into the body, causing various adverse effects. For cost effectiveness, this chip sealing is performed as post-processing at wafer level, using modifications of standard clean room (CR) fabrication techniques. Well known conductive and insulating CR materials are investigated with respect to their biocompatibility, biostability, diffusion barrier properties and sensitivity to corrosion. Material selection and integration aspects are modified until good properties are obtained. In a second phase of the packaging process, all chips of the final device should be electrically connected, applying a biocompatible metallization scheme. We selected the use of Pt due to its excellent biocompatibility and corrosion resistance. Since Pt is very expensive, a cost effective Pt-selective plating process is developed. During the third packaging step, all system components such as electronics, passives, a battery,… will be interconnected. To provide sufficient mechanical support, all components are finally embedded using a medical grade elastomer such as PDMS or Poly-urethane.
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Hackler, Douglas, and Edward Prack. "Ultra-thin Flip-Chip Assembly for Heterogenous and Hybrid Integration." International Symposium on Microelectronics 2020, no. 1 (September 1, 2020): 000146–49. http://dx.doi.org/10.4071/2380-4505-2020.1.000146.

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Abstract Flip-chip packaging of thin-die, in fact any packaging of thin-die, is one of today’s most significant challenges for die handling. Despite the difficulties presented as the thickness of chips continues to decrease, the wide range of applications they have enabled across multiple industries has led to increasing interest, as evidenced by the growth in the cumulative total number of publications on thin silicon based electronics, including Ultra-Thin Chips (UTCs), thinning of Silicon-on-Insulator, and wafer thinning. Smart devices including labels, loggers, wearables, implantable medical, and IoT are in demand. A key area of difficulty in the packaging of thin chips comes from removing the individual chips from dicing tape due to the adhesive nature of the tape and die cracking and edge chipping characteristic of thin die. As the industry continues to embrace the benefits afforded by thin devices, two trends are being witnessed. Devices continue to grow larger in area and thinner in thickness. American Semiconductor’s automated production process for packaging and assembly of chips ≤35um in thickness will be presented. This includes details regarding needleless die eject, pick tip design for ultra-thin devices, ultra-thin flip-chip interconnects, thin-chip overcoat, process controls, and assembly on flexible circuit boards (FCB).
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de Beeck, Maaike Op, Karen Qian, Paolo Fiorini, Karl Malachowski, and Chris Van Hoof. "Design and Characterization of a Biocompatible Packaging Concept for Implantable Electronic Devices." Journal of Microelectronics and Electronic Packaging 9, no. 1 (January 1, 2012): 43–50. http://dx.doi.org/10.4071/imaps.314.

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A biocompatible packaging process for implantable electronic systems is described, combining biocompatibility and hermeticity with extreme miniaturization. In Phase 1 of the total packaging sequence, all chips are encapsulated in order to realize a bidirectional diffusion barrier, preventing body fluids from leaching into the package, which would cause corrosion, and preventing IC materials such as Cu from diffusing into the body, which would cause various adverse effects. For cost-effectiveness, this hermetic chip sealing is performed as a postprocessing step at the wafer level using modifications of standard clean room (CR) fabrication techniques. Well-known conductive and insulating CR materials are investigated with respect to their biocompatibility, diffusion barrier properties, and sensitivity to corrosion. In Phase 2 of the packaging process, all chips of the final device should be electrically connected, applying a biocompatible metallization scheme using, for example, gold or platinum. For electrodes in direct contact with the tissue after implantation, IrOx metallization is proposed. Phase 3 of device assembly is the final packaging step, during which all system components, such as electronics, passives, a battery, among others, will be interconnected. To provide sufficient mechanical support, all these components are embedded using a biocompatible elastomer such as PDMS.
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Op de Beeck, Maaike, Karen Qian, Paolo Fiorini, Karl Malachowski, and Chris Van Hoof. "Design and characterization of a biocompatible packaging concept for implantable electronic devices." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000152–60. http://dx.doi.org/10.4071/isom-2011-ta5-paper2.

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A biocompatible packaging process for implantable electronic systems is described, combining biocompatibility and hermeticity with extreme miniaturization. In a first phase of the total packaging sequence, all chips are encapsulated in order to realize a bi-directional diffusion barrier preventing body fluids to leach into the package causing corrosion, and preventing IC materials such as Cu to diffuse into the body, causing various adverse effects. For cost effectiveness, this hermetic chip sealing is performed as post-processing at wafer level, using modifications of standard clean room (CR) fabrication techniques. Well known conductive and insulating CR materials are investigated with respect to their biocompatibility, diffusion barrier properties and sensitivity to corrosion. In a second phase of the packaging process, all chips of the final device should be electrically connected, applying a biocompatible metallization scheme using eg. gold or platinum. For electrodes being in direct contact with the tissue after implantation, IrOx metallization is proposed. Device assembly is the final packaging step, during which all system components such as electronics, passives, a battery,… will be interconnected. To provide sufficient mechanical support, all these components are embedded using a biocompatible elastomer such as PDMS.
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Nabovati, Ghazal, Abdollah Mirbozorgi, Mohammad Maymandi-Nejad, and Hooman Nabovati. "Ultra-low power self-calibrating process-insensitive BPSK demodulator for bio-implantable chips." IEICE Electronics Express 8, no. 11 (2011): 819–24. http://dx.doi.org/10.1587/elex.8.819.

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Weidenmüller, Jens, Oezgue Dogan, Alexander Stanitzki, Mario Baum, Tim Schröder, Dirk Wünsch, Michael Görtz, and Anton Grabmaier. "Implantable multi-sensor system for hemodynamic controlling." tm - Technisches Messen 85, no. 5 (May 25, 2018): 359–65. http://dx.doi.org/10.1515/teme-2017-0116.

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Abstract A miniaturized implantable multi-sensor system for cardiovascular monitoring of physiological parameters is presented. High accuracy pressure measurements within the vessel can be performed by a capacitive pressure sensor. Additional information about the patient, e. g., sudden movement, inclination or increased temperature can be obtained by additional sensor components such as an acceleration sensor and a temperature sensor unit. This information facilitates compensation of interferences for more accurate pressure measurements. A multi-functional ASIC enables, amongst others, sensor signal processing, power management and telemetric communication with extracorporeal electronics. Sensor chips, the multi-functional ASIC and passive components are assembled on a LTCC circuit board in which an antenna coil is integrated for telemetric energy and data transmission at a frequency of 13.56 MHz. In order to support further miniaturization, the implant shall be encapsulated with a stack of very thin and hermetic ceramics applied by ALD instead of using bulky metal housings. Further encapsulation with polymers, which can be functionalised with appropriate biomolecules, is necessary for a proper shape, a biocompatible interface to the surrounding tissue and, thereby, reduction of thrombogenicity.
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Dissertations / Theses on the topic "Implantable chips"

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Young, Antony, and antony young@rmit edu au. "Accountants' acceptance of a cashless monetary system using an implantable chip." RMIT University. Accounting and Law, 2007. http://adt.lib.rmit.edu.au/adt/public/adt-VIT20080618.093806.

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A logical control extension surrounding cashless means of exchange is a permanent personal verification mark. An implanted micro chip such as ones that have been successfully implanted into humans could identify and store information. Connected with global positioning satellites and a computer system, a cashless monetary system could be formed in the future. The system would provide complete and continual real time records for individuals, businesses and regulators. It would be possible for all trading to occur in this way in the future. A modified Technology Acceptance Model was developed based on Davis' (1989) model and Fishbein and Ajzen's (1975) theory to test the acceptance level of the new monetary system by professional accountants in Australia. The model includes perceived ease of use, perceived usefulness, perceived risk, and a subjective norm component. 523 accountants were surveyed in December 2003 with a response rate of 27%. 13% either strongly agree d or agreed that they would accept the implantable chip. The analysis showed that Perception of Risk, Subjective Norm and Perception of Usefulness were all significant in explaining the dependent variable at the 95% confidence level. The Perception of Ease of Use was not proved to be significant. In consideration of response bias, it was found that with respect to the perception of usefulness at the 0.01 level, two elements were not significant, those being
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Inanlou, Farzad Michael-David. "Innovative transceiver approaches for low-power near-field and far-field applications." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/52245.

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Wireless operation, near-field or far-field, is a core functionality of any mobile or autonomous system. These systems are battery operated or most often utilize energy scavenging as a means of power generation. Limited access to power, expected long and uninterrupted operation, and constrained physical parameters (e.g. weight and size), which limit overall power harvesting capabilities, are factors that outline the importance for innovative low-power approaches and designs in advanced low-power wireless applications. Low-power approaches become especially important for the wireless transceiver, the block in charge of wireless/remote functionality of the system, as this block is usually the most power hungry component in an integrated system-on-chip (SoC). Three such advanced applications with stringent power requirements are examined including space-based exploratory remote sensing probes and their associated radiation effects, millimeter-wave phased-array radar for high-altitude tactical and geological imaging, and implantable biomedical devices (IMDs), leading to the proposal and implementation of low-power wireless solutions for these applications in SiGe BiCMOS and CMOS and platforms.
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Chen, Ting-You, and 陳亭佑. "A Programmable Bi-phasic Current Stimulator for Implantable Vision Chips." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/76824000364048190939.

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碩士
國立東華大學
電機工程學系
97
A charge-balance biphasic current pulse of electrical stimulation generated by implantable devices has been reported as an effective approach to partially recover the visual sensation of blind patients caused by retinitis pigmentosa (RP) and age-related macular degeneration (AMD). Epi-retinal prosthesis and sub-retinal prosthesis of the implant chip are two main methods to generate charge-balance bi-phasic current pulse in the retina stimulation system. Electrical stimulation signals provided by the circuits can replace the original signals provided by the retinal cells. The epi-retinal implant prosthesis uses an external camera to captures the image, transmits the data wirelessly to the implant, and converts the data to stimulus parameters. This thesis is focused on the design of an epi-retinal implant chip. A programmable stimulus driver is proposed with low power consumption which is suitable for the high-density retinal prosthesis. The stimulator includes the digital controller and the biphasic current generator. The biphasic current parameter can be varied by a digital controller. The digital controller includes a counter, a pulse width initial setting controller, a pulse width controller, an interphase delay controller, multiplexers, and a decoder. The biphasic current generator includes a high linearity digital-to-analog converter (DAC) which can provide an output swing with large biphasic current and can save chip area by switching in different time. A low power consumption voltage level shifter in the front stage of DAC is designed for the retina stimulator. The proposed voltage level shifter can limit the output swing so as to avoid the damage to the embedded integrated circuits (ICs). The signal of retinal stimulation generated by the stimulus driver is proved through HSPICE simulation. The stimulus driver is implemented by tsmc 0.35μm iii CMOS process. The proposed topology of the retina stimulator can stimulate 8 pixels with ±5V supply voltage. The frequency of input clock is 10KHz. The frequency of current stimulus signals is 39Hz. The maximum amplitude of the biphasic current pulse is 441μA. The pulse width of the interphase delay are 0.1ms~1ms. The impedance of the retinal tissue is around l0kΩ. In the proposed retina stimulation, 6 bit DAC with high linearity has INL and DNL to be 0.2LSB and 0.4 LSB, respectively.
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Tseng, Jsung-Chieh, and 曾聰傑. "A Programmable PWM Biphasic Current Stimulus Circuit for Implantable Retinal Chips." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/9ackr9.

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碩士
國立東華大學
電機工程學系
95
Retina is a thin sense organization inside the eyeball and it is also the essential part that makes the eyeball receive light and color.If one loses his sight due to the injured retina,which results from the pathological changes,it will be inconvenient for his life.Thus,the purpose of this paper is to design a implantable retinal chips which can replace the injured retina.By using reticulate distribution to stimulate those injured sensitization rod and cone cell of Epi-Retina,this circuitry can transfer the light signal to bipolar pulse of circuitry and then further help those acquired blind people recover part of the sense of sight.This implantable retinal chips mainly includes two parts:One is the external construction that retina deals with the images.The other is the stimulus circuitry that retina embeds light signal and transfer it to bipolar pulse signal.This construction of stimulus circuitry includes 4 bits line(row) shift register,which produces a register in sequence,bipolar retina stimulus circuit,delay locked loop(DLL),pulse frequency modulation(PFM),digital-to-analog converter(DAC),multiplexer and pulse width modulation(PWM).The standard design of biochip is based on the stimulus signal of clinical experimentation definition. The work frequency is 10~125MHz and the work voltage is ±1.8V.The chip is based on 0.18μm 1P6M technology design of Taiwan Semiconductor Manufacturing Company(TSMC).The measure satisfies the design specification.Under the load of 10kΩ in retina,the magnitude of output current is 10~325μA.
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Chio, U.-Fat, and 趙汝法. "Analog Frontend of an Implantable Biological Nerve Micro-stimulation Chip." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/13008309888201215119.

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碩士
國立中山大學
通訊工程研究所
92
An analog frontend of an implantable baseband SOC (System-on-a-chip) chip design for the interface of neural micro-stimulation is present in this thesis. The mentioned neural interface including controllable stimulators, and telemetry for data and power transmission which is powered by transcutaneous magnetic coupling. An external transmitter coil is required to power and communicate with the implanted device. It can avoid the risk of causing infection and the problem of limited battery life. The first topic of this thesis proposes a single stage differential amplifier to be used as an Error Amplifier in an LDO (Low Dropout) regulator. It increases the bandwidth and decreases the chip’s area at the same time. When a bandgap bias is integrated with our design in a feedback loop, a stable voltage source is constituted to become a power supply for the entire implanted chip. The second topic reveals a C-less (no capacitor) area-saving ASK (Amplitude Shift keying) demodulator. Since there is no capacitor used in the demodulator, it can substantially reduce the layout area of the SOC without any sacrifice of the performance of the SOC
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Liu, Yu-Chun. "RF Energy Harvesting for Implantable ICs with On-chip Antenna." Master's thesis, 2014. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/6129.

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Nowadays, as aging population increasing yearly, the health care technologies for elder people who commonly have high blood pressure or Glaucoma issues have attracted much attention. In order to care of those people, implantable integrated circuits (ICs) in human body are the direct solution to have 24/7 days monitoring with real-time data for diagnosis by patients themselves or doctors. However, due to the small size requirement for the implanted ICs located in human organs, it's quite challenging to integrate with transmitting and receiving antenna in a single chip, especially operating in 5.8-GHz ISM band. This research proposes a new idea to solve the issue of integrating an on-chip antenna with implanted ICs. By adding an additional dielectric substrate upon the layer of silicon oxide in CMOS technology, utilizing the metal-6, it can form an extremely compact 3D-structure on-chip antenna which is able to be placed in human eye, heart or even in a few mm-diameter vessels. The proposed 3D on-chip antenna is only 1x1x2.8 mm3 with -10 dB gain and 10% efficiency, which has capability to communicate at least within 5 cm distance. The entire implanted battery-less wireless system has also been developed in this research. A designed 30% efficiency Native NMOS rectifier could generate 1 V and 1 mA to supply the designed low power transmitter including voltage-controlled oscillator (VCO) and power amplifier (PA). The entire system performance is well evaluated by link budget analysis and the simulation result demonstrates the possibility and feasibility of future on-demand easy-to-design implantable SoC.
M.S.E.E.
Masters
Electrical Engr & Computing
Engineering and Computer Science
Electrical Engineering
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Oh, Taeho. "A Low Power Integrated Circuit for Implantable Biosensor Incorporating an On-Chip FSK Modulator." 2008. http://trace.tennessee.edu/utk_gradthes/422.

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Medical care has been significantly improved in recent years due to tremendous technological advancement in the field of CMOS technology. Among those improvements, integrated circuit design and sensing techniques have brought to the doctors more flexibility and accuracy of examinations of their patients. For example, a diabetic patient needs to visit a hospital on a regular basis for the examination and proper treatment. However, with the tremendous advancement in electronic technology, a patient can soon monitor his or her own blood glucose level at home or at office with an implantable sensor which can also trigger insulin pump attached to the body. The insulin delivery system can be precisely controlled by the electronics embedded in the implantable device.In this thesis, a low power integrated circuit for the implantable biosensor incorporating an on-chip FSK modulator is presented. This design has been fabricated using AMI 0.5-μm CMOS process available through MOSIS. The simulation and test results are also presented to verify its operation.
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Tseng, Shao-Bin, and 曾紹賓. "Design of One-Time Implantable SCS System SOC and Inter-chip Capacitance Coupling Circuit." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/21954355338018382465.

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碩士
國立中山大學
電機工程學系研究所
99
The thesis is composed of two topics: A SOC design for one-time implantable spinal cord stimulation system （SCS）, and the design of an inter-chip capacitance coupling circuit. In the first topic, the SOC design using wireless power and data transmission techniques for the SCS system is presented in this work. The proposed SOC can control 4 electrodes to generate different patterns of stimulation waves. It has multiple modes to drive whole the SCS system. Notably, the SOC contains a novel ASK demodulator which converts the ASK signals into digital signals reliably. The SOC is implemented using a typical 0.18-μm 1P6M CMOS process. The chip area is only 1.71 * 1.41 mm2. Besides, the volume of the implantable SCS pulse generator utilizing this SOC is less than 24 cm3, and the power consumption is only 59.4 mW. In the second topic, a high-speed inter-chip capacitance coupling circuit is presented. Digital signals between two chips can be transceived through capacitive coupling of the proposed circuit. Notably, the transceivers are designed below the capacitors to attain the area reduction. It is an advanced application for high-speed wafer testing and 3D IC communication. A prototype chip is presented to achieve 2 Gbps on silicon using a typical 0.18 μm 1P6M CMOS process. The chip area is 1045 × 894 μm2. Besides, it only costs 21.47 mW in terms of power consumption. This capacitive coupling technique for high-speed digital circuit has great potential in the coming future.
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Wan, Chen, and 萬諶. "A CMOS IMPLANTABLE RETINAL CHIP WITH SOLAR CELL POWER SUPPLY CONTROL CIRCUIT FOR RETINA PROSTHESES." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/51720270594050108887.

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碩士
國立交通大學
電子工程系所
96
In this thesis, a retinal chip has been designed, analyzed, and fabricated to improve the power efficiency of the sub-retinal prostheses. The preliminary in vitro experiment of the silicon retina chip which composed of micro photodiode array has also been designed and verified. The silicon retina with MPA can successfully trigger the retina cell and the electrical-response is similar to the light-response in retina cell. The feasibility of on-chip solar cell supply system which integrated with circuit system in CMOS technology has been verified in the work. An ultra-low power clock generator is also designed and verified in this work. This clock generator can generate a clock signal with 1.632KHz under 3.6mW/cm2 incident light intensity with only 5.2nW power consumption. A three times output stimulating current is achieved by taking advantage of the bio-inspired divisional power supply architecture. The stimulating output current is approximately 844nA under the illumination of 3.6mW/cm2 light intensity and 1.72μA under the illumination of 5.06mW/cm2 light intensity. The retinal chip fabricated with a standard 0.18μm tsmc CMOS process demonstrate good mimic of electrical behavior of human retina with low-power consumption. Because of its characteristic, the proposed power management system could be considered as one of the highly integrated solutions for the sub-retinal implant chips.
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Chen, Wei-Ming, and 陳煒明. "The Design and Analysis of CMOS Integrated Circuits and System-on-Chip (SoC) for Implantable Neural-Prosthetic Devices." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/41153822071789795527.

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博士
國立交通大學
電子工程學系 電子研究所
102
In recent years, with the rapid development in technologies of medical devices, biopotential signal recording system is widely used in health monitoring, brain-machine interface, neural prosthesis, etc. The key element for medical devices is the analog front-end amplifier (AFEA) for accurate signal acquisition. The design challenge arises from the small-amplitude and low-frequency characteristics of the biopotential signal. Moreover, to further develop the medical device to clinical application, the device must be designed with the characteristics of low power consumption and small chip area. In this thesis, system architectures and key design techniques for implantable AFEA and neural-prosthetic device are discussed. To demonstrate the design concepts, three works are designed, implemented and tested. Except the functional verification, the designed devices are tested with Long-Evan rates to demonstrate the purpose of clinical application. In the first work, a voltage-mode 8-channel CMOS general-purpose AFEA circuit with tunable gain and bandwidth for biopotential signal recording systems is presented. The proposed AFEA consists of eight chopper stabilized pre-amplifier, an 8-to-1 analog multiplexer, and a programmable gain amplifier. The AFEA is designed and fabricated in 0.18-μm CMOS technology. By adopting the pseudo resistor, the high-pass corner can achieve as low as 0.8Hz without external component and low-pass corner can be adjusted from 1 kHz to 7 kHz to suit for different kinds of biopotential signals with tunable gain up to 74 dB. In the second work, a current-mode front-end amplifier (CMFEA) for neural signal recording systems is implemented. In the proposed CMFEA, a current-mode preamplifier with an active feedback loop operated at very low frequency is designed as the first gain stage to bypass any dc offset current generated by the electrode-tissue interface and to achieve a low high-pass cutoff frequency. No reset signal or ultra-large pseudo resistor is required. The current-mode preamplifier has low dc operation current to enhance low-noise performance and decrease power consumption. A programmable current gain stage is adopted to provide adjustable gain for adaptive signal scaling. A following current-mode filter is designed to adjust the low-pass cutoff frequency for different neural signals. Based on the experiment results, a low-power CMFEA is proposed and simulated. The deigned active feedback loop can bypass the DC offset current to realize a low high-pass cut-off frequency. In addition to the AFEA, an 8-channel closed-loop neural-prosthetic SoC is presented for real-time intracranial EEG (iEEG) acquisition, epileptic seizure detection, and adaptive feedback stimulation control. The SoC is composed of 8 energy-efficient AFEAs, a 10b delta-modulated SAR ADC, a configurable bio-signal processor, and an adaptive high-voltage-tolerant stimulator. A wireless power-and-data transmission system is also embedded to transmit data and power wirelessly. The AFEA, ADC and BSP are used to record and recognize the seizures. Once a seizure is detected, the processor sends a command to activate the adaptive stimulator to suppress the aberrant brain activities. The recorded neural signals are transmitted to the outside of the body over MedRadio band (401 to 406MHz) for system monitoring. The power required for the SoC is transmitted through inductive coils over ISM band (13.56MHz). Data packets are encoded through cyclic redundancy check (CRC) for reliable data transmission. Verified on Long Evans rats, the proposed SoC can detect and feedback control the seizure correctly. From the implementation and measurement results, the proposed architecture and design methodology for voltage-mode and current-mode AFEAs show the low-noise and low-power characteristics which suit for biopotential signal recording and provide a promising solution for medical device. Moreover, the proposed SoC demonstrated an alternative, efficient, and safe treatment for closed-loop epileptic seizure treatment.
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Books on the topic "Implantable chips"

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Nawito, Moustafa. CMOS Readout Chips for Implantable Multimodal Smart Biosensors. Wiesbaden: Springer Fachmedien Wiesbaden, 2018. http://dx.doi.org/10.1007/978-3-658-20347-4.

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CMOS Readout Chips for Implantable Multimodal Smart Biosensors. Springer Vieweg, 2017.

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Lepora, Nathan F. Biohybrid systems. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780199674923.003.0048.

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This chapter introduces the “biohybrid systems” section of the Handbook of Living Machines and briefly reviews some important examples of systems formed by coupling biological to engineered components. These include brain–machine interfaces, both non-invasive, using different external measurement and scanning devices, and invasive approaches focusing on implantable probes. Next we consider fabrication methods for micro- and nanobiohybrid systems and an example of a biohybrid system at the organism level, in the form of a robot–animal biohybrid, developed using methods from synthetic biology. There are many application for biohybrid systems in healthcare: we include exemplar chapters describing intelligent prostheses such as artificial hands with tactile sensing capabilities, sensory organ–chip hybrids in the form of cochlear implants, and artificial implants designed to replace damaged neural tissue and restore lost memory function.
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Book chapters on the topic "Implantable chips"

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Kumar, Vikas. "Implantable RFID Chips." In The Future of Identity in the Information Society, 151–57. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-79026-8_11.

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Nawito, Moustafa. "Introduction." In CMOS Readout Chips for Implantable Multimodal Smart Biosensors, 1–6. Wiesbaden: Springer Fachmedien Wiesbaden, 2017. http://dx.doi.org/10.1007/978-3-658-20347-4_1.

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Nawito, Moustafa. "The SMARTImplant Project." In CMOS Readout Chips for Implantable Multimodal Smart Biosensors, 7–18. Wiesbaden: Springer Fachmedien Wiesbaden, 2017. http://dx.doi.org/10.1007/978-3-658-20347-4_2.

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Nawito, Moustafa. "ASIC Version 1." In CMOS Readout Chips for Implantable Multimodal Smart Biosensors, 19–40. Wiesbaden: Springer Fachmedien Wiesbaden, 2017. http://dx.doi.org/10.1007/978-3-658-20347-4_3.

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Nawito, Moustafa. "ASIC Version 2." In CMOS Readout Chips for Implantable Multimodal Smart Biosensors, 41–84. Wiesbaden: Springer Fachmedien Wiesbaden, 2017. http://dx.doi.org/10.1007/978-3-658-20347-4_4.

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Nawito, Moustafa. "ASIC Version 3." In CMOS Readout Chips for Implantable Multimodal Smart Biosensors, 85–96. Wiesbaden: Springer Fachmedien Wiesbaden, 2017. http://dx.doi.org/10.1007/978-3-658-20347-4_5.

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Nawito, Moustafa. "Measurement Results." In CMOS Readout Chips for Implantable Multimodal Smart Biosensors, 97–118. Wiesbaden: Springer Fachmedien Wiesbaden, 2017. http://dx.doi.org/10.1007/978-3-658-20347-4_6.

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Nawito, Moustafa. "Summary, Conclusions and Outlook." In CMOS Readout Chips for Implantable Multimodal Smart Biosensors, 119–23. Wiesbaden: Springer Fachmedien Wiesbaden, 2017. http://dx.doi.org/10.1007/978-3-658-20347-4_7.

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Ikuta, Koji, Atsushi Takahashi, Kota Ikeda, and Shoji Maruo. "User-Assembly, Fully Integrated Micro Chemical Laboratory Using Biochemical IC Chips for Wearable/Implantable Applications." In Micro Total Analysis Systems 2002, 37–39. Dordrecht: Springer Netherlands, 2002. http://dx.doi.org/10.1007/978-94-010-0295-0_12.

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Bhunia, Swarup, Abhishek Basak, Seetharam Narasimhan, and Maryam Sadat Hashemian. "Ultralow Power and Robust On-Chip Digital Signal Processing for Closed-Loop Neuro-Prosthesis." In Implantable Bioelectronics, 155–93. Weinheim, Germany: Wiley-VCH Verlag GmbH & Co. KGaA, 2014. http://dx.doi.org/10.1002/9783527673148.ch9.

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Conference papers on the topic "Implantable chips"

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Puers, Robert. "Implantable chips and sensors: Quo vadis?" In 2013 IEEE Sensors. IEEE, 2013. http://dx.doi.org/10.1109/icsens.2013.6688305.

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Li, W., D. C. Rodger, and Y. C. Tai. "Implantable RF-coiled chip packaging." In 2008 IEEE 21st International Conference on Micro Electro Mechanical Systems. IEEE, 2008. http://dx.doi.org/10.1109/memsys.2008.4443604.

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Li-Jie Xu, Yong-Xin Guo, and Wen Wu. "On-chip antenna for implantable applications." In 2013 Cross Strait Quad-Regional Radio Science and Wireless Technology Conference (CSQRWC). IEEE, 2013. http://dx.doi.org/10.1109/csqrwc.2013.6657382.

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Ryan, J. G., K. J. Carroll, and B. D. Pless. "A four chip implantable defibrillator/pacemaker chipset." In 1989 Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/cicc.1989.56708.

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Guenther, T., C. W. D. Dodds, N. H. Lovell, and G. J. Suaning. "Chip-scale hermetic feedthroughs for implantable bionics." In 2011 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE, 2011. http://dx.doi.org/10.1109/iembs.2011.6091656.

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Sun, Yuxiang, Brian Greet, David Burkland, Mathews John, Mehdi Razavi, and Aydin Babakhani. "Wirelessly powered implantable pacemaker with on-chip antenna." In 2017 IEEE/MTT-S International Microwave Symposium - IMS 2017. IEEE, 2017. http://dx.doi.org/10.1109/mwsym.2017.8058831.

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Bleck, L., H. Steins, and R. von Metzen. "Interface Adhesion in Implantable Chip-in-Foil Systems." In 2018 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC). IEEE, 2018. http://dx.doi.org/10.1109/embc.2018.8512982.

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Lund, J. L., and K. D. Wise. "CHIP-LEVEL ENCAPSULATION OF IMPLANTABLE CMOS MICROELECTRONIC ARRAYS." In 1994 Solid-State, Actuators, and Microsystems Workshop. San Diego, CA USA: Transducer Research Foundation, Inc., 1994. http://dx.doi.org/10.31438/trf.hh1994.7.

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AQUILINO, F., and F. G. DELLA CORTE. "ON-CHIP ANTENNA STRUCTURES FOR BIOMEDICAL IMPLANTABLE SENSORS." In Proceedings of the 13th Italian Conference. WORLD SCIENTIFIC, 2008. http://dx.doi.org/10.1142/9789812835987_0043.

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Lund, J. L., and K. D. Wise. "CHIP-LEVEL ENCAPSULATION OF IMPLANTABLE CMOS MICROELECTRONIC ARRAYS." In 1994 Solid-State, Actuators, and Microsystems Workshop. San Diego, CA USA: Transducer Research Foundation, Inc., 1994. http://dx.doi.org/10.31438/trf.hh1994.7.

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