Dissertations / Theses on the topic 'Impedance amplifier'
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Cheong, Heng Wan. "Generalized impedance converter (GIC) filter utilizing composite amplifier." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2005. http://library.nps.navy.mil/uhtbin/hyperion/05Sep%5FCheong.pdf.
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Kauffman, John Gabriel. "Design of a High Impedance Preamplifier for Coil Arrays." Link to electronic thesis, 2005. http://www.wpi.edu/Pubs/ETD/Available/etd-050205-141036/.
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Bani-Khaled, Ghazi, D. Snizhko, K. Muzyka, and G. Xu. "Trans-impedance Ampli er for ECL Analyzer." Thesis, ISBC 2018, 2018. http://openarchive.nure.ua/handle/document/5790.
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Use of apparatus "Spark" with electrochemical station CHI 800C CH Instrument and pho-
tomultiplier tube CR-105 by Hamamatsu Photonics is shown by over an electrochemilumi-
nescent assay of the test solution.
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Sun, Yichuang. "Analysis and synthesis of impedance matching networks and transconductance amplifier filters." Thesis, University of York, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.297262.
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Denson, Stephen Charles. "Improving the Sensitivity and Resolution of Miniature Ion Mobility Spectrometers with a Capacitive Trans Impedance Amplifier." Diss., Tucson, Arizona : University of Arizona, 2005. http://etd.library.arizona.edu/etd/GetFileServlet?file=file:///data1/pdf/etd/azu%5Fetd%5F1314%5F1%5Fm.pdf&type=application/pdf.
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Acimovic, Igor. "Contributions to the Design of RF Power Amplifiers." Thesis, Université d'Ottawa / University of Ottawa, 2013. http://hdl.handle.net/10393/24406.
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In this thesis we introduce a two-way Doherty amplifier architecture with multiple feedbacks for digital predistortion based on impedance-inverting directional coupler (transcoupler). The tunable two-way Doherty amplifier with a tuned circulator-based impedance inverter is presented. Compact N-way Doherty architectures that subsume impedance inverter and offset line functionality into output matching networks are derived. Comprehensive N-way Doherty amplifier design and analysis techniques based on load-pull characterization of active devices and impedance modulation effects are developed. These techniques were then applied to the design of a two-way Doherty amplifier and a three-way Doherty amplifier which were manufactured and their performance measured and compared to the amplifier performance specifications and simulated results.
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Ramachandran, Narayan Prasad. "Design of a 3.3 V analog video line driver with controlled output impedance." [College Station, Tex. : Texas A&M University, 2003. http://hdl.handle.net/1969.1/106.
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Thesis (M.S.)--Texas A&M University, 2003."Major Subject: Electrical Engineering" Title from author supplied metadata (record created on Jul. 18, 2005.) Vita. Abstract. Includes bibliographical references.
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Refai, Wael Yahia. "A Linear RF Power Amplifier with High Efficiency for Wireless Handsets." Diss., Virginia Tech, 2014. http://hdl.handle.net/10919/25886.
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This research presents design techniques for a linear power amplifier with high efficiency in wireless handsets. The power amplifier operates with high efficiency at the saturated output power, maintains high linearity with enhanced efficiency at back-off power levels, and covers a broadband frequency response. The amplifier is thus able to operate in multiple modes (2G/2.5G/3G/4G). The design techniques provide contributions to current research in handset power amplifiers, especially to the converged power amplifier architecture, to reduce the number of power amplifiers within the handset while covering all standards and frequency bands around the globe.
Three main areas of interest in power amplifier design are investigated: high power efficiency; high linearity; and broadband frequency response. Multiple techniques for improving the efficiency are investigated with the focus on maintaining linear operation. The research applies a new technique to the handset industry, class-J, to improve the power efficiency while avoiding the practical issues that hinder the typical techniques (class-AB and class-F). Class-J has been implemented using GaN FET in high power applications. To our knowledge, this work provides the first implementation of class-J using GaAs HBT in a handset power amplifier.
The research investigates the linearity, and the nature and causes of nonlinearities. Multiple concepts for improving the linearity are presented, such as avoiding odd-degree harmonics, and linearizing the relationship between the output current and the input voltage of the amplifier at the fundamental frequency. The concept of bias depression in HBT transistors is introduced with a bias circuit that reduces the bias-offset effect to improve linearity at high output power.
A design methodology is presented for broadband matching networks, including the component loss. The methodology offers a quick and accurate estimation of component values, giving more degrees of freedom to meet the design specifications. It enables a trade-off among high out-of-band attenuation, number/size of components, and power loss within the network.
Although the main focus is handset power amplifiers, most of the developed techniques can be applied to a wide range of power amplifiers.Ph. D.
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Malan, Pieter Jacob De Villiers. "Low impedance characterisation and modeling of high power LDMOS devices." Thesis, Stellenbosch : University of Stellenbosch, 2005. http://hdl.handle.net/10019.1/2510.
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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005.In RF power transistor characterisation, the designer is confronted with low impedance measurements (typically from 1 Ohm to 12 Ohm). These transistors are contained in metal-ceramic packages of which the lead widths vary with power capability. This thesis presents a high-quality fixture design with low impedance TRL calibration standards for characterisation of an LDMOS transistor. Pre-matching networks are used to transform to the low impedance environment. Since these pre-matching networks are independent of the termination impedance, the low impedance port can always be designed to comply with the same dimension as the device which is being measured.
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Bozanic, Mladen. "Design methods for integrated switching-mode power amplifiers." Thesis, University of Pretoria, 2011. http://hdl.handle.net/2263/26616.
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While a lot of time and resources have been placed into transceiver design, due to the pace of a conventional engineering design process, the design of a power amplifier is often completed using scattered resources; and not always in a methodological manner, and frequently even by an iterative trial and error process. In this thesis, a research question is posed which enables for the investigation of the possibility of streamlining the design flow for power amplifiers. After thorough theoretical investigation of existing power amplifier design methods and modelling, inductors inevitably used in power amplifier design were identified as a major drawback to efficient design, even when examples of inductors are packaged in design HIT-Kits. The main contribution of this research is engineering of an inductor design process, which in-effect contributes towards enhancing conventional power amplifiers. This inductance search algorithm finds the highest quality factor configuration of a single-layer square spiral inductor within certain tolerance using formulae for inductance and inductor parasitics of traditional single-π inductor model. Further contribution of this research is a set of algorithms for the complete design of switch-mode (Class-E and Class-F) power amplifiers and their output matching networks. These algorithms make use of classic deterministic design equations so that values of parasitic components can be calculated given input parameters, including required output power, centre frequency, supply voltage, and choice of class of operation. The hypothesis was satisfied for SiGe BiCMOS S35 process from Austriamicrosystems (AMS). Several metal-3 and thick-metal inductors were designed using the abovementioned algorithm and compared with experimental results provided by AMS. Correspondence was established between designed, experimental and EM simulation results, enabling qualification of inductors other than those with experimental results available from AMS by means of EM simulations with average relative errors of 3.7% for inductors and 21% for the Q factor at its peak frequency. For a wide range of inductors, Q-factors of 10 and more were readily experienced. Furthermore, simulations were performed for number of Class-E and Class-F amplifier configurations with HBTs with ft greater than 60 GHz and total emitter area of 96 μm² as driving transistors to complete the hypothesis testing. For the complete PA system design (including inductors), simulations showed that switch-mode power amplifiers for 50 Ω load at 2.4 GHz centre frequency can be designed using the streamlined method of this research for the output power of about 6 dB less than aimed. This power loss was expected, since it can be attributed to non-ideal properties of the driving transistor and Q-factor limitations of the integrated inductors, assumptions which the computations of the routine were based on. Although these results were obtained for a single micro-process, it was further speculated that outcome of this research has a general contribution, since streamlined method can be used with a much wider range of CMOS and BiCMOS processes, when low-gigahertz operating power amplifiers are needed. This theory was confirmed by means of simulation and fabrication in 180 nm BiCMOS process from IBM, results of which were also presented. The work presented here, was combined with algorithms for SPICE netlist extraction and the spiral inductor layout extraction (CIF and GDSII formats). This secondary research outcome further contributed to the completeness of the design flow. All the above features showed that the routine developed here is substantially better than cut-and-try methods for design of power amplifiers found in the existing body of knowledge.Thesis (PhD(Eng))--University of Pretoria, 2011.
Electrical, Electronic and Computer Engineering
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Najjari, Hamza. "Power Amplifier Design Based on Electro-Thermal Considerations." Thesis, Bordeaux, 2019. http://www.theses.fr/2019BORD0422.
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L’objectif de ce travail de recherche est de concevoir un amplificateur de puissance sur la base de considérations électrothermiques. Il décrit la question du dynamique EVM et du « paquet long » lors de la conception de l’amplificateur avec des transistors bipolaires à hétérojonctions. Basé sur le comportement électrothermique du circuit, une méthode d’optimisation de l’EVM statique et dynamique est proposée. Un frontend RF complet (amplificateur de puissance + coupleur + interrupteur + amplificateur faible bruit) est conçu pour le dernier standard WLAN : le Wi-Fi 6. La distribution de temperature dynamique dans le circuit est analysée. Son effet sur les performances de la puce est quantifié. Enfin, une polarisation adaptative programmable a été conçue pour garder des performances optimales sur toute la plage de température. Les mesures du circuit montre tout l’effet bénéfique de cette compensation, permettant de garder le dynamique EVM en dessous de -47 dB sur la plage de température ambiante de -40 à 85°CThe aim of this work is to design a power amplifier based on electrothermal considerations. It describes the Dynamic Error Vector Magnitude challenge and long packet issue when designing a power amplifier with hetero-junction bipolar transistors. Based on the circuit electrothermal behavior, an optimization method of both the static and dynamic linearity is proposed. A complete RF front-end (PA + coupler + switch + LNA) is designed for the latest WLAN standard: the Wi-Fi 6. The dynamic temperature distribution in the circuit is analyzed. It’s impact on the performances is quantified. Finally, a programmable temperature dependent bias is designed to compensate for performance degradation. The measurements show a significant linearity improvement with this compensation, allowing the PA to maintain the DEVM lower than -47dB at 14.5 dBm output power, over a large ambient temperature range from -40°C to 85°C
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Ronaghzadeh, Amin. "Improving The Efficiency Of Microwave Power Amplifiers Without Linearity Degradation Using Load And Bias Tuning In A New Configuration." Phd thesis, METU, 2013. http://etd.lib.metu.edu.tr/upload/12615730/index.pdf.
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Advanced digital modulation schemes used in the wireless applications, result in the modulated RF signals with high peak to average power ratio which requires linear amplification. On the other hand, the demand for a longer talk time with less battery volume and weight, especially in hand-held radio units, necessitate more power efficient methods to be utilized in power amplifier design. But improved linearity and efficiency have always been contradicting requirements demanding innovative power amplifier and linearizer design techniques.
Dynamically varying the load impedance and bias point of a transistor according to the varying envelope of the incoming RF signal also known as Dynamic Load Modulation (DLM) and Dynamic Supply Modulation (DSM), respectively, are two separate methods for improving the efficiency in power amplifier
design. In this dissertation, a combination of both variable gate bias and tunable load concepts is applied in an amplifier structure consisting of two transistors in parallel.
A novel computer aided design methodology is proposed for careful selection of the load and biasing points of the individual transistors. The method which is based on load-pull analysis performs sweeps on the gate bias voltages of the active devices and input drive level of the amplifier in order to obtain ranges of biases that result in the generation of IMD sweet spots. Following that, the amplifier is designed employing the load line theory and bias switching at the same time in order to enhance the efficiency in reduced drive levels while extending the output 1 dB compression point to higher values at higher drives.
Tunable matching networks are implemented utilizing varactor stacks in a &Picon
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Connor, Mark Anthony. "Design of Power-Scalable Gallium Nitride Class E Power Amplifiers." University of Dayton / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1405437893.
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Marek, Pavel. "Měření přenosových a imitančních charakteristik aktivních obvodových prvků." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218000.
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This diploma work deals with active circuit elements and proposals of methods for measuring of some parameters of these elements. In the opening part the work deals with general classification of elements used in electronic circuits, ideal and real current sources and power supplies. Further there are stated basic parameters and characteristics presented by producers in a catalogue sheet for active elements MAX435, OPA660, AD844 and MAA741 element which already belongs to the history of IC. Main attention is paid to active circuit elements with current sources driven by CCCS (Current Controlled Current Source) and AD844 (high speed monolithic operational amplifier). In the work there is described a method for determining of selected parameters of active elements with CCCS. Examined parameters were frequency characteristics of current transfer, input impedance and output impedance. The proposed method was verified by a computer simulation on above mentioned active elements by means of PSpice software. Findings along with the description are summarized at the end of the work. In the closing part of the work there is undertaken a real measure of AD844 element based on the proposed method and the findings are compared with particular simulations. However, at first a flat connection board was made by means of EAGLE software and then the measure was performed on it.
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Figueiredo, Rafael Carvalho 1982. "Circuito equivalente e extração dos parâmetros em função da corrente de amplificadores ópticos a semicondutor." [s.n.], 2010. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259026.
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Orientadores: Evandro Conforti, Napoleão dos Santos RibeiroDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-16T11:21:52Z (GMT). No. of bitstreams: 1 Figueiredo_RafaelCarvalho_M.pdf: 10424465 bytes, checksum: b93608291545cc7a53e52e2050a3dc39 (MD5) Previous issue date: 2010
Resumo: Apresenta-se a modelagem de um circuito elétrico equivalente e a extração de parâmetros de amplificadores ópticos a semicondutor (SOA), a partir de um modelo para lasers semicondutores. Foi realizado um estudo do comportamento da impedância de um SOA em chip, sem encapsulamento, em função da corrente de polarização e em ampla faixa de frequência . de 300 kHz a 40 GHz. A modelagem do circuito equivalente da montagem, a qual é cascateada com os modelos da região ativa do SOA, é apresentada para correntes abaixo e acima da operação em transparência. A metodologia utilizada para a extração dos parâmetros dos elementos parasitas que compõe o circuito é descrita; resultados obtidos através de simulações em programa comercial (Agilent ADS) são comparados com medidas experimentais obtidas em mesa óptica. São apresentados ainda resultados teóricos da impedância do SOA quando desconsiderada a presença dos elementos parasitas da montagem. A modelagem e extração dos parâmetros realizada para o chip foi repetida para SOAs encapsulados, também apresentando boa concordância entre teoria e experimento, reforçando a viabilidade da abordagem utilizada
Abstract: The equivalent electric circuits and its parameters.extraction of semiconductor optical amplifiers (SOA) are attained based on a diode-laser model. Additionally, the impedance behavior of a SOA-chip (without package) was measured as function of the bias current in wide frequency range, from 300 kHz to 40 GHz. In these procedures, the microwave setup used for the SOA current injection was also characterized and its equivalent circuit obtained. Next, a theoretical analysis is developed for this setup for currents below and above the transparency condition. A methodology for the parameters extraction of parasitic elements is also described, as well as the results obtained through simulations using the Agilent ADS software, compared with the experimental data. The optical bench used in the experiments is also described, and theoretical results illustrates the SOA impedance without parasitic elements. The equivalent circuits with parameters.extraction were also obtained for packaged SOAs, with good agreement between theory and experiment, conforming the employed methodology
Mestrado
Telecomunicações e Telemática
Mestre em Engenharia Elétrica
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Straka, Petr. "Ultrazvukový drtič konkrementů." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219202.
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This thesis is focused on the methodes of crushing kidney’s concrements with continual wave for the frequency 27 kHz and the intensity of ultrasound 10 W/cm2. The main aim is design of the ultrasound head with layer converter and design circuitry. First part of this work describes physical principle of ultrasound, ultrasound waves and methods by which could be remove kidney’s concretions. Practical part of this work is focused on compreshive design of ultrasound crushing system. In the introdiction is analyzed the proposal of applicator and the next step decscribing proposal excitation generator. The work contains results of simulation which was done on proposal curcuit, drawings of scheme, list of components and drawing of PCB.
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Přecechtěl, Vít. "Modul elektrochemické impedanční spektroskopie pro výzkum vodíkových palivových článků." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221186.
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This thesis deals with diagnostic fuel-cell parameters using electrochemical impedance spectroscopy. The document begins with brief explanation of fuel-cell operation and its basic principles. Thesis continues with description of fuel-cell voltage generation and influence of charge dual-layer on impedance. After that electrochemical impedance spectroscopy, signals used for perturbation and evaluation of impedance spectrum using Bode a Nyquist plot is described. Next part explains measurement of impedance spectrum using potentiostat in combination with lock-in amplifier or frequency response analyzer. Practical part of thesis is dedicated to electric circuit design of EIS module and software designed for automatic measurement of impedance spectrum. Last part shows results of EIS module testing.
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Janse, van Rensburg Christo. "A SiGe BiCMOS LNA for mm-wave applications." Diss., University of Pretoria, 2012. http://hdl.handle.net/2263/26501.
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A 5 GHz continuous unlicensed bandwidth is available at millimeter-wave (mm-wave) frequencies around 60 GHz and offers the prospect for multi gigabit wireless applications. The inherent atmospheric attenuation at 60 GHz due to oxygen absorption makes the frequency range ideal for short distance communication networks. For these mm-wave wireless networks, the low noise amplifier (LNA) is a critical subsystem determining the receiver performance i.e., the noise figure (NF) and receiver sensitivity. It however proves challenging to realise high performance mm-wave LNAs in a silicon (Si) complementary metal-oxide semiconductor (CMOS) technology. The mm-wave passive devices, specifically on-chip inductors, experience high propagation loss due to the conductivity of the Si substrate at mm-wave frequencies, degrading the performance of the LNA and subsequently the performance of the receiver architecture. The research is aimed at realising a high performance mm-wave LNA in a Si BiCMOS technology. The focal points are firstly, the fundamental understanding of the various forms of losses passive inductors experience and the techniques to address these issues, and secondly, whether the performance of mm-wave passive inductors can be improved by means of geometry optimising. An associated hypothesis is formulated, where the research outcome results in a preferred passive inductor and formulates an optimised passive inductor for mm-wave applications. The performance of the mm-wave inductor is evaluated using the quality factor (Q-factor) as a figure of merit. An increased inductor Q-factor translates to improved LNA input and output matching performance and contributes to the lowering of the LNA NF. The passive inductors are designed and simulated in a 2.5D electromagnetic (EM) simulator. The electrical characteristics of the passive structures are exported to a SPICE netlist which is included in a circuit simulator to evaluate and investigate the LNA performance. Two LNAs are designed and prototyped using the 13μ-m SiGe BiCMOS process from IBM as part of the experimental process to validate the hypothesis. One LNA implements the preferred inductor structures as a benchmark, while the second LNA, identical to the first, replaces one inductor with the optimised inductor. Experimental verification allows complete characterization of the passive inductors and the performance of the LNAs to prove the hypothesis. According to the author's knowledge, the slow-wave coplanar waveguide (S-CPW) achieves a higher Q-factor than microstrip and coplanar waveguide (CPW) transmission lines at mm-wave frequencies implemented for the 130 nm SiGe BiCMOS technology node. In literature, specific S-CPW transmission line geometry parameters have previously been investigated, but this work optimises the signal-to-ground spacing of the S-CPW transmission lines without changing the characteristic impedance of the lines. Optimising the S-CPW transmission line for 60 GHz increases the Q-factor from 38 to 50 in simulation, a 32 % improvement, and from 8 to 10 in measurements. Furthermore, replacing only one inductor in the output matching network of the LNA with the higher Q-factor inductor, improves the input and output matching performance of the LNA, resulting in a 5 dB input and output reflection coefficient improvement. Although a 5 dB improvement in matching performance is obtained, the resultant noise and gain performance show no significant improvement. The single stage LNAs achieve a simulated gain and NF of 13 dB and 5.3 dB respectively, and dissipate 6 mW from the 1.5 V supply. The LNA focused to attain high gain and a low NF, trading off linearity and as a result obtained poor 1 dB compression of -21.7 dBm. The LNA results are not state of the art but are comparable to SiGe BiCMOS LNAs presented in literature, achieving similar gain, NF and power dissipation figures.Dissertation (MEng)--University of Pretoria, 2012.
Electrical, Electronic and Computer Engineering
unrestricted
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Wolf, Robert, Niko Joram, Stefan Schumann, and Frank Ellinger. "Dual-band impedance transformation networks for integrated power amplifiers." Cambridge University Press, 2016. https://tud.qucosa.de/id/qucosa%3A70680.
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This paper shows that the two most common impedance transformation networks for power amplifiers (PAs) can be designed to achieve optimum transformation at two frequencies. Hence, a larger bandwidth for the required impedance transformation ratio is achieved. A design procedure is proposed, which takes imperfections like losses into account. Furthermore, an analysis method is presented to estimate the maximum uncompressed output power of a PA with respect to frequency. Based on these results, a fully integrated PA with a dual-band impedance transformation network is designed and its functionality is proven by large signal measurement results. The amplifier covers the frequency band from 450 MHz to 1.2 GHz (3 dB bandwidth of the output power and efficiency), corresponding to a relative bandwidth of more than 100%. It delivers 23.7 dBm output power in the 1 dB compression point, having a power-added efficiency of 33%.
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Weststrate, Marnus. "LC-ladder and capacitive shunt-shunt feedback LNA modelling for wideband HBT receivers." Thesis, University of Pretoria, 2011. http://hdl.handle.net/2263/26615.
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Although the majority of wireless receiver subsystems have moved to digital signal processing over the last decade, the low noise amplifier (LNA) remains a crucial analogue subsystem in any design being the dominant subsystem in determining the noise figure (NF) and dynamic range of the receiver as a whole. In this research a novel LNA configuration, namely the LC-ladder and capacitive shunt-shunt feedback topology, was proposed for use in the implementation of very wideband LNAs. This was done after a thorough theoretical investigation of LNA configurations available in the body of knowledge from which it became apparent that for the most part narrowband LNA configurations are applied to wideband applications with suboptimal results, and also that the wideband configurations that exist have certain shortcomings. A mathematical model was derived to describe the new configuration and consists of equations for the input impedance, input return loss, gain and NF, as well as an approximation of the worst case IIP3. Compact design equations were also derived from this model and a design strategy was given which allows for electronic design automation of a LNA using this configuration. A process for simultaneously optimizing the circuit for minimum NF and maximum gain was deduced from this model and different means of improving the linearity of the LNA were given. This proposed design process was used successfully throughout this research. The accuracy of the mathematical model has been verified using simulations. Two versions of the LNA were also fabricated and the measured results compared well with these simulations. The good correlation found between the calculated, simulated and measured results prove the accuracy of the model, and some comments on how the accuracy of the model could be improved even further are provided as well. The simulated results of a LNA designed for the 1 GHz to 18 GHz band in the IBM 8HP process show a gain of 21.4 dB and a minimum NF of only 1.7 dB, increasing to 3.3 dB at the upper corner frequency while maintaining an input return loss below -10 dB. After steps were taken to improve the linearity, the IIP3 of the LNA is -14.5 dBm with only a small degradation in NF now 2.15 dB at the minimum. The power consumption of the respective LNAs are 12.75 mW and 23.25 mW and each LNA occupies a chip area of only 0.43 mm2. Measured results of the LNA fabricated in the IBM 7WL process had a gain of 10 dB compared to an expected simulated gain of 20 dB, however significant path loss was introduced by the IC package and PCB parasitics. The S11 tracked the simulated response very well and remained below -10 dB over the feasible frequency range. Reliable noise figure measurements could not be obtained. The measured P1dB compression point is -22 dBm. A 60 GHz LNA was also designed using this topology in a SiGe process with ƒT of 200 GHz. A simulated NF of 5.2 dB was achieved for a gain of 14.2 dB and an input return loss below -15 dB using three amplifier stages. The IIP3 of the LNA is -8.4 dBm and the power consumption 25.5 mW. Although these are acceptable results in the mm-wave range it was however found that the wideband nature of this configuration is redundant in the unlicensed 60 GHz band and results are often inconsistent with the design theory due to second order effects. The wideband results however prove that the LC-ladder and capacitive shunt-shunt feedback topology is a viable means for especially implementing LNAs that require a very wide operating frequency range and also very low NF over that range.Thesis (PhD(Eng))--University of Pretoria, 2011.
Electrical, Electronic and Computer Engineering
unrestricted
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Ramadan, Ashraf. "Active antennas with high input impedance low noise and highly linear amplifiers." [S.l. : s.n.], 2005. http://deposit.ddb.de/cgi-bin/dokserv?idn=975739174.
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Port, Martin. "Čtyřelektrodový impedanční pletysmograf." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2014. http://www.nusl.cz/ntk/nusl-220285.
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This master’s thesis is an introduction to the measurement of changes in tissue impedance of blood flow by impedance plethysmography. Other chapters deal with the kinds of plethysmographs and their principles. The aim is to draft four-electrode impedance plethysmograph to measure changes in tissue impedance depending on blood flow. First, describe the individual blocks of the medical instrument. The practical part of the master’s thesis involves circuit design four-electrode plethysmograph. Given that a very important role in its function plays a constant current source operating at a frequency of 60kHz, this subset was implemented and verified its correct function. To draw component schemes used program EAGLE version 5.10.0.
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Šnajdr, Václav. "Vysokofrekvenční a mezifrekvenční obvody krátkovlnné radiostanice." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217792.
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The study, description, design and implementation of selected blocks of multiband shortwave radio station are dealt with in the thesis. Focus is placed on the concept of multiband shortwave radio stations, with an emphasis on high frequency and intermediate frequency circuits. The first chapter is devoted to description of the transceiver block diagram which is designed as superheterodyne. The design of bandpass input filters, intermediate frequency crystal filters and output filters is described. Simulation results and the measured characteristics of the implemented functional blocks are presented. Furthermore, the amplifier circuits which maintain impedance matching of individual blocks are discussed. SSB signal generation in the transmitter part of radio station and final stage power amplification are depicted.
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Hjern, Gunnar. "The modernization of a DOS-basedtime critical solar cell LBICmeasurement system." Thesis, Karlstads universitet, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-74322.
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LBIC is a technique for scanning the local quantum efficiency of solar cells. This kind of measurements needs a highly specialized, and time critical controlling software. In 1996 the client, professor Markus Rinio, constructed an LBIC system, and wrote the controlling software as a Turbo-Pascal 7.0 application, running under the MS-DOS 6.22 operating system. By now (2018) both the software and several hardware components are in dire need to be modernized. This thesis thoroughly describes several important aspects of this work, and the considerations needed for a successful result. This includes both very foundational choices about the software architecture, the choice of suitable operating system, the threading model, and the adaptation to new hardware with vastly different behavior. The project also included a new hardware module for position reports and instrument triggering, as well as several adaptations to transform the DOS-based LBIC software into a pleasant modern GUI application.
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Bertondini, Giulio. "Progetto di un sistema di misura integrato per la calibrazione statica di un Current-Steering RF-DAC a 14 bit in tecnologia FinFET." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2020. http://amslaurea.unibo.it/19822/.
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Il presente lavoro di tesi, svolto nel corso di 6 mesi di tirocinio presso Xilinx Irlanda, è focalizzato sullo studio e calibrazione degli effetti introdotti dalle non-idealità di tipo statico presenti nei convertitori digitale-analogici (Digital to Analog Converter: DAC) a radio frequenza con architettura Current-Steering, basata su un insieme di generatori di corrente con segmentazione mista termometrica e binaria: 14 bit binari suddivisi in 8 LSB binari e 6 MSB binari convertiti in 63 bit termometrici.
Le non-idealità statiche includono i mismatch dei generatori e un gradiente di processo che condiziona fortemente il valore delle correnti dei generatori. Questo porta ad avere problemi di distorsione armonica nel segnale analogico generato dal DAC.
Sono stati implementati e simulati, in Verilog-A, algoritmi per la riduzione della distorsione utilizzando dapprima i valori di corrente dei generatori forniti da un modello Verilog-A del DAC. In realtà, su silicio, queste correnti devono essere misurate con precisione con un sistema di misura. È stato quindi progettato, utilizzando librerie FinFET TSMC (Taiwan Semiconductor Manufacturing Company) in Cadence Virtuoso, un sistema di misura integrato che consente di misurare le correnti di tutti i 63 generatori termometrici del valore nominale di 500uA, con una precisione di circa 50nA, impiegando un tempo di alcune decine di ms e consentendo in questo modo la calibrazione del DAC.
Infine sono stati modificati gli algoritmi precedentemente introdotti nel modello del DAC, inserendo degli opportuni coefficienti legati alla precisione di misura del sistema progettato, ottenendo risultati molto positivi in cui si nota l'efficacia del sistema di misura e della calibrazione del DAC in situazioni realistiche.
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Wang, Xusheng. "Ultrasonic Generator for Surgical Applications and Non-invasive Cancer Treatment by High Intensity Focused Ultrasound." Thesis, Université Paris-Saclay (ComUE), 2016. http://www.theses.fr/2016SACLS052/document.
Full textAbstract:
La technique de haute intensité ultrasons focalisés (HIFU) est maintenant largement utilisée pour le traitement du cancer, grâce à son avantage non-invasif. Dans un système de HIFU, une matrice de transducteurs à ultrasons est pilotée en phase pour produire un faisceau focalisé d'ultrasons (1M ~ 10 MHz) dans une petite zone de l'emplacement de la cible sur le cancer dans le corps. La plupart des systèmes HIFU sont guidées par imagerie par résonance magnétique (IRM) dans de nos jours. Dans cette étude de doctorat, un amplificateur de puissance de classe D en demi-pont et un système d'accord automatique d'impédance sont proposés. Tous deux circuits proposés sont compatibles avec le système IRM. L'amplificateur de puissance proposé a été réalisé par un circuit imprimé (PCB) avec des composants discrets. Selon les résultats du test, il a rendement de conversion en puissance de 82% pour une puissance de sortie conçue de 1,25W à une fréquence de travail de 3MHz. Le système d'accord automatique d'impédance proposé a été conçu en deux versions: une version en PCB et une version en circuit intégré (IC). Contrairement aux systèmes d'accord automatique proposés dans la littérature, il n'y a pas besoin de l'unité de microcontrôleur (MCU) ou de l'ordinateur dans la conception proposée. D'ailleurs, sans l'aide de composants magnétiques volumineux, ce système d'auto-réglage est entièrement compatible avec l'équipement IRM. La version en PCB a été conçue pour vérifier le principe du système proposé, et il est également utilisé pour guider à la conception du circuit intégré. La réalisation en PCB occupe une surface de 110cm². Les résultats des tests ont confirmé la performance attendue. Le système d'auto-tuning proposé peut parfaitement annuler l'impédance imaginaire du transducteur, et il peut également compenser l'impédance de la dérive causée par les variations inévitables (variation de température, dispersion technique, etc.). La conception du système d'auto-réglage en circuit intégré a été réalisé avec une technologie CMOS (C35B4C3) fournies par Austrian Micro Systems (AMS). La surface occupée par le circuit intégré est seulement de 0,42mm². Le circuit intégré conçu est capable de fonctionner à une large gamme de fréquence tout en conservant une consommation d'énergie très faible (137 mW). D'après les résultats de la simulation, le rendement de puissance de ce circuit peut être amélioré jusqu'à 20% comparant à celui utilisant le réseau d'accord statiqueHigh intensity focused ultrasound (HIFU) technology is now broadly used for cancer treatment, thanks to its non-invasive property. In a HIFU system, a phased array of ultrasonic transducers is utilized to generate a focused beam of ultrasound (1M~10MHz) into a small area of the cancer target within the body. Most HIFU systems are guided by magnetic resonance imaging (MRI) in nowadays. In this PhD study, a half-bridge class D power amplifier and an automatic impedance tuning system are proposed. Both the class D power amplifier and the auto-tuning system are compatible with MRI system. The proposed power amplifier is implemented by a printed circuit board (PCB) circuit with discrete components. According to the test results, it has a power efficiency of 82% designed for an output power of 3W at 1.25 MHz working frequency. The proposed automatic impedance tuning system has been designed in two versions: a PCB version and an integrated circuit (IC) version. Unlike the typical auto-impedance tuning networks, there is no need of microprogrammed control unit (MCU) or computer in the proposed design. Besides, without using bulky magnetic components, this auto-tuning system is completely compatible with MRI equipment. The PCB version was designed to verify the principle of the proposed automatic impedance tuning system, and it is also used to help the design of the integrated circuit. The PCB realization occupies a surface of 110cm². The test results confirmed the expected performance. The proposed auto-tuning system can perfectly cancel the imaginary impedance of the transducer, and it can also compensate the impedance drifting caused by unavoidable variations (temperature variation, technical dispersion, etc.). The IC design of the auto-tuning system is realized in a CMOS process (C35B4C3) provided by Austrian Micro Systems (AMS). The die area of the integrated circuit is only 0.42mm². This circuit design can provide a wide working frequency range while keeping a very low power consumption (137 mW). According to the simulation results, the power efficiency can be improved can up to 20% by using this auto-tuning circuit compared with that using the static tuning network
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Miri, Lavasani Seyed Hossein. "Design and phase-noise modeling of temperature-compensated high frequency MEMS-CMOS reference oscillators." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41096.
Full textAbstract:
Frequency reference oscillator is a critical component of modern radio transceivers. Currently, most reference oscillators are based on low-frequency quartz crystals that are inherently bulky and incompatible with standard micro-fabrication processes. Moreover, their frequency limitation (<200MHz) requires large up-conversion ratio in multigigahertz frequency synthesizers, which in turn, degrades the phase-noise. Recent advances in MEMS technology have made realization of high-frequency on-chip low phase-noise MEMS oscillators possible.
Although significant research has been directed toward replacing quartz crystal oscillators with integrated micromechanical oscillators, their phase-noise performance is not well modeled. In addition, little attention has been paid to developing electronic frequency tuning techniques to compensate for temperature/process variation and improve the absolute frequency accuracy.
The objective of this dissertation was to realize high-frequency temperature-compensated high-frequency (>100MHz) micromechanical oscillators and study their phase-noise performance. To this end, low-power low-noise CMOS transimpedance amplifiers (TIA) that employ novel gain and bandwidth enhancement techniques are interfaced with high frequency (>100MHz) micromechanical resonators. The oscillation frequency is varied by a tuning network that uses frequency tuning enhancement techniques to increase the tuning range with minimal effect on the phase-noise performance. Taking advantage of extended frequency tuning range, and on-chip temperature-compensation circuitry is embedded with the sustaining circuitry to electronically temperature-compensate the oscillator. Finally, detailed study of the phase-noise in micromechanical oscillators is performed and analytical phase-noise models are derived.
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Candito, Antonio. "Modelling, simulation and characterization of epithelial cell culture biochip." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2015. http://amslaurea.unibo.it/8483/.
Full textAbstract:
A microfluidic Organ-on-Chip has been developed for monitoring the epithelial cells monolayer.
Equivalent circuit Model was used to determine the electrical properties from the impedance spectra of the epithelial cells monolayer.
Black platinum on platinum electrodes was electrochemically deposited onto the surface of electrodes to reduce the influence of the electrical double layer on the impedance measurements.
Measurements of impedance with an Impedance Analyzer were done to validate the equivalent circuit model and the decrease of the double layer effect.
A Lock-in Amplifier was designed to measure the impedance.
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Guimarães, Murilo. "Circuito equivalente e extração de parametros em um amplificador optico a semicondutor." [s.n.], 2007. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259024.
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Orientadores: Evandro Conforti, Cristiano de Melo GalleDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e Computação
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Resumo: O advento das comunicações por fibras ópticas esteve intrinsecamente ligado aos lasers a diodo semicondutor. Posteriormente, principalmente na área de redes metropolitanas, iniciaram-se as aplicações envolvendo o amplificador óptico a semicondutor (SOA, em inglês). O SOA é muito similar ao laser a diodo semicondutor, pois também amplifica a luz incidente através da emissão estimulada, a qual advém da emissão pelos portadores elétricos da região ativa. Estes são bombeados na região ativa através da corrente elétrica injetada na porta elétrica do SOA. A similaridade não é completa devido ao fato do amplificador não possuir realimentação de luz através de uma cavidade óptica ressonante, uma vez que sua região ativa é terminada por faces anti-refletivas. Dessa forma, a luz é amplificada apenas em uma passagem pela região ativa do SOA, sendo também denominado neste caso, SOA-TW, ou de onda caminhante. Desta forma, fazendo-se uma analogia com circuitos, a diferença SOAlaser é semelhante à diferença amplificador-oscilador eletrônico. Devido a esta semelhança, o estudo desenvolvido no presente trabalho, sobre o comportamento da impedância do amplificador óptico a semicondutor, foi baseado em um modelo equivalente de circuito de microondas desenvolvido para o laser a diodo semicondutor. O comportamento da impedância do SOA, composto por seu encapsulamento e chip, é de extrema importância para o controle e aprimoramento de chaveamento eletro-óptico do SOA em redes de última geração. Visando ao aprofundamento deste estudo, análises teóricas a respeito do laser a diodo semicondutor e do amplificador óptico a semicondutor são apresentados. Em seguida, são apresentados os resultados experimentais, com a extração do circuito equivalente do SOA e sua montagem eletro-óptica, com a comparação entre as respostas experimentais e teóricas. Nas considerações finais discutem-se as sugestões para trabalhos futuros sobre o comportamento da impedância eletro-óptica do SOA
Abstract: The advent of communications using optical fiber was always connected, intrinsically, with the semiconductor diode laser. Later, in metropolitan optical networks, the semiconductor optical amplifier (SOA) was introduced to amplify up to eight channels in a WDM (wavelength division multiplex) system. The semiconductor optical amplifier and the semiconductor laser diode are similar since both of them amplify the input light through stimulated emission, which result from electric carriers that are pumped in the active layer through the injection current in the electrical gate in these devices. The similarity is not complete since the SOA has anti-reflection coatings at the end emission faces. Therefore, the light is amplified by the active layer only in one pass; in this case the SOA is called TW SOA (traveling wave SOA). Due to the similarity between the devices, the present study of the SOA impedance behavior was based in an equivalent model from researches about microwave circuits used in the literature to analyze semiconductor diode lasers. The SOA impedance behavior is given by the chip itself and its package; it is important to control and to improve the electrical-optical switch using the SOA for next generation networks. Looking for a deep knowledge about this research, theoretical analyses of the semiconductor diode lasers and SOA was presented in this research. After it, the experimental results are showed with the extraction of the SOA equivalent circuit and the electrical-optical assembly, and the comparison between the experimental and theoretical results was done. At the end of this work, some suggestions for future works are proposed regarding the behavior of the SOA electrical-optical impedance
Mestrado
Telecomunicações e Telemática
Mestre em Engenharia Elétrica
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Fröhlich, Lubomír. "Aktivní kmitočtové filtry pro vyšší frekvence." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2014. http://www.nusl.cz/ntk/nusl-233616.
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This thesis deals with the synthesis and optimization of frequency analogue filters with modern active elements usable for higher frequencies. The thesis is divided into three parts, the first part deals with the problematic concerning Leap-Frog combined ARC structure. Due to a difficult design, this method is not described in a detail and used in practice, although it shows e.g. low sensitivity. Firstly, a complete analysis of individual filters was made (for and T endings) and consequently these findings were used during implementation of this method to NAF program. Finally, samples of real filters were realized (for verification of functioning and correct design). Another very interesting topic concerning filters is usage of coupled band-pass for small bandwidth, where it is necessary to solve the problems concerning ratio of building elements values, but also price, quality, size of coils, sensitivity, Q factors, coefficients etc. That is why in practice a coil is very often substituted with other equivalent lossy and lossless blocks which create ARC filters structure. The design and the possibility of usage of lossy grounded elements were described here (such as synthetic inductors, frequency dependent negative resistor). Some parts of the design are individual computer sensitivity analysis, setting of usage and quality comparison of individual lossy grounded blocks. Besides, a program for these elements was created, it is useful for a quick design and depiction of transfer characteristics. The third part deals with the usage of tuning universal filters consisting three or more operational amplifiers, which secures its universality and possibility to create different kinds of transfer characteristic. In practice, Akerberg - Mossberg and Kerwin - Huelsman - Newcomb are the most used types of filters. These were also compared with less common universal filters. In the end, the possibility of digital tuning of universal filter with the help of digital potentiometers for filters of 10th order and frequency around 1 MHz was shown.
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Weisz, Mario. "Electrothermal device-to-circuit interactions for half THz SiGe∶C HBT technologies." Thesis, Bordeaux 1, 2013. http://www.theses.fr/2013BOR14909/document.
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Ce travail concerne les transistors bipolaires à hétérogène TBH SiGe. En particulier, l'auto-échauffement des transistors unitaires et le couplage thermique avec leurs plus proches voisins périphériques sont caractérisés et modélisés. La rétroaction électrothermique intra- et inter-transistor est largement étudiée. En outre, l’impact des effets thermiques sur la performance de deux circuits analogiques est évalué. L'effet d'autoéchauffement est évalué par des mesures à basse fréquence et des mesures impulsionnelles DC et AC. L'auto-échauffement est diminué de manière significative en utilisant des petites largeurs d'impulsion. Ainsi la dépendance fréquentielle de l’autoéchauffementa été étudiée en utilisant les paramètres H et Y. De nouvelles structures de test ont été fabriqués pour mesurer l'effet de couplage. Les facteurs de couplage thermique ont été extraits à partir de mesures ainsi que par simulations thermiques 3D. Les résultats montrent que le couplage des dispositifs intra est très prononcé. Un nouvel élément du modèle de résistance thermique récursive ainsi que le modèle de couplage thermique a été inclus dans un simulateur de circuit commercial. Une simulation transitoire entièrement couplée d'un oscillateur en anneau de 218 transistors a été effectuée. Ainsi, un retard de porte record de 1.65ps est démontré. À la connaissance des auteurs, c'est le résultat le plus rapide pour une technologie bipolaire. Le rendement thermique d'un amplificateur de puissance à 60GHz réalisé avec un réseau multi-transistor ou avec un transistor à plusieurs doigts est évalué. La performance électrique du transistor multidoigt est dégradée en raison de l'effet de couplage thermique important entre les doigts de l'émetteur. Un bon accord est constaté entre les mesures et les simulations des circuits en utilisant des modèles de transistors avec le réseau de couplage thermique. Enfin, les perspectives sur l'utilisation des résultats sont donnéesThe power generate by modern silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) can produce large thermal gradients across the silicon substrate. The device opering temperature modifies model parameters and can significantly affect circuit operation. This work characterizes and models self-heating and thermal coupling in SiGe HBTs. The self-heating effect is evaluated with low frequency and pulsed measurements. A novel pulse measurement system is presented that allows isothermal DC and RF measurements with 100ns pulses. Electrothermal intra- and inter-device feedback is extensively studied and the impact on the performance of two analog circuits is evaluated. Novel test structures are designed and fabricated to measure thermal coupling between single transistors (inter-device) as well as between the emitter stripes of a multi-finger transistor (intra-device). Thermal coupling factors are extracted from measurements and from 3D thermal simulations. Thermally coupled simulations of a ring oscillator (RO) with 218 transistors and of a 60GHz power amplifier (PA) are carried out. Current mode logic (CML) ROs are designed and measured. Layout optimizations lead to record gate delay of 1.65ps. The thermal performance of a 60GHz power amplifier is compared when realized with a multi-transistor array (MTA) and with a multi-finger trasistor (MFT). Finally, perspectives of this work within a CAD based circuit design environment are discussed
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Lin, Jieh, and 林杰. "A Tunable Impedance Wideband Low Noise Amplifier." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/07796748563386267332.
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碩士國立臺灣大學
工程科學及海洋工程學研究所
100
Low noise amplifier ( LNA ) is a critical component for ultrasound medical equipment, since it amplifies tiny echo signals reflected from tissues without adding much noise. Wideband input impedance match with the loading of ultrasound transducers is therefore important for LNAs to provide constant gain over a wide frequency range. State-of-the-art LNA for general applications is designed such that the impedance is matched with a specific impedance. To extend the capability of LNA to different transducers, which would lead to significantly lower cost, a wideband tunable input impedance of the amplifier is designed by varying bias current of the transistor, which is used to provide the system gain. Two prototypes amplifier are constructed to validate the proposed architecture with discrete HBT transistors and 0.35 μm CMOS process, respectively. And it has shown the small gain variation with a wide tuning range of input impedance from 30 to 90 Ohm. The measured noise figure is 7.33 dB with an average gain of 13.5 dB over the range of input impedance.
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HE, JIAN-XUN, and 何建勳. "Design of broadband impedance matching network and amplifier." Thesis, 1987. http://ndltd.ncl.edu.tw/handle/72254748977017305159.
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Alibakhshikenari, M., B. S. Virdee, C. H. See, Raed A. Abd-Alhameed, F. Falcone, and E. Limiti. "Automated reconfigurable antenna impedance for optimum power transfer." 2019. http://hdl.handle.net/10454/18104.
Full textAbstract:
YesThis paper presents an approach to implement an automatically tuning antenna for optimising power transfer suitable for software defined radio (SDR). Automatic tuning is accomplished using a closed loop impedance tuning network comprising of an impedance sensor and control unit. The sensor provides the control unit with data on the transmit or receive power, and the algorithm is used to impedance of a T-network of LC components to optimize the antenna impedance to maximise power transmission or reception. The effectiveness of the proposed tuning algorithm in relation to impedance matching and convergence on the optimum matching network goal is shown to be superior compared with the conventional tuning algorithm.
This work is partially supported by innovation programme under grant agreement H2020-MSCA-ITN-2016 SECRET-722424 and the financial support from the UK Engineering and Physical Sciences Research Council (EPSRC) under grant EP/E022936/1
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Hong, Chung-Hung, and 洪宗宏. "A 3-10GHz Broadband Balanced Power Amplifier with Output Impedance Transformation." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/93111819751052545515.
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碩士國立臺灣大學
電子工程學研究所
102
This thesis investigates the broadband balanced power amplifier operating from 3GHz to 10GHz. Both the design method and procedure of this balanced power amplifier are presented in detail. TSMC 0.18um CMOS is selected as the active process to design unit power amplifiers, and low temperature co-fired ceramics (LTCC) is used as the passive process to design two types of quadrature power splitters (QPS). The broadband power amplifier was achieved by using flip-chip interconnects to combine T18 chips with LTCC substrate. The first part of this thesis shows the design of the unit power amplifier using CMOS 0.18um process. By using an inductance and parasitic capacitances (Cds) to produce resonance and using unit matching network to the 25ohm load impedance of output port, the output networks can be simplified and reduce unnecessary loss if designed for load. S21 can be regulated much more flat by adding the impedance transform network at input part. Negative feedback network is also added to improve return loss. The second part of this thesis presents two kinds quadrature power splitters, one for output load of 50ohm, and the other one for 25ohm. The quadrature power splitter with output load of 25ohm acts as power combiner for unit amplifiers, and transform to system’s output impedance of 50ohm. Finally, this thesis combines unit power amplifier with broadband quadrature power splitter/combiner to form a broadband balanced power amplifier which can improve return loss greatly. The measurement results of the unit amplifier show that at 3-10GHz, it achieves gain of 11.6±2.2dB, PAE at OP1dB 22%-35%, and OP1dB of 14.8-19.3dBm.
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Chou, Chien-I., and 周千譯. "ESD Protection Design with Impedance Isolation Technique for CMOS RF Low Noise Amplifier." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/83056830904121068689.
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碩士國立交通大學
電子工程系
91
A CMOS RF LNA with high ESD sustain ability is presented in this thesis. A novel LC tank ESD protected LNA based on impedance isolation is proposed. The whole ESD design includes power rail ESD clamp circuit between VDD to VSS. In the second part, a detailed and comprehensive noise analysis of the LNA without and with input ESD protection has been investigated, including modified power gain by ESD devices, input matching property, noise figure and the portion of the noise power generated by ESD devices. We provide some noise equation and simulation results in this section. In the third part, three types of 5.2GHz CMOS RF LNA are designed and implement in 0.25-μm CMOS process, including pure LNA without any ESD protection, LNA with novel LC tank ESD protection and LNA with conventional diode ESD protection. We also develop some on-chip inductor modeling. The experimental results show that the center frequencies of ESD protected LNA are shifting. After adding proper output matching network, the ESD protected LNA will have the same center frequency. Re-simulation results based on measured S-parameter show that LC tank protected LNA has better RF performance than diode protected one. And measured noise figure also shows that LC tank protected LNA has lower noise level than diode protected one. Thus the ESD protection with LC tank is more suitable for RF application of higher operating frequency in the future. The LC tank ESD protected LNA can pass a HBM ESD level of 4.9kV and a MM ESD level of 275V.
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Marijanovic, Srdjan. "Optimized multi-stage amplifier compensation method for wide load variations." Thesis, 2012. http://hdl.handle.net/2152/ETD-UT-2012-08-6362.
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Due to variations in process, voltage, and temperature (PVT), amplifiers are almost solely designed for use in a negative feedback loop. The feedback loop mitigates the effect of PVT, however maintaining stability becomes the main design challenge. Further, multi-stage amplifiers with high open-loop gain are used for powering headphone speakers in modern portable electronics. As there are many different headphone manufacturers and compatibility specifications, headphone amplifiers are subjected to a wide variation in capacitive and resistive loads, which further complicates the stability upkeep. This thesis explores a two-stage (Common-Gate Feedback) and three-stage (Impedance Adapting Compensation) amplifier topology with respect to performance under wide load variations. For both compensation topologies, an analytical analysis is presented, followed by a design proposal for a headphone amplifier application. Finally, the trade-offs for maintaining stability under varying loads are discussed.text
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Lu, Tzon-Tzer, and 呂宗澤. "Design and Implementation of Trans-impedance Amplifier Circuit for 10 GBASE Optical Communication System." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/18187588091496389638.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
99
In this thesis, the design of trans-impedance amplifier (TIA) used in optical receiver system is discussed. With the rapid development of communication industry, 10 GBASE Ethernet has become popular in the local area network media interface. With the low noise and high speed characteristics, the high-speed receiver front-end was often realized by III-V or SiGe BJT in the past. However, benefiting from the rapid development of CMOS process, CMOS has comparable high speed characteristics to other materials. In addition, low power consumption and easy integration with digital circuits make the CMOS process as the best choice to pursue the lowest cost. In the front-end of optical receiver, the parasitic capacitance appearing at the TIA input has significant impact on the bandwidth. Hence, low input impedance architectures, such as Common-Gate (CG) and Regulated Cascode (RGC), are widely adopted in TIA designs, and become popular candidates of design. This thesis presents two RGC-TIAs for 10 GBASE Ethernet. Both chips are implemented in 1P6M CMOS technology. In the first design, the inductive peaking technique is used. The gain of the TIA is 56.5 dBΩ with the bandwidth of 4.7 GHz. It consumes 27 mW from a 1.8-V power supply with a core area of 0.54 x 0.52 mm2.For the second work, a low voltage low power TIA for 3.125 Gb/s is realized. The power supply voltage is only 1.3-V. According to the experimental results, the measured gain is 61.4 dBΩ with the bandwidth of 2.9 GHz. Since the supply voltage is 72 % of the nominal value, the power consumption of the whole SOC system can be reduced 28 % off. The power consumption is 4.9 mW and the chip occupies a core area of 0.18 x 0.18 mm2. All chips are verified from the post-layout simulation and measurement.
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Hsieh, Kai-An, and 謝凱安. "Dual-Frequency Impedance Transformation Technique Incorporated in a 10 and 24 GHz Dual-Band Amplifier." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/00170418574930656651.
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碩士國立臺灣大學
電信工程學研究所
99
This thesis presents a complete theory of a dual-frequency impedance transformer based on transmission lines. The theoretical analysis is insightfully described, and a limitation from the design equations is investigated. Subsequently, a design procedure is proposed to resolve this situation. To substantiate the theory, a dual-band amplifier operating at 10 and 24 GHz is fabricated by standard 0.13-μm 1P8M CMOS technology. The amplifier involves synthetic quasi-TEM transmission lines to build the dual-frequency matching circuits. The comparisons between simulations and on-wafer measurements are reported to establish the feasibility and flexibility of the presented technique in microwave applications.
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Yang, Ren-Ruei, and 楊仁瑞. "Optimum Design of Ultra-Wideband Low Noise Amplifier with Active Impedance Matching Using Design of Experiment." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/20264990555363068899.
Full textAbstract:
碩士逢甲大學
電子工程所
95
A novel ultra wideband low noise amplifier (UWB LNA) with active input matching and excellent noise figure and gain operating at frequency range of 3.1 GHz to 10.6 GHz is designed using a TSMC 0.18 μm RF CMOS process. The purpose of this paper will develop a Response Surface Model (RSM) to design an UWB LNA with input impedance match, low power consumption, low noise figure, and high flat gain. With the aid of ADS (Advanced Design System) circuit simulation software of Agilent, Design of Experiment (DOE), the Genetic Algorithm (GA) and Weighted Composite Response Surface Model (WCR), this RSM model can be used to make a decision in the tradeoff between the noise figure and flatness of gain of the UWB LNA for the Ultra Wideband communication system applications.
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Chen, Cheng-Heng, and 陳建亨. "Ku-Band Balanced Power Amplifier Using Impedance-Transforming Branch-Line Coupler with DC-Blocking Coupled-Lines." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/06330334961238886934.
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碩士國立交通大學
電信工程研究所
84
Abstract In this project, we demonstrate a modified Ku-band microstrip line impedance -transforming branch-line coupler used for a narrowband balanced power amplifier. In this new coupler design, the original four branches of the coupler are replaced by coupled-lines, and the coupled-lines can be chosen carefully to obtain the necessary low impedance, and use the inherent open characteristic to get the DC-isolations between the four ports. This design not only suppr進而esses the high order-mode excitations, which result from the discontinui supreesses T- junctions at high frequencies, it can also make the simulation mties of and the relative size of the circuit reduced. In additions, impedance- tdesign, the overall amplifier circuit area are smaller, high density, and more suitable for MMIC design. In additions, in this project, we program a design procedure for the small-signal model extraction of chip-form MESFET and HEMT. An equivalent large-signal model using the small-signal parameters is derived, and included in the power amplifier design. In this project, the TRL de-embedding method is also discussed for the accuracy measurement of small-signal S-parameters.
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Fu, Xin. "Dual-band Power Amplifier for Wireless Communication Base Stations." Thesis, 2012. http://hdl.handle.net/10012/6922.
Full textAbstract:
In wireless communication systems, multiple standards have been implemented to meet the past and present demands of different applications. This proliferation of wireless standards, operating over multiple frequency bands, has increased the demand for radio frequency (RF) components, and consequently power amplifiers (PA) to operate over multiple frequency bands.
In this research work, a systematic approach for the synthesis of a novel dual-band matching network is proposed and applied for effective design of PA capable of maintaining high power efficiency at two arbitrary widely spaced frequencies. The proposed dual-band matching network incorporates two different stages. The first one aims at transforming the targeted two complex impedances, at the two operating frequencies, to a real one. The second stage is a dual-band filter that ensures the matching of the former real impedance to the termination impedance to 50 Ohm. Furthermore, an additional transmission line is incorporated between the two previously mentioned stages to adjust the impedances at the second and third harmonics without altering the impedances seen at the fundamental frequencies. Although simple, the harmonic termination control is very effective in enhancing the efficiency of RF transistors, especially when exploiting the Class J design space.
The proposed dual-band matching network synthesis methodology was applied to design a dual-band power amplifier using a packaged 45 W gallium nitride (GaN) transistor. The power amplifier prototype maintained a peak power efficiency of about 68% at the two operating frequencies, namely 800 MHz and 1.9 GHz. In addition, a Volterra based digital predistortion technique has been successfully applied to linearize the PA response around the two operating frequencies. In fact, when driven with multi-carrier wideband code division multiple access (WCDMA) and long term evolution (LTE) signals, the linearized amplifier maintained an adjacent channel power ratio (ACPR) of about 50 dBc and 46 dBc, respectively.
43
Chen, Hsin-Han, and 陳信翰. "An Inverter-based Capacitive Trans-impedance Amplifier Readout with Offset Cancellation and Temporal Noise Reduction for IR Focal Plane Array." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/21760135484565533663.
Full textAbstract:
碩士國立清華大學
電機工程學系
102
This Thesis presents a readout integrated circuit (ROIC) with inverter-based capacitive transimpedance amplifier (CTIA), in-pixel correlated double sampling (CDS) mechanism, and pseudo-multiple sampling technique for infrared focal plane array (IRFPA). The proposed inverter-based CTIA with a coupling capacitor, executing auto-zeroing technique to cancel out the varied offset voltage from process variation, is used to substitute differential amplifier in conventional CTIA. The tunable detector bias is applied from a global external bias before exposure. This scheme not only retains stable detector bias voltage and signal injection efficiency, but also reduces the pixel area as well. CDS is a useful signal processing method to suppress the low frequency noise and fixed pattern noise (FPN). Compared to the conventional CDS, this in-pixel CDS is achieved by only one capacitor and a single switch connected to external reference voltage. Pseudo-multiple sampling technique is adopted to reduce the temporal noise of readout circuit. The noise reduction performance is comparable to the conventional multiple sampling operation without need of longer readout time proportional to the number of samples A prototype 55×65 pixel imager employed these schemes has been designed and fabricated in 0.18μm CMOS technology. The functions and performance of the proposed readout circuit have been verified by experimental measurements at 3.3V supply voltage. It achieves a 12μm×12μm pixel size, a frame rate of 72 fps, a FPN of 0.45%, and a temporal readout noise of 1.09mVrms (with 16 times of pseudo-multiple sampling), respectively.
44
Barros, Diogo Rafael Bento. "Video-bandwidth impact and compensation in wideband high-efficiency power amplifiers." Doctoral thesis, 2021. http://hdl.handle.net/10773/33534.
Full textAbstract:
The aim of this work is to determine, quantify and model the performance
degradation of wideband power amplifiers when subject to concurrent multiband
excitation, with a particular focus on the average efficiency variation.
The origins of this degradation are traced to two main transistor properties:
the output baseband current generation by the nonlinear transconductance,
and the input baseband current generation by the nonlinear gate-source
capacitance variation. Each mechanism is analised separately, first by providing
a qualitative and intuitive explanation of the processes that lead to
the observed efficiency degradation, and then by deriving models that allow
the prediction of the average efficiency dependence with the input signal
bandwidth. The resulting knowledge was used to improve matching network
design, in order to optimize baseband impedance terminations and
prevent the efficiency degradation. The derived models were experimentally
validated with several PA prototypes implemented with Gallium Nitride
HEMT devices, using both conventional and optimized baseband impedance
matching networks, achieving over 400MHz instantaneous bandwidth with
uncompromised efficiency. The consolidation of the wideband degradation
mechanisms described in this work are an important step for modelling and
design of wideband, high-efficiency power amplifiers in current and future
concurrent multi-band communication systems.O objetivo deste trabalho é determinar, quantificar e modelar a degradação do desempenho de amplificadores de banda-larga quando submetidos a excitação multi-banda concorrente, com particular ênfase na variação do rendimento energético. As origens desta degradação são devidas a duas das principais propriedades do transístor: a geração de corrente em banda-base na saída pela variação não-linear da transcondutância, e a geração de corrente de banda-base na entrada pela variação não-linear da capacidade interna porta-fonte. Cada um destes mecanismos é analisado isoladamente, primeiro por uma explicação qualitativa e intuitiva dos processos que levam à degradação de eficiência observada e, em seguida, através da derivação de modelos que permitem a previsão da degradação do rendimento médio em função da largura de banda do sinal de entrada. O conhecimento resultante foi utilizado para melhorar o desenvolvimento de malhas de adaptação, por forma a otimizar as terminações de impedância em banda-base e prevenir a degradação do rendimento. Os modelos desenvolvidos foram validados experimentalmente em vários amplificadores de potência implementados com transístores de tecnologia GaN HEMT, utilizando malhas de adaptação convencionais e otimizadas, onde se obteve 400MHz de largura de banda instantânea sem degradação do rendimento. A consolidação dos mecanismos de degradação descritos neste trabalho são um importante passo para a modelação e projeto de amplificadores de elevado rendimento e largura-debanda para os sistemas de comunicação multi-banda concorrente convencionais e do futuro.
Programa Doutoral em Engenharia Eletrotécnica
45
Kim, Ju Sung. "Broadband RF Front-End Design for Multi-Standard Receiver with High-Linearity and Low-Noise Techniques." Thesis, 2011. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10512.
Full textAbstract:
Future wireless communication devices must support multiple standards and features on a single-chip. The trend towards software-defined radio requires flexible and efficient RF building blocks which justifies the adoption of broadband receiver front-ends in modern and future communication systems. The broadband receiver front-end significantly reduces cost, area, pins, and power, and can process several signal channels simultaneously. This research is mainly focused on the analysis and realization of the broadband receiver architecture and its various building blocks (LNA, Active Balun-LNA, Mixer, and trans-impedance amplifier) for multi-standard applications.
In the design of the mobile DTV tuner, a direct-conversion receiver architecture is adopted achieving low power, low cost, and high dynamic-range for DVB-H standard. The tuner integrates a single-ended RF variable gain amplifier (RFVGA), a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. The proposed RFVGA achieves high dynamic-range and gain-insensitive input impedance matching performance. The current-mode passive mixer achieves high gain, low noise, and high linearity with low power supplies.
A wideband common-gate LNA is presented that overcomes the fundamental trade-off between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure over the previously reported feedback amplifiers in common-gate configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback.
For the wideband Inductorless Balun-LNA, active single-to-differential architecture has been proposed without using any passive inductor on-chip which occupies a lot of silicon area. The proposed Balun-LNA features lower power, wider bandwidth, and better gain and phase balance than previously reported architectures of the same kind.
A surface acoustic wave (SAW)-less direct conversion receiver targeted for multistandard applications is proposed and fabricated with TSMC 0.13?m complementary metal-oxide-semiconductor (CMOS) technology. The target is to design a wideband SAW-less direct coversion receiver with a single low noise transconductor and current-mode passive mixer with trans-impedance amplifier utilizing feed-forward compensation. The innovations in the circuit and architecture improves the receiver dynamic range enabling highly linear direct-conversion CMOS front-end for a multi-standard receiver.
46
Κυρίτσης, Δημήτριος. "Σχεδιασμός υψίσυχνου αναλογικού ενισχυτικού κυκλώματος χαμηλού θορύβου." Thesis, 2014. http://hdl.handle.net/10889/8178.
Full textAbstract:
Αντικείμενο αυτής της διπλωματικής εργασίας είναι ο σχεδιασμός ενός αναλογικού ενισχυτικού κυκλώματος χαμηλού θορύβου το οποίο θα λειτουργεί σε υψηλές συχνότητες.
Ο ενισχυτής αυτός προορίζεται για χρήση στο analog front end κυκλωμάτων τα οποία θα υποστηρίζουν πρωτόκολλα μεταφοράς πληροφορίας σε δίκτυα ισχύος (Power Line Communication, Internet of Things).
Για τον σχεδιασμό γίνεται η χρήση της κλασικής θεωρίας μικροηλεκτρονικών κυκλωμάτων αλλά και της μικροκυματικής θεωρίας. Παρουσιάζονται οι διάφορες τοπολογίες των τρανζίστορ BJT, γίνεται μία παρουσίαση των βασικότερων πηγών θορύβου και αναφέρονται βασικές αρχές των S παραμέτρων και της προσαρμογής εμπέδησης.
Ο ενισχυτής κοινού εκπομπού απορρίφθηκε καθώς αποδείχθηκε αμφίπλευρος οπότε καταλήξαμε στην επιλογή της cascode τοπολογίας η οποία προσδίδει ευστάθεια, απομόνωση και καλή γραμμικότητα. Η απόλυτη προδιαγραφή που τέθηκε για το θόρυβο δεν επιτεύχθηκε και οπότε αναφέραμε τους λόγους που οδήγησαν σε αυτό και προτείναμε πιθανές λύσεις μέσω άλλων υλοποιήσεων.The subject of this diploma thesis is the design of a low noise high-frequency analogue amplifier. The amplifier is designed to be used in the analog front end of circuits designed to support protocols that control the transmission of information over power lines (internet of things). To achieve this goal we make use of classic microelectronics theory but also microwave theory. The topologies of the BJT transistors are presented, we also go through the basic noise production reasons and we also make a short reference on the s-parameters and on the basic principles of impedance matching. The common emitter amplifier proved to be bilateral, so the cascode amplifier, which provides stability, isolation and linearity, was preferred. The noise specification was not achieved so we present the basic reasons of this, as well as we propose possible solutions.
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Chen, Tzeshin, and 陳澤昕. "The Research of Capacitive Trans-Impedance Amplifier and Direct Injection Readout Integrated Circuit Design for the Photo Focal Plane Array Detectors and Wireless Transmission Applications." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/08017196662599260036.
Full textAbstract:
碩士國立暨南國際大學
電機工程學系
100
This thesis proposes a new dual-band readout circuit with variable integration time and builds a wireless image sensor network. The hybrid type pixel architecture of DI (Direct Injection) and CTIA (Capacitive Transimpedance Amplifier) is adopted in the readout circuit. The integration time and readout mode are controlled by the external pins. Direction Injection with the features of higher impedance and low-power consumption is suitable for high sensing photocurrent. Capacitive transimpedance amplifier has the characteristics of high linearity and noise immunity, which is applied to low sensing photocurrent. The transportation protocol of the wireless image sensor network is using Zigbee, that has the superiorities of low-power and ad-hoc network. The system can display sensing image in real-time, and it supports remote control integration time and image correction. The readout chip is achieved by using TSMC 0.35um 2P4M COMS 5V process. The layout area of unit pixel circuit is 40um x 40um. The input photocurrent range of CTIA is 0.11pA ~ 10nA and DI is 3.3pA ~ 153nA. The chip can operate at 2 kHz ~ 4 MHz. The output swing is 2.08V, the dynamic range is 46dB, the power consumption is 9.3 mW and the max pixel rate is 12 MHz. The wireless image sensor network employs Arduino Duemilanove as the sensor node processor. The antenna is adopted XBee and the man-machine interface of the receiver is built by LabVIEW. The max transmission rate is 115200 bps. The grayscale images have a maximum color depth of 8 bits.
48
Кабиров, Д. Д., and D. D. Kabirov. "Увеличение полосы частот электрически малой антенны с использованием конвертора отрицательного сопротивления на основе операционного усилителя : магистерская диссертация." Master's thesis, 2017. http://hdl.handle.net/10995/54215.
Full textAbstract:
В работе представлены результатыисследования метода, который позволяет увеличить полосу частот электрически малой антенны с помощью “нефостеровской цепи”на основе операционного усилителя.
Были получены графики, которые позволяют оценить входное реактивное сопротивление и полосу частот электрически малой антенны с представленным методом расширения полосы частот.The paper presents the results of a study of the method, which makes it possible to increase the frequency band of an electrically small antenna by means of a "Non-foster circuit"with operational amplifier. The graphs were obtain, which allow estimating the input reactance and the bandwidth of an electrically small antenna with the method of bandwidth extension represented.
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Gonçalves, Cristiano Ferreira. "Load insensitive radio frequency power amplifiers." Doctoral thesis, 2021. http://hdl.handle.net/10773/33222.
Full textAbstract:
Solid state power amplifiers (SSPAs) evolved significantly over the last few
decades, mainly, due to the use of new transistor technologies, such as
gallium nitride (GaN) high-electron-mobility transistors (HEMTs), very advanced
computer-aided design (CAD) software, and very effective digital
pre-distortion (DPD) algorithms. This led to a considerable performance
improvement, in terms of energy efficiency, output power, and linearity. To
achieve this performance, power amplifier (PA) designers normally push the
used transistors very close to their physical safe operating limits, and consider
them to operate for a fixed output load. However, the designed PAs are
used for many different industrial and/or telecommunication applications,
and, in some cases, such as, for example, microwave cooking or massive
multiple-input multiple-output (MIMO) fifth generation (5G) base stations
(BSs), the output load of these amplifiers can change. Under this nonoptimal
scenario, the used transistors will operate for non-nominal loads,
and the PAs performance can be severely degraded. Moreover, in highly
optimized designs, where the transistors are operated close to their safe
limits, their reliability can be reduced or, in extreme cases, they can even be
permanently damaged. Therefore, load insensitive PA architectures, and/or
techniques that aim at reducing the load variation seen by the PA, are necessary
to improve the performance under load varying scenarios. This thesis
presents various strategies to improve load insensitiveness of PAs. The presented
techniques are based on tunable matching networks (TMNs) and on
the amplifiers’ drain supply voltage (VDS) variation. The developed TMNs
successfully reduced the load variation seen by the PA, and its performance
was greatly improved, for non-optimal loading, by also using the derived load
dependent VDS variation. These different approaches were tested and validated
on single-ended PAs and then, based on their advantages and disadvantages,
the most promising technique – the supply voltage modulation –
was selected for the design of a Doherty power amplifier (DPA), which is of
paramount importance for telecommunication applications. Moreover, since
in some applications the output load variation can be unpredictable, we also
developed a complete quasi-load insensitive (QLI) PA system that includes
an impedance tracking circuit and an automatic real-time compensation of
the amplifier performance.Os amplificadores de potência de estado sólido (SSPAs) evoluíram significativamente nas últimas décadas, principalmente devido à utilização de novas tecnologias de transístores, como os transístores de alta mobilidade (HEMTs) de nitreto de gálio (GaN), de ferramentas muito avançadas de projeto assistido por computador (CAD) e de algoritmos de pré-distorção digital (DPD) muito evoluídos. Isto levou a uma melhoria de desempenho considerável, em termos de eficiência energética, potência de saída e linearidade. Normalmente, para obter estes níveis de desempenho, os engenheiros projetam os amplificadores permitindo que os transístores utilizados operem muito perto do seu limite físico de funcionamento seguro e considerando que vão operar para uma carga fixa. No entanto, os amplificadores projetados são utilizados em diversas aplicações industriais e/ou telecomunicações e, em alguns casos, como por exemplo fornos micro-ondas ou estações base 5G, a sua carga de saída pode variar devido a várias causas, que podem ser previsíveis ou imprevisíveis. Neste cenário não ideal, os transístores utilizados operam para cargas não ótimas e o desempenho dos amplificadores pode ser muito degradado. Além disso, em projetos muito otimizados, onde os transístores são operados perto do seu limite de funcionamento seguro, a sua durabilidade pode ser reduzida ou, em casos extremos, podem até ser permanentemente danificados. Portanto, para melhorar o desempenho dos amplificadores em cenários de carga variável, são necessárias novas arquiteturas e/ou técnicas que visam reduzir a variação da carga vista pelos transístores utilizados. Esta tese apresenta várias estratégias para melhorar a insensibilidade dos amplificadores em relação à variação de carga. As técnicas apresentadas são baseadas em malhas de adaptação dinâmicas (TMNs) e na variação da tensão de alimentação dos amplificadores. As malhas de adaptação desenvolvidas permitiram reduzir a variação de carga vista pelo amplificador e a variação da sua tensão de alimentação permitiu melhorar o desempenho para operação com cargas não ótimas. Estas abordagens foram testadas e validadas em amplificadores baseados num só transístor, e, posteriormente, com base nas suas vantagens e desvantagens, a técnica mais promissora – a modulação da tensão de alimentação – foi selecionada para o projeto de um amplificador Doherty, que é imprescindível para telecomunicações. Além disso, como em algumas aplicações a variação da carga de saída pode ser imprevisível, também desenvolvemos um sistema completo que inclui um circuito de medida de impedância e compensação do desempenho do amplificador em tempo real.
Programa Doutoral em Engenharia Eletrotécnica
50
Ramadan, Ashraf [Verfasser]. "Active antennas with high input impedance low noise and highly linear amplifiers / by Ashraf Ramadan." 2005. http://d-nb.info/975739174/34.
Full text