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Mastro, Michael A., Neeraj Nepal, Fritz Kub, Jennifer K. Hite, Jihyun Kim, and Charles R. Eddy. "Nickel Foam as a Substrate for III-nitride Nanowire Growth." MRS Proceedings 1538 (2013): 311–16. http://dx.doi.org/10.1557/opl.2013.504.
ABSTRACTThis article presents the use of flexible metal foam substrates for the growth of III-nitride nanowire light emitters to tackle the inherent limitations of thin-film light emitting diodes as well as fabrication and application issues of traditional substrates. A dense packing of gallium nitride nanowires were grown on a nickel foam substrate. The nanowires grew predominantly along the a-plane direction, normal to the local surface of the nickel foam. Strong luminescence was observed from undoped GaN and InGaN quantum well light emitting diode nanowires.
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Leshchenko E. D. and Dubrovskii V. G. "Modeling the growth of tapered nanowires on reflecting substrates." Technical Physics Letters 48, no. 12 (2022): 11. http://dx.doi.org/10.21883/tpl.2022.12.54937.19358.
The formation of tapered self-catalyzed nanowires grown on reflecting substrates is studied theoretically. Within the model, the nanowire radius may be obtained as a function of length. The model describes the morphology of tapered nanowires. We study the influence of different growth parameters, including the III/V flux ratio and pitch, on the nanowire morphology. Keywords: III-V nanowires, morphology, self-focusing effect, modeling
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Dubrovskii, Vladimir G., and Egor D. Leshchenko. "Modeling the Radial Growth of Self-Catalyzed III-V Nanowires." Nanomaterials 12, no. 10 (May 16, 2022): 1698. http://dx.doi.org/10.3390/nano12101698.
A new model for the radial growth of self-catalyzed III-V nanowires on different substrates is presented, which describes the nanowire morphological evolution without any free parameters. The model takes into account the re-emission of group III atoms from a mask surface and the shadowing effect in directional deposition techniques such as molecular beam epitaxy. It is shown that radial growth is faster for larger pitches of regular nanowire arrays or lower surface density, and can be suppressed by increasing the V/III flux ratio or decreasing re-emission. The model describes quite well the data on the morphological evolution of Ga-catalyzed GaP and GaAs nanowires on different substrates, where the nanowire length increases linearly and the radius enlarges sub-linearly with time. The obtained analytical expressions and numerical data should be useful for morphological control over different III-V nanowires in a wide range of growth conditions.
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GAO, Q., H. J. JOYCE, S. PAIMAN, J. H. KANG, H. H. TAN, Y. KIM, L. M. SMITH, et al. "III-V COMPOUND SEMICONDUCTOR NANOWIRES FOR OPTOELECTRONIC DEVICE APPLICATIONS." International Journal of High Speed Electronics and Systems 20, no. 01 (March 2011): 131–41. http://dx.doi.org/10.1142/s0129156411006465.
GaAs and InP based III-V compound semiconductor nanowires were grown epitaxially on GaAs (or Si ) (111)B and InP (111)B substrates, respectively, by metalorganic chemical vapor deposition using Au nanoparticles as catalyst. In this paper, we will give an overview of nanowire research activities in our group. In particular, the effects of growth parameters on the crystal structure and optical properties of various nanowires were studied in detail. We have successfully obtained defect-free GaAs nanowires with nearly intrinsic exciton lifetime and vertical straight nanowires on Si (111)B substrates. The crystal structure of InP nanowires, i.e., WZ or ZB , can also be engineered by carefully controlling the V/III ratio and catalyst size.
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Лещенко, Е. Д., and В. Г. Дубровский. "Моделирование роста заостренных нитевидных нанокристаллов на маскированных подложках." Письма в журнал технической физики 48, no. 23 (2022): 14. http://dx.doi.org/10.21883/pjtf.2022.23.53945.19358.
The formation of tapered self-catalyzed nanowires grown on reflecting substrates is studied theoretically. Within the model the nanowire radius is obtained as a function of length. The model describes the morphology of tapered nanowires. We study the influence of different growth parameters on the nanowire morphology, including the III/V flux ratio and pitch.
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Yip, Sen Po, Wei Wang, and Johnny C. Ho. "(Invited, Digital Presentation) Ternary III-Sb Nanowires: Synthesis and Their Electronic and Optoelectronics Applications." ECS Meeting Abstracts MA2022-02, no. 36 (October 9, 2022): 1306. http://dx.doi.org/10.1149/ma2022-02361306mtgabs.
Nowadays, the increasing demand for low power and highly efficient electronics and optoelectronics has driven the semiconductor industry to look for the alternatives of Si which is approaching its physical limit. Materials like graphene, carbon nanotube, III-V materials and so on, are the most promising candidates as the replacement of silicon. Among them, III-Sb materials, a sub-group of III-V materials, have been extensively researched due to their narrow and direct bandgap, high charge carrier mobility and high g-factor which makes them suitable for transistor, infra red detection and so on. Their nanowire counterparts have also been explored as the geometry of nanowire provide unique advantages. One of the research directions of III-Sb nanowire is to study their ternary counterpart (III-V-Sb or III-III’-Sb) like InAsSb, GaAsSb and InGaSb. Compares with binary compounds, ternary compound provides more room for engineering freedom like lattice parameter engineering and bandgap tuning. In this presentation, the synthesis and the electronic and optoelectronic applications of ternary III-Sb nanowires will be introduced. The high-crystal quality and high-aspect ratio ternary III-Sb nanowires were synthesized by using solid-source chemical vapor deposition method. Composition tunability was demonstrated successfully by adjusting the precursor ratio which allowed us to control the physical properties. We further integrated these nanowires into transistors and photodetectors which exhibit good performance like high carrier mobility and good photoresponse.
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Saleem, Samra, Ammara Maryam, Kaneez Fatima, Hadia Noor, Fatima Javed, and Muhammad Asghar. "Phase Control Growth of InAs Nanowires by Using Bi Surfactant." Coatings 12, no. 2 (February 15, 2022): 250. http://dx.doi.org/10.3390/coatings12020250.
To realize practical applications of nanowire-based devices, it is critical, yet challenging, to control crystal structure growth of III-V semiconductor nanowires. Here, we demonstrate that controlled wurtzite and zincblende phases of InAs nanowires can be fabricated using bismuth (Bi) as a surfactant. For this purpose, catalyst free selective area epitaxial growth of InAs nanowires was performed using molecular beam epitaxy (MBE). During the growth, Bi was used which may act as a wetting agent influencing the surface energy at growth plane ends, promoting wurtzite crystal phase growth. For a demonstration, wurtzite and zincblende InAs nanowires were obtained with and without using Bi-flux. Photoluminescence spectroscopy (PL) analysis of the nanowires indicates a strong correlation between wurtzite phase and the Bi-flux. It is observed that the bandgap energy of wurtzite and zincblende nanowires are ∼0.50 eV and ∼0.42 eV, respectively, and agree well with theoretical estimated bandgap of corresponding InAs crystal phases. A blue shift in PL emission peak energy was found with decreasing nanowire diameter. The controlled wurtzite and zincblende crystal phase and its associated heterostructure growth of InAs nanowires on Si may open up new opportunities in bandgap engineering and related device applications integrated on Si. Furthermore, this work also illustrates that Bi as a surfactant could play a dynamic role in the growth mechanism of III-V compound semiconductors.
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Kang, Sung Bum, Rahul Sharma, Minhyeok Jo, Su In Kim, Jeongwoo Hwang, Sang Hyuk Won, Jae Cheol Shin, and Kyoung Jin Choi. "Catalysis-Free Growth of III-V Core-Shell Nanowires on p-Si for Efficient Heterojunction Solar Cells with Optimized Window Layer." Energies 15, no. 5 (February 28, 2022): 1772. http://dx.doi.org/10.3390/en15051772.
The growth of high-quality compound semiconductor materials on silicon substrates has long been studied to overcome the high price of compound semiconductor substrates. In this study, we successfully fabricated nanowire solar cells by utilizing high-quality hetero p-n junctions formed by growing n-type III-V nanowires on p-silicon substrates. The n-InAs0.75P0.25 nanowire array was grown by the Volmer–Weber mechanism, a three-dimensional island growth mode arising from a lattice mismatch between III-V and silicon. For the surface passivation of n-InAs0.75P0.25 core nanowires, a wide bandgap InP shell was formed. The nanowire solar cell was fabricated by benzocyclobutene (BCB) filling, exposure of nanowire tips by reactive-ion etching, electron-beam deposition of ITO window layer, and finally metal grid electrode process. In particular, the ITO window layer plays a key role in reducing light reflection as well as electrically connecting nanowires that are electrically separated from each other. The deposition angle was adjusted for conformal coating of ITO on the nanowire surface, and as a result, the lowest light reflectance and excellent electrical connectivity between the nanowires were confirmed at an oblique deposition angle of 40°. The solar cell based on the heterojunction between the n-InAs0.75P0.25/InP core-shell nanowire and p-Si exhibited a very high photoelectric conversion efficiency of 9.19% with a current density of 27.10 mA/cm2, an open-circuit voltage of 484 mV, and a fill factor of 70.1%.
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Дубровский, В. Г., А. С. Соколовский, and И. В. Штром. "Свободная энергия образования зародыша при росте III-V нитевидного нанокристалла." Письма в журнал технической физики 46, no. 18 (2020): 3. http://dx.doi.org/10.21883/pjtf.2020.18.49991.18401.
An expression for the free energy of forming an island from a catalyst droplet in the vapor-liquid-solid growth of III-V nanowires is obtained. The effect of the droplet depletion with its group V (As) content is studied in the presence of material influx from vapor. Different growth regimes of a nanowire monolayer are theoretically analyzed, including the regime with the stopping size under very low As concentrations in liquid. It is shown that the island stops growing when the As content in the droplet decreases to its equilibrium value. The obtained results should be useful for understanding and modeling the growth kinetics of III-V nanowires, their crystal phase, nucleation statistics and length distributions within the ensembles of nanowires as well as the doping process.
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Demontis, Valeria, Valentina Zannier, Lucia Sorba, and Francesco Rossella. "Surface Nano-Patterning for the Bottom-Up Growth of III-V Semiconductor Nanowire Ordered Arrays." Nanomaterials 11, no. 8 (August 16, 2021): 2079. http://dx.doi.org/10.3390/nano11082079.
Ordered arrays of vertically aligned semiconductor nanowires are regarded as promising candidates for the realization of all-dielectric metamaterials, artificial electromagnetic materials, whose properties can be engineered to enable new functions and enhanced device performances with respect to naturally existing materials. In this review we account for the recent progresses in substrate nanopatterning methods, strategies and approaches that overall constitute the preliminary step towards the bottom-up growth of arrays of vertically aligned semiconductor nanowires with a controlled location, size and morphology of each nanowire. While we focus specifically on III-V semiconductor nanowires, several concepts, mechanisms and conclusions reported in the manuscript can be invoked and are valid also for different nanowire materials.
Chereau, Emmanuel. "Synthèse et modélisation de nanofils III-As par SAG-HVPE : vers des dispositifs pour l'infrarouge et la conversion d'énergie." Electronic Thesis or Diss., Université Clermont Auvergne (2021-...), 2024. http://www.theses.fr/2024UCFA0020.
Ce travail porte sur la croissance sélective (SAG) de nanofils (NFs) III-As par épitaxie en phase vapeur par la méthode aux hydrures (HVPE). Dans un premier temps, nous avons étudié la SAG de NFs de GaAs sur des substrats de GaAs. Des études systématiques portant sur les conditions de croissance ont mis en évidence une suppression de la croissance sous atmosphère riche en arsenic. Ces observations ont été appuyées par un modèle cinétique qui, pour la première fois en HVPE, prend en compte la diffusion des adatomes de Ga sur les facettes latérales des NFs. Puis, une étude préliminaire du dopage des NFs a été conduite, ainsi que des croissances de jonctions p-i-n dans des NFs. Les résultats sont encourageants quant à la réalisation de dispositifs à base de NFs par HVPE. Dans un second temps, nous avons étudié la SAG de NFs d’InAs et d’InGaAs sur des substrats de GaAs et Si. Il s’est avéré que la suppression de la croissance se produit également pour les NFs d’InAs. Concernant l’InGaAs, des réseaux de NFs de compositions variées ont été obtenus avec succès. Un modèle de croissance a été développé révélant que la composition des NFs est contrôlée par la cinétique de croissance plutôt que par des facteurs thermodynamiques. Cela simplifie considérablement le contrôle de la composition dans une large gamme de paramètres HVPE. Ces résultats montrent la capacité de la HVPE pour la fabrication de réseaux de NFs d’InGaAs homogènes avec des compositions facilement ajustables This work focuses on the selective area growth (SAG) of III-As nanowires (NWs) by hydride vapor-phase epitaxy (HVPE). First, we have studied the SAG of GaAs NWs on GaAs substrates. Systematic studies according to growth conditions have demonstrated a growth suppression effect under arsenic-rich atmosphere. These observations were supported by a kinetic model which, for the first time in HVPE, takes into account the diffusion of Ga adatoms on the NWs side facets. Then, a preliminary study of the doping of NWs was carried out, as well as the growth of p-i-n junctions in NWs. The results are encouraging regarding the fabrication of NW-based devices by HVPE. Secondly, we have studied the SAG of InAs and InGaAs on GaAs and Si substrates. It turned out that growth suppression also occurs for InAs NWs. As for InGaAs, NW arrays with various compositions have been successfully obtained. A growth model was developed revealing that the NWs composition is controlled by growth kinetics rather than thermodynamic factors. This greatly simplifies the control of the composition across a wide range of HVPE parameters. These results show the capability of HVPE for the fabrication of homogeneous InGaAs NW arrays with widely tunable compositions
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Burgess, Timothy. "From Dopant to Source: The Use of Zinc as an Enabler in the Synthesis of Nanostructures by Metalorganic Vapour Phase Epitaxy." Phd thesis, 2017. http://hdl.handle.net/1885/144611.
As conventional methods of semiconductor fabrication approach
fundamental physical limits, new paradigms are required for
progress. One concept with the potential to deliver such a
paradigm shift is the bottom-up synthesis of semiconductor
nanostructures. Beyond further scaling, bottom-up methods promise
novel geometries and heterostructures unavailable by conventional
top-down methods. This is particularly true in the case of
nanostructure growth by the vapour-liquid-solid (VLS) method.
Commonly realised using existing vapour phase epitaxy techniques,
a range of high-performance VLS devices have now been
demonstrated including photovoltaic cells, lasers and
high-frequency-transistors.
In this dissertation, selected applications of diethylzinc (DEZn)
are used to step through a range of opportunities and challenges
arising from the VLS synthesis of semiconductor nanostructures by
metal-organic vapour phase epitaxy (MOVPE). These applications
are broadly grouped into four chapters focusing on the use of
zinc firstly as a dopant and then morphological agent, internal
quantum efficiency (IQE) enhancer and finally, source.
In the context of doping, relatively high DEZn flows are shown to
alter the morphology of GaAs nanowires by introducing planar
defects, kinking and seed-splitting. Growth studies are used to
establish the threshold for these effects and thus the range of
DEZn flows suitable for doping. Successful incorporation of up to
5 x1020 Zn/cm3 is demonstrated through atom probe tomography
(APT) and electrical characterisation.
Building on these results, DEZn is then used to generate periodic
twinning in GaAs nanowires. The morphology and overgrowth of
these twinning superlattice (TSL) nanowires is studied. Unlike
for other III-V materials, twin spacing is found to be a linear
function of nanowire diameter. By analysing the probability of
twin formation, this result is related to the relatively high
twin plane and solid-liquid interface energies of GaAs. Values
for the wetting angle and supersaturation of the seed particle
during growth are also extracted.
In addition to acting as a dopant, zinc is also shown to produce
an orders of magnitude increase in the IQE of GaAs nanowires.
Performance gains are quantified by measuringthe absolute
efficiency of individual nanowires. This increase in IQE with
doping enables room-temperature lasing from unpassivated GaAs
nanowires. The performance of doped nanolasers, including the
transition to lasing, is fully characterised. In addition to
increasing radiative efficiency, Zn doping also increases
differential gain while reducing the transparency carrier
density. The threshold pump power of a Zn doped nanowire is thus
shown to be less than that of an equivalent AlGaAs passivated
structure.
In the final chapter, DEZn is used as a source for the growth of
ZnAs, ZnP and ZnSb nanostructures by MOVPE. A range of growth
conditions, substrates and seed materials are investigated.
Individual nanostructures of both ZnAs and ZnP are shown to
exhibit excellent optoelectronic performance with emission from
individual nanostructures at 1.0 and 1.5 eV respectively.
Overall, this thesis underlines the vast range of possibilities
offered by VLS growth and opens to the door to both a variety of
new techniques and new family of semiconductor nanomaterials.
Book chapters on the topic "III-As nanowires":
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Shilla, Pooja, Raj Kumar, and Arvind Kumar. "III-V-Based Gate-All-Around Cylindrical Nanowire Junctionless Field Effect Transistor." In Advances in Computer and Electrical Engineering, 101–21. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-6467-7.ch005.
This chapter represents some essential aspects of nanowires and their transport properties. Scaling of MOSFETs becomes a huge problem for industries due to short channel effects (SCEs) and sub-threshold leakage current. So, nanowires become a good solution to SCEs due to their structure. This chapter is divided into three parts. The first part gives a brief introduction of nanowire and different materials that can replace Si (channel material) and SiO2 (oxide material) due to their superior performance over Si. In the second part, the device structure and device structural measurement is discussed. In the third part, transport properties are discussed. This chapter shows the behavior of nanowire on changing different device materials and device dimensions. Electrical characteristics of Si and III-V based nanowires FETs will be analyzed and compared. High-k dielectric as oxide material also helps in improving device performance. HfO2 shows improvement in device characteristics over SiO2 taken as an oxide material. Junctionless nanowire MOSFET has also been designed and analyzed.
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Routray, Soumyaranjan, and Trupti Lenka. "III-Nitride Nanowires: Future Prospective for Photovoltaic Applications." In Nanowires - Recent Progress [Working Title]. IntechOpen, 2020. http://dx.doi.org/10.5772/intechopen.95011.
Photovoltaic (PV) technology could be a promising candidate for clean and green source of energy. The nanowire technology provides extra mileage over planar solar cells in every step from photon absorption to current generation. Indium Gallium Nitride (InxGa1-xN) is a recently revised material with such a bandgap to absorb nearly whole solar spectrum to increase the conversion efficiency copiously. One of the major technological challenge is in-built polarization charges. This chapter highlights the basic advantageous properties of InxGa 1−xN materials, its growth technology and state-of-the-art application towards PV devices. The most important challenges that remain in realizing a high-efficiency InxGa 1−xN PV device are also discussed. III-Nitride nanowires are also explored in detail to overcome the challenges. Finally, conclusions are drawn about the potential and future aspect of InxGa 1−xN material based nanowires towards terrestrial as well as space photovoltaic applications.
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Takele Geldasa, Fikadu. "Solar Energy Conversion Efficiency, Growth Mechanism and Design of III–V Nanowire-Based Solar Cells: Review." In Advances in Nanowires Synthesis and Applications to Sensing Technologies [Working Title]. IntechOpen, 2022. http://dx.doi.org/10.5772/intechopen.105985.
Nanowires (NWs) are 1D nanostructures with unique and wonderful optical and electrical properties. Due to their highly anisotropic shape and enormous index of refraction, they behave as optical antennae with improved absorption and emission properties, and thus better photovoltaic cell efficiency compared to a planar material with equivalent volume. Implying important advantages of reduced material usage and cost as well as due to its direct bandgap and its flexibility for designing solar cells, we choose to review III–V NWs. Their bandgap can easily be tunable for growing on the cheapest Si substrate. The recent developments in NW-based photovoltaics with attractive III–V NWs with different growth mechanisms, device fabrication, and performance results are studied. Recently, III–V NW solar cells have achieved an interesting efficiency above 10%. GaAsP NW has achieved 10.2%; InP NW has achieved 13.8%; GaAs NW has achieved 15.3%; and moreover the highest 17.8% efficiency is achieved by InP NW. While the III–V NW solar cells are much more vital and promising, their current efficiencies are still much lower than the theoretically predicted maximum efficiency of 48%. In this review, the chapter focused on the synthesis processes of III–V nanowires, vapor-liquid-solid growing mechanisms, solar light harvesting of III–V nanowire solar cells, and designing high-efficiency and low-cost III–V nanowire solar cells.
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Nguyen, Hoang-Duy, Mano Bala Sankar Muthu, and Hieu Pham Trung Nguyen. "Phosphor-Converted III-Nitride Nanowire White Light-Emitting Diodes." In Nanoelectronic Devices and Applications, 72–89. BENTHAM SCIENCE PUBLISHERS, 2024. http://dx.doi.org/10.2174/9789815238242124010005.
III-nitride nanowire light-emitting diodes (LEDs) have emerged as the nextgeneration solid-state lighting technology. Currently, white-light LEDs rely on the phosphor-converted white LED (pc-WLEDs) technology, which normally depends on the mixture of blue/ultraviolet emitters and green/yellow/red color-converters. In this chapter, a summary of current research progress on nanophosphors and their applications in improving the device performance of InGaN nanowire pc-WLEDs in terms of color rendering properties and optical and electrical characteristics is presented. These investigations have concentrated on manufacturing methods, morphologies, optoelectronic characterizations and device performances. By concentrating on these critical elements, our goal is to contribute valuable insights and advancements to the field, paving the way for the continued development and application of III-nitride nanowire LEDs in the landscape of solid-state lighting technologies.
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Kumar, Raj, Shashi Bala, and Arvind Kumar. "Comparative Performance Analysis of Nanowire and Nanotube Field Effect Transistors." In Advances in Computer and Electrical Engineering, 54–70. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-6467-7.ch003.
To have enhanced drive current and diminish short channel effects, planer MOS transistors have migrated from single-gate devices to three-dimensional multi-gate MOSFETs. The gate-all-around nanowire field-effect transistor (GAA NWFET) and nanotube or double gate-all-around field-effect transistors (DGGA-NTFET) have been proposed to deal with short channel effects and performance relates issues. Nanowire and nanotube-based field-effect transistors can be considered as leading candidates for nanoscale devices due to their superior electrostatic controllability, and ballistic transport properties. In this work, the performance of GAA NWFETs and DGAA-NT FETs will be analyzed and compared. III-V semiconductor materials as a channel will also be employed due to their high mobility over silicon. Performance analysis of junctionless nanowire and nanotube FETs will also be compared and presented.
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Bala, Shashi, Raj Kumar, Jeetendra Singh, and Sanjeev Kumar Sharma. "Design and Simulation Analysis of NWFET for Digital Application." In Advances in Computer and Electrical Engineering, 123–38. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-6467-7.ch006.
This chapter presents the design and simulation analysis nanowire-based FET (NWFET) for best possible Ig-Vgs characteristics. A NWFET is a device in which channel is wire-like structure with diameter or lateral dimension in nanometer (10-9 m) range. Performance analysis has been done for various design and process parameters variation to propose optimized parameter for best performance. Although a lot of focus has been put on homogenous Si based NWFETs, there has been a rising interest in III-V NWFETs. This is mainly due to the excellent carrier transport properties are provided by these materials. NWFETs have ability to suppress SCEs and are also good in suppressing OFF-current (IOFF), because of gate all around (GAA) configuration. Secondly, NWFETs have large ON-current (ION) due to quasi one-dimensional (1D) conduction of NWs, and as a result of low carrier scattering, conduction of NWs-based devices is very large.
Conference papers on the topic "III-As nanowires":
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Saerens, G., I. Tang, E. Bloch, K. Frizyuk, M. Reig Escalé, C. Renaut, F. Timpu, et al. "Semiconductor III-V Nanowires as Building Blocks for Flexible Nonlinear Photonic Components." In CLEO: QELS_Fundamental Science. Washington, D.C.: OSA, 2020. http://dx.doi.org/10.1364/cleo_qels.2020.ftu3q.3.
When crystalline solids are confined to the nanometer range, phonon transport within them can be significantly altered due to various effects, namely (i) increased boundary scattering; (ii) changes in phonon dispersion relation; and (iii) quantization of phonon transport. For example, theoretical studies (e.g., Chung et al., 2000) have suggested that, as the diameter of a silicon nanowire (NW) becomes smaller than 20 nm, the phonon dispersion relation, and therefore its density of states, could be modified due to phonon confinement. This in turn impacts the phonon group velocities and scattering rates that can further reduce the thermal conductivity of confined structures.
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Florini, Nikoletta. "Core-shell nanowires based on III-V alloys: Strain distribution as a function of structure and composition." In European Microscopy Congress 2020. Royal Microscopical Society, 2021. http://dx.doi.org/10.22443/rms.emc2020.1230.
Lyeo, Ho-Ki, C. K. Ken Shih, Uttam Ghoshal, and Li Shi. "Thermoelectric Mapping of Nanostructures." In ASME 2002 International Mechanical Engineering Congress and Exposition. ASMEDC, 2002. http://dx.doi.org/10.1115/imece2002-32766.
There is intense interest to develop nanowires [1] and superlattices [2] that may offer superior thermoelectric figure of merit for efficient energy conversion. Meanwhile, the advance of semiconductor processing techniques has yielded impurity-doped semiconductor nanostructures with a doped region as small as a few nanometers. These include shallow junction Si field-effect transistors, strained Si/SiGe/Ge heterostructures and quantum dots, III-V heterostructures, and doped nanowires and nanotubes. Due to various size confinement effects, these doped semiconductor nanostructures often have unique electrical, optoelectronic, or thermoelectric properties that may lead to a wide range of applications. In contrast to the progress made in synthesizing thermoelectric nanostructures and in fabricating doped semiconductor nanostructures, the ability to quantify thermoelectric property and carrier concentration in comparable length scale has been lagging behind. For example, the 1997 U.S. Roadmap of Semiconductors from the Semiconductor Industry Association (SIA) defines the need for nanometer-scale measurements of carrier concentration profiles [3]. Though progress has been made, currently no technique can satisfy the requirements posted by the SIA roadmap due to the lack of either spatial resolution or accuracy.
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Kleindienst, R., V. Cimalla, M. Eickhoff, A. Grewe, K. Holc, J. Schätzle, U. Schwarz, J. Teubert, and S. Sinzinger. "Micro-optical system as integration platform for III-N nanowire based opto-chemical detectors." In SPIE MOEMS-MEMS, edited by Georg von Freymann, Winston V. Schoenfeld, and Raymond C. Rumpf. SPIE, 2013. http://dx.doi.org/10.1117/12.2002411.
Geelhaar, L. "(Invited) Nanowire Growth as a Means for the Monolithic Integration of III-V Compound Semiconductors on Si." In 2015 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2015. http://dx.doi.org/10.7567/ssdm.2015.d-6-1.
Stellari, Franco, Alan J. Weger, Seongwon Kim, Dzmitry Maliuk, Peilin Song, Herschel A. Ainspan, Young Kwark, et al. "A Superconducting Nanowire Single-Photon Detector (SnSPD) System for Ultra Low Voltage Time-Resolved Emission (TRE) Measurements of VLSI Circuits." In ISTFA 2013. ASM International, 2013. http://dx.doi.org/10.31399/asm.cp.istfa2013p0182.
Abstract In this paper, we present a Superconducting Nanowire Single Photon Detector (SnSPD) system and its application to ultra low voltage Time-Resolved Emission (TRE) measurements (also known as Picosecond Imaging Circuit Analysis, PICA) of scaled VLSI circuits. The 9 µm-diameter detector is housed in a closed loop cryostat and fiber coupled to an existing Emiscope III tool for collecting spontaneous emission light from the backside of integrated circuits (ICs) down to a world record 0.5 V supply voltage in a few minutes.
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Romero, David A., Elham Pakseresht, Daniel Sellan, Aydin Nabovati, and Cristina Amon. "A Hierarchical Framework for Thermal Modelling of Electronic Devices: From Atoms to Chips." In ASME 2013 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2013. http://dx.doi.org/10.1115/ipack2013-73202.
In this work, we provide an overview of a hierarchical computational framework to predict thermal transport in electronic devices through integration of physics-based models at different length scales. Information from atomistic simulations at the smallest length scales are transferred to upper levels of the hierarchy, up to thermal models for the chip. The proposed methodology includes five levels of length scales in electronic devices, namely (i) atomistic level, (ii) thin film and nanowire level, (iii) transistor and logic gate level, (iv) functional block level, and (v) chip level. At the first level of the hierarchy, properties of energy carriers in a semiconductor material (e.g., phonons) are obtained from atomistic level simulations, such as Molecular Dynamics (MD) and Lattice Dynamics (LD) calculations. At the second level, thermal transport in thin silicon films is modelled using a Lattice Boltzmann Method (LBM) for phonons. The outcome of these simulations is a size-dependent thermal conductivity for silicon films. At the third level of the hierarchy, these effective thermal conductivities are used in thermal modelling of logic gates. Detailed structures of different types of logic gates are reconstructed based on different manufacturing technologies (MOSFET and FinFET) at different technology nodes. Since the characteristic sizes of different parts of the logic gates are comparable to the mean free path of energy carriers, we use the size-dependent, effective thermal conductivities that were calculated at lower levels of the hierarchy to build simulation models for the logic gates. Based on these models, we calculate an equivalent thermal conductance for the logic gates, which would then be used in the upper level simulations to determine an equivalent thermal conductance for different functional blocks of the die based on their internal structure and the number and type of logic gates found in each functional block. Overall, the proposed hierarchical model enables us to include the effect of atomistic-level physics into package-level simulations, and thus, have an accurate prediction of thermal transport in an electronic device.
