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Journal articles on the topic 'High-voltage technique'

Author: Grafiati

Published: 30 May 2022

Last updated: 31 May 2022

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1

W.N, Auni. "A Review: Partial Discharge Sensor Applications and Classification Technique in High Voltage Cable." Journal of Advanced Research in Dynamical and Control Systems 12, SP7 (July 25, 2020): 1290–301. http://dx.doi.org/10.5373/jardcs/v12sp7/20202229.

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2

Salimov, R. A., N. K. Kuksanov, and A. B. Malinin. "Electron beam technique for high-voltage electron cooling." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 391, no. 1 (May 1997): 138–41. http://dx.doi.org/10.1016/s0168-9002(97)00022-3.

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3

Santos, Josemir Coelho, and Kunihiko Hidaka. "Optical High Voltage Measurement Technique Using Pockels Device." Japanese Journal of Applied Physics 36, Part 1, No. 4A (April 15, 1997): 2394–98. http://dx.doi.org/10.1143/jjap.36.2394.

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4

de Oliveira, Adriano Costa, Edson Guedes da Costa, Alexandre Jean Rene Serres, Herbet Filipe dos Santos Sousa, Tarso Vilela Ferreira, and Henrique Nunes de Santana. "Radiometric Monitoring Technique for High-Voltage Circuit Breakers." IEEE Transactions on Power Delivery 34, no. 4 (August 2019): 1656–65. http://dx.doi.org/10.1109/tpwrd.2019.2917380.

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5

Abdel Mageed, Hala M., and Rehab S. Salah Eldeen. "Adapted Technique for Calibrating Voltage Dividers of AC High-Voltage Measuring Systems." MAPAN 35, no. 1 (September 3, 2019): 11–17. http://dx.doi.org/10.1007/s12647-019-00334-8.

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6

C. Rathod, Mihirkumar. "Generation High Voltage: A Technique for Laboratory Educational Works." International Journal for Research in Applied Science and Engineering Technology V, no. II (February 28, 2017): 176–81. http://dx.doi.org/10.22214/ijraset.2017.2029.

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7

Cho, Seung-Yeon, and In-Soung Chang. "Solubilization of wasted sludge using high voltage impulse technique." Journal of the Korean Society of Water and Wastewater 31, no. 3 (June 30, 2017): 257–62. http://dx.doi.org/10.11001/jksww.2017.31.3.257.

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8

Myono, T., E. Nishibe, K. Iwatsu, S. Kikuchi, T. Suzuki, Y. Sasaki, K. Itoh, and H. Kobayashi. "Modelling technique for high-voltage MOS devices with BSIM3v3." Electronics Letters 34, no. 18 (1998): 1790. http://dx.doi.org/10.1049/el:19981240.

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9

Rezal, M., Dahaman Ishak, and M. Sabri. "High voltage magnetic pulse generation using capacitor discharge technique." Alexandria Engineering Journal 53, no. 4 (December 2014): 803–8. http://dx.doi.org/10.1016/j.aej.2014.10.001.

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10

Siderakis, K., D. Pylarinos, E. Thalassinakis, I. Vitellas, and E. Pyrgioti. "Pollution Maintenance Techniques in Coastal High Voltage Installations." Engineering, Technology & Applied Science Research 1, no. 1 (February 1, 2011): 1–7. http://dx.doi.org/10.48084/etasr.6.

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Pollution of outdoor high voltage insulators is a common problem for utilities, with a considerable impact to power system reliability. In an effort to prevent possible flashovers due to pollution, many methods have been applied, aiming to improve the insulation performance, either by suppressing the formation of surface conductivity or by increasing the possible insulation level. In the case of substations, the selection of the appropriate technique is complex due to certain issues correlated to the nature of the installation. In this paper, several techniques usually implemented by utilities, are investigated based on the experienced gained in the case of Crete, a Greek island in southern Europe, where due to the coastal development of the power system, the majority of high voltage installations are exposed to intense marine pollution. The technique of coating insulators with Room Temperature Vulcanized Silicone Rubber (RTV SIR) has proved rather efficient and therefore is presented extendedly. Correlation of the material behaviour with environmental conditions is discussed and results from long term monitoring, including environmental parameters and leakage current measurements, in a 150 kV Substation are presented. It is shown that RTV SIR coatings have remarkably suppressed surface activity and that porcelain insulators exhibit different activity period when coated.

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11

Chen, Yung Chin, Kun Long Zheng, Zong Ye Wu, Tin Fang Zheng, and Chie Nan Lai. "High Pumping Gain Dickson Charge Pump Using Bootstrapped Technique." Applied Mechanics and Materials 145 (December 2011): 557–61. http://dx.doi.org/10.4028/www.scientific.net/amm.145.557.

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This paper proposed a bootstrapped type high-efficient charge pump circuit based on the Dickson charge pump for high output power and pump-efficiency. By using bootstrapped technique, it can increase both of pump-efficiency and power-efficiency. The proposed bootstrapped based charge pump can avoid the threshold voltage drop and enable to generate a higher output voltage. Simulation by using HSPICE level 3 model shows that for conventional Dickson charge pump, it convert the input low DC-voltage (Vin=1.5V) up to 3.8 times of it (VOUT=5.77V), the pump efficiency was 76.93%. Our work, however, can convert the low input DC-voltage (Vin=1.5V) up near to 4.4 times of it (VOUT=6.62V), pump efficiency can reach up to 88.26%.

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12

Suhaimi, Saiful Mohammad Iezham, Nouruddeen Bashir, Nor Asiah Muhamad, Nurun Najah Abdul Rahim, Noor Azlinda Ahmad, and Mohd Nazri Abdul Rahman. "Surface Discharge Analysis of High Voltage Glass Insulators Using Ultraviolet Pulse Voltage." Energies 12, no. 2 (January 9, 2019): 204. http://dx.doi.org/10.3390/en12020204.

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Surface discharges are precursors to flashover. To pre-empt the occurrence of flashover incidents, utility companies need to regularly monitor the condition of line insulators. Recent studies have shown that monitoring of UV signals emitted by surface discharges of insulators is a promising technique. In this work, the UV signals’ time and frequency components of a set of contaminated and field-aged insulator under varying contamination levels and degrees of ageing were studied. Experimental result shows that a strong correlation exists between the discharge intensity levels under varying contamination levels and degree of ageing. As the contamination level increases, the discharge level of the insulator samples also intensifies, resulting in the increase of total harmonic distortion and fundamental frequencies. Total harmonic distortion and fundamental frequencies of the UV signals were employed to develop a technique based on artificial neural networks (ANNs) to classify the flashover prediction based on the discharge intensity levels of the insulator samples. The results of the ANN simulation showed 87% accuracy in the performance index. This study illustrates that the UV pulse detection method is a potential tool to monitor insulator surface conditions during service.

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13

Chebli, Robert, Mohamad Sawan, Kamal El-Sankary, and Yvon Savaria. "High-voltage DMOS integrated circuits using floating-gate protection technique." Analog Integrated Circuits and Signal Processing 62, no. 2 (August 13, 2009): 223–35. http://dx.doi.org/10.1007/s10470-009-9363-1.

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14

Kong, Moufu, and Xingbi Chen. "Novel technique for lateral high‐voltage totem‐pole power devices." IET Power Electronics 7, no. 9 (September 2014): 2396–402. http://dx.doi.org/10.1049/iet-pel.2013.0561.

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15

Fujihira, Tatsuhiko, Yukio Yano, Shigeyuki Obinata, Naoki Kumagai, and Kenya Sakurai. "Proposal of New Interconnection Technique for Very High-Voltage IC's." Japanese Journal of Applied Physics 35, Part 1, No. 11 (November 15, 1996): 5655–63. http://dx.doi.org/10.1143/jjap.35.5655.

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16

Wu, Wenguo, Shibin Wang, Yuangang Liu, and Aizheng Chen. "Paclitaxel-Alginate/Chitosan Microcapsules Prepared Using High-Voltage Electrostatic Technique." Journal of Bionanoscience 8, no. 2 (April 1, 2014): 127–32. http://dx.doi.org/10.1166/jbns.2014.1206.

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17

Yilmaz, H., and W. R. Van Dell. "Floating metal rings (FMR), a novel high-voltage blocking technique." IEEE Electron Device Letters 6, no. 11 (November 1985): 600–601. http://dx.doi.org/10.1109/edl.1985.26244.

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18

Kannan, Sukeshwar, Kaushal Kannan, Bruce C. Kim, Friedrich Taenzler, Richard Antley, Ken Moushegian, Kenneth M. Butler, and Doug Mirizzi. "Physics-Based Low-Cost Test Technique for High Voltage LDMOS." Journal of Electronic Testing 29, no. 6 (November 15, 2013): 745–62. http://dx.doi.org/10.1007/s10836-013-5417-5.

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19

Chen, Yung Chin. "High Pumping Gain Dickson Charge Pump Using Improved Bootstrapped Technique." Applied Mechanics and Materials 764-765 (May 2015): 506–10. http://dx.doi.org/10.4028/www.scientific.net/amm.764-765.506.

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This paper proposed an improved bootstrapped type high-efficient charge pump circuit based on the Dickson charge pump in order to get a higher pumping efficiency. It is not only avoid the threshold voltage drop in conventional Dickson charge pump circuits but enable them to generate a higher output voltage. Simulation by HSPICE shows that for conventional Dickson charge pump, it convert the input low DC-voltage (Vin=1.5V) up to 3.8 times of it (VOUT=5.77V), the pump efficiency was 76.93%. Our work, however, can convert the low input DC-voltage (Vin=1.5V) up near to 4.76 times of it (VOUT=7.14V), the pump efficiency can reaches as high as 95.2%.

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20

P. Nithin and Dr. R. Rajeswari. "High Gain DC-DC Converter Integrating Dickson Charge Pump with Coupled Inductor Technique." International Journal for Modern Trends in Science and Technology 7, no. 6 (September 9, 2021): 272–77. http://dx.doi.org/10.46501/ijmtst0706046.

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In this paper, a novel high voltage gain DC-DC converter based on coupled inductor and voltage multiplier technique is proposed. The benefits of the proposed converter are ultra-high voltage gain, low voltage stress across the power switch and very low input current ripple by employing a low current ripple structure (LCR) at the input side. A low on state resistance (RDS(on)) of the power switch can be employed since the voltage stress is a maximum of 25% of the output voltage and the conduction losses of the switch is also reduced. Design of a 1.9kW, 48V at the low voltage side and 430V at the high voltage side is done and verified by simulation. Simulation results show an efficiency of over 93% when operating in continuous conduction mode (CCM).

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21

Munir, Muhammad Miftahul, Dian Ahmad Hapidin, and Khairurrijal. "Designing of a High Voltage Power Supply for Electrospinning Apparatus Using a High Voltage Flyback Transformer (HVFBT)." Applied Mechanics and Materials 771 (July 2015): 145–48. http://dx.doi.org/10.4028/www.scientific.net/amm.771.145.

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Research on nanofiber materials is actively done around the world today. Various types of nanofibers have been synthesized using an electrospinning technique. The most important component when synthesizing nanofibers using the electrospinning technique is a DC high voltage power supply. Some requirements must be fulfilled by the high voltage power supply, i.e., it must be adjustable and its output voltage reaches tens of kilovolts. This paper discusses the design and development of a high voltage power supply using a diode-split transformer (DST)-type high voltage flyback transformer (HVFBT). The DST HVFBT was chosen because of its simplicity, compactness, inexpensiveness, and easiness of finding it. A pulse-width modulation (PWM) circuit with controlling frequency and duty cycle was fed to the DST HVFBT. The high voltage power supply was characterized by the frequency and duty cycle dependences of its output voltage. Experimental results showed that the frequency and duty cycle affect the output voltage. The output voltage could be set from 1 to 18 kV by changing the duty cycle. Therefore, the nanofibers could be synthesized by employing the developed high voltage power supply.

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22

Chen, Shen Li, and Hsin Yang Shih. "A Novel Method to Extract Carrier Mobility and Threshold Voltage in High-Voltage DDD MOSFETs." Advanced Materials Research 706-708 (June 2013): 1709–15. http://dx.doi.org/10.4028/www.scientific.net/amr.706-708.1709.

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In this work, we apply the Hauser technique and combine a newer inversion layer charge model to extract the effective channel carrier mobility (μeff) and threshold voltage (Vth) of several high-voltage DDD MOSFETs with different dimensions in channel length and width. This paper proposes and demonstrates that our new method is a novel and efficient to extract the carrier mobility and threshold voltage in the DDD MOSFET, meanwhile, the extracted data is well consistent with UT model. And, only the extracted values by our new method and BCV method can clearly reflect the narrow-width effect which results from the so called LOCOS isolation technique. Therefore, it is clearly to see that our extraction technique can exactly reflect the device characteristics in high-voltage DDD MOSFETs.

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23

Katyara, Sunny, Ashfaque Hussain Hashmani, and Bhawani Shanker Chowdhry. "Development and Analysis of Pulse Width Modulation Techniques for Induction Motor Control." January 2020 39, no. 1 (January 1, 2020): 81–96. http://dx.doi.org/10.22581/muet1982.2001.09.

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SVPWM (Space Vector Pulse Width Modulation) technique is type of traditional PWM method that efficiently utilizes its dc link voltage and generates high voltage pulses with low harmonic content and high modulation index. VSI (Voltage Source Inverter) with SVPWM generates adjustable voltage and frequency signals for VSDs (Variable Speed Drives). This research work presents the simplified SVPWM technique for controlling the speed and torque of induction motor. The performance of developed SVPWM technique is analyzed in terms of its switching losses and harmonic content and compared with SPWM (Sinusoidal Pulse Width Modulation). Mathematical modeling for induction motor control through two-level VSI with SVPWM and SPWM is presented. The voltage and current TDHs (Total Harmonic Distortions) of the drive with SVPWM technique are 73.23 and 63.3% respectively as compared to 101.99 and 77.89% with SPWM technique. Similarly, the switching losses with SVPWM technique are 178.79 mW and that of with SPWM are 269.45 mW. Simulink modeling and laboratory setup are developed to testify the efficacy of SVPWM and SPWM techniques. The modulation factor of SVPWM technique is 0.907 which is higher as compared to SPWM technique with 0.785 modulation factor.

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24

Sachs, F., and M. J. Song. "High-voltage electron microscopy of patch-clamped membranes." Proceedings, annual meeting, Electron Microscopy Society of America 45 (August 1987): 582–83. http://dx.doi.org/10.1017/s0424820100127402.

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Cellular electrophysiology has been revolutionized by the introduction of patch clamp techniques. The patch clamp records current from a small patch of the cell membrane which has been sucked into a glass pipette. The membrane patch, a few micons in diameter, is attached to the glass by a seal which is electrically, diffusionally and mechanically tight. Because of the tight electrical seal, the noise level is low enough to record the activity of single ion channels over a time scale extending from 10μs to days. However, although the patch technique is over ten years old, the patch structure is unknown. The patch is inside a glass pipette where it has been impossible to see with standard electron microscopes. We show here that at 1 Mev the glass pipette is transparent and the membrane within can be seen with a resolution of about 30 A.

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25

Elserougi, Ahmed A., Ahmed M. Massoud, and Shehab Ahmed. "Modular Multilevel Converter-Based Bipolar High-Voltage Pulse Generator With Sensorless Capacitor Voltage Balancing Technique." IEEE Transactions on Plasma Science 44, no. 7 (July 2016): 1187–94. http://dx.doi.org/10.1109/tps.2016.2575861.

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26

Xunwei Zhou, Peng Xu, and F. C. Lee. "A novel current-sharing control technique for low-voltage high-current voltage regulator module applications." IEEE Transactions on Power Electronics 15, no. 6 (November 2000): 1153–62. http://dx.doi.org/10.1109/63.892830.

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27

Takada, Yoshiharu, Wataru Saito, Masahiko Kuraguchi, Ichiro Omura, and Kunio Tsuda. "High voltage GaN-based power HEMTs with field plate technique: Breakdown voltage and switching characteristics." physica status solidi (c), no. 7 (December 2003): 2347–50. http://dx.doi.org/10.1002/pssc.200303531.

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28

Kim, Suk Min, Byungkyu Song, and Seong-Ook Jung. "Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 10 (October 2019): 2413–22. http://dx.doi.org/10.1109/tvlsi.2019.2920630.

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29

Fisher, Robert M. "High-voltage and high-resolution TEM in materials research: Penetration and Resolution Issues." Proceedings, annual meeting, Electron Microscopy Society of America 49 (August 1991): 500–501. http://dx.doi.org/10.1017/s0424820100086805.

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Transmission electron microscopy has produced most of what is known about the microstructures of inorganic materials. Although some internal structures can be seen on etched surfaces using replicas or the SEM, the lack of electron diffraction data eliminates the availability of crystallographic information so that the identity and habit plane of precipitates or characteristics of lattice defects cannot be determined. However, the old extraction replica technique has come back into vogue for analytical microscopy because matrix effects in X-ray or ELS spectra can be eliminated. Extraction replicas can also be used for HREM studies of small constituents in multi-phase materials when standard specimen thinning techniques are inapplicable.

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30

Ruknudin, A., M. J. Song, A. Auerbach, and F. Sachs. "The structure of patch-clamped membranes in high voltage Electron Microscopy." Proceedings, annual meeting, Electron Microscopy Society of America 47 (August 6, 1989): 936–37. http://dx.doi.org/10.1017/s0424820100156663.

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The study of single ion channel kinetics in cell electrophysiology has been made possible by the introduction of patch-clamp techniques. Recordings can be made from a patch of membrane either attached to the cell or excised into controlled solutions. Though this technique has been widely used for more than a decade, the structure of the membrane patch and its associated cytoplasmic elements are not known except for recent work done in this laboratory . We have improved this technique to visualize membrane patches using high voltage electron microscope and also identified one class of channels in the patch by immunocytochemistry.The procedure for preserving biological structure in a glass patch pipette is basically same as described earlier as “dry mounting technique” . Briefly, after making a patch, the pipette is removed from the bath and the tip is freeze-fixed in liquid propane. A slight negative pressure is applied to the pipette while freeze-fixing in order to stretch the shape of the patch. Once fixed, the tip is not exposed to temperatures higher than-126° C. A 0.5 cm bit of the pipette tip is broken off, stored in IN2, and then freeze dried between -126° to -80° C under high vaccum (10-6 Torr).

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31

Wildermuth, Stephan, Klaus Bohnert, Hubert Brändle, Jean-Marie Fourmigue, and Didier Perrodin. "Growth and Characterization of Single Crystalline Bi4Ge3O12Fibers for Electrooptic High Voltage Sensors." Journal of Sensors 2013 (2013): 1–7. http://dx.doi.org/10.1155/2013/650572.

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The micro-pulling-down technique for crystalline fiber growth is employed to grow fibers and thin rods of bismuth germanate, Bi4Ge3O12(BGO), for use in electrooptic high voltage sensors. The motivation is the growth of fibers that are considerably longer than the typical lengths (100–250 mm) that are achieved by more conventional growth techniques like the Czochralski technique. At a given voltage (several hundred kilovolts in high voltage substation applications) longer sensors result in lower electric field strengths and therefore more compact and simpler electric insulation. BGO samples with lengths up to 850 mm and thicknesses from 300 μm to 3 mm were grown. Particular challenges in the growth of BGO fibers are addressed. The relevant optical properties of the fibers are characterized, and the electrooptic response is investigated at voltages up to .

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32

Jiang, Qiang. "The Design of 25KV High-Frequency High-Voltage Power Supply." Advanced Materials Research 912-914 (April 2014): 927–30. http://dx.doi.org/10.4028/www.scientific.net/amr.912-914.927.

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In this paper, a HV and HF switch power supply was designed, which was controlled through a single chip microcomputer, also the MOSFET was used as the switch power tube. The PWM (pulse width modulation) technique and half-bridge inverter topology have been used to invert AC into the DC that can be adjust from 0V~25KV and the operating frequency is 35KHz, Through the simulation with the Saber software and practical use, the feasibility of the scheme and the correctness of the design have been verified.

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33

Asyaei, Mohammad, and Farshad Moradi. "A Domino Circuit Technique for Noise-Immune High Fan-In Gates." Journal of Circuits, Systems and Computers 27, no. 10 (May 24, 2018): 1850151. http://dx.doi.org/10.1142/s0218126618501517.

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Noise immunity is an important concern in deep nano-scale technologies, especially for high fan-in gates. In this paper, a new domino circuit technique is proposed by which the noise immunity of high fan-in gates increases while the power consumption reduces. The proposed technique is based on the comparison of two currents, which vary with respect to the voltage across the pull-down network (PDN). By comparing these currents, the voltage level of the dynamic node is pulled up or pulled down depending on the input voltages. Using this technique, the voltage swing on the PDN can be decreased to reduce the power consumption. Moreover, a diode-connected NMOS transistor is added in series with the PDN in the proposed technique. This will result in reducing the subthreshold leakage current due to the stacking effect and, as a result, the noise immunity will improve. To demonstrate the efficacy of the proposed domino design over the conventional techniques, high fan-in gates are designed and compared in 90[Formula: see text]nm CMOS technology. Simulation results exhibit at least 1.87X noise immunity improvement and 20% power consumption reduction in comparison to the standard footless domino (SFLD) circuits at the same delay.

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34

Tian, XingGuo, XiaoNing Xin, and DongYang Han. "A high precision bandgap voltage reference." MATEC Web of Conferences 232 (2018): 04072. http://dx.doi.org/10.1051/matecconf/201823204072.

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In order to meet the market demand for wide temperature range and high precision bandgap voltage reference, this paper designs a bandgap reference with wide temperature range and low temperature coefficient. In this paper, the basic implementation principle of the bandgap reference is analyzed.On the basis of the traditional bandgap reference circuit structure,this design adds a trimming network and a temperature compensation network. A new Gaussian bell curve compensation technique is adopted to compensate the low temperature section, and the normal temperature section and the high temperature section respectively. Compared with the existing compensation technology, the versatility and the compensation effect is better. The designed circuit is designed and manufactured based on the Huahong HHNECGE0.35um process. The results show that the output voltage is 2.5V at 2.7V supply voltage and temperature range of -40-125°C.at typical process angle ,the temperature coefficient is 0.54618 PPm/°C,and is within 1PPm/°C at other process angles.

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35

Martínez, C. M., L. E. Flores, and A. D. Hernández. "A multichannel averager technique for current-voltage measurements in high- superconductors." Measurement Science and Technology 9, no. 10 (October 1, 1998): 1785–87. http://dx.doi.org/10.1088/0957-0233/9/10/021.

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36

Zhou, Ze-kun, Hongming Yu, Yue Shi, Zhuo Wang, and Bo Zhang. "A High-Precision Bandgap Voltage Reference with Automatic Curvature-Compensation Technique." Journal of Circuits, Systems and Computers 28, no. 13 (January 8, 2019): 1950214. http://dx.doi.org/10.1142/s0218126619502141.

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A high-precision bandgap voltage reference (BGR) with a novel curvature-compensation scheme is proposed in this paper. The temperature coefficient (TC) can be automatically optimized with a built-in adaptive curvature-compensation technique, which is realized in a digitization control way. An exponential curvature-compensation method is first adopted to reduce the TC in a certain degree, especially in low temperature range. Then, the temperature drift of BGR in higher temperature range can be further minimized by dynamic zero-temperature-coefficient point tracking (ZTCPT) with temperature changes. With the help of proposed adaptive signal processing, the output voltage of BGR can approximately maintain zero TC in a wider temperature range. Verification results of the BGR proposed in this paper, which is implemented in 0.35-[Formula: see text]m BiCMOS process, illustrate that the TC of 1.4[Formula: see text]ppm/∘C is realized under the power supply voltage of 3[Formula: see text]V and the power supply rejection of the proposed circuit is [Formula: see text][Formula: see text]dB without any filter capacitor.

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37

Hoque, M. R., T. Ahmad, T. R. McNutt, H. A. Mantooth, and M. M. Mojarradi. "A technique to increase the efficiency of high-voltage charge pumps." IEEE Transactions on Circuits and Systems II: Express Briefs 53, no. 5 (May 2006): 364–68. http://dx.doi.org/10.1109/tcsii.2006.869922.

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38

Sayadian, H. A., S. Feng, J. Goldhar, and C. H. Lee. "Generation and shaping of megawatt high-voltage pulses by optoelectronic technique." IEEE Transactions on Microwave Theory and Techniques 38, no. 5 (May 1990): 622–28. http://dx.doi.org/10.1109/22.54931.

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39

Taguchi, Shinya, Kazuya Hasegawa, Kazuki Nomoto, and Tohru Nakamura. "High threshold voltage normally-off GaN MISFETs using self-alignment technique." physica status solidi (c) 9, no. 3-4 (December 7, 2011): 858–60. http://dx.doi.org/10.1002/pssc.201100321.

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40

Venema, Henk W., Marcel van Straten, and Gerard J. den Heeten. "Digital Radiography of the Chest: Reassessment of the High-Voltage Technique?" Radiology 235, no. 1 (April 2005): 336–38. http://dx.doi.org/10.1148/radiol.2351041679.

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41

Li, Qiang, Yuan Yang, Haohao Ma, Yangle Zhou, Guolong You, Minmin Zhang, and Wei Xiang. "A Novel Floating High-Voltage Level Shifter with Pre-Storage Technique." Sensors 22, no. 5 (February 24, 2022): 1774. http://dx.doi.org/10.3390/s22051774.

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This paper proposes a novel floating high-voltage level shifter (FHV-LS) with the pre-storage technique for high speed and low deviation in propagation delay. With this technology, the transmission paths from input to output are optimized, and thus the propagation delay of the proposed FHV-LS is reduced to as low as the sub-nanosecond scale. To further reduce the propagation delay, a pull-up network with regulated strength is introduced to reduce the fall time, which is a crucial part of the propagation delay. In addition, a pseudosymmetrical input pair is used to improve the symmetry of FHV-LS structurally to balance between the rising and falling propagation delays. Moreover, a start-up circuit is developed to initialize the output state of FHV-LS during the VDDH power up. The proposed FHV-LS is implemented using 0.3-µm HVCMOS technology. Post-layout simulation shows that the propagation delays and energy per transition of the proposed FHV-LS are 384 ps and 77.7 pJ @VH = 5 V, respectively. Finally, the 500-points Monte Carlo are performed to verify the performance and the stability.

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Eguchi, Kei, Farzin Asadi, Akira Shibata, Hiroto Abe, and Ichirou Oota. "Reduction of Inrush Current in a Shockwave Non-Thermal Food Processing System Using an Exponential Clock Pulse Generator." Sustainability 12, no. 15 (July 29, 2020): 6095. http://dx.doi.org/10.3390/su12156095.

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Recently, shockwave food processing is drawing much attention as a low-cost non-thermal food process technique. In shockwave non-thermal food processing, underwater shockwaves are generated by a high voltage generator. Therefore, high inrush currents and high voltage stress on circuit components significantly reduce the reliability and life expectancy of the circuit. However, to the best of our knowledge, stress reduction techniques and their experimental verification have not been studied yet in the shockwave non-thermal food processing system. In this paper, we propose a stress reduction technique for the shockwave non-thermal food processing system and investigate the effectiveness of the proposed technique experimentally. To achieve high reliability and life expectancy, a new high voltage multiplier with an exponential clock pulse generator is proposed for the shockwave non-thermal food processing system. By slowing down the rate at which the capacitors charge in the high voltage multiplier, the exponential clock pulse generator significantly reduces the inrush current. Furthermore, to perform shockwave non-thermal food processing continuously at a lower voltage level, we present a new electrode with a reset mechanism for wire electric discharge (WED), where a square-shaped metal wire swings on a hinge in the proposed electrode. The proposed electrode enables not only shockwave generation at a lower voltage level but also continuous non-thermal food processing, because the square-shaped metal wire is not melted in the WED process. To confirm the validity of the proposed techniques, some experiments are performed regarding the laboratory prototype of the shockwave non-thermal food processing system. In the performed experiments, reduction of inrush currents and effective food processing are confirmed.

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Li, Zhongyang, Lin Du, Jianshe Lou, Yun Jiang, Kunshu Wang, Wei Wen, Zhizhe Wang, Shenglei Zhao, Jincheng Zhang, and Yue Hao. "High‐Breakdown‐Voltage AlGaN Channel High‐Electron‐Mobility Transistors with Reduced Surface Field Technique." physica status solidi (a) 217, no. 7 (January 24, 2020): 1900793. http://dx.doi.org/10.1002/pssa.201900793.

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Et. al., R. Durga Rao,. "Nanocrystalline based Mitigation Technique for Very Fast Transient over Voltages in Gas Insulated Substations." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 2 (April 10, 2021): 1025–39. http://dx.doi.org/10.17762/turcomat.v12i2.1117.

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: in gas insulated substations, issue of very fast transient over voltages is very familiar problem because of its effects on live ultra-high voltage equipment. During switching events of disconnectors and circuit breakers prestrikes and restrikes occur due to which voltage transients propagate through gas insulated switchgear. Reflection retraction of these transients increases voltage magnitude and generates very high frequency oscillations. Mitigation or suppression of these voltage transients is important to protect equipment and their dielectric strength and insulation. Due to very high frequency stress, they wield on the apparatus and their magnitude (up to 3.5pu), they create an important problem in the design of ultra-high voltage Gas Insulated Substations. In this paper nanocrystalline based mitigation technique for VFTOs is presented. Nanocrystalline rings can be placed around inner conductor of GIS switchgear. This method of mitigation technique is investigated with four ultra-high voltage substations simulation test setup. Simulation results are presented in MATLAB/SIMULINK

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Aurilio, Gianluca, Marco Balato, Giorgio Graditi, Carmine Landi, Mario Luiso, and Massimo Vitelli. "Fast Hybrid MPPT Technique for Photovoltaic Applications: Numerical and Experimental Validation." Advances in Power Electronics 2014 (June 3, 2014): 1–15. http://dx.doi.org/10.1155/2014/125918.

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In PV applications, under mismatching conditions, it is necessary to adopt a maximum power point tracking (MPPT) technique which is able to regulate not only the voltages of the PV modules of the array but also the DC input voltage of the inverter. Such a technique can be considered a hybrid MPPT (HMPPT) technique since it is neither only distributed on the PV modules of the PV array or only centralized at the input of the inverter. In this paper a new HMPPT technique is presented and discussed. Its main advantages are the high MPPT efficiency and the high speed of tracking which are obtained by means of a fast estimate of the optimal values of PV modules voltages and of the input inverter voltage. The new HMPPT technique is compared with simple HMPPT techniques based on the scan of the power versus voltage inverter input characteristic. The theoretical analysis and the results of numerical simulations are widely discussed. Moreover, a laboratory test system, equipped with PV emulators, has been realized and used in order to experimentally validate the proposed technique.

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Kadom, Haider Fathi, Ali Nasser Hussain, and Waleed Khalid Shakir Al-Jubori. "Dual technique of reconfiguration and capacitor placement for distribution system." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 1 (February 1, 2020): 80. http://dx.doi.org/10.11591/ijece.v10i1.pp80-90.

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Radial Distribution System (RDS) suffer from high real power losses and lower bus voltages. Distribution System Reconfiguration (DSR) and Optimal Capacitor Placement (OCP) techniques are ones of the most economic and efficient approaches for loss reduction and voltage profile improvement while satisfy RDS constraints. The advantages of these two approaches can be concentrated using of both techniques together. In this study two techniques are used in different ways. First, the DSR technique is applied individually. Second, the dual technique has been adopted of DSR followed by OCP in order to identify the technique that provides the most eﬀective performance. Three optimization algorithms have been used to obtain the optimal design in individual and dual technique. Two IEEE case studies (33bus, and 69 bus) used to check the effectiveness of proposed approaches. A Direct Backward Forward Sweep Method (DBFSM) has been used in order to calculate the total losses and voltage of each bus. Results show the capability of the proposed dual technique using Modified Biogeography Based Optimization (MBBO) algorithm to find the optimal solution for significant loss reduction and voltage profile enhancement. In addition, comparisons with literature works done to show the superiority of proposed algorithms in both techniques.

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KIROLOS, SAMI, and YEHIA MASSOUD. "DYNAMIC VOLTAGE SCALING CONTINUOUS ADAPTIVE-SIZE CELL DESIGN TECHNIQUE." Journal of Circuits, Systems and Computers 17, no. 05 (October 2008): 871–83. http://dx.doi.org/10.1142/s0218126608004630.

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In this paper, we present an adaptive circuit design that is capable of increasing the effective size-ratio of combinational logic gates to extend the balanced operation in the subthreshold region as well as to maintain high performance at the nominal VDD. We optimize the sizes of the PMOS transistors in the pull-up network for minimum power dissipation and propagation delay over a wide range of supply voltage. In addition to the minimized energy operation, the dynamically adjustable gate size-ratio allows the gate to preserve a symmetric voltage transfer characteristic at both normal supply and subthreshold operation, which translates to maximized noise margins. Simulation results show that up to 70.9% reduction in the energy can be achieved for a ring oscillator, as compared to the fixed size design capable of operating under supply voltage in the range of 75 mV to 1.2 V. For designs working under dynamic voltage scaling schemes, our technique presents a very effective and efficient solution for balanced minimum energy operation in the subthreshold region while preserving high performance at the nominal supply voltage.

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A. Rahiman, Riyaz, and M. C. John Wiselin. "Implementation of a Novel Control Technique in Landsman Converter Using Bumble Bee Optimization." International Journal of Engineering & Technology 7, no. 3.27 (August 15, 2018): 339. http://dx.doi.org/10.14419/ijet.v7i3.27.17968.

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This paper focuses on a solar PV array based BLDC motor employing Landsman converter under partial shading condition (PSC). A converter acts as an interface between the SPV array under PSC and Voltage Source Inverter (VSI) feeding the Brushless DC (BLDC) motor. BLDC motor incorporating the merits of higher efficiency, high reliability, high ruggedness, easy-to-drive, capability to operate successfully at low voltage and excellent performance over a wide range of speed. The speed control of BLDC motor by variable DC-link voltage. This eliminates the additional phase current sensing, DC-link voltage sensing, additional control and associated circuitry. The proposed system includes simplicity control, compactness, and soft starting of the BLDC motor. The operation of Landsman converter in CCM results reduced stress on devices. To optimize the operating point of the SPV array in order to get maximum possible power output by means of the better maximum power point tracking (MPPT) technique. The technique is Bumble Bee Mating Optimization (BBMO) based MPPT. The novel technique is compared to the conventional techniques. The simulated results are executed in MATLAB/SIMULINK.

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Yurish, Sergey Y. "Advanced Analog-to-Digital Conversion Using Voltage-to-Frequency Converters for Remote Sensors." Key Engineering Materials 381-382 (June 2008): 623–26. http://dx.doi.org/10.4028/www.scientific.net/kem.381-382.623.

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This paper presents an advanced analog-to-digital conversion technique based on a voltage-to-frequency-to-digital conversion that is suitable for remote sensors, telemetry applications and multichannel data acquisition systems. A voltage-to-frequency conversion part can be based, for example, on high performance, charge-balance voltage-to-frequency converter (VFC), where monostable is replaced by a bistable, driven by an external clock, or other existing high performance VFCs. The frequency-to-digital converter “bottleneck” problem in such promised ADC scheme was solved due to proposed advanced method of the dependent count for frequency-to-digital conversion. This ADC technique lets receive many advantages such as high accuracy, relatively low power consumption, low cost solution, wide dynamic range, great stability and faster conversion time in comparison with existing VFC-based techniques. The conversion rate (6.25 µs to 6.25 ms) in such ADC scheme is programmable, non-redundant, shorter than for pulse counting technique and comparable with successive-approximation and Σ- ADC.

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Abbott, R. S., J. P. Ellul, R. A. Hadaway, and J. J. White. "High-voltage n-channel metal-oxide-semiconductor technology." Canadian Journal of Physics 63, no. 6 (June 1, 1985): 897–900. http://dx.doi.org/10.1139/p85-147.

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High-voltage devices have been integrated into a standard silicon-gate NMOS IC fabrication process utilizing a novel front-end processing technique. Fabrication-process steps and modelling results are described in this paper. Driver transistors are characterized in terms of drift-region implant dose, design parameters, and substrate resistivities. Present work has optimized process parameters and device structures to yield "off" state breakdown up to 270 V for 6–10 Ω∙cm, p-type, [Formula: see text] substrates.

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