Dissertations / Theses on the topic 'High Voltage High Pulse Power Switch'

This work is concerned with power inverters for alternate high voltage power sources. The theoretical part describes the topology of inverters that can be used in alternate power sources. A model of voltage transformer is described in details to better understand the parasitic effects that are inevitably present in high voltage power sources and, therefore, have to be taken into consideration at the design of high voltage power sources. The work is oriented to problems of alternate high voltage power sources for ozone generators. This is the reason, why the theoretical and, partially, also the experimental part deal with the properties of ozone and its use. The experimental part solves high voltage inverter with capacitive load that is formed by discharge element of an ozone generator. Designed inverter is able to feed the capacitive load with high voltage at very short periods of time from several microseconds up to tens of nanoseconds. In comparison with the length of voltage pulses in common ozone generators, this pulses are more than 100-time shorter. This has a positive effect to silent discharge characteristics.

Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.
Includes bibliographical references (p. 145).
by John Israel Rodriguez.
M.Eng.

Thesis (M.S.)--University of Missouri-Columbia, 2006.
The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on April 22, 2009) Includes bibliographical references.

The main contribution of this project was to investigate power electronics technology in designing and developing high frequency high power converters for industrial applications. Therefore, the research was conducted at two levels; first at system level which mainly encapsulated the circuit topology and control scheme and second at application level which involves with real-world applications. Pursuing these objectives, varied topologies have been developed and proposed within this research. The main aim was to resolving solid-state switches limited power rating and operating speed while increasing the system flexibility considering the application characteristics. The developed new power converter configurations were applied to pulsed power and high power ultrasound applications for experimental validation.

Demands for delivering high instantaneous power in a compressed form (pulse shape) have widely increased during recent decades. The flexible shapes with variable pulse specifications offered by pulsed power have made it a practical and effective supply method for an extensive range of applications. In particular, the release of basic subatomic particles (i.e. electron, proton and neutron) in an atom (ionization process) and the synthesizing of molecules to form ions or other molecules are among those reactions that necessitate large amount of instantaneous power. In addition to the decomposition process, there have recently been requests for pulsed power in other areas such as in the combination of molecules (i.e. fusion, material joining), gessoes radiations (i.e. electron beams, laser, and radar), explosions (i.e. concrete recycling), wastewater, exhausted gas, and material surface treatments. These pulses are widely employed in the silent discharge process in all types of materials (including gas, fluid and solid); in some cases, to form the plasma and consequently accelerate the associated process. Due to this fast growing demand for pulsed power in industrial and environmental applications, the exigency of having more efficient and flexible pulse modulators is now receiving greater consideration. Sensitive applications, such as plasma fusion and laser guns also require more precisely produced repetitive pulses with a higher quality. Many research studies are being conducted in different areas that need a flexible pulse modulator to vary pulse features to investigate the influence of these variations on the application. In addition, there is the need to prevent the waste of a considerable amount of energy caused by the arc phenomena that frequently occur after the plasma process. The control over power flow during the supply process is a critical skill that enables the pulse supply to halt the supply process at any stage. Different pulse modulators which utilise different accumulation techniques including Marx Generators (MG), Magnetic Pulse Compressors (MPC), Pulse Forming Networks (PFN) and Multistage Blumlein Lines (MBL) are currently employed to supply a wide range of applications. Gas/Magnetic switching technologies (such as spark gap and hydrogen thyratron) have conventionally been used as switching devices in pulse modulator structures because of their high voltage ratings and considerably low rising times. However, they also suffer from serious drawbacks such as, their low efficiency, reliability and repetition rate, and also their short life span. Being bulky, heavy and expensive are the other disadvantages associated with these devices. Recently developed solid-state switching technology is an appropriate substitution for these switching devices due to the benefits they bring to the pulse supplies. Besides being compact, efficient, reasonable and reliable, and having a long life span, their high frequency switching skill allows repetitive operation of pulsed power supply. The main concerns in using solid-state transistors are the voltage rating and the rising time of available switches that, in some cases, cannot satisfy the application’s requirements. However, there are several power electronics configurations and techniques that make solid-state utilisation feasible for high voltage pulse generation. Therefore, the design and development of novel methods and topologies with higher efficiency and flexibility for pulsed power generators have been considered as the main scope of this research work. This aim is pursued through several innovative proposals that can be classified under the following two principal objectives. • To innovate and develop novel solid-state based topologies for pulsed power generation • To improve available technologies that have the potential to accommodate solid-state technology by revising, reconfiguring and adjusting their structure and control algorithms. The quest to distinguish novel topologies for a proper pulsed power production was begun with a deep and through review of conventional pulse generators and useful power electronics topologies. As a result of this study, it appears that efficiency and flexibility are the most significant demands of plasma applications that have not been met by state-of-the-art methods. Many solid-state based configurations were considered and simulated in order to evaluate their potential to be utilised in the pulsed power area. Parts of this literature review are documented in Chapter 1 of this thesis. Current source topologies demonstrate valuable advantages in supplying the loads with capacitive characteristics such as plasma applications. To investigate the influence of switching transients associated with solid-state devices on rise time of pulses, simulation based studies have been undertaken. A variable current source is considered to pump different current levels to a capacitive load, and it was evident that dissimilar dv/dts are produced at the output. Thereby, transient effects on pulse rising time are denied regarding the evidence acquired from this examination. A detailed report of this study is given in Chapter 6 of this thesis. This study inspired the design of a solid-state based topology that take advantage of both current and voltage sources. A series of switch-resistor-capacitor units at the output splits the produced voltage to lower levels, so it can be shared by the switches. A smart but complicated switching strategy is also designed to discharge the residual energy after each supply cycle. To prevent reverse power flow and to reduce the complexity of the control algorithm in this system, the resistors in common paths of units are substituted with diode rectifiers (switch-diode-capacitor). This modification not only gives the feasibility of stopping the load supply process to the supplier at any stage (and consequently saving energy), but also enables the converter to operate in a two-stroke mode with asymmetrical capacitors. The components’ determination and exchanging energy calculations are accomplished with respect to application specifications and demands. Both topologies were simply modelled and simulation studies have been carried out with the simplified models. Experimental assessments were also executed on implemented hardware and the approaches verified the initial analysis. Reports on details of both converters are thoroughly discussed in Chapters 2 and 3 of the thesis. Conventional MGs have been recently modified to use solid-state transistors (i.e. Insulated gate bipolar transistors) instead of magnetic/gas switching devices. Resistive insulators previously used in their structures are substituted by diode rectifiers to adjust MGs for a proper voltage sharing. However, despite utilizing solid-state technology in MGs configurations, further design and control amendments can still be made to achieve an improved performance with fewer components. Considering a number of charging techniques, resonant phenomenon is adopted in a proposal to charge the capacitors. In addition to charging the capacitors at twice the input voltage, triggering switches at the moment at which the conducted current through switches is zero significantly reduces the switching losses. Another configuration is also introduced in this research for Marx topology based on commutation circuits that use a current source to charge the capacitors. According to this design, diode-capacitor units, each including two Marx stages, are connected in cascade through solid-state devices and aggregate the voltages across the capacitors to produce a high voltage pulse. The polarity of voltage across one capacitor in each unit is reversed in an intermediate mode by connecting the commutation circuit to the capacitor. The insulation of input side from load side is provided in this topology by disconnecting the load from the current source during the supply process. Furthermore, the number of required fast switching devices in both designs is reduced to half of the number used in a conventional MG; they are replaced with slower switches (such as Thyristors) that need simpler driving modules. In addition, the contributing switches in discharging paths are decreased to half; this decrease leads to a reduction in conduction losses. Associated models are simulated, and hardware tests are performed to verify the validity of proposed topologies. Chapters 4, 5 and 7 of the thesis present all relevant analysis and approaches according to these topologies.

Thesis (M.S.)--University of Missouri-Columbia, 2007.
The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on March 18, 2008) Includes bibliographical references.

The Queensland University of Technology (QUT) allows the presentation of theses for the Degree of Doctor of Philosophy in the format of published or submitted papers, where such papers have been published, accepted or submitted during the period of candidature. This thesis is composed of ten published /submitted papers and book chapters of which nine have been published and one is under review. This project is financially supported by an Australian Research Council (ARC) Discovery Grant with the aim of investigating multilevel topologies for high quality and high power applications, with specific emphasis on renewable energy systems. The rapid evolution of renewable energy within the last several years has resulted in the design of efficient power converters suitable for medium and high-power applications such as wind turbine and photovoltaic (PV) systems. Today, the industrial trend is moving away from heavy and bulky passive components to power converter systems that use more and more semiconductor elements controlled by powerful processor systems. However, it is hard to connect the traditional converters to the high and medium voltage grids, as a single power switch cannot stand at high voltage. For these reasons, a new family of multilevel inverters has appeared as a solution for working with higher voltage levels. Besides this important feature, multilevel converters have the capability to generate stepped waveforms. Consequently, in comparison with conventional two-level inverters, they present lower switching losses, lower voltage stress across loads, lower electromagnetic interference (EMI) and higher quality output waveforms. These properties enable the connection of renewable energy sources directly to the grid without using expensive, bulky, heavy line transformers. Additionally, they minimize the size of the passive filter and increase the durability of electrical devices. However, multilevel converters have only been utilised in very particular applications, mainly due to the structural limitations, high cost and complexity of the multilevel converter system and control. New developments in the fields of power semiconductor switches and processors will favor the multilevel converters for many other fields of application. The main application for the multilevel converter presented in this work is the front-end power converter in renewable energy systems. Diode-clamped and cascade converters are the most common type of multilevel converters widely used in different renewable energy system applications. However, some drawbacks – such as capacitor voltage imbalance, number of components, and complexity of the control system – still exist, and these are investigated in the framework of this thesis. Various simulations using software simulation tools are undertaken and are used to study different cases. The feasibility of the developments is underlined with a series of experimental results. This thesis is divided into two main sections. The first section focuses on solving the capacitor voltage imbalance for a wide range of applications, and on decreasing the complexity of the control strategy on the inverter side. The idea of using sharing switches at the output structure of the DC-DC front-end converters is proposed to balance the series DC link capacitors. A new family of multioutput DC-DC converters is proposed for renewable energy systems connected to the DC link voltage of diode-clamped converters. The main objective of this type of converter is the sharing of the total output voltage into several series voltage levels using sharing switches. This solves the problems associated with capacitor voltage imbalance in diode-clamped multilevel converters. These converters adjust the variable and unregulated DC voltage generated by renewable energy systems (such as PV) to the desirable series multiple voltage levels at the inverter DC side. A multi-output boost (MOB) converter, with one inductor and series output voltage, is presented. This converter is suitable for renewable energy systems based on diode-clamped converters because it boosts the low output voltage and provides the series capacitor at the output side. A simple control strategy using cross voltage control with internal current loop is presented to obtain the desired voltage levels at the output voltage. The proposed topology and control strategy are validated by simulation and hardware results. Using the idea of voltage sharing switches, the circuit structure of different topologies of multi-output DC-DC converters – or multi-output voltage sharing (MOVS) converters – have been proposed. In order to verify the feasibility of this topology and its application, steady state and dynamic analyses have been carried out. Simulation and experiments using the proposed control strategy have verified the mathematical analysis. The second part of this thesis addresses the second problem of multilevel converters: the need to improve their quality with minimum cost and complexity. This is related to utilising asymmetrical multilevel topologies instead of conventional multilevel converters; this can increase the quality of output waveforms with a minimum number of components. It also allows for a reduction in the cost and complexity of systems while maintaining the same output quality, or for an increase in the quality while maintaining the same cost and complexity. Therefore, the asymmetrical configuration for two common types of multilevel converters – diode-clamped and cascade converters – is investigated. Also, as well as addressing the maximisation of the output voltage resolution, some technical issues – such as adjacent switching vectors – should be taken into account in asymmetrical multilevel configurations to keep the total harmonic distortion (THD) and switching losses to a minimum. Thus, the asymmetrical diode-clamped converter is proposed. An appropriate asymmetrical DC link arrangement is presented for four-level diode-clamped converters by keeping adjacent switching vectors. In this way, five-level inverter performance is achieved for the same level of complexity of the four-level inverter. Dealing with the capacitor voltage imbalance problem in asymmetrical diodeclamped converters has inspired the proposal for two different DC-DC topologies with a suitable control strategy. A Triple-Output Boost (TOB) converter and a Boost 3-Output Voltage Sharing (Boost-3OVS) converter connected to the four-level diode-clamped converter are proposed to arrange the proposed asymmetrical DC link for the high modulation indices and unity power factor. Cascade converters have shown their abilities and strengths in medium and high power applications. Using asymmetrical H-bridge inverters, more voltage levels can be generated in output voltage with the same number of components as the symmetrical converters. The concept of cascading multilevel H-bridge cells is used to propose a fifteen-level cascade inverter using a four-level H-bridge symmetrical diode-clamped converter, cascaded with classical two-level Hbridge inverters. A DC voltage ratio of cells is presented to obtain maximum voltage levels on output voltage, with adjacent switching vectors between all possible voltage levels; this can minimize the switching losses. This structure can save five isolated DC sources and twelve switches in comparison to conventional cascade converters with series two-level H bridge inverters. To increase the quality in presented hybrid topology with minimum number of components, a new cascade inverter is verified by cascading an asymmetrical four-level H-bridge diode-clamped inverter. An inverter with nineteen-level performance was achieved. This synthesizes more voltage levels with lower voltage and current THD, rather than using a symmetrical diode-clamped inverter with the same configuration and equivalent number of power components. Two different predictive current control methods for the switching states selection are proposed to minimise either losses or THD of voltage in hybrid converters. High voltage spikes at switching time in experimental results and investigation of a diode-clamped inverter structure raised another problem associated with high-level high voltage multilevel converters. Power switching components with fast switching, combined with hard switched-converters, produce high di/dt during turn off time. Thus, stray inductance of interconnections becomes an important issue and raises overvoltage and EMI issues correlated to the number of components. Planar busbar is a good candidate to reduce interconnection inductance in high power inverters compared with cables. The effect of different transient current loops on busbar physical structure of the high-voltage highlevel diode-clamped converters is highlighted. Design considerations of proper planar busbar are also presented to optimise the overall design of diode-clamped converters.

Control of a low voltage ac/dc/ac converter for high-speed induction machine drive applications has been investigated. Such a configuration can be applied, for example, in microturbines and high-speed spindles. Scalar control is usually applied for the control of high-speed drives especially in the case of very high-speed drives. Indirect rotor-flux-oriented control and direct torque control are designed and compared for the control of an exemplary high-speed induction machine drive. The 2L VSC is the most widely applied converter for high-speed drives. However, the 3L-NPC VSC is an attractive topology if drastically increased switching frequencies are required. A detailed comparison between a 2L VSC and a 3L-NPC VSC as the machine side converter of the exemplary high-speed induction machine drive is carried out. Voltage-oriented control is applied for the control of the grid side PWM active front end converter. In several industrial applications PWM active front end converters commonly operate in parallel to thyristor converter fed dc drives. Behavior of the voltage-oriented controlled active front end converter with L-filter in the presence of a parallel thyristor converter is investigated. The design of the LCL-filter components according to the given maximum grid current harmonics (e.g. IEEE-519) is a complex task. So far a precise and clear design procedure has not been presented. A new procedure to design the grid side filter (L- and LCL-filter) is proposed using the analytical expression of the converter voltage harmonics based on Bessel functions to achieve the compliance with the grid standard of IEEE-519. Voltage-oriented control with active damping is used to control the active front end converter with LCL-filter. A simple method is proposed to design the required lead-lag compensator in the active damping loop.

Tato dizertační práce představuje novou techniku laterární rezonanční vazby, která je využita v návrhu galvanicky izolovaného posouvače úrovně, který je následně implementován v 800 V půlmůstkovém kontroléru pro průmyslové aplikace. Ve srovnání s tradičními galvanickými izolátory jsou výrobní náklady tohoto řešení nižší. Pro aplikace vyžadující vyšší úroveň galvanické izolace je popsán následný vývoj galvanicky izolovaného posouvače úrovně, který využívá pouze jeden galvanicky oddělený posouvač úrovní pro komunikaci v obou směrech, což výrazně snižuje plochu struktury izolátoru. Jako součást následného návrhu je představen galvanický izolátor který je schopen přenášet analogovou hodnotu napětí. Analogový izolátor byl testován v reálné aplikaci síťového spínaného zdroje jako náhrada standardního optočlenu. Tato konstrukce umožňuje integraci primárních a sekundárních obvodů v jednom pouzdře, což umožní snížit složitost a cenu spínaného zdroje.

The ability of a piezoelectric transducer in energy conversion is rapidly expanding in several applications. Some of the industrial applications for which a high power ultrasound transducer can be used are surface cleaning, water treatment, plastic welding and food sterilization. Also, a high power ultrasound transducer plays a great role in biomedical applications such as diagnostic and therapeutic applications. An ultrasound transducer is usually applied to convert electrical energy to mechanical energy and vice versa. In some high power ultrasound system, ultrasound transducers are applied as a transmitter, as a receiver or both. As a transmitter, it converts electrical energy to mechanical energy while a receiver converts mechanical energy to electrical energy as a sensor for control system. Once a piezoelectric transducer is excited by electrical signal, piezoelectric material starts to vibrate and generates ultrasound waves. A portion of the ultrasound waves which passes through the medium will be sensed by the receiver and converted to electrical energy. To drive an ultrasound transducer, an excitation signal should be properly designed otherwise undesired signal (low quality) can deteriorate the performance of the transducer (energy conversion) and increase power consumption in the system. For instance, some portion of generated power may be delivered in unwanted frequency which is not acceptable for some applications especially for biomedical applications. To achieve better performance of the transducer, along with the quality of the excitation signal, the characteristics of the high power ultrasound transducer should be taken into consideration as well. In this regard, several simulation and experimental tests are carried out in this research to model high power ultrasound transducers and systems. During these experiments, high power ultrasound transducers are excited by several excitation signals with different amplitudes and frequencies, using a network analyser, a signal generator, a high power amplifier and a multilevel converter. Also, to analyse the behaviour of the ultrasound system, the voltage ratio of the system is measured in different tests. The voltage across transmitter is measured as an input voltage then divided by the output voltage which is measured across receiver. The results of the transducer characteristics and the ultrasound system behaviour are discussed in chapter 4 and 5 of this thesis. Each piezoelectric transducer has several resonance frequencies in which its impedance has lower magnitude as compared to non-resonance frequencies. Among these resonance frequencies, just at one of those frequencies, the magnitude of the impedance is minimum. This resonance frequency is known as the main resonance frequency of the transducer. To attain higher efficiency and deliver more power to the ultrasound system, the transducer is usually excited at the main resonance frequency. Therefore, it is important to find out this frequency and other resonance frequencies. Hereof, a frequency detection method is proposed in this research which is discussed in chapter 2. An extended electrical model of the ultrasound transducer with multiple resonance frequencies consists of several RLC legs in parallel with a capacitor. Each RLC leg represents one of the resonance frequencies of the ultrasound transducer. At resonance frequency the inductor reactance and capacitor reactance cancel out each other and the resistor of this leg represents power conversion of the system at that frequency. This concept is shown in simulation and test results presented in chapter 4. To excite a high power ultrasound transducer, a high power signal is required. Multilevel converters are usually applied to generate a high power signal but the drawback of this signal is low quality in comparison with a sinusoidal signal. In some applications like ultrasound, it is extensively important to generate a high quality signal. Several control and modulation techniques are introduced in different papers to control the output voltage of the multilevel converters. One of those techniques is harmonic elimination technique. In this technique, switching angles are chosen in such way to reduce harmonic contents in the output side. It is undeniable that increasing the number of the switching angles results in more harmonic reduction. But to have more switching angles, more output voltage levels are required which increase the number of components and cost of the converter. To improve the quality of the output voltage signal with no more components, a new harmonic elimination technique is proposed in this research. Based on this new technique, more variables (DC voltage levels and switching angles) are chosen to eliminate more low order harmonics compared to conventional harmonic elimination techniques. In conventional harmonic elimination method, DC voltage levels are same and only switching angles are calculated to eliminate harmonics. Therefore, the number of eliminated harmonic is limited by the number of switching cycles. In the proposed modulation technique, the switching angles and the DC voltage levels are calculated off-line to eliminate more harmonics. Therefore, the DC voltage levels are not equal and should be regulated. To achieve this aim, a DC/DC converter is applied to adjust the DC link voltages with several capacitors. The effect of the new harmonic elimination technique on the output quality of several single phase multilevel converters is explained in chapter 3 and 6 of this thesis. According to the electrical model of high power ultrasound transducer, this device can be modelled as parallel combinations of RLC legs with a main capacitor. The impedance diagram of the transducer in frequency domain shows it has capacitive characteristics in almost all frequencies. Therefore, using a voltage source converter to drive a high power ultrasound transducer can create significant leakage current through the transducer. It happens due to significant voltage stress (dv/dt) across the transducer. To remedy this problem, LC filters are applied in some applications. For some applications such as ultrasound, using a LC filter can deteriorate the performance of the transducer by changing its characteristics and displacing the resonance frequency of the transducer. For such a case a current source converter could be a suitable choice to overcome this problem. In this regard, a current source converter is implemented and applied to excite the high power ultrasound transducer. To control the output current and voltage, a hysteresis control and unipolar modulation are used respectively. The results of this test are explained in chapter 7.

Une étude sur la réduction/suppression de l'inductance de limitation di/dt pour IGCTs et du clamp RCD en utilisant des diodes rapides en silicium (Si) et des diodes en carbure de silicium (SiC) dans les convertisseurs multiniveaux modulaires (MMC). Cette thèse contient :- Analyse des sous-modules de MMC HVDC existants.- Évaluation de l'intérêt des IGCTs dans les sous-modules MMC HVDC et comparaison des pertes avec les IGBT, en utilisant des facteurs de mérite spécifiques aux MMC créés dans cette thèse.- Test de double pulse avec diode à récupération rapide dans un module plastique pour tenter de réduire et supprimer l'inductance limitant le di/dt.- Packaging de puces de diodes SiC PiN à haute tension et courant élevé, test avec IGCT dans le même montage, pour tenter de réduire et supprimer l'inductance limite di/dt, et analyser les spécificités de la diode SiC dans ce montage
A study on Integrated gate-commutated thyristors (IGCT) di/dt limiting inductance and RCD-clamp reduction/suppression using plastic module silicon (Si) fast recovery diodes and silicon carbide (SiC) diodes, in Modular Multilevel Converters (MMC). This PhD contains:- Analysis of existing HVDC MMC Submodules.- Assessment of the interest of the IGCT in HVDC MMC Submodules and losses comparison with IGBTs, using MMC-specific figures-of-merit created in this thesis.- Double pulse test with fast recovery diode in plastic module to attempt to reduce and suppress the limiting di/dt inductor.- Packaging of High-Voltage High-Current SiC PiN diode dies, test with IGCT in the same setup to attempt to reduce and suppress the limiting di/dt inductor and analyze the specificities of the SiC diode in this setup

L’urgence énergétique mondiale impose d’utiliser des systèmes plus économes en énergie. De plus, il devient nécessaire d’effectuer une transition énergétique vers des technologies rejetant moins de gaz à effet de serre. Pour ces raisons, les technologies à base de puissances pulsées auront un rôle à jouer dans le panel énergétique de demain.De nombreuses ressources se situent sous la surface de notre planète (eau, gaz, énergies fossiles, minéraux précieux, énergie géothermique ...). De plus, l’urbanisation de nos villes avec le développement des moyens de transport, du traitement des eaux usées, des réseaux électriques et de chaleurs nous pousse à exploiter l’espace sous terrain. Pour cette exploitation, la mise en place de méthodes industrielles est inévitable pour permettre un avancement rapide, économe en énergie et à moindre coût de production. Les méthodes actuelles de concassage, fracturation ou forage se heurtent néanmoins à une faible vitesse de production lors du traitement de roches dures et abrasives. La fracturation dite électrique pourrait être une méthode alternative. Cette technique utilise des décharges électriques dans des fluides pour concasser les roches.L’objet de cette thèse est d’établir une base de données expérimentales pour la compréhension, la prédiction et l’optimisation du processus. Il s’agit plus particulièrement d’étudier l’influence de l’ensemble des paramètres liés à la fois aux propriétés du milieu (température, conductivité et pression) et aux caractéristiques du circuit électrique sur la rigidité diélectrique des isolants testés. Une attention particulière est portée à la maîtrise de la phénoménologie de la décharge dans ces conditions expérimentales.Dans ce manuscrit, les décharges électriques sont caractérisées à partir d’essais expérimentaux qui sont interprétés par l’intermédiaire d’études théoriques et de simulations numériques. Dans un premier temps, la tension minimale nécessaire pour amorcer un arc est déterminée par la méthode U50 et sa consommation d’énergie associée est calculée. Ces essais sont réalisés à la fois en fonction des paramètres internes au système d’impulsions (énergie stockée, tension d’alimentation et géométrie des électrodes) et aussi en fonction de paramètres externes (conductivité, pression et température du milieu). Dans un second temps, le seuil de champ électrique qui permet de changer de mode de claquage est déterminé en fonction des paramètres externes au système d‘impulsions. Cette transition entre le mode subsonique et le mode supersonique est déterminée à partir du temps de propagation de la décharge électrique et de la consommation d’énergie pendant la phase de pré-arc. Les conditions menant à l’amorçage de l’arc électrique dans les fluides ou dans les roches sont comparées. Une attention particulière est donnée à la résistance de l’arc et au courant maximal qui définissent la puissance transmise au milieu
The global energy emergency requires more energy-efficient systems. In addition, it is necessary to make an energy transition to technologies that emit less greenhouse gases. For these reasons, pulse power technologies will have a role to play in tomorrow’s energy mix.Many resources are located below the surface of our planet (water, gas, fossil fuels, precious minerals, geothermal energy...). In addition, the urbanization of our cities with the development of means of transport, wastewater treatment, electricity and heat networks pushes us to exploit the underground space. For this operation, the implementation of industrial methods is inevitable in allowing a fast, energy-efficient and low-cost production. However, current methods of crushing, fracturing or drilling encounter a low production rate when processing hard and abrasive rocks. The fracturing method called electric fracturing could be an alternative method. This method uses electrical discharges in fluids to crush rocks.The purpose of this thesis is to establish an experimental database for understanding, predicting and optimizing the process. In particular, the influence of all parameters related to both the properties of the medium (temperature, conductivity and pressure) and the characteristics of the electrical circuit on the insulators dielectric strength tested must be studied. Particular attention is paid to controlling the phenomenology of the landfill under these experimental conditions.In this manuscript, electrical discharges are characterized on the basis of experimental tests that are interpreted through theoretical studies and numerical simulations. First, the minimum voltage required to initiate an arc is determined by the U50 method and its associated energy consumption is calculated. These tests are performed both according to the internal parameters of the pulse system (stored energy, supply voltage and electrode geometry) and also according to external parameters (conductivity, pressure and temperature of the medium). In a second step, the electric field threshold that allows to change the breakdown mode is determined according to the parameters external to the pulse system. This transition from subsonic to supersonic mode is determined from the propagation time of the electrical discharge and the energy consumption during the pre-arc phase. The conditions leading to the initiation of the electric arc in fluids or rocks are compared. Particular attention is paid to the arc resistance and maximum current that define the power transmitted in the medium

The project shows the problems of power supply in electrical engineering. It describes the general parameters of these types of supplies and presents their characteristics. Based on these findings, it is also focused on the selection of specific elements of the laboratory supply, to reach the given parameters. It contains the recalculations of the parameters of other additional components. The overall scheme of the supply is divided into several blocks, thematically corresponded to subchapters. According to the accomplished concept the laboratory supply is realized and its parameters had been tested. Projects results are assessed at the end.

Depuis plus d'une trentaine d'années, la menace d'impulsion électromagnétique provoquée par une explosion à haute altitude (IEMN-HA) d'une arme nucléaire est un sujet d'actualité avec les préoccupations croissantes de sécurité. L'IEMN-HA se couple de manière privilégiée sur les lignes aériennes de distribution en électricité permettant d'alimenter les habitations et les usines. Une fois couplée à ces lignes, la contrainte générée peut alors se propager de façon conduite jusqu'aux premiers systèmes qu'elle rencontrera, et les perturber voire les détruire. Dans la majorité des cas, ces systèmes sont les alimentations des appareils domestiques ou industriels. Dans ce cadre, les effets de destruction d'alimentations électroniques lors de l'injection d'un courant impulsionnel de forte amplitude sont étudiés grâce à un moyen d'injection appelé PIC pour Plateforme d'Injection en Courant. Une alimentation à découpage de type flyback, représentative d'une majorité des alimentations actuelles, a été conçue pour la thèse afin de maîtriser entièrement sa topologie et ses constituants. Les composants les plus susceptibles dans une alimentation à découpage ont été mis en évidence, et il a été montré qu'ils sont détruits à cause d'une amplitude trop importante de courant pendant une durée excessive par rapport aux maximums de leurs capacités. Des analyses aux rayons~X et au microscope optique ont été réalisées sur les composants pour aider à la compréhension. Celles-ci ont permis de fournir des premières hypothèses sur la cause de leur destruction, qui ont ensuite été confirmées par des mesures de courants et de tensions autour de chaque composant lors de l'injection de l'impulsion en entrée de l'alimentation. Enfin, le moyen d'injection ainsi que l'alimentation conçue ont été modélisés sous un logiciel de simulation électronique de type Spice. Cette thèse est la première étape d'un travail dont l'objectif final est de modéliser la susceptibilité des alimentations à découpage afin de prédire leur niveau de destruction
For thirty years, the threat of electromagnetic pulses caused by a high-altitude nuclear explosion (NEMP / HEMP) is still an actual concern in the field of security and safety. NEMP couples efficiently on aerial lines of the electricity network allowing to supply houses and factories. Once coupled to these lines, the generated interference can then be propagated to the first encountered systems and disturb or destroy them. In most cases, these systems are household or industries appliances power supplies. In this context, destruction effects of electronic power supplies due to high level current pulse injectionare studied thanks to an injection generator called PIC for Current Injection Platform. A flyback switch mode power supply (SMPS), representative of a majority of common power supplies, has been designed for the thesis in order to fully control its topology and components. The most susceptible components in SMPS have been identified and have been destroyed due to a too high level current over an excessive duration compared to their maximum ratings. These understandings have been supported by X-rays and optical microscope analyzes. These ones allowed to provide first hypotheses on their destruction cause, which were then confirmed by current and voltage measurements on each component during the pulse injection. Finally, PIC and the designed SMPS have been modeled using a Spice electronic simulation software. This thesis is the first step of a work whose final objective is to model the susceptibility of SMPS in order to predict their destruction level

L’émergence d’interrupteurs de puissance en SiC permet d’envisager des convertisseurs de puissance capables de fonctionner au sein des environnements sévères tels que la haute tension (> 10 kV ) et la haute température (> 300 °C). Aucune solution de commande spécifique à ces environnements n’existe pour le moment. Le développement de fonctions élémentaires en SiC (comparateur, oscillateur) est une étape préliminaire à la réalisation d’un premier démonstrateur. Plusieurs laboratoires ont développé des fonctions basées sur des transistors bipolaires, MOSFETs ou JFETs. Cependant les recherches ont principalement portées sur la conception de fonctions logiques et non sur l’intégration de drivers de puissance. Le laboratoire AMPERE (INSA de Lyon) et le Centre National de Microélectronique de Barcelone (Espagne) ont conçu un MESFET latéral double grille en SiC. Ce composant élémentaire sera à la base des différentes fonctions intégrées envisagées. L’objectif de ces recherches est la réalisation d’un convertisseur élévateur de tension "boost" monolithique et de sa commande en SiC. La démarche scientifique a consisté à définir dans un premier temps un modèle de simulation SPICE du MESFET SiC à partir de caractérisations électriques statique et dynamique. En se basant sur ce modèle, des circuits analogiques tels que des amplificateurs, oscillateurs, paires différentielles, trigger de Schmitt ont été conçus pour élaborer le circuit de commande (driver). La conception de ces fonctions s’avère complexe puisqu’il n’existe pas de MESFETs de type P et une polarisation négative de -15 V est nécessaire au blocage des MESFETs SiC. Une structure constituée d’un pont redresseur, d’un boost régulé avec sa commande basée sur ces différentes fonctions a été réalisée et simulée sous SPICE. L’ensemble de cette structure a été fabriqué au CNM de Barcelone sur un même substrat SiC semi-isolant. L’intégration des éléments passifs n’a pas été envisagée de façon monolithique (mais pourrait être considérée pour les inductances et capacités dans la mesure où les valeurs des composants intégrés sont compatibles avec les processus de réalisation). Le convertisseur a été dimensionné pour délivrer une de puissance de 2.2 W pour une surface de 0.27 cm2, soit 8.14 W/cm2. Les caractérisations électriques des différents composants latéraux (résistances, diodes, transistors) valident la conception, le dimensionnement et le procédé de fabrication de ces structures élémentaires, mais aussi de la majorité des fonctions analogiques. Les résultats obtenus permettent d’envisager la réalisation d’un driver monolithique de composants Grand Gap. La perspective des travaux porte désormais sur la réalisation complète du démonstrateur et sur l’étude de son comportement en environnement sévère notamment en haute température (> 300 °C). Des analyses des mécanismes de dégradation et de fiabilité des convertisseurs intégrés devront alors être envisagées
The new SiC power switches is able to consider power converters, which could operate in harsh environments as in High Voltage (> 10kV) and High Temperature (> 300 °C). Currently, they are no specific solutions for controlling these devices in harsh environments. The development of elementary functions in SiC is a preliminary step toward the realization of a first demonstrator for these fields of applications. AMPERE laboratory (France) and the National Center of Microelectronic of Barcelona (Spain) have elaborated an elementary electrical compound, which is a lateral dual gate MESFET in Silicon Carbide (SiC). The purpose of this research is to conceive a monolithic power converter and its driver in SiC. The scientific approach has consisted of defining in a first time a SPICE model of the elementary MESFET from electric characterizations (fitting). Analog functions as : comparator, ring oscillator, Schmitt’s trigger . . . have been designed thanks to this SPICE’s model. A device based on a bridge rectifier, a regulated "boost" and its driver has been established and simulated with the SPICE Simulator. The converter has been sized for supplying 2.2 W for an area of 0.27 cm2. This device has been fabricated at CNM of Barcelona on semi-insulating SiC substrate. The electrical characterizations of the lateral compounds (resistors, diodes, MESFETs) checked the design, the "sizing" and the manufacturing process of these elementary devices and analog functions. The experimental results is able to considerer a monolithic driver in Wide Band Gap. The prospects of this research is now to realize a fully integrated power converter in SiC and study its behavior in harsh environments (especially in high temperature > 300 °C). Analysis of degradation mechanisms and reliability of the power converters would be so considerer in the future

AC motors are largely used in a wide range of modern systems, from household appliances to automated industry applications such as: ventilations systems, fans, pumps, conveyors and machine tool drives. Inverters are widely used in industrial and commercial applications due to the growing need for speed control in ASD systems. Fast switching transients and the common mode voltage, in interaction with parasitic capacitive couplings, may cause many unwanted problems in the ASD applications. These include shaft voltage and leakage currents. One of the inherent characteristics of Pulse Width Modulation (PWM) techniques is the generation of the common mode voltage, which is defined as the voltage between the electrical neutral of the inverter output and the ground. Shaft voltage can cause bearing currents when it exceeds the amount of breakdown voltage level of the thin lubricant film between the inner and outer rings of the bearing. This phenomenon is the main reason for early bearing failures. A rapid development in power switches technology has lead to a drastic decrement of switching rise and fall times. Because there is considerable capacitance between the stator windings and the frame, there can be a significant capacitive current (ground current escaping to earth through stray capacitors inside a motor) if the common mode voltage has high frequency components. This current leads to noises and Electromagnetic Interferences (EMI) issues in motor drive systems. These problems have been dealt with using a variety of methods which have been reported in the literature. However, cost and maintenance issues have prevented these methods from being widely accepted. Extra cost or rating of the inverter switches is usually the price to pay for such approaches. Thus, the determination of cost-effective techniques for shaft and common mode voltage reduction in ASD systems, with the focus on the first step of the design process, is the targeted scope of this thesis. An introduction to this research – including a description of the research problem, the literature review and an account of the research progress linking the research papers – is presented in Chapter 1. Electrical power generation from renewable energy sources, such as wind energy systems, has become a crucial issue because of environmental problems and a predicted future shortage of traditional energy sources. Thus, Chapter 2 focuses on the shaft voltage analysis of stator-fed induction generators (IG) and Doubly Fed Induction Generators DFIGs in wind turbine applications. This shaft voltage analysis includes: topologies, high frequency modelling, calculation and mitigation techniques. A back-to-back AC-DC-AC converter is investigated in terms of shaft voltage generation in a DFIG. Different topologies of LC filter placement are analysed in an effort to eliminate the shaft voltage. Different capacitive couplings exist in the motor/generator structure and any change in design parameters affects the capacitive couplings. Thus, an appropriate design for AC motors should lead to the smallest possible shaft voltage. Calculation of the shaft voltage based on different capacitive couplings, and an investigation of the effects of different design parameters are discussed in Chapter 3. This is achieved through 2-D and 3-D finite element simulation and experimental analysis. End-winding parameters of the motor are also effective factors in the calculation of the shaft voltage and have not been taken into account in previous reported studies. Calculation of the end-winding capacitances is rather complex because of the diversity of end winding shapes and the complexity of their geometry. A comprehensive analysis of these capacitances has been carried out with 3-D finite element simulations and experimental studies to determine their effective design parameters. These are documented in Chapter 4. Results of this analysis show that, by choosing appropriate design parameters, it is possible to decrease the shaft voltage and resultant bearing current in the primary stage of generator/motor design without using any additional active and passive filter-based techniques. The common mode voltage is defined by a switching pattern and, by using the appropriate pattern; the common mode voltage level can be controlled. Therefore, any PWM pattern which eliminates or minimizes the common mode voltage will be an effective shaft voltage reduction technique. Thus, common mode voltage reduction of a three-phase AC motor supplied with a single-phase diode rectifier is the focus of Chapter 5. The proposed strategy is mainly based on proper utilization of the zero vectors. Multilevel inverters are also used in ASD systems which have more voltage levels and switching states, and can provide more possibilities to reduce common mode voltage. A description of common mode voltage of multilevel inverters is investigated in Chapter 6. Chapter 7 investigates the elimination techniques of the shaft voltage in a DFIG based on the methods presented in the literature by the use of simulation results. However, it could be shown that every solution to reduce the shaft voltage in DFIG systems has its own characteristics, and these have to be taken into account in determining the most effective strategy. Calculation of the capacitive coupling and electric fields between the outer and inner races and the balls at different motor speeds in symmetrical and asymmetrical shaft and balls positions is discussed in Chapter 8. The analysis is carried out using finite element simulations to determine the conditions which will increase the probability of high rates of bearing failure due to current discharges through the balls and races.

碩士
南台科技大學
電機工程系
97
This thesis discusses control methods of high-frequency high-voltage pulse power supply system. It can be applied to the dielectric barrier discharging, corona discharging, and so on. The proposed structure’s first stage is active power factor corrector, It is provides steady DC voltage by boost AC-DC conveter to second stage’s full-bridge ZVS converter to get the desired voltage. The second stage is controlled by pulse width modulation and pulse density modulation, As the pulse width modulation can’t control the system in low power, range a pulse density modulation control is propose to improve. This thesis used the Microchip controller to achieve the pulse density modulation control, thus the high-frequency high-voltage pulse power supply system can have both the pulse width modulation control and pulse density modulation control functions.

碩士
國立臺灣科技大學
電機工程系
106
This thesis presents an adjustable pulse-width high voltage pulsed power supply based on the full-bridge LLC resonant topology with a digital controller. First, the system transfer function including parastic capacitance effect is derived to select the resonant component. Moreover, the proposed system can achieve zero voltage switching to reduce power loss even under pulsed output. In addition, the modified burst PWM control is combined with variable frequency control to eliminate the output voltage spike. Furthermore, the voltage feedback control is implemented by using the auxiliary winding to simplify the circuit design and to provide electrical isolation. Finally, both the computer simulation and experimental results are used to verify the feasibility and validity of the proposed system.

碩士
崑山科技大學
電機工程研究所
95
In this thesis, the design and implementation of a high power factor full bridge converter with phase-shift-zero-voltage switching is presented.The controlling device IC UC3854N is used so that the input current will track the input voltage to achieve high power factor and to reduce the harmonic pollution,moreover, the output of active power factor corrector is transferred to a full-bridge voltage converter with phase-shift and zero-voltage-switch.The IC UC3875 is used to achieve zero voltage switching. It can reduce the noise and loss while the switch is switching, and the total efficiency is increased.

碩士
國立高雄應用科技大學
電機工程系博碩士班
106
In this thesis, a Single Active-Power-Switch High Step-up DC-to-DC Voltage Converter with Coupled Inductors is proposed. During the non-magnetization period of the inductor which is used in the circuit, the clamp capacitor is charged by the inductor and a part of energy. And during the process of magnetization of the inductor, the energy of input voltage can be transmitted to secondary side in order to be charged to a boost capacitor and a double voltage capacitor. Furthermore, the energy of the clamp capacitor is transferred to the boost capacitor by the inductor during the process of magnetization of the inductor. A high boost voltage gain and high efficiency can be achieved with a proper duty ratio by the input voltage, primary and second dary outputs of the coupled inductors, boost capacitor and the voltage double capacitor. In the circuit, a single active switch doesn’t make the control complicated. Moreover, high boost voltage gain reduces the voltage surge of the leakage inductor in the active switch and switching losses. In addition, a high switching frequency design can reduce the physical volume of the circuit. This article will discuss the operating principle of the circuit in continuous, discontinuos conduction modes and its steady-state characteristics. The boundary operating conditions will also be mentioned in the discussed. Finally, we implemented a experimental circuits with an input voltage of 18V~30V, output voltage of 200V, and output power of 200W to verify the performance.

abstract: Silicon Carbide (SiC) junction field effect transistors (JFETs) are ideal for switching high current, high voltage loads in high temperature environments. These devices require external drive circuits to generate pulse width modulated (PWM) signals switching from 0V to approximately 10V. Advanced CMOS microcontrollers are ideal for generating the PWM signals but are limited in output voltage due to their low breakdown voltage within the CMOS drive circuits. As a result, an intermediate buffer stage is required between the CMOS circuitry and the JFET. In this thesis, a discrete silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) was used to drive the gate of a SiC power JFET switching a 120V RMS AC supply into a 30Ω load. The wide operating temperature range and high breakdown voltage of up to 50V make the SOI MESFET ideal for power electronics in extreme environments. Characteristic curves for the MESFET were measured up to 250°C.; To drive the JFET, the MESFET was DC biased and then driven by a 1.2V square wave PWM signal to switch the JFET gate from 0 to 10V at frequencies up to 20kHz. For simplicity, the 1.2V PWM square wave signal was provided by a 555 timer. The JFET gate drive circuit was measured at high temperatures up to 235°C.; The circuit operated well at the high temperatures without any damage to the SOI MESFET or SiC JFET. The drive current of the JFET was limited by the duty cycle range of the 555 timer used. The SiC JFET drain current decreased with increased temperature. Due to the easy integration of MESFETs into SOI CMOS processes, MESFETs can be fabricated alongside MOSFETs without any changes in the process flow. This thesis demonstrates the feasibility of integrating a MESFET with CMOS PWM circuitry for a completely integrated SiC driver thus eliminating the need for the intermediate buffer stage.
Dissertation/Thesis
M.S. Electrical Engineering 2010

碩士
國立清華大學
工程與系統科學系
99
本研究中成功的使用高功率脈衝磁控濺鍍技術 (HiPIMS) 鍍著奈米晶 氮化鈦薄膜於P型 (100) 矽基板上。本研究主要的目的為研究調控脈衝靶材 電壓及脈衝間隔時間對高功率脈衝磁控濺鍍技術鍍著之氮化鈦薄膜於成 分、結構、機械性質與導電性質上的影響。此研究可幫助我們了解高功率 脈衝磁控濺鍍應用於鍍膜製程上的特性。本研究的結果顯示,薄膜 (111) 平面的織構係數、結晶性以及晶粒大小皆隨著脈衝靶材電流由 550 V 上升 至 750 V ,或脈衝間隔時間由 800 μs 上升至 1700 μs 而增加。提昇脈衝靶 材電流能夠使得薄膜堆積因子顯著的增加直到其值接近於一,亦即塊材的 程度。在硬度方面,約介於14~25 GPa間,並與脈衝靶材電壓高度相關, 但對脈衝間隔時間的變化則不明顯。本實驗中所有試片的殘餘應力皆為壓 縮應力,且增加脈衝靶材電壓或脈衝間隔時間都會使殘餘應力增加。當脈 衝間隔時間增加時,靶材極限電流議會增加,顯示電漿氣體的補充足夠與 否可能是此情況下影響電漿密度的重要因素。在本實驗中,增加脈衝靶材 電壓與脈衝間隔時間都能使電漿密度增加,並因此能鍍著具優異機械與介 電性質的氮化鈦薄膜。

Experimental research on high-power converters, particularly in an academic environment, faces severe infrastructural constraints. Usually, power source and loads of required ratings are not available. Further, more importantly, the energy consumption is huge. One possibility is to establish an experimental research platform, comprising of a network of high-power converters, through which power is circulated and which draws only the losses from the mains. This work deals with the establishment of a circulating power test set-up, comprising of two line-side PWM converters, inclusive of control and modulation methods for the two converters. Two types of circulating power test setups are developed. In the first setup, the converters are connected in parallel, on ac as well as dc sides, such that real and/or reactive power is circulated between them. In the second test setup, the dc buses of the converters are separated; hence, only reactive power circulation is possible. These setups are used to conduct heat-run tests with low energy expenditure on the PWM converters at various operating conditions up to power levels of 150 kVA. Further, these are used to validate analytically-evaluated thermal characteristics of high-power PWM converters. A safe thermal limit is derived for such converters in terms of apparent power (kVA) handled, power factor and switching frequency. The effects of voltage sag and of unequal current sharing between parallel IGBT modules on the safe thermal limit are studied. While the power drawn by the circulating-power setup from the grid is much lower than the ratings of the individual converters, the harmonic injection into the mains by the setup could be significant since the harmonics drawn by both converters tend to add up. This thesis investigates carrier interleaving to improve the waveform quality of grid current, drawn by the circulating-power test setup. The study of carrier interleaving is quite general and covers various applications of parallel-connected converters such as unity power factor rectification, static reactive power compensation and grid-connected renewable energy systems. In literature, carrier interleaving has been employed mainly for unity power factor rectifiers, sharing a common dc load equally. In such case, the fundamental components of the terminal voltages of the parallel converters are equal. However, when the power sharing between the two converters is unequal, or when power is circulated between the two converters, the terminal voltages of the two converters are not equal. A method to estimate rms grid current ripple, drawn by parallel-connected converters with equal and/or unequal terminal voltages, in a synchronous reference frame is presented. Further, the influence of carrier interleaving on the rms grid current ripple is studied. The optimum interleaving angle, which minimizes the rms grid current ripple under various applications, is investigated. This angle is found to be a function of modulation index of the converters in the equal terminal voltages case. In the unequal terminal voltages case, the optimum interleaving angle is shown to be a function of the average modulation index of the two parallel converters. The effect of carrier interleaving is experimentally studied on the reactive power circulation setup at different values of kVA and different dc bus voltages. The grid current ripple is measured for different values of interleaving angle. It is found experimentally that the optimum interleaving angle reduces the rms grid current ripple by between 37% and 48%, as compared without interleaving, at various operating conditions. Further, the reactive power circulation test set-up is used to evaluate and compare power conversion losses corresponding to different PWM techniques such as conventional space-vector PWM (CSVPWM), bus-clamping PWM (BCPWM) and advanced bus-clamping PWM methods for static reactive power compensator (STATCOM) application at high power levels. It is demonstrated theoretically as well as experimentally that an advanced bus-clamping PWM method, termed minimum switching loss PWM (MSLPWM), leads to significantly lower power conversion loss than CSVPWM and BCPWM techniques at a given average switching frequency.

碩士
大同大學
電機工程研究所
88
The purpose of this thesis is to study single-phase switch-mode UPS with high power factor, low voltage regulation, and low total harmonic distortion. The system consists of a switch-mode PFC rectifier, dc/ac converter, a bidirectional chopper, and a battery set. A single-phase switch-mode high PF rectifier has been introduced without a need for a complex control circuitry. Taking the advantage of a chip-UC3854AN and additional feedback circuits to draw sinusoidal ac current from the ac line to get the high input power factor and low voltage regulation. Importing a bidirectional chopper, it can perform buck/boost output voltage arbitrarily for storing energy to battery set when the utility is in normal condition and providing power when the utility is breakdown or outage. Finally, a single-chip microprocessor, 80C196MC is used to implement the control scheme of the proposed system with proper hardware. Via the experimentation with prototype established, it confirms that the UPS structure can performs its feasibility and good characteristics as ex

The electronic control, instrumentation and communication hardware is becoming more and more compact and faster in operation due to the increased use of large scale integration of semiconductor devices operating at higher speeds. The use of VLSI circuit based systems in various industrial and defence sectors is also increasing continuously. Since the operating threshold voltages and currents of these devices are very small they are very prone to electrical disturbance in their operation by the Electromagnetic Interference (EMI) signals. Their proper functioning is very important particularly in the case of systems used in mission mode, critical defence/industrial platforms. EMI can be generated within the electronic system/equipment itself or may result due to some external electromagnetic source. The high power Ultra Wide Band system is one such kind of external High Power Electromagnetic (HPEM) interference source which may cause malfunctioning/physical damage to the sensitive electronic systems. Hence it is necessary to test the susceptibility of electronics to such high power UWB based intentional EMI or IEMI sources. The sources for generating these transient EM fields may also be used in impulse radars and offensive applications to mal-operate/damage non-friendly electronics. The UWB system consists of a high voltage pulsed power source called pulser along with a high bandwidth (Ultra Wide Band) antenna to radiate the UWB signal. The pulse fed by the pulser to the antenna through a switch is of high voltage type (amplitude of few 10s of kV to about a MV) and has a sub-nanosecond rise time. Most of the UWB systems developed over the world have the switch employing gaseous dielectric switching media used at pressures above the atmospheric level to generate such a fast rise time voltage pulse. Use of gaseous switching media at sub-atmospheric pressures to achieve sub-ns rise time, short duration high voltage pulses required for the high power UWB applications is another possibility. This possibility has not been exploited till date. Hence it was decided to develop a pulser switch with gaseous switching media at sub-atmospheric pressures (up to 50 mbar) and achieve sub-ns rise time voltage pulses of up to 50 kV. The energy delivered out by the UWB system depends upon the pulser output energy per switching shot and the repetitive switching rate of the pulser. To achieve maximum energy output it is required to maximize either the energy per switching shot or the pulse repetition rate (PRR) of the pulser switch. The optimization of the pulser operation to achieve maximum pulser energy output in every switching shot has not been tried so far. In this work it was decided to analyze the circuit so as to achieve maximum pulser output energy per switching shot. Another objective of the study was to systematically characterize the pulser switch using various gases and gas mixtures as the switching media to evaluate the switch performance as a function of gas pressure and switch breakdown voltage. The effect of pulser and antenna performance parameters on the UWB system performance was also decided to be evaluated. Hence the present thesis work deals with the design, development, evaluation and performance optimization of a 50 kV, 25 MW UWB system based on Half Impulse Radiating Antenna (HIRA) fed by a coaxial capacitive pulser. The spark gap type self triggered pulser switch is designed to have a fixed gap spacing and variable gas pressure in order to vary the switch breakdown voltage. The switch is designed for operation with dry air, nitrogen, sulphur hexafluoride (SF6) and a mixture of different gases as the dielectric switching media with pressures of up to 5 bar above the atmospheric level and up to 50 mbar below the atmospheric level. Physical placement of the switch just above the coaxial pulser capacitor terminal offered a low inductance geometry. The rise time estimation of the switch has been carried out as a function of gas pressure and the switch arc inductance. These rise time values have been compared with the measured ones and a good agreement was found between the two. The rise time values indicate that an inverse relationship exists between the gas pressure and the rise time. The rise time was found to decrease at increased pressures. SF6 gas offered the minimum rise time out of all the gases/mixtures studied. The pulse repetition rate (PRR) of the UWB system depends upon the dielectric recovery of the gaseous switch and the charging time of the pulser capacitor. To estimate the PRR a circuit model has been proposed based on these parameters. The model shows an inverse relationship between the switch breakdown voltage (BDV) and the gas pressure with the PRR. The estimated PRR values were found to vary between 800 Hz and 5 kHz in the experimented range of the switch breakdown voltage. The PRR values have also been experimentally measured. There is a good match between the measured and the estimated values up to the switch BDV of 12.5 kV after which the difference is increased to about 20 %. The feed for the reflector of the HIRA antenna consists of a pair of coplanar conical transverse electromagnetic (TEM) feed plates as they have a better antenna aperture blockage performance. The angles of the TEM feed plates have been chosen using stereographic projections of the feed plates into the HIRA reflector. Each TEM feed plate of 200  characteristic impedance has been terminated by matched resistor. An analytical expression has been derived to optimize the pulser output voltage at which the energy output per switching shot of the UWB system is maximum. It was found that when the pulser output voltage i.e. the switch breakdown voltage is 75 % of the dc source voltage the output energy delivered is maximum. It was possible to achieve a maximum output energy of 10 J per switching shot for the designed 25 MW high power UWB system. The HIRA antenna has been analysed for the impedance profile for frequencies up to 3.5 GHz and was found to maintain a reflection performance better than -10 dB over the frequency range. The radiated field analysis of the antenna was carried out using an analytical model and numerically by using a commercially available software. It was found that as per the analytical model, the Figure of Merit (FoM) of the designed UWB system is 1.41 V for a normalized excitation feed pulse of 1 V and the 3 dB spectral content of the radiated field is between 180 MHz-1.8 GHz. The corresponding results using computer simulations of the UWB system indicate a slightly lesser FoM of 1.1. Higher FoM obtained using the analytical model is due to ignoring the antenna aperture blockage and the field diffraction effects over the TEM feed arms as well as from the rim of the reflector of the antenna. The radiated field amplitude and gain of the HIRA antenna were found to be a direct function of the frequency of the radiated signal. Higher gains and narrower beam width for the radiated field were observed with an increase in the frequency. The radiated field spectral waveform in the near field region was observed to have a notch at a particular frequency and its harmonics. The notch frequency was found to be a function of the propagation time difference called clear time. The effect of pulser rise time, antenna feed arm impedance and position on the radiated far field amplitude and wave shape was analysed. It was observed that with decrease in the pulser rise time from 700 ps to 100 ps, the radiated field amplitude increases by about 600 %. A matched termination impedance with position of 30of the TEM feed arms with respect to the vertical symmetry axis of the antenna provides a higher radiated field amplitude and lower post pulse oscillations in the radiated field waveform. The pulser switch was evaluated systematically for various performance parameters such as BDV, rise time, PRR, voltage recovery and jitter characteristics as a function of switch gas pressure, type of gaseous switching media and breakdown voltage at pressures above and below the atmospheric level. The switch BDV was found to be a linear function of pressure of the gas used i.e. dry air, nitrogen, sulphur hexafluoride (SF6) and a mixture of air and SF6. The measured rise times of all the gases were found to be in inverse proportion to the switch gas pressure. SF6 gas offered the best rise time and hence was found to be a good contender for achieving higher radiated field amplitudes and bandwidth. The voltage recovery characteristics of SF6 gas and air were experimentally studied as a function of the recovery time. It is found that both the gases have similar recovery characteristics having a distinct saturation plateau region. It was found that for a given recovery time SF6 recovers to a higher voltage than air and the recovery further improves for SF6 at increased pressures (between 0.5-2 bar). The effect of the number of switching shots on the jitter in the switch rise time was measured by operating the switch continuously at a PRR of 1 kHz and for total number shots up to 10.8 M. It was observed that the jitter increases by an order of magnitude after 10.8 M shots. This indicates that for the present switch design, the switch electrodes require maintenance (buffing, polishing, etc.) after every 3.5 M shots to maintain a reasonably low jitter. SF6 gas was characterized for a fixed source voltage to determine the effect of pressure on rise time in the sub atmospheric regime (up to 50 mbar). It was found that the rise time vs. pressure characteristics follows the Paschen’s curve with a value of pressure at which rise time is the lowest for a given source voltage. With increase in the source voltage the rise time was found to decrease. The HIRA based UWB radiating system was evaluated for radiated fields in the near and far field region for the temporal and spectral characteristics. It was found that for the source voltage of 25 kV, the FoM in the near and far field region are 29.4 kV and 28.9 kV respectively. The fields in the distant far field region have more oscillatory post pulses due to the effect of ground reflections and the low frequency dipole moment mismatch of the antenna. Since SF6 gas offered the best rise time of 193 ps at a voltage of 46 kV than the other gases tried, the radiated field is the highest (5.3 kV/m) with SF6 at a distance of 10 m offering a gain factor of 1.15. Dry air offered a radiated field gain factor of 0.83 which got improved by 33 % by just 30 % addition of SF6 gas into the air. The field amplitudes measured were in good agreement with those computed using the analytical model and the computer simulations and they follow the 1/R rule as a function of the far field distance, R in the bore sight direction. The measured radiation pattern of the UWB system showed a focussed and narrow radiated field beam at higher frequencies with a half field beam width (HFBW) of 8 at 2 GHz. The UWB system was measured to have dominant highest cut off frequency of 1.79 GHz with a band ratio and percentage band width of 9.56 and 162.11 % respectively. This confirmed that the developed system is of sub-hyper band radiator type. The UWB system developed through this work is having a better performance than some of the other systems developed elsewhere in the world, in terms of FoM (53 kV) and the PRR (> 1 kHz). The system can be further improved in terms of consistency (jitter) and intensity by use of a triggered switch and hydrogen gas at 100 bar pressure as the switching medium respectively. The profile of the TEM feed plates of the HIRA antenna may be further improved to have a better antenna aperture fill factor. Such multiple systems in an arrayed manner may be used either for higher power output/better agility of the radiated field beam. This system will be fully exploited for the applications of susceptibility evaluation of electronic circuits, non-friendly applications as well as impulse radars

Pulsed electric field (PEF) processing has been demonstrated to be an effective non-thermal pasteurization method for food-treatment applications. With this method, high voltage, short-duration pulses are applied to a chamber through which liquid food is passed. If the voltage applied and the corresponding electric field develops a potential higher than a critical trans-membrane potential, the pores expand, and the membrane of the living cell is ruptured. Due to the lower amount of energy consumed during a PEF process, the temperature of the liquid is kept much lower than as opposed to conventional pasteurization. The PEF method thus kills bacteria and other microorganisms while preserving the nutrition and taste of the liquid foods. Although the parameter responsible for inactivation is the voltage applied, for any given voltage, the conductivity of the liquid defines a current through the liquid that causes the temperature to rise. Therefore, preventing excessive heating of the liquid requires the application of an efficient waveform. According to the literature, the most efficient waveform is a square wave since the entire energy applied would be used for the inactivation process. Although some power supplies are capable of generating such a waveform, the generation of an efficient waveform that satisfies all the requirements for producing a viable product for PEF applications is still a challenging problem. In this research, a cascadable pulse generator, based on a Marx generator design, was designed and implemented in order to generate a pulsed waveform for the treatment of liquid food. IGBT switches were used to charge capacitors in parallel and to discharge them in series as a means of generating a high voltage at the output. The design was implemented and tested for two stages, generating up to 6 kV and 1.6 kA square pulses with a controllable pulse width from 1 µs to 10 µs. Up to 3 switches were connected in parallel to enhance the current capability of the system. Also investigated are ways to improve the transient time by enhancing the IGBT driver circuit. The effect of design parameters such as pulse width, voltage, and current on the temperature rise in the liquid was also studied. A variety of liquid foods with different conductivities were tested in order to confirm the functionality of the system.

Over the past few years, there has been a growing need for wireless communications with higher data rates and ubiquitous coverage, and these must be achieved at reduced cost and with a lower carbon footprint. This evolution in wireless demand places a big burden on transmitter architectures. The need for higher efficiency has stimulated research into the potential replacement of current linear power amplifiers (PAs) by switch mode power amplifiers (SMPAs) at cellular frequencies. The radio frequency (RF) PA currently accounts for a significant part of the cost, and most of the power requirements of a typical wireless base station. This research is focused on the modulation and up-conversion circuits for generating the SMPA drive signals. The switched (‘on’/‘off’) nature of the amplifier drive signal creates an opportunity for an all-digital solution removing traditional analog components such as the digital to analog converters, reconstruction filters, quadrature modulator and local oscillators. Digital signal processing techniques used for signal modulation are extended to digital up-conversion to generate suitable drive signals for the SMPA. In this thesis, a sigma-delta (ΣΔ) based technique is used to embed a complex modulation scheme such as OFDM into a single ‘on’-‘off’ bit stream.

In high-power electric drives, multilevel inverters are generally deployed to address issues such as electromagnetic interference, switch voltage stress and harmonic distortion. The switching frequency of the inverter is always kept low, of the order of 1KHz or even less to reduce switching losses and synchronous pulse width modulation (PWM) is used to avoid the problem of sub-harmonics and beat frequencies. This is particularly important if the switching frequency is very low. The synchronous PWM is getting popularity as its realization is very easy with digital controllers compared to analog controllers. Neutral-point-clamped (NPC) inverters, cascaded H-bridge, and flying-capacitor multilevel inverters are some of the popular schemes used for high-power applications. Hybrids of these multilevel inverters have also been proposed recently to take advantage of the basic configurations. Multilevel inverters can also be realized by feeding the induction motor from both ends (open-end winding) using conventional inverter structures. For controlling the output voltage of these inverters, various PWM techniques are used. Chapter-1 of this thesis provides an over view of the various multilevel inverter schemes preceded by a discussion on basic two-level VSI topology. The inverters used in motor drive applications have to be operated in over-modulation range in order to extract the maximum fundamental output voltage that is possible from the dc-link. Operation in this high modulation range is required to meet temporary overloads or to have maximum power operation in the high speed range (flux weakened region). This, however, introduces a substantial amount of low order harmonics in the Motor phase voltages. Due to these low-order harmonic frequencies, the dynamic performance of the drive is lost and the current control schemes are severely affected especially due to 5th and 7th harmonic components. Further, due to these low-order harmonics and non-linear PWM operation in over-modulation region, frequent over-current fault conditions occur and reliability of the drive is jeopardized. The twelve sided-polygonal space vector diagram (dodecagonal space vectors) can be used to overcome the problem of low order 5th and 7th harmonics and to give more range for linear modulation while keeping the switching frequency at a minimum compared to conventional hexagonal space vector based inverters. Thus, the dodecagonal space-vector switching can be viewed as an engineering compromise between low switching frequency and quality load current waveform. Most of the previous works of dodecagonal space-vector generation schemes are based on NPC inverters. However, sophisticated charge control schemes are required in NPC inverters to deal with the neutral-point voltage fluctuation and the neutral-point voltage shifting issues. The losses in the clamping diodes are another major concern. In the second chapter, a multilevel dodecagonal space-vector generation scheme based on flying capacitor topology, utilizing an open end winding induction motor is presented. The neutral point charge-balancing problem reported in the previous works is not present in this scheme, the clamping diodes are eliminated and the number of power supplies required has been reduced. The capacitors have inherent charge balancing capability, and the charge control is done once in every switching cycle, which gives tight voltage control for the capacitors. For the speed control of induction motors, the space-vector PWM scheme is more advantageous than the sine-triangle PWM as it gives a more linear range of operation and improved harmonic performance. One major disadvantage with the conventional space-vector PWM is that the trigonometric operations demand formidable computational efforts and look-up tables. Carrier based, common-mode injected PWM schemes have been proposed to simplify the PWM process. However, the freedom of selecting the PWM switching sequences is limited here. Another way of obtaining SVPWM is using the reference voltage samples and the nearest vector information to switch appropriate devices for proper time intervals, realizing the reference vector in an average sense. In-formation regarding the sector and nearest vectors can be easily obtained by comparing the instantaneous amplitudes of the reference voltages. This PWM approach is pro-posed for the speed control of the motor in this thesis. The trigonometric operations and the requirement of large look-up tables in the conventional SVPWM are avoided in this method. It has the additional advantage that the switching sequences can be decided at will, which is helpful in reducing further, the harmonic distortion in certain frequency ranges. In this way, this method tries to combine the advantages of vector based methods (conventional SVPWM) and scalar methods (carrier-based methods). The open-end winding schemes allowed the required phase voltage levels to be generated quite easily by feeding from both ends of the windings. Thus, most of the multilevel inverters based on dodecagonal space-vector structures relied on induction motors with open-end windings. The main disadvantage of open-end winding induction motor is that six wires are to be run from the inverter to the motor, which may be unacceptable in certain applications. Apart from the inconvenience of laying six wires, the voltage reflections in the wires can lead to over voltages at the motor terminals, causing insulation failures. Where as the topology presented in chapter-2 of this thesis uses open-end winding motor with flying-capacitor inverters for the generation of dodecagonal space-vectors, the topology presented in chapter-3 utilizes a cascade connection of flying-capacitors and floating H-bridge cells to generate the same set of voltage space-vectors, thus allowing any standard induction motor as the load. Of the methods used for the speed control of induction motors, namely sine-triangle PWM and space vector PWM, the latter that provides extra modulation range is naturally preferred. It is a well-understood fact that the way in which the PWM switching sequences are applied has a significant influence on the harmonic performance of the drive. However, this topic has not been addressed properly for dodecagonal voltage space-vector based multilevel inverter drives. In chapter-4 of the thesis, this aspect is taken into ac-count and the notion of “harmonic flux trajectories” and “stator flux ripple” are used to analyze the harmonic performance of the various PWM switching schemes. Although the PWM method used in this study is similar to that in chapter-2, the modification in the PWM switching sequence in the PWM algorithm yields significant improvements in harmonic performance. The proposed topologies and PWM schemes are extensively simulated and experimentally verified. The control scheme was implemented using a DSP processor running at a clock frequency 150MHz and a four-pole, 3.7kW, 50Hz, 415V three-phase induction motor was used as the load. Since the PWM ports are limited in a DSP, a field-programmable gate array (FPGA) was used to decode the PWM signals from the DSP to generate timing information required for PWM sequencing for all the power devices. The same FPGA was used to generate the dead-time signals for the power devices also.

For medium and high-voltage drive applications, multilevel inverters are very popular. It is due to their superior performance compared to 2-level inverters such as reduced harmonic content in the output voltage and current, lower common mode voltage and dv=dt, and lesser voltage stress on power switches. The popular circuit topologies for multilevel inverters are neutral point clamped, cascaded H-bridge and flying capacitor based circuits. There exist different combinations of these basic topologies to realize multilevel inverters with modularity, better fault tolerance, and reliability. Due to these advantages, multilevel converters are getting good acceptance from the industry, and researchers all over the world are continuously trying to improve the performance of these converters. To meet such demands, three multilevel inverter topologies are proposed in this thesis. These topologies can be used for high-power induction motor drives, and the concepts presented are also applicable for synchronous motor drives, grid-connected inverters, etc. To get nearly sinusoidal phase current waveforms, the switching frequency of the conventional inverter has to be increased. It will lead to higher switching losses and electromagnetic interference. The problem with lower switching frequency is the intro- duction of low order harmonics in phase currents and undesirable torque ripple in the motor. The 5th and 7th harmonics are dominant for hexagonal voltage space-vector based low frequency switching, and it is possible to eliminate these harmonics by dodecagonal switching. Further improvement in the waveform quality is possible by octadecagonal voltage space-vectors. In this case, the complete elimination of 11th and 13th harmonic is possible for the entire modulation range. The concepts of dodecagonal and octadecagonal voltage space-vectors are used in the proposed inverter topologies. The first topology proposed in this thesis consists of cascaded connection of two H-bridge cells. The two cells are fed from unequal DC voltage sources having a ratio of 1 : 0:366, and this inverter can produce six concentric dodecagonal voltage space- vectors. This ratio of voltages can be obtained easily from a combination of star-delta transformers, since 1 : 0:366 = ( p 3 + 1) : 1. The cascaded connection of two H-bridge cells can generate nine asymmetric pole voltage levels, and the combined three-phase inverter can produce 729 voltage space-vectors (9 9 9). From this large number of combinations, only certain voltage space-vectors are selected, which forms dodecagonal pattern. In the case of conventional multilevel inverters, the voltage space-vector diagram consists of equilateral triangles of equal size, but for the proposed inverter, the triangular regions are isosceles and are having different sizes. By properly placing the voltage space-vectors in a sampling period, it is possible to achieve lower switching frequency for the individual cells, with substantial improvement in the harmonic spectrum of the output voltage. During the experimental veri cation, the motor is operated at di erent speeds using open loop v=f control method. The samples taken are always synchronised with the start of the sector to get synchronised PWM. The number of samples per sector is decreased with increase in the fundamental frequency to limit the switching frequency. Even though many topologies are available in literature, the most preferred topology for drives application such as traction drives is the 3-level NPC structure. This implies that the industry is still looking for viable alternatives to construct multilevel inverter topologies based on available power circuits. The second work focuses on the development of a multilevel inverter for variable speed medium-voltage drive application with dodecagonal voltage space-vectors, using lesser number of switches and power sources compared to earlier implementations. It can generate three concentric 12-sided polygonal voltage space-vectors and it is based on commonly available 2-level and 3-level inverters. A simple PWM timing computation method based on the hexagonal space-vector PWM is developed. The sampled values of the three-phase reference voltages are initially converted to the timings of a two-level inverter. These timings are mapped to the dodecagonal timings using a change of basis transformation. The voltage space- vector diagram of the proposed drive consists of sixty isosceles triangular regions, and the dodecagonal timings calculated are converted to the timings of the inner triangles. A searching algorithm is used to identify the triangular region in which the reference vector is located. A front-end recti er that may be easily implemented using standard star-delta transformers is also developed, to provide near-unity power factor. To test the performance of the inverter drive, an open-loop v=f control is used on a three-phase induction motor under no-load condition. The harmonic spectra of the phase voltages were computed in order to analyse the harmonic distortion of the waveforms. The carrier frequency was kept around 1.2 KHz for the entire range of operation. If the switching frequency is decreased, the conventional hexagonal space-vector based switching introduce signifi cant 5th, 7th, 11th and 13th harmonics in the phase currents. Out of these dominant harmonics, the 5th and 7th harmonics can be completely suppressed using dodecagonal voltage space-vector based switching as observed in the first and second work. It is also possible to remove the 11th and the 13th harmonics by using voltage space-vectors with 18 sides. The last topology is based on multilevel octadecagonal (18-sided polygon) voltage space-vectors, and it has better harmonic performance than the previously mentioned topologies. Here, a multilevel inverter system capable of producing three octadecagonal voltage space-vectors is proposed for the fi rst time, along with a simple timing calculation method. The conventional three-level inverters are only required to construct the proposed drive. Four asymmetric power supply voltages with 0:3054Vdc, 0:3473Vdc, 0:2266Vdc and 0:1207Vdc are required for the operation of the drive, and it is the main drawback of the circuit. Generally front-end isolation transformer is essential for high-power drives and these asymmetric voltages can be easily obtained from the multiple windings of the isolation transformer. The total harmonic distortion of the phase current is improved due to the 18-sided voltage space-vector switching. The ratio of the radius of the largest polygon and its inscribing circle is cos10 = 0:985. This ratio in the case of hexagonal voltage space-vector modulation is cos30 = 0:866, which means that the range of the linear modulation for the proposed scheme is signifi cantly higher. The drive is designed for open-end winding induction motors and it has better fault tolerance. It any of the inverter fails, it can be easily bypassed and the drive will be still functional with reduced speed. Open loop v=f control and rotor flux oriented vector control schemes were used during the experimental verifi cation. TMS320F2812 DSP platform was used to execute the control code for the proposed drive schemes. For the entire range of operation, the carrier was synchronized with the fundamental. For the synchronization, the sampling period is varied dynamically so that the number of samples in a triangular region is fi xed, keeping the switching frequency around 1.2 KHz. The average execution time for the v=f code was found to be 20 S, where as for vector control it took nearly 100 S. The PWM terminals and I/O lines of the DSP is used to output the timings and the triangle number respectively. To convert the triangle number and the timings to IGBT gate drive logic, an FPGA (XC3S200) was used. A constant dead-time of 1.5 S is also implemented inside the FPGA. Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. Hall-effect sensors were used to measure the phase currents and DC bus voltages. An incremental shaft position encoder with 2500 pulse per revolution is also connected to the motor shaft, to measure the angular velocity. 1200 V, 75 A IGBT half-bridge module is used to realize the switches. The concepts were initially simulated and experimentally verifi ed using laboratory prototypes at low power. While these concepts maybe easily extended to higher power levels by using suitably rated devices, the control techniques presented shall still remain applicable.

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.

Multilevel converters are finding increased attention in industry and academia as the preferred choice of electronic power conversion for high power applications. They have a wide application area in a variety of industries involving transportation and energy management, a significant portion of which comprises of multilevel inverter fed induction motor drives. Multilevel inverters are ideally suitable for high power drives, since the switching frequency of the devices is limited for high power applications. In low power drives, the switching frequency is often in the range of tens of kHz, so that switching frequency harmonics are pushed higher in the frequency spectrum thereby the size and cost of the filter are reduced. But higher switching frequency has its own drawbacks, in particular for high voltage, high power applications. They cause large dv/dt stress on the motor and the devices, increased EMI problems and higher switching losses. An engineering trade-o is thus needed to select the minimum switching frequency without compromising on the output voltage quality. The present work is an alternate approach in this direction. Here, new inverter topologies and PWM strategies are developed that can eliminate a set of harmonics in the phase voltage using 12-sided polygonal space vector diagrams, also called dodecagonal space vector diagrams. A dodecagonal space vector diagram has many advantages over a hexagonal one. Switching space vectors on a dodecagon will not produce any harmonics of the order 6n 1, (n=odd) in the phase voltage. The next set of harmonics thus reside at 12n 1, (n=integer). By increasing the number of samples in a sector, it is also possible to suppress the lower order harmonics and a nearly sinusoidal voltage can be obtained. This is possible to achieve at a low switching frequency of the inverters. At the same time, a dodecagon is closer to a circle than a hexagon; so the linear modulation range is extended by about 6.6% compared to the hexagonal case. For a 50 Hz rated frequency operation, under constant V/f ratio, the linear modulation can be achieved upto a frequency of 48.3 Hz. Also, the harmonics of the order 6n 1, (n=odd) are absent in the over-modulation region. Maximum fundamental voltage is obtained from this inverter at the end of over-modulation region, where the phase voltage becomes a 12-step waveform. The present work is developed on dodecagonal space vector diagrams. The entire work can be summarized and explained through Fig. 1. This figure shows the development of hexagonal and dodecagonal space vector diagrams. It is known that, 3-level and 5-level space vector diagrams have been developed as an improvement over 2-level ones. They Figure 1: Development of hexagonal and dodecagonal space vector diagrams have better harmonic performance, reduced dv/dt stress on the motor and devices, better electromagnetic compatibility and improvement of efficiency over 2-level space vector diagrams. This happens because the instantaneous error between the reference vector and the switching vectors reduces, as the space vector density increases in the diagram. This is shown at the top of the figure. In the bottom part, the development of the dodecagonal space vector diagram is shown, which is the contribution of this thesis work. This is explained in brief in the following lines. Initially, a space vector diagram is proposed which switches on hexagonal space vectors in lower-modulation region and dodecagonal space vectors in the higher modulation region. As the reference vector length increases, voltage vectors at the vertices of the outer dodecagon and the vertices from the outer most hexagon is used for PWM control. This results in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at rated voltage where all the 5th and 7th order harmonics are completely eliminated. At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible. The presence of multilevel space vector structure also limits the switching frequency of the inverters. In the next work, the single dodecagonal space vector diagram is improved upon to form two concentric dodecagons spanning the space vector plane (Fig. 1). The radius of the outer dodecagon is double the inner one. It reduces the device rating and the dv/dt stress on the devices to half compared to existing 12-sided schemes. The entire space vector diagram is divided into smaller sized isosceles triangles. PWM switching on these smaller triangles reduces the inverter switching frequency without compromising on the output voltage quality. The space vector diagram is further refined to accommodate six concentric dodecagons in the space vector plane (Fig. 1). Here the space vector diagram is characterized by alternately placed dodecagons which become closer to each other at higher radii. As such the harmonics in the phase voltage are reduced, in particular at higher modulation indices. At the same time, because of the dodecagonal space vector structure, all the 6n ± 1, (n=odd) harmonics are eliminated from the phase voltage. A nearly sinusoidal phase voltage can be generated without resorting to high frequency switching of the inverters. The above space vector diagrams are developed using different inverter circuits. The first work is developed from cascaded combination of three 2-level inverters, while the second and third works use 3-level NPC inverters feeding an open end induction motor drive. The circuit topologies are explained in detail in the respective chapters. Apart from this, PWM switching schemes and detailed analysis on duty cycle calculations using the concept of volt-second balance are also presented. They show that with proper switching schemes, the proposed configurations can substantially reduce the overall loss of the inverter. Other operational issues like capacitor voltage balancing of 3-level NPC inverters and improvement of input current drawn from the grid are also covered. All the above propositions are first simulated by MATLAB and subsequently verified by an experimental laboratory prototype. Motor current waveforms both at steady state and transient conditions during motor acceleration show that the induction motor can be fed from nearly sinusoidal voltage at all operating conditions. Simplified comparative studies are also made with the proposed converters and higher level inverters in terms of output voltage quality and losses. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of multilevel inverter. The thesis concludes with some interesting ideas for further thought and exploration.

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suffer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically. Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main configurations that have gained popularity are the neutral point clamped converter, the flying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications. A novel five-level inverter topology formed by cascading a floating capacitor H-bridge module to a regular three-level flying capacitor inverter has been explored in chapter 2. The three-level flying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another floating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique effect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level flying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels can be generated from the single DC link. This enables back to back grid connected operation possible where multiple converters can interact with a single DC link. Various pole voltage switching combination and its effect on individual capacitor has been studied. A control algorithm to balance the capacitor voltages by switching through multiple redundancies for the same pole voltage has been developed. The proposed configuration has been implemented in hardware using IGBT H-bridge modules and the control circuitry is realized using DSP and FPGA. The performance of the drive is verified for various frequencies and modulation indices during steady state by running a three phase induction motor at no load. The stability of the drive during transients has been studied by accelerating the machine suddenly at no load and analyzing the performance of the drive. The capacitor voltages are made to deviate from their intended values and the capacitor balancing algorithm has been verified for its ability to bring the capacitor voltages back to their intended values. The experimental results have been presented and discussed in detail in the chapter 2. In the third chapter a common-mode voltage eliminated three-level inverter using a single DC link has been proposed. The power schematic is similar to the one presented in chapter 2. In this chapter the space vector polygon formed by the three phases of the proposed topology has been presented. The common-mode voltage generated by different pole voltage combinations for same space vector location and the redundant switching state combinations has been studied. The pole voltage combinations with zero common mode voltage have been studied. The switching state redundancies for the the pole voltage have been studied. The space vector polygon formed with the pole voltage combinations has been analyzed. A drive is made with the proposed common-mode voltage eliminated inverter. The performance of the drive is tested for various modulation indices and frequencies by running a three phase squirrel cage induction motor at no load. The transient performance is verified by accelerating the motor suddenly and checking the common-mode voltage along with the capacitor voltages. The results have been presented and discussed in detail in chapter 3. This converter has advantages like use of single DC supply, ability to operate as a regular three level converter in case of failure of one of the H-bridges. The work presented in fourth chapter proposes a novel three phase 17-level inverter configuration which utilizes a single DC supply. The rest of voltages are generated using three floating capacitor H-bridges. The redundant switching combinations for generating various pole voltages and their effect on the capacitors have been studied and suitable capacitor balancing algorithm has been developed. The proposed topology has been realized in hardware and the performance of the drive during steady state has been studied by running an induction motor at various modulation indices and frequencies. The transient response of the drive has been observed by accelerating the motor suddenly under no load. The results have been presented in detail in chapter four. This configuration also needs a single DC link. The advantages of this configuration is in case of failure of any devices in the H-bridge, the drive can be operated at reduced number of levels while supplying full load current. This feature helps the drive to be used in fault tolerant applications like marine and traction drives where reliability of the drive is of prime importance. All the topologies that have been presented in the previous chapters have mentioned about the usage of the proposed genre of topologies use single DC link and hence will enable back to back grid tied inverter connection. In the fifth chapter this has has been verified experimentally. The three phase squirrel cage induction motor is driven by using the seventeen-level inverter drive proposed in chapter four. A five-level active front-end is realized by the converter topology proposed in chapter two. The converter is run and the performance of the drive is studied at various modulation indices and speeds of the motor. Various aspects like re-generation operation, acceleration and other aspects of the drive have been studied experimentally and the results are presented in detail. For experimental setup, Semikron SKM75GB12T4 IGBT modules have been used to realize the power topology. These IGBTs are driven by M56972L drivers. The control circuit is realized using TMS320F2812 DSP along with Xilinx Spartan 3 FPGA (XC3S200) has been used. The voltages and currents are sensed using LEM LV-20P and LA 55-P hall effect based sensors.

This thesis deals with the design of Hybrid Energy Storage System (HESS) for Light Electric Vehicles (LEV) and EVs. More specifically, a tri-mode high-efficiency non-isolated half-bridge converter is developed for the LEV based HESS applications. A 2 kW, 100 V interleaved two-phase converter prototype was implemented. The peak efficiency of 97.5% and a minimum efficiency of 88% over the full load range are achieved. Furthermore, a power-mix optimizer utilizing the real-time Global Positioning System (GPS) data for the EV based HESS is proposed. For a specific design, it is shown that at the cost of less than 1.5% of the overall energy savings, the proposed scheme reduces the peak battery charge and discharge rates by 76% and 47%, respectively. A 30 kW bi-directional dc-dc converter is also designed and implemented for future deployment of the designed HESS into a prototype EV, known as A2B.