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1
Slater, Conor, Radisav Cojbasic, Thomas Maeder, Yusuf Leblebici, and Peter Ryser. "Packaging technologies for high temperature control electronics." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (January 1, 2013): 000184–92. http://dx.doi.org/10.4071/hiten-tp15.
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Current low temperature electronics (<175°C) with logical functions (CPUs, MCUs) have exceptional levels of reliability in terms of packaging, stemming from decades of research. However, electronics that operate at higher temperatures (>175°C) for prolonged periods of time require packaging technologies that have to tackle many new problems. At high temperatures traditionally used materials such as organic circuit boards, adhesives and standard solders degrade rapidly or undergo changes in structure and properties. An even more critical issue than high-temperature survivability is resistance to temperature cycling. Thermal mismatch between organic boards and semiconductor dies leads to high thermomechanical strains during swings from high to low temperature extremes, which can make an otherwise high temperature resistant assembly fail after a relatively low number of cycles. This work focuses on the packaging technologies for high temperature control modules, those with logical and signal conditioning applications. Although control modules share many similarities with power modules, they present their own unique design challenges, such as significantly higher complexity and a limitation of compatible materials. Here, recent research on substrates, die attach technologies and wirebond interconnects suited for high temperature ICs are presented along with packaging technologies for discrete components (capacitors and resistors) with the aim of identifying the current best solutions. Test vehicles for the various technologies were constructed and were subjected to high temperature storage at temperatures higher than 200°C. They were analysed in terms of degradation (i.e. loss in shear strength, pull strength, change in resistance, etc.). In parallel, a separate set of samples were subjected to temperature cycles from −20°C to 180°C and then analysed using the same tests as before for comparison. The combined data allow a recommendation to be made on how to assemble a viable control module such as one based on an SOI microcontroller designed at EPFL to operate at high temperatures.
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Fraley, John R., Edgar Cilio, and Bryon Western. "Advanced Applications of High Temperature Magnetics." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (January 1, 2013): 000046–55. http://dx.doi.org/10.4071/hiten-ma17.
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In recent years, high temperature magnetic structures have been developed and used for inductors and transformers in high temperature applications ranging from power electronics to wireless telemetry systems. Research in the high temperature magnetics field has led to the development of more advanced magnetic structures that can enable diverse applications ranging from regulators to amplifiers, with far reaching implications for the high temperature electronics community. Current high temperature electronics have shown potential in lab and rig tests, but high temperature electronics systems suffer from the relatively limited lifetime of the semiconductor devices themselves. The advanced magnetics discussed in this paper can be designed to have extreme lifetime capabilities even at elevated temperatures, and as such can have an immediate impact on the implementation of true field deployable high temperature electronic systems. Aerospace, power generation, and automotive industries may especially benefit from this technology, as significant advances in health monitoring and active engine control will be enabled by these advanced magnetic structures. A theoretical understanding of these advanced magnetic structures is necessary for initial design and feasibility, while the true development and implementation of this technology depends on state of the art high temperature packaging approaches. By combining high temperature, grain-oriented magnetic materials along with high temperature packaging processes, APEI, Inc. has created advanced high temperature magnetic systems that indicate the technology described in this paper is a viable one, with applications across a wide range of high temperature electronics systems.
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Kumar, Rakesh. "A High Temperature and UV Stable Vapor Phase Polymer for Electronics Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (January 1, 2011): 000207–14. http://dx.doi.org/10.4071/hiten-paper3-rkumar.
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A recent development in the area of high temperature and UV stable polymers, which offers solutions to many existing packaging and reliability challenges of electronics industry, is described. Packaging, protection and reliability of various electronic devices and component, including PCB's, MEMS, optoelectronic devices, fuel cell components and nano-electronic parts are, becoming more challenging due to their long-term performance requirements. This high temperature polymer, named Parylene HT, offers solutions to many existing protective, packaging and reliability issues in the electronics and medical industries, in part because of its excellent electrical and mechanical properties, chemical inertness and long-term thermal stability at high temperature exposure (up to 350°C long-term and short-term at 450 °C). Experimental results and trial runs demonstrate the ability of Parylene HT coating to meet the growing requirements of higher dielectric capabilities, higher temperature integrity, mechanical processing, etc. of a dynamic electronics industry. In addition, Parylene HT polymer coating truly conforms to parts due to its molecular level deposition characteristics. Its suitability and biocompatibility encourage researchers to explore Parylene HT's role in sensors and in active electronic devices for various industries.
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Kumar, Rakesh. "Parylene HT®: A High Temperature Vapor Phase Polymer for Electronics Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000108–13. http://dx.doi.org/10.4071/hitec-rkumar-tp13.
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A development in the area of high temperature polymers, which offers solutions to many existing packaging and reliability challenges of electronics industry, is described. Packaging, protection and reliability of various electronic devices and components that include PCB's, MEM's, optoelectronic devices, fuel cell components and nano-electronic parts are becoming more challenging due to their long-term performance requirements. Parylene HT offers solutions to many existing packaging and reliability issues of electronics industry in part because of its excellent electrical & mechanical properties, chemical inertness and long-term thermal stability at high temperature exposure to over 350°C (short-term at 450 °C). Experimental results and trial runs demonstrate the ability of Parylene HT coating to meet the growing requirements of higher dielectric capabilities, higher temperature integrity and mechanical processing etc. of dynamic electronic industry. In addition, Parylene HT polymer coating truly conforms to the parts due to its molecular level deposition characteristics. Its suitability and biocompatibilty encourage researchers to explore Parylene HT's role in sensors and in active electronic devices for various industries, which include enhancing high temperature application/technologies.
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Nasiri, Ardalan, Simon S. Ang, Tom Cannon, Errol V. Porter, Kaoru Uema Porter, Caitlin Chapin, Ruiqi Chen, and Debbie G. Senesky. "High-Temperature Electronics Packaging for Simulated Venus Condition." Journal of Microelectronics and Electronic Packaging 17, no. 2 (April 1, 2020): 59–66. http://dx.doi.org/10.4071/imaps.1115241.
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Abstract An electronic packaging technology that survives the simulated Venusian surface temperature of 465°C and 96 bar pressure in carbon dioxide (CO2) and nitrogen environments, without the corrosive trace gases, was developed. Alumina ceramic substrates and gold conductors on alumina were evaluated for electrical and mechanical performance. The most promising die-attach materials are thick-film gold and alumina-based ceramic pastes. Alumina, sapphire, silicon, and silicon carbide dies were attached to the alumina substrates using these die-attach materials and exposed to 96 bar pressure in a CO2 environment at 465°C for 244 h. The ceramic die-attach material showed consistent shear strengths before and after the test. An alumina ceramic encapsulation material was also evaluated for thermomechanical stability. The devices on the packaging substrates were encapsulated by a ceramic encapsulation with no significant increase in cracks and voids after the Venusian simulator test. Wire pull strength tests were conducted on the gold bond wire to evaluate mechanical durability before and after the Venusian simulator exposure. The average gold bond wire pull strengths before and after exposure were 5.78 g-F and 4 g-F for 1-mil gold bond wires, respectively, meeting the minimum MIL-STD-885 2011.9 standard. The overall wire bond daisy chain resistance change was .47% after the Venus simulator test, indicating a promising wire bond integrity. A titanium package was fabricated to house the ceramic packaging substrate and a two-level metalized feedthrough was fabricated to provide electrical interfaces to the package.
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Daves, Glenn G. "Trends in Automotive Packaging." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (January 1, 2014): 001818–50. http://dx.doi.org/10.4071/2014dpc-keynote_th1_daves.
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The long-term trend in automobiles has been increasing electronics content over time. This trend is expected to continue and drives diverse functional, form factor, and reliability requirements. These requirements, in turn, are leading to changes in the package types selected and the performance specifications of the packages used for automotive electronics. Several examples will be given. This abstract covers the development of a distributed high temperature electronics demonstrator for integration with sensor elements to provide digital outputs that can be used by the FADEC (Full Authority Digital Electronic Control) system or the EHMS (Engine Health Monitoring System) on an aircraft engine. This distributed electronics demonstrator eliminates the need for the FADEC or EHMS to process the sensor signal, which will assist in making the overall system more accurate and efficient in processing only digital signals. This will offer weight savings in cables, harnesses and connector pin reduction. The design concept was to take the output from several on-engine sensors, carry out the signal conditioning, multiplexing, analogue to digital conversion and data transmission through a serial data bus. The unit has to meet the environmental requirements of DO-160 with the need to operate at 200°C, with short term operation at temperatures up to 250°C. The work undertaken has been to design an ASIC based on 1.0 μm Silicon on Insulator (SOI) device technology incorporating sensor signal conditioning electronics for sensors including resistance temperature probes, strain gauges, thermocouples, torque and frequency inputs. The ASIC contains analogue multiplexers, temperature stable voltage band-gap reference and bias circuits, ADC, BIST, core logic, DIN inputs and two parallel ARINC 429 serial databuses. The ASIC was tested and showed to be functional up to a maximum temperature of 275°C. The ASIC has been integrated with other high temperature components including voltage regulators, a crystal oscillator, precision resistors, silicon capacitors within a hermetic hybrid package. The hybrid circuit has been assembled within a stainless steel enclosure with high temperature connectors. The high temperature electronics demonstrator has been demonstrated operating from −40°C to +250°C. This work has been carried out under the EU Clean Sky HIGHTECS project with the Project being led by Turbomeca (Fr) and carried out by GE Aviation Systems (UK), GE Research – Munich (D) and Oxford University (UK).
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Shaddock, David, Cathleen Hoel, Nancy Stoffel, Mark Poliks, and Mohammed Alhendi. "Additively Manufactured Extreme Temperature Electronics Packaging." International Symposium on Microelectronics 2021, no. 1 (October 1, 2021): 000189–94. http://dx.doi.org/10.4071/1085-8024-2021.1.000189.
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Abstract There is growing interest in extreme temperature electronics to support the mission needs to sense, actuate, and communicate at temperatures beyond the normal range of operations in commercial and military applications. Reliable packaging in the temperature range of more than 300°C has been demonstrated using ceramic multi-chip modules using conventional hybrid circuit technology. This approach typically requires high NRE costs and lead time. Additive manufacturing processes of metals, ceramics, conductors, and dielectrics provides a digital transformation of hybrid circuit manufacturing technology that reduces time and cost for packaging with the added benefits of novel 3D structures and embedded features. This report presents the results of testing to characterize important electrical and mechanical properties of additively manufactured packaging materials (substrates, conductor, dielectrics) and die interconnect methods needed for 300 to 750 °C electronic packaging designs.
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Fang, Kun, Rui Zhang, Tami Isaacs-Smith, R. Wayne Johnson, Emad Andarawis, and Alexey Vert. "Thin Film Multichip Packaging for High Temperature Digital Electronics." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (January 1, 2011): 000039–45. http://dx.doi.org/10.4071/hiten-paper1-rwjohnson.
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Digital silicon carbide integrated circuits provide enhanced functionality for electronics in geothermal, aircraft and other high temperature applications. A multilayer thin film substrate technology has been developed to interconnect multiple SiC devices along with passive components. The conductor is vacuum deposited Ti/Ti:W/Au followed by an electroplated Au. A PECVD silicon nitride is used for the interlayer dielectric. Adhesion testing of the conductor and the dielectric was performed as deposited and after aging at 320°C. The electrical characteristics of the dielectric as a function of temperature were measured. Thermocompression flip chip bonding of Au stud bumped SiC die was used for electrical connection of the digital die to the thin film substrate metallization. Since polymer underfills are not compatible with 300°C operation, AlN was used as the base ceramic substrate to minimize the coefficient of thermal expansion mismatch between the SiC die and the substrate. Initial die shear results are presented.
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McCluskey, F. P., L. Condra, T. Torri, and J. Fink. "Packaging Reliability for High Temperature Electronics: A Materials Focus." Microelectronics International 13, no. 3 (December 1996): 23–26. http://dx.doi.org/10.1108/13565369610800386.
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Guo, Xiaorui, Qian Xun, Zuxin Li, and Shuxin Du. "Silicon Carbide Converters and MEMS Devices for High-temperature Power Electronics: A Critical Review." Micromachines 10, no. 6 (June 19, 2019): 406. http://dx.doi.org/10.3390/mi10060406.
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The significant advance of power electronics in today’s market is calling for high-performance power conversion systems and MEMS devices that can operate reliably in harsh environments, such as high working temperature. Silicon-carbide (SiC) power electronic devices are featured by the high junction temperature, low power losses, and excellent thermal stability, and thus are attractive to converters and MEMS devices applied in a high-temperature environment. This paper conducts an overview of high-temperature power electronics, with a focus on high-temperature converters and MEMS devices. The critical components, namely SiC power devices and modules, gate drives, and passive components, are introduced and comparatively analyzed regarding composition material, physical structure, and packaging technology. Then, the research and development directions of SiC-based high-temperature converters in the fields of motor drives, rectifier units, DC–DC converters are discussed, as well as MEMS devices. Finally, the existing technical challenges facing high-temperature power electronics are identified, including gate drives, current measurement, parameters matching between each component, and packaging technology.
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Kumar, Rakesh. "A high temperature nano/micro vapor phase conformal coating for electronics applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, HiTEN (January 1, 2015): 000083–90. http://dx.doi.org/10.4071/hiten-session3a-paper3a_1.
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Through characterization of dielectric and other properties at high temperatures, this work describes the development of a high temperature and UV stable nano/micro vapor phase deposited polymer coating for providing electrical insulation and protection of various electronics from chemical corrosion and other harsh environmental effects. Packaging, protection and reliability of various electronic devices and components, including PCBs, MEMS, optoelectronic devices, fuel cell components and nanoelectronic parts, are becoming more challenging due to the long-term performance requirements on devices. A recently commercialized high temperature polymer, Parylene HT®, offers solutions to many existing protective, packaging and reliability issues of electronic and medical applications, in part because of its excellent electrical and mechanical properties, chemical inertness and long-term thermal stability (high temperature exposure to over 350°C, short-term at 450 °C). Experimental results and commercial applications demonstrate the ability of Parylene HT coating to meet the growing requirements for higher dielectric capabilities, higher temperature integrity and mechanical processing, etc. of dynamic electronics applications. In addition, Parylene HT polymer coating truly conforms to parts due to its molecular level deposition characteristics. Its suitability and biocompatibility encourage researchers to explore Parylene HT's role in sensors and in active electronic devices for various industries.
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KE, Haotao, and Douglas C. Hopkins. "Development of Printed Power Packaging for a High Voltage SiC Module." International Symposium on Microelectronics 2012, no. 1 (January 1, 2012): 000955–60. http://dx.doi.org/10.4071/isom-2012-wp55.
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Due to rapidly developing post silicon power devices, in particular SiC and GaN, three primary parameters in power packaging: temperature, voltage and current, are much more difficult to manage. The SiC devices are being developed for high voltage (>15kV). The GaN devices will have extremely low internal resistance, operate at extreme current densities (≫10A/mm2), and can account for <50% of the resistance in a power module. Both devices can operate at high temperatures (>300°C) and >10-times frequency compared to Si. The traditional power electronics packaging approaches need augmentation or replacement. Most technologies used in packaging of power electronic systems, or more generally Electronic Energy Systems, are ported from microelectronics. The recent development of printable 3D circuit techniques, e.g. jetting and dispensing, provide additional major approaches applicable to power packaging. Some printing techniques are already applied to solar cells and batteries. This paper explores the printable electronics technologies for application to power.
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Khazaka, R., L. Mendizabal, D. Henry, and R. Hanna. "Survey of High-Temperature Reliability of Power Electronics Packaging Components." IEEE Transactions on Power Electronics 30, no. 5 (May 2015): 2456–64. http://dx.doi.org/10.1109/tpel.2014.2357836.
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Yiying Yao, Guo-Quan Lu, Dushan Boroyevich, and Khai D. T. Ngo. "Survey of High-Temperature Polymeric Encapsulants for Power Electronics Packaging." IEEE Transactions on Components, Packaging and Manufacturing Technology 5, no. 2 (February 2015): 168–81. http://dx.doi.org/10.1109/tcpmt.2014.2337300.
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Riches, S. T., K. Cannon, C. Johnston, M. Sousa, P. Grant, J. Gulliver, M. Langley, et al. "Application of High Temperature Electronics Packaging Technology to Signal Conditioning and Processing Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000089–96. http://dx.doi.org/10.4071/hitec-sriches-tp11.
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The requirement to install electronic power and control systems in high temperature environments has posed a challenge to the traditional limit of 125°C for high temperature exposure of electronics systems. The leap in operating temperature to above 200°C in combination with high pressures, vibrations and potentially corrosive environments means that different semiconductors, passives, circuit boards and assembly processes will be needed to fulfil the target performance specifications. Bare die mounted onto ceramic and insulated metal substrates can withstand higher temperatures than soldered surface mount devices on printed circuit boards. The results of the evaluation of electronic interconnect and substrate materials that have been submitted to temperatures of 250°C for up to 2000 hours will be presented, including details on novel adhesive formulations and high temperature insulated metal substrates. The materials and processes developed have been applied to the manufacture of high temperature circuits representative of analogue signal conditioning and processing, using silicon on insulator devices and passive components mounted into HTCC packages and onto thick film on ceramic substrates. Results of the characterisation of these devices and circuits at temperatures of 250°C for up to 2000 hours will be presented. This work forms part of the UPTEMP project has been set-up with support from UK Technology Strategy Board and the EPSRC, which started in March 2007 with 3 years duration. The project brings together a consortium of end-users (Sondex Wireline and Vibro-Meter UK), electronic module manufacturers (GE Aviation Systems Newmarket) and material suppliers (Gwent Electronic Materials and Thermastrate Ltd) with Oxford University-Materials Department, the leading UK high temperature electronics research centre.
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Riches, S. T., C. Johnston, M. Sousa, and P. Grant. "High Temperature Endurance of Packaged SOI Devices for Signal Conditioning and Processing Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (January 1, 2011): 000251–54. http://dx.doi.org/10.4071/hiten-paper8-sriches.
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Silicon on Insulator (SOI) device technology is fulfilling a niche requirement for electronics that functions satisfactorily at operating temperatures of >200°C. Most of the reliability data on the high temperature endurance of the devices is generated on the device itself with little attention being paid to the packaging technology around the device. Similarly, most of the reliability data generated on high temperature packaging technologies uses testpieces rather than real devices, which restricts any conclusions on long term electrical performance. This paper presents results of high temperature endurance studies on SOI devices combined with high temperature packaging technologies relevant to signal conditioning and processing functions for sensors in down-well and aero-engine applications. The endurance studies have been carried out for up to 7,056 hours at 250°C, with functioning devices being tested periodically at room temperature, 125°C and 250°C. Different die attach and wire bond options have been included in the study and the performance of multiplexers, transistors, bandgap voltage, oscillators and voltage regulators functional blocks have been characterised. This work formed part of the UPTEMP project which was set-up with support from UK Technology Strategy Board and the EPSRC. The project brought together a consortium of end-users (Sondex Wireline and Vibro-Meter UK), electronic module manufacturers (GE Aviation Systems Newmarket) and material suppliers (Gwent Electronic Materials and Thermastrate Ltd) with Oxford University-Materials Department, the leading UK high temperature electronics research centre.
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Williams, Jennifer, and Johnson Matthey. "High Temperature Protection against Unwanted Species within Hermetic Packaging." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, HiTEN (January 1, 2015): 000116–22. http://dx.doi.org/10.4071/hiten-session3b-paper3b_3.
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The need for electronic applications to be able to withstand high temperatures has become more prevalent in recent years. With drilling in the oil and gas industry getting deeper, the operating temperatures are getting higher, with typical geothermal gradients of 25 °C/km. Temperatures up to 250 °C are often seen by drilling operations, which is putting a greater strain on the electronics and associated packaging. Standard methods of cooling are not viable for these harsh environments, so new technology is required to negate the effects of the extreme temperatures. As well as the use of high temperature stable electronic components, High Temperature Getters are required to remove gaseous contaminants from electronic housings to negate the associated deleterious effect on performance. The contaminating species to be removed are commonly H2O, CO2, and H2, and sometimes short chain organic molecules. Conventional getter materials can remove damaging species at temperatures up to about 80 °C. New technology is however required to eliminate these species at temperatures up to 250 °C, where existing getter formulations would certainly fail. Johnson Matthey has developed a range of getters that can remove multiple contaminants at both ambient and elevated temperatures. The first product in the series, HTA 1 can remove water and carbon dioxide. Addition of a metal oxide component in HTA 2 facilitates hydrogen removal at elevated temperatures, with capacities in excess of 70 cm3/g achieved. HTA 3 can adsorb unwanted organic contaminants in addition to removing water and carbon dioxide. HTA 4 is a combined getter capable of eliminating all of the aforementioned contaminant species. These products, combined with the unique, precision engineered Hi-Rel encapsulation (Figure 1) allow getters to be supplied pre-activated, without the end user needing to apply a thermal treatment prior to use. The product can be fitted into any hermetic device to extend the lifetime, thus decreasing the number of failures within electronic assemblies, improving system reliability and preventing operations being shut down as frequently.
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Hunter, Gary W., Philip G. Neudeck, Robert S. Okojie, Glenn M. Beheim, J. A. Powell, and Liangyu Chen. "An Overview of High-Temperature Electronics and Sensor Development at NASA Glenn Research Center." Journal of Turbomachinery 125, no. 4 (October 1, 2003): 658–64. http://dx.doi.org/10.1115/1.1579508.
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This paper gives a brief overview of the status of high-temperature electronics and sensor development at NASA Glenn Research Center supported in part or in whole by the Ultra Efficient Engine Technology Program. These activities contribute to the long-term development of an intelligent engine by providing information on engine conditions even in high temperature, harsh environments. The technology areas discussed are: 1) high-temperature electronics, 2) sensor technology development (pressure sensor and high-temperature electronic nose), 3) packaging of harsh environment devices and sensors, and 4) improved silicon carbide electronic materials. A description of the state-of-the-art and technology challenges is given for each area. It is concluded that the realization of a future intelligent engine depends on the development of both hardware and software including electronics and sensors to make smart components. When such smart components become available, an intelligent engine composed of smart components may become a reality.title
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Phua, Eric Jian Rong, Ming Liu, Bokun Cho, Qing Liu, Shahrouz Amini, Xiao Hu, and Chee Lip Gan. "Novel high temperature polymeric encapsulation material for extreme environment electronics packaging." Materials & Design 141 (March 2018): 202–9. http://dx.doi.org/10.1016/j.matdes.2017.12.029.
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Quintero, Pedro O., and F. Patrick McCluskey. "Silver-Indium Transient Liquid Phase Sintering for High Temperature Die Attachment." Journal of Microelectronics and Electronic Packaging 6, no. 1 (January 1, 2009): 66–74. http://dx.doi.org/10.4071/1551-4897-6.1.66.
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The demand for electronics capable of operating at temperatures above the traditional 125°C limit continues to increase. Devices based on wide band gap semiconductors have been demonstrated to operate at temperatures up to 500°C, but packaging remains a major hurdle to product development. Recent regulations, such as RoHS and WEEE, increase the complexity of the packaging task as they prohibit the use of certain materials in electronic products such as lead (Pb), which has traditionally been used in high temperature solder die attach. In this investigation, an Ag-In solder paste is presented as a die attach alternative for high temperature applications. The proposed material has been processed by a transient liquid phase sintering method resulting in an in situ alloying of its main constituents. A shift of the melting point of the system, confirmed by differential scanning calorimetry, provided the basis for a breakthrough in the typical processing temperature rule. The mechanical integrity and reliability of this novel attachment material is discussed.
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Riches, S. T., C. Johnston, and A. Lui. "Realisation of High Temperature Electronics Packaging Technology for Sensor Conditioning and Processing Applications." International Symposium on Microelectronics 2012, no. 1 (January 1, 2012): 000192–99. http://dx.doi.org/10.4071/isom-2012-ta61.
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The requirement to install electronic power and control systems in high temperature environments in aero-engines and in down-well exploration has posed a challenge to the traditional limit of 125°C of electronics systems. The leap in operating temperature to above 200°C in combination with high pressures, vibrations and potentially corrosive environments means that different semiconductors, passives, circuit boards and assembly processes will be needed to fulfil target performance specifications. Silicon on Insulator (SOI) device technology has been shown to be capable of functioning satisfactorily at operating temperatures of >200°C. Most of the applications to date have required performance for short times (<2,000 hours) at the highest operating temperatures of up to 225°C in down-well drilling applications. There is interest in extending the endurance of high temperature electronics into aero-engine and other applications where a minimum 20 year operating life is stipulated. Most of the reliability data on the high temperature endurance of the integrated circuit is generated with little consideration of the packaging technologies, whilst most of the reliability data pertinent to high temperature packaging technologies uses test pieces, which limits any conclusions relating to long term electrical performance. This paper will present results of studies on high temperature packaging technologies relevant to signal conditioning and processing functions for sensors in down-well and aero-engine applications. Different die attach and wire bond options have been included in the study and the performance of several functional blocks on a high temperature SOI device has been tracked over the endurance tests which have lasted for >11,000 hours at 250°C. Degradation phenomena such as thermal migration and material deterioration due to high temperature exposure in air and inert atmospheres will be described. An assessment of the availability of high temperature materials and components to meet long term requirements for operation at 250°C will be presented.
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Fang, Kun, Tami Isaacs-Smith, R. Wayne Johnson, Alexey Vert, Tan Zhang, and David Shaddock. "Recent Progress in Thin Film Multichip Packaging for High Temperature Digital Electronics." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000407–12. http://dx.doi.org/10.4071/hitec-thp23.
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A thin film material and process technology is being developed and evaluated for high temperature (300°C) digital multichip modules for use in geothermal well instrumentation. The substrate technology selected is AlN to minimize the difference in the coefficient of thermal expansion between the substrate and the SiC digital die. A thin film/plated Ti/Ti:W/Au metallization is used with a plasma enhanced chemical vapor deposited Si3N4 to create multilayer interconnections. Active components are assembled to the interconnect substrate using Au stud bump thermocompression bonding. The Au stud bump maintains a monometallic interface between the substrate Au pad surface and the Au pads on the SiC die. A digital circuit has been built and successfully tested as an initial demonstration.
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Chiolino, N., A. M. Francis, J. Holmes, M. Barlow, and C. Perkowski. "470 Celsius Packaging System for Silicon Carbide Electronics." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2021, HiTEC (April 1, 2021): 000083–88. http://dx.doi.org/10.4071/2380-4491.2021.hitec.000083.
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Abstract High temperature Silicon Carbide (SiC) integrated circuit (IC) processes have enabled devices that operate at >450°C for more than a year. These results have established the need for more advanced and practical packaging strategies. Off the shelf state of the art packages cannot withstand the same high temperatures as the semiconductor can for long periods of time. Packaging SiC die to survive temperatures >450°C, while also maintaining a reasonable packaging strategy that is agile, rapid, and modular, presents new challenges. Presented is a technique for packaging SiC die with a focus on additive manufacturing, modular design scaling, and rugged survivability. This packaging strategy utilizes state of the art Additive Manufacturing (AM) methods, using an nScrypt 3Dn-Tabletop printer, together with stereolithography (SLA) digital light processing (DLP) 3D printing. Ultra-violet (UV) curable ceramic resins are used to create high temperature connectors. A design environment is also described, in which first time correct, interconnect layers are verified in software to reduce the risk of errors. A Ceramic Wiring Board Process Design Kit (CWBPDK) allows the design of single or multiple layers of metal, with fabricated SiC die. This interconnect is verified with standard design rule checking (DRC) and layout vs. schematic (LVS) software. Entire systems in packages can be verified using multiple SiC die. Input and output pins (I/O) are connected to these modules using metal connectors. After design, manufacturing can be performed in just a few days. A system in package for driving a stepper motor was designed and fabricated using this packaging method. The motor actuator design utilizes four separate SiC die. These die contain large JFETs designed for sourcing current in a unipolar stepper motor architecture. This module was placed in a furnace at 470°C and demonstrated functional operation for over 1000 hours. These devices were able to source an average of 30 mA in >400°C temperatures to drive the room temperature stepper motor. A high I/O count, next generation package for discrete SiC chips was also designed using this packaging system. A single large JFET component was soaked for over 100 hours at both 500°C and 800°C. Utilizing Ozark IC’s automated test design environment, several DC and transient variables were captured for both tests and will be presented.
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Vert, Alexey, Cheng-Po Chen, Amita Patil, Rich Saia, Emad Andarawis, Avinash Kashyap, Tan Zhang, et al. "Silicon Carbide High Temperature Operational Amplifier." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000378–83. http://dx.doi.org/10.4071/hitec-thp12.
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Development of silicon carbide operational amplifier offers an attractive alternative building block for the replacement of silicon and silicon-on-insulator analog circuits in harsh environment applications. NMOS-based enhancement mode silicon carbide device technology was utilized to demonstrate feasibility of operational amplifiers for use in harsh environment applications. This study reports on the results of characterization of operational amplifiers at room temperature and high temperatures up to 350°C. The development of high temperature packaging techniques enabled assembly of a functional oscillator board tested up to 350°C. A test fixture with high temperature sockets enabling quick swap of operational amplifiers is also discussed as an important tool in high temperature electronics research and development.
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Rashid, S. J., C. Mark Johnson, F. Udrea, Andrej Mihaila, G. Amaratunga, and Rajesh Kumar Malhan. "Analysis of Novel Packaging Techniques for High Power Electronics in SiC." Materials Science Forum 556-557 (September 2007): 971–74. http://dx.doi.org/10.4028/www.scientific.net/msf.556-557.971.
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A novel high temperature wire bondless packaging technique is numerically investigated in this paper. Extraction of device effective resistivity with temperature from numerical characteristics of 1.2kV 4H-SiC MOSFETs at a current density of 400A/cm2 have demonstrated a T−2 temperature dependence. Electro-thermal finite element analysis (FEA) of 1.2kV 4H-SiC MOSFETs sandwiched between two etched direct-bonded-copper substrate tiles has been performed. The thermal resistance of the ceramic sandwich package shows a 75% reduction in thermal resistance compared to conventional wire bonded assemblies. Mechanical analysis of the assembly has been used to investigate the residual stresses in the SiC dies at room temperature, which are then alleviated at higher temperatures during device operation. Mismatch of the expansion coefficients of the auxiliary materials in the assembly result in elevated stresses at full load operation, however these are well below the tensile strength of the respective materials and hence do not compromise the mechanical integrity of the package.
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Fan, Jiajie, Dawei Jiang, Hao Zhang, Dong Hu, Xu Liu, Xuejun Fan, and Guoqi Zhang. "High-temperature nanoindentation characterization of sintered nano-copper particles used in high power electronics packaging." Results in Physics 33 (February 2022): 105168. http://dx.doi.org/10.1016/j.rinp.2021.105168.
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Becker, K. F., T. Thomas, J. Bauer, R. Kahle, T. Braun, R. Aschenbrenner, M. Schneider-Ramelow, and K. D. Lang. "Smart Power Module Molding Advances: Evaluating high temperature suitability of Molding Compounds." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000177–82. http://dx.doi.org/10.4071/isom-2013-ta62.
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During the last years within power electronics packaging a trend towards compact power electronics modules for automotive and industrial applications could be observed, where a smart integrated control unit for motor drives is replacing bulky substrates with discrete control logic and power electronics. Most recent modules combine control and power electronics yielding maximum miniaturization. Transfer molding is the method of choice for cost effective encapsulation of such modules due to robustness of the molded modules and moderate cost of packaging. But there are challenges with this type of package: Typically those packages are asymmetric, a substrate with single sided assembly is overmolded on the component side and the substrate backside is exposed providing a heat path for optimized cooling. This asymmetric geometry is prone to yield warped substrates, preventing optimum thermal contact to the heatsink and also putting thermo-mechanical stress on the encapsulated components, possibly reducing reliability. Such packages being truly heterogeneous, combining powerICs, wire bonds, SMDs, controlICs, substrate and leadframe surfaces, the encapsulant used needs to adhere sufficiently to all surfaces present. Additionally those packages need to operate at elevated temperatures for long time, e.g. operate at 200 °C for 1000 h and more, so high thermal stability is of ample importance. Within this paper the main goal is to identify transfer molding compounds suitable for the encapsulation of smart power modules, ready to be used at 200 °C and determine the actual maximum temperature of use of such high performance molding compounds currently available in the market. Summarized a detailed description of the high temperature suitability of high performance molding compounds is provided – additionally an extended test methodology is described to facilitate future material evaluation for HT or harsh environment use of polymeric materials as encapsulants or base materials.
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Fraley, John R., Lauren Kegley, Stephen Minden, Jimmy L. Davidson, and David Kerns. "HIGH TEMPERATURE HYBRID NANODIAMOND SENSOR SYSTEMS." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (January 1, 2014): 000034–39. http://dx.doi.org/10.4071/hitec-ta23.
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In recent years, high temperature semiconductors have been utilized in wireless telemetry systems for use in military and commercial applications, wherein a high temperature environment combined with other factors such as rotating machinery or weight-constraints preclude the use of conventional silicon based wireless telemetry or wired sensor solutions. Present systems include those which can measure temperatures, pressures, vibrations, and strains. By combining the advanced electronics developed for these systems with novel sensor elements created using chemical vapor deposition (CVD) nanodiamond technology, a wide range of other high temperature sensing systems can be enabled. The unique properties of the diamond sensors have proven in principle the capability to sense, with quantifiable signal, a wide variety of parameters under extreme conditions including very high temperatures and pressures. It has been clear for some time that diamond would be the ideal material of choice for solid-state sensors, but only in recent years has the advent of CVD diamond (as opposed to natural or HPHT [high pressure, high temperature] formation) opened the door for its practical development into harsh environment sensor systems. By combining these diamond sensor elements with high temperature electronics and high temperature packaging approaches, smart sensors can be developed to measure parameters ranging from gas chemical species on the surface of Venus, to neutron flux rates outside of a nuclear reactor core. The research presented here is centered around the use of hybrid diamond sensors for neutron detection applications in Nuclear Thermal Propulsion systems. The current technology state and development needs for these hybrid high temperature diamond smart sensors will be highlighted to potentially encourage future R&D from the high-temperature electronics community.
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Smarra, Devin A., Guru Subramanyam, Vamsy P. Chodavarapu, Sivaram P. Gogineni, Kenneth J. Semega, and Alireza R. Behbahani. "Embedded Passive Circuit Elements in Low Temperature Co-Fired Ceramic Substrates for Aerospace Electronics." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000417–25. http://dx.doi.org/10.4071/isom-2017-wp35_142.
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Abstract The packaging technology plays a critical role in the development of environmentally robust microelectronic systems. There is great demand for microelectronic systems that can withstand harsh environments and high temperatures in numerous applications including down-hole drilling, geothermal drilling, aerospace, heavy industrial, and automotive industries. In these applications, both sensors and interface electronics could be subjected to temperatures of 200°C and beyond. Standard plastic or epoxy based printed circuit boards are not reliable at these temperatures for long term operation. Packaging techniques such as Low Temperature Co-fired Ceramic (LTCC) offer a versatile and reliable alternative to form electronic substrates. LTCC is a multi-layer packaging system that also provides the ability to embedded passive components, such as resistors and capacitors, and thermal management structures within the substrate. This work evaluates the performance of LTCC embedded passive elements from 25°C to 225°C. A variety of passive component designs are evaluated using theoretical calculations, simulations, and measurements of fabricated test structures.
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Hornberger, J., B. McPherson, J. Bourne, R. Shaw, E. Cilio, W. Cilio, B. Reese, et al. "High Temperature Silicon Carbide Power Modules for High Performance Systems." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (January 1, 2011): 000159–66. http://dx.doi.org/10.4071/hiten-paper5-jhornberger.
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The demands of modern high-performance power electronics systems are rapidly surpassing the power density, efficiency, and reliability limitations defined by the intrinsic properties of silicon-based semiconductors. The advantages of silicon carbide (SiC) are well known, including high temperature operation, high voltage blocking capability, high speed switching, and high energy efficiency. In this discussion, APEI, Inc. presents two newly developed high performance SiC power modules for extreme environment systems and applications. These power modules are rated to 1200V, are operational at currents greater than 100A, can perform at temperatures in excess of 250 °C, and are designed to house various SiC devices, including MOSFETs, JFETs, or BJTs. One newly developed module is designed for high performance, ultra-high reliability systems such as aircraft and spacecraft, and features a hermetically sealed package with a ring seal technology capable of sustaining temperatures in excess of 400°C. The second module is designed for high performance commercial and industrial systems such as hybrid electric vehicles or renewable energy applications, implements a novel ultra-low parasitic packaging approach that enables high switching frequencies in excess of 100 kHz, and weighs in at just over 130 grams (offering ~5× mass reduction and ~3× size reduction in comparison with industry standard power brick packaging technology). It is configurable as either a half or full bridge converter. In this discussion, APEI, Inc. introduces these products and presents practical testing of each.
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Guo, Wei, Zhi Zeng, Xiaoying Zhang, Peng Peng, and Shanping Tang. "Low-Temperature Sintering Bonding Using Silver Nanoparticle Paste for Electronics Packaging." Journal of Nanomaterials 2015 (2015): 1–7. http://dx.doi.org/10.1155/2015/897142.
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Ag nanoparticles (NPs) with about 40 nm diameter covered with 5–8 nm organic shell were prepared by chemical reduction reaction. The thermal characteristics of Ag nanoparticle (NP) paste were measured by thermogravimetric analysis (TGA) and differential scanning calorimetry (DSC). The low-temperature sintering bonding processes using Ag NP paste were carried out at the temperature range of 150–350°C for 5 min under the pressure of 3 MPa. The microstructures of the sintered joint and the fracture morphology were evaluated by scanning electron microscopy (SEM). The shear strength was used to evaluate the mechanical property of the sintered joint. TGA-DSC test showed that the Ag content is approximately 95.5 mass% in Ag NP paste. The average shear strength of the joint fabricated at 250°C for 5 min under the pressure of 3 MPa was about 28 MPa, which could meet the requirements of electronics packaging working at high temperature. The joint shear strength increased with the increase of the sintering temperature due to much denser sintered Ag NPs and more comprehensive metallurgical bonds formed in the joint.
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Low, Yee L., Ronald E. Scotti, David A. Ramsey, Cristian A. Bolle, Steven P. O’Neill, and Khanh C. Nguyen. "Packaging of Optical MEMS Devices." Journal of Electronic Packaging 125, no. 3 (September 1, 2003): 325–28. http://dx.doi.org/10.1115/1.1535933.
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Recently, optical MEMS devices have gained considerable attention in the telecommunications industry—particularly in the optical networking and switching arenas. Since optical MEMS are micro-systems which rely on high precision optics, electronics and mechanics working in close concert, these emerging devices pose some unique packaging challenges yet to be addressed by the general packaging industry. Optical MEMS packages often are required to provide both optical and electrical access, hermeticity, mechanical strength, dimensional stability, and long-term reliability. Hermetic optical access necessitates the use of metallized and anti-reflection coated windows, and ever-increasing electrical I/O count has prompted the use of higher density substrate/package technologies. Taking these requirements into consideration, we explore three ceramic packaging technologies, namely high-temperature co-fired ceramic (HTCC), low-temperature co-fired ceramic (LTCC), and thin-film ceramic technologies. In this paper, we describe some optical MEMS packages designed using these three technologies and discuss their substrate designs, package materials, ease of integration and assembly.
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Tatsumi, Hiroaki, and Hiroshi Nishikawa. "Anisotropic highly conductive joints utilizing Cu-solder microcomposite structure for high-temperature electronics packaging." Materials & Design 223 (November 2022): 111204. http://dx.doi.org/10.1016/j.matdes.2022.111204.
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Kaessner, Stefan, Markus G. Scheibel, Stefan Behrendt, Bianca Boettge, Christoph Berthold, and Klaus G. Nickel. "Reliability of Novel Ceramic Encapsulation Materials for Electronic Packaging." Journal of Microelectronics and Electronic Packaging 15, no. 3 (July 1, 2018): 132–39. http://dx.doi.org/10.4071/imaps.661015.
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Abstract Enhancements on power electronic systems with reduced chip area and miniaturized passive components are subject of several research activities in academics and industry. To realize such future electronic devices, it is necessary to incorporate wide bandgap semiconductor technology such as silicon carbide and gallium nitride operating at higher temperatures. Therefore, the development of novel materials with high thermal conductivities and stability, withstanding harsh environments up to 300°C is of major interest. Especially, polymeric encapsulation materials have to be improved because of common degradation effects above 175°C. Ceramic (nonpolymeric) materials with thermal conductivities above 5 W/(m·K) already illustrated promising results for the encapsulation of power electronics. The present work illustrates recent developments and improvements on novel ceramic encapsulation materials, which finally avoid critical interactions with the chip surface. Furthermore, advances in reliability will be discussed in terms of passed high-temperature reverse bias and humidity tests correlated with relevant material properties.
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Kaessner, S., M. G. Scheibel, S. Behrendt, B. Boettge, and K. G. Nickel. "Reliability of Novel Ceramic Encapsulation Materials for Electronic Packaging." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000425–33. http://dx.doi.org/10.4071/2380-4505-2018.1.000425.
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Abstract Enhancements on power electronic systems with reduced chip area and miniaturized passive components are subject of several research activities in academics and industry. To realize such future electronic devices, it is necessary to incorporate wide bandgap semiconductor technology such as silicon carbide and gallium nitride operating at higher temperatures. Therefore, the development of novel materials with high thermal conductivities and stability, withstanding harsh environments up to 300°C is of major interest. Especially, polymeric encapsulation materials have to be improved because of common degradation effects above 175°C. Ceramic (nonpolymeric) materials with thermal conductivities above 5 W/(m·K) already illustrated promising results for the encapsulation of power electronics. The present work illustrates recent developments and improvements on novel ceramic encapsulation materials, which finally avoid critical interactions with the chip surface. Furthermore, advances in reliability will be discussed in terms of passed high-temperature reverse bias and humidity tests correlated with relevant material properties.
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Chen, Liang-Yu. "Electrical Performance of Cofired Alumina Substrates at High Temperatures." Journal of Microelectronics and Electronic Packaging 10, no. 3 (July 1, 2013): 89–94. http://dx.doi.org/10.4071/imaps.375.
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A 96% polycrystalline alumina (Al2O3) based prototype packaging system with Au thick-film metallization successfully facilitated long term testing of high temperature SiC electronic devices for over 10,000 h at 500°C previously. However, the 96% Al2O3 chip-level packages of this prototype system were not fabricated via a commercial cofire process, which would be more suitable for large scale commercial production. The cofired alumina materials adopted by the packaging industry today usually contain several percent of glass constituents to allow cofiring processes at temperatures usually lower than the regular sintering temperature for alumina. In order to answer the question of whether cofired alumina substrates can provide a reasonable high temperature electrical performance comparable to regular 96% alumina sintered at 1700°C, this paper reports on the dielectric performance of a selected high temperature cofired ceramic (HTCC) alumina substrate and a low temperature cofired ceramic (LTCC) alumina (polycrystalline aluminum oxides with glass constituents) substrate from room temperature to 550°C at frequencies of 120 Hz, 1 KHz, 10 KHz, 100 KHz, and 1 MHz. Parallel-plate capacitive devices with dielectrics of these cofired alumina and precious metal electrodes were used for measurement of the dielectric properties of the cofired alumina materials in the temperature and frequency ranges. The capacitance and AC parallel conductance of these capacitive devices were directly measured by an AC impedance meter, and the dielectric constant and parallel AC conductivity of the dielectric were calculated from the capacitance and conductance measurement results. The temperature and frequency dependent dielectric constant, AC conductivity, and dissipation factor of selected LTCC and HTCC cofired alumina substrates are presented and compared with those of 96% alumina. Metallization schemes for cofired alumina for high temperature applications are discussed to address the packaging needs for low-power 500°C SiC electronics.
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Slater, Conor, Fabrizio Vecchio, Thomas Maeder, and Peter Ryser. "Characterisation of test vehicle for in-situ measurement of die attach thermal conductivity." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, CICMT (September 1, 2012): 000030–34. http://dx.doi.org/10.4071/cicmt-2012-ta15.
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The continuing trend in the automotive and aviation industries to reduce complexity of electronic systems by removing cooling results in a need for high temperature electronics and associated packaging technologies. To ensure reliability over long periods of time the degradation of the packaging materials should be characterised. Epoxies show great promise as a reliable die attach solution for high temperature electronics due to their high bond strength, resistance to fatigue and chemical stability at temperatures up to 250°C. This work presents a method and test vehicle for measuring the thermal conductivity of an epoxy die attach. The test vehicle is constructed by using the epoxy under test to bond a die with an integrated PTC heater to an alumina substrate. To measure the thermal conductivity the heater heats the die for a few seconds after which the die allowed to cool down to the temperature of the substrate. The temperature of the cooling die is monitored and the time constant of the temperature decay is used to calculate the thermal conductivity of the die attach. Previous work demonstrated that this method can provide realistic information on the state of the die attach by relating the measured thermal conductivity to the shear strength of the die. Additionally the method is non destructive and can be used to monitor the degradation of the attach, such as fatigue cracking during thermal cycling. Here the test vehicle is modeled using the finite element method to get a better understanding of what temperatures the die attach is subjected to and to improve the thermal conductivity measurement.
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Kaplar, Robert J., Jason C. Neely, Dale L. Huber, and Lee J. Rashkin. "Generation-After-Next Power Electronics: Ultrawide-bandgap devices, high-temperature packaging, and magnetic nanocomposite materials." IEEE Power Electronics Magazine 4, no. 1 (March 2017): 36–42. http://dx.doi.org/10.1109/mpel.2016.2643098.
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Hirose, Akio, Naoya Takeda, Yosuke Konaka, Hiroaki Tatsumi, Yusuke Akada, Tomo Ogura, Eiichi Ide, and Toshiaki Morita. "Low Temperature Sintering Bonding Process Using Ag Nanoparticles Derived from Ag2O for Packaging of High-Temperature Electronics." Materials Science Forum 706-709 (January 2012): 2962–67. http://dx.doi.org/10.4028/www.scientific.net/msf.706-709.2962.
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A novel bonding process using Ag2O paste composed of Ag2O particles and a reducing agent has been proposed as a Pb-free alternative of high melting point solders in electronics packaging. Ag2O paste formed Ag nanoparticles through the redox reaction in the bonding process and in-situ formed Ag nanoparticles sintered immediately. While the bonding process using Ag metallo-organic nanoparticles, which have been proposed, was unfavorable to the bonding at 250 degree Celsius or lower in terms of requiring removal of stable organic shells, the bonding process using Ag2O paste demonstrated the possibility of further low-temperature bonding.
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Chen, Liang-Yu. "Electrical Performance of Co-Fired Alumina Substrates at High Temperatures." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000173–78. http://dx.doi.org/10.4071/hitec-2012-wa22.
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A 96% polycrystalline alumina (Al2O3) based prototype packaging system with Au thick-film metallization successfully facilitated long term testing of high temperature SiC electronic devices for over 10,000 hours at 500°C previously. However, the 96% Al2O3 chip-level packages of this prototype system were not fabricated via a commercial co-fire process which is more suitable for large scale commercial production. The co-fired alumina materials adopted by the packaging industry today usually contain several percent of glass constituents to provide better adhesion and sealing at interfaces formed during a co-firing process at temperatures usually lower than the regular sintering temperature for alumina. In order to answer the question if co-fired alumina substrates can provide reasonable high temperature electrical performance comparable to those of regular 96% alumina sintered at 1700°C, this paper reports on the dielectric performance of a selected high temperature co-fired ceramic (HTCC) alumina substrate and a low temperature co-fired ceramic (LTCC) alumina (polycrystalline aluminum oxides with glass constituents) substrate from room temperature to 550°C at frequencies of 120 Hz, 1 KHz, 10 KHz, 100 KHz, and 1 MHz. Parallel-plate capacitive devices with dielectrics of these co-fired alumina and precious metal electrodes were used for measurement of the dielectric properties of the co-fired alumina materials in the temperature and frequency ranges. The capacitance and AC parallel conductance of these capacitive devices were directly measured by an AC impedance meter, and the dielectric constant and parallel AC conductivity of the dielectric were calculated from the capacitance and conductance measurement results. The temperature and frequency dependent dielectric constant, AC conductivity, and dissipation factor of selected LTCC and HTCC co-fired alumina substrates are presented and compared to those of 96% alumina. Metallization schemes for co-fired alumina for high temperature applications are discussed to address packaging needs for low power 500°C SiC electronics.
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Li, Mingli, Na Gong, Jinhui Wang, and Zhibin Lin. "Phase Change Material for Thermal Management in 3D Integrated Circuits Packaging." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000649–53. http://dx.doi.org/10.4071/isom-2015-tha44.
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Effective thermal control and management in three-dimensional electronic packaging are desirable to ensure the heat generated in integrated circuits can be dissipated. Conventional base materials in electronics from substrate to protective layers, due to low coefficient of thermal conductivity, cannot help to cool down the circuits, while such elevated temperature could highly impact the performance of the chips. In this study, phase change material (PCM) is selected for potential applications in thermal management of electronic packaging due to its isothermal nature and high thermal storage capability. PCM based composite is developed through the impregnation technology using highly porous expanded graphite. Heat transfer test results reveal that the PCM based composite displays superior heat storage capacity, while maintaining the favorable feature of thermal and chemical stabilization for electronic applications. Toward the end, the concept of implementation of PCM based composite is proposed in thermal control of 3D integrated circuits. It is expected the proposed composite will improve heat dissipation, and ultimately enhance the performance of the chips.
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Wang, Baron, Andrea S. Chen, and Randy H. Y. Lo. "Characteristics of Organic-Based Thermal Interface Materials Suitable for High Temperature Operation." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, HiTen (July 1, 2019): 000041–44. http://dx.doi.org/10.4071/2380-4491.2019.hiten.000041.
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Abstract Historically, for semiconductors subject to standard operating temperatures--which tend not to exceed 125°C--the Tg (glass transition temperatures) of the organic packaging materials protecting the chips is usually around 175°C. Given that, when it comes to electronics operating at high temperatures—typically an environment where the ambient temperature exceeds 200°C—the use of organic materials is generally prohibited due to rapid degradation. At those elevated temperatures, the packaging materials selected are generally composed of metals and ceramics but these materials come with their own shortfalls as well as higher material and manufacturing costs. Therefore, it would be desirable if there were ‘ruggedized’ versions of the organic compounds so commonly used in semiconductor packaging but available for more extreme temperatures, both to reduce cost and package footprint. Meanwhile, the demands from recent developments in high performance computing (HPC) and high-speed data networks means a greater need for increased power and thermal dissipation coupled with very large package body sizes to accommodate the high I/O count. The latest in server microprocessor (MPU) products can easily generate up to 300W during operation, and the heat generated must be quickly transported away from chip to prevent the threat of thermal shutdown. The thermal dissipation issue is controlled by the use of heat spreaders and heat sinks, both of which are intended to make contact with the back-side of a flipped MPU via a thermal interface material (TIM), as part of a large die, large body-size flip-chip ball grid array (FCBGA) package. The thermal interface materials discussed here are examples of organic engineered materials that are capable of withstanding higher operating temperatures than typically seen by semiconductors encased in organic-based packaging. This paper will look at the key material and mechanical attributes for a good thermal interface material, examines the pros-and-cons of various thermal interface material formulations, and discusses the factors for reliable thermal dissipation performance.
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Riches, S. T., C. Johnston, A. Crossley, and P. Grant. "End of Life Failure Modes for Packaged SOI Devices for Signal Conditioning and Processing Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000327–34. http://dx.doi.org/10.4071/hitec-2012-tha21.
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Silicon on Insulator (SOI) device technology has been shown to be capable of functioning satisfactorily at operating temperatures of >200°C. Most of the applications to date have required performance for short times (<2,000 hours) at the highest operating temperatures of up to 225°C in down-well drilling applications. There is interest in extending the endurance of high temperature electronics into aero-engine and other applications where a minimum 20 year operating life is stipulated. In order to gain confidence in high temperature electronics that can meet this requirement, accurate reliability data are needed and end of life failure modes need to be identified. Most of the reliability data on the high temperature endurance of the integrated circuit is generated with little consideration of the packaging technologies, whilst most of the reliability data pertinent to high temperature packaging technologies uses test pieces rather than devices, which limits any conclusions relating to long term electrical performance. This paper presents results of temperature storage and cycling endurance studies on SOI devices combined with high temperature packaging technologies relevant to signal conditioning and processing functions for sensors in down-well and aero-engine applications. The endurance studies have been carried out for up to 11,088 hours at 250°C, with functioning devices being tested periodically at room temperature, 125°C and 250°C and rapid thermal cycling from −40°C to +225°C. Different die attach and wire bond options have been included in the study and the performance of several functional blocks on the SOI device has been tracked over the endurance tests. The failure modes observed on completion of the endurance tests include die cracking and deterioration of the device bond pads accelerated due to degradation of some die attach materials. The routes to achieving stable long term performance of packaged devices at temperatures of 250°C will be outlined.
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Spory, Erick M. "Increased High-Temperature IC Packaging Reliability Using Die Extraction and Additive Manufacturing Assembly." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (January 1, 2016): 000018–22. http://dx.doi.org/10.4071/2016-hitec-18.
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Abstract Semiconductor parts are most often specified for use in the “commercial” 0 to 70°C and, to a lesser extent, in the “industrial” −40 to 85°C operating temperature range. These operating temperature ratings generally satisfy the demands of the dominant semiconductor customers in the computer, telecommunications, and consumer electronic industries. There is also a demand for parts rated beyond the “industrial” temperature range, primarily from the aerospace, military, oil and gas exploration, and automotive industries (−55 to +125C, and even higher). However, the demand has not been large enough to attract or retain the interest of major semiconductor part manufacturers to make these parts. In fact, wide temperature range parts are becoming obsolete and functionally equivalent parts are not replacing them. Today, for some applications, it is difficult to procure parts that meet engineering, economic, logistical, and technical integration requirements of product manufacturers, and that are rated for an extended temperature range (typically beyond 0 to 70°C). In some applications, the product is available only in the “commercial” temperature range, with commercial packaging. If the product application environment is outside the commercial range, steps must be taken to address this apparent incompatibility. For example, oil exploration and drilling applications require small, advanced communication electronics to work underground at high temperatures where cooling is not possible. This is where uprating comes into play. Despite the fact that a part can be uprated relative to functional performance at higher than specified temperatures, the original packaging and connectivity may not be reliable with long term exposure to greater than 150C due to Kirkendall voiding and general plastic degradation. However, if the original die with gold wire and aluminum pad bond is extracted from the original plastic commercial package and reassembled into a new ceramic package body, excellent reliability at temperatures exceeding 200C can be achieved. The original gold/aluminum bond interface can be removed and replaced with an electroless nickel, electroless palladium, immersion gold (ENEPIG) process, or a much more economical, automated process can be used. This process is discussed in the accompanying paper and utilizes additive manufacturing to place an aerosol jet silver deposition over the existing gold ball, interfacing with the remaining exposed aluminum. In this manner, a high-reliability connection system can be achieved which is immune to Kirkendall voiding for the temperature range of interest.
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Liu, Canyu, Allan Liu, Yutai Su, Zhaoxia Zhou, and Changqing Liu. "Nano Ag sintering on Cu substrate assisted by self-assembled monolayers for high-temperature electronics packaging." Microelectronics Reliability 126 (November 2021): 114241. http://dx.doi.org/10.1016/j.microrel.2021.114241.
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Valdez-Nava, Zarel, Sophie Guillemet-Fritsch, Marc Ferrato, Masahiro Kozako, and Thierry Lebey. "Co-fired AlN–TiN assembly as a new substrate technology for high-temperature power electronics packaging." Ceramics International 39, no. 8 (December 2013): 8743–49. http://dx.doi.org/10.1016/j.ceramint.2013.04.060.
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Paul, Riya, Amol Deshpande, Fang Luo, and Wei Fan. "Thermal Management in High-Density High-Power Electronics Modules Using Thermal Pyrolytic Graphite." International Symposium on Microelectronics 2020, no. 1 (September 1, 2020): 000259–63. http://dx.doi.org/10.4071/2380-4505-2020.1.000259.
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Abstract Tremendous effort is going on towards the packaging of power electronics modules to reduce the parasitic impedances and in turn, the voltage spikes during switching transients of power devices. The heat dissipated in terms of switching losses for high frequency applications need to be eliminated further to have some flexibility regarding the layout and, for the safe functioning of a power module by reducing junction temperature. Thermal pyrolytic graphite (TPG), with its high basal-plane thermal conductivity along the vertical direction helps direct heat towards the module bottom (cooling system), whereas its extremely low through-plane thermal conductivity along the horizontal direction guarantees minimum heat coupling among devices placed on the substrate surface. FEA simulations to verify thermal benefits of TPG and experimental results have been shown in this work which validates the junction temperature drop of up to 17 °C when using TPG as substrate and heat spreader compared with traditional materials.
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Cobley, A. J., J. E. Graves, A. Kassim, B. Mkhlef, and B. Abbas. "Ultrasonically Enabled Low Temperature Electroless Plating for Advanced Electronic Manufacture." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000183–87. http://dx.doi.org/10.4071/isom-2013-ta63.
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Electroless plating is an important process for the metallization of non-conductive substrates and is therefore widely utilized throughout the electronics and packaging industry. Electronic manufacture now requires processes and materials that can meet the demands for miniaturization and reliability since holes and via diameters in both printed circuit boards (PCBs) and microelectronics are being reduced whilst aspect ratios are getting higher. It is critical for the future development of electronics that manufacturing processes become adapted to meet these requirements. In terms of electroless plating, miniaturization means that ensuring full coverage in vias and holes is extremely challenging whilst the electroless deposit structure is important to ensure high reliability, high conductivity etc. In addition the plating process must be able to meet the need for high production volumes (i.e. high deposition rates) whilst enabling more sustainable, low energy manufacturing. Performing electroless plating in an ultrasonic field has great potential to enhance the deposit properties and meet these advanced manufacturing requirements. This paper will discuss the results from the IeMRC funded ULTIEMet (Ultrasonically enabled Low Temperature Immersion and Electroless Metallization) research project which has utilized a methodology incorporating a mixture of electrochemical and laboratory plating tests. It has been found that by optimizing how ultrasound is introduced to the electroless process benefits such as reduced temperature plating, enhanced coverage and a finer grain structure deposit can be realized.
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Chen, Liang-Yu. "Improvement of Dielectric Performance of a Prototype AlN High Temperature Chip-level Package." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, HITEN (January 1, 2011): 000052–57. http://dx.doi.org/10.4071/hiten-paper3-lchen.
Full textAbstract:
Aluminum nitride (AlN) has been proposed as a packaging substrate material for reliable high temperature electronics operating in a wide temperature range. However, it was discovered in a recent study that the dielectric properties of some commercial polycrystalline AlN materials change quite significantly with temperature at high temperatures. These material properties resulted in undesired large and temperature-dependent parasitic parameters for a prototype chip-level package based on an AlN substrate with the yttrium oxide dopant. This paper reports a method using a coating layer of a commercial thick-film glass on the AlN substrate surface to significantly reduce both the parasitic capacitances and parasitic conductances between neighboring inputs/outputs (I/Os) of a prototype AlN chip-level package. The parasitic parameters of 8-I/Os low power chip-level packages with the insulating glass coating were characterized at frequencies from 120 Hz to 1 MHz between room temperature and 500°C. These results were compared with the parameters of AlN packages without the glass coating. The results indicate that the parasitic capacitances and conductances between I/Os of the improved prototype AlN packages are significantly reduced and stable at high temperatures. The method using a glass coating provides a feasible way to mitigate the temperature dependence of dielectric properties of AlN and further utilize AlN as a reliable packaging substrate material for high temperature applications.
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Ross, R. G. "A Systems Approach to Solder Joint Fatigue in Spacecraft Electronic Packaging." Journal of Electronic Packaging 113, no. 2 (June 1, 1991): 121–28. http://dx.doi.org/10.1115/1.2905377.
Full textAbstract:
Differential expansion induced fatigue resulting from temperature cycling is a leading cause of solder joint failures in spacecraft. Achieving high reliability flight hardware requires that each element of the fatigue issue be addressed carefully. This includes defining the complete thermal-cycle environment to be experienced by the hardware, developing electronic packaging concepts that are consistent with the defined environments, and validating the completed designs with a thorough qualification and acceptance test program. This paper describes a useful systems approach to solder fatigue based principally on the fundamental log-strain versus log-cycles-to-failure behavior of fatigue. This fundamental behavior has been useful to integrate diverse ground test and flight operational thermal-cycle environments into a unified electronics design approach. Each element of the approach reflects both the mechanism physics that control solder fatigue, as well as the practical realities of the hardware build, test, delivery, and application cycle.