Journal articles on the topic 'High static power dissipation'
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1
J. Raut, Ketan, Abhijit V. Chitre, Minal S. Deshmukh, and Kiran Magar. "Low Power VLSI Design Techniques: A Review." Journal of University of Shanghai for Science and Technology 23, no. 11 (November 9, 2021): 172–83. http://dx.doi.org/10.51201/jusst/21/11881.
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Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.
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Di Meo, Gennaro, Davide De Caro, Nicola Petra, and Antonio G. M. Strollo. "A Novel Low-Power High-Precision Implementation for Sign–Magnitude DLMS Adaptive Filters." Electronics 11, no. 7 (March 24, 2022): 1007. http://dx.doi.org/10.3390/electronics11071007.
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This paper investigates the use of approximate fixed-width and static segment multipliers in the design of Delayed Least Mean Square (DLMS) adaptive filters based on the sign–magnitude representation for the error signal. The fixed-width approximation discards part of the partial product matrix and introduces a compensation function for minimizing the approximation error, whereas the static segmented multipliers reduce the bit-width of the multiplicands at runtime. The use of sign–magnitude representation for the error signal reduces the switching activity in the filter learning section, minimizing power dissipation. Simulation results reveal that, by properly sizing the two approaches, a steady state mean square error practically unchanged with respect to the exact DLMS can be achieved. The hardware syntheses in a 28 nm CMOS technology reveal that the static segmented multipliers perform better in the learning section of the filter and are the most efficient approach to reduce area occupation, while the fixed-width multipliers offer the best performances in the finite impulse response section and provide the lowest power dissipation. The investigated adaptive filters overcome the state-of-the-art, exhibiting an area and power reduction with respect to the standard implementation up to −18.0% and −64.1%, respectively, while preserving the learning capabilities.
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Bhargavi, K. Manju. "Design of Linear Feedback Shift Register for Low Power Applications." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 31, 2021): 3912–18. http://dx.doi.org/10.22214/ijraset.2021.37251.
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This paper presents the design & implementation of the Linear Feedback Shift Register (LFSR) using the Mentor Graphics tool in 90nm technology. LFSR’s have a wide variety of applications. They are used in pseudo-random variety generation, whitening sequences and pseudo-noise sequences. MOS current-mode logic (MCML) and Dynamic current-mode logic (DYCML) are employed to design an LFSR. MCML is widely used in high-speed applications and these MCML circuits are based on current steering logic. The advantages of the MCML method are that they have high noise immunity due to their differential nature of inputs. The disadvantage of MCML approach is static power dissipation. To overcome these issues of MCML logic, Dynamic CML logic is used. Its advantages include low static power dissipation and high performance. This paper shows the comparison results of CMOS, Dynamic CML and MCML designs in terms of delay, power and transistor count.
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Patel, Ambresh, and Ritesh Sadiwala. "Optimizing and Recuperating the Leakages in Low Voltage CMOS Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 14, no. 02 (June 30, 2022): 202–5. http://dx.doi.org/10.18090/samriddhi.v14i02.13.
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With the advancement of technology, small and handy electronic devices are built with low supply voltage and lower power dissipation in designing deep submicron static CMOS circuits. Small devices scaling down with burst-mode type integrated circuits have two major challenges: area and power dissipation. This paper presents a method for decreasing dynamic power, area, and leakage of application-specific integrated circuits without sacrificing performance. The High Threshold Leakage Control Transistor, TG-Based Technique, Supply Voltage Scaling, Sleep Transistor approaches are covered, and a dynamic CMOS architecture with stack transistor. With certain area and delay considerations, these strategies are utilized to diminish both types of power dissipation in the CMOS logic designs.
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Zhang, Liang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, and Paul D. Franzon. "A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 9 (September 2009): 1267–74. http://dx.doi.org/10.1109/tvlsi.2008.2002682.
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This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5-10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5-48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80-1.52 pJ/b. This work demonstrates a 15.0%-67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.
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Bansal, Deepika, Brahmadeo Prasad Singh, and Ajay Kumar. "Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic." Bulletin of Electrical Engineering and Informatics 6, no. 2 (June 1, 2017): 122–32. http://dx.doi.org/10.11591/eei.v6i2.597.
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The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.
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Wang, Yue, Aiying Guo, Shiwei Qin, Jianghua Zhang, Fei Wang, and Feng Ran. "A Single-Ended 9T SRAM Cell With Improved Noise Margin for Low-Power Applications Used in LEDoS." Journal of Physics: Conference Series 2524, no. 1 (June 1, 2023): 012024. http://dx.doi.org/10.1088/1742-6596/2524/1/012024.
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Abstract As a silicon-based microdisplay for Augment reality (AR), the high power dissipation of digital CMOS driver is a significant barrier to approaching the higher performance of microdisplay. In this paper, a new low-power SRAM cell with a single bitline is proposed to reduce the power dissipation of digital CMOS drivers. Compared with conventional differential 6T SRAM cell, the proposed 9T uses the single-ended read/write and read/write separation technology by reducing bitline and adding word lines, and write/read static noise margin (WSNM/RSNM) has been improved while the power dissipation is reduced effectively by stacking effect. When VDD is 0.8 V, the proposed cell achieves 1.4× and 2.2× improvement in WSNM and RSNM compared to D6T. Besides, the proposed cell consumes 1.4× less power during hold mode compared to D6T at VDD=0.8 V.
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Krishna, B. T., and Shaik mohaseena Salma. "A Flux Controlled Memristor using 90nm Technology." Indian Journal of Signal Processing 1, no. 2 (May 10, 2021): 1–6. http://dx.doi.org/10.54105/ijsp.b1004.051221.
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A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.
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Patel, Ambresh, and Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, no. 01 (January 30, 2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.
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The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits because it requires fewer transistors, has lower parasitic capacitance, is faster, and enables pipelinedsystem architecture with glitch-free circuits. It has, however, increased power dissipation. Both types of CMOS circuits withlow power dissipation overcome their own shortcomings.This paper discusses dynamic CMOS logic circuits and their structures. Various logics are also discussed and on the basisof the results obtained, logic which is best suited for designing CMOS logic circuit will be found out. The logic on the basisof structure layout and design which gives best results for high-speed VLSI circuits, is found out.
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Faghih Mirzaee, Reza, Keivan Navi, and Nader Bagherzadeh. "High-Efficient Circuits for Ternary Addition." VLSI Design 2014 (September 1, 2014): 1–15. http://dx.doi.org/10.1155/2014/534587.
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New ternary adders, which are fundamental components of ternary addition, are presented in this paper. They are on the basis of a logic style which mostly generates binary signals. Therefore, static power dissipation reaches its minimum extent. Extensive different analyses are carried out to examine how efficient the new designs are. For instance, the ternary ripple adder constructed by the proposed ternary half and full adders consumes 2.33 μW less power than the one implemented by the previous adder cells. It is almost twice faster as well. Due to their unique superior characteristics for ternary circuitry, carbon nanotube field-effect transistors are used to form the novel circuits, which are entirely suitable for practical applications.
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Vidhyia, M. "Reordering of Test Vectors Using Weighting Factor Based on Average Power for Test Power Minimization." Asian Journal of Electrical Sciences 4, no. 2 (November 5, 2015): 10–15. http://dx.doi.org/10.51983/ajes-2015.4.2.1950.
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Power consumption is one of the biggest challenges in high performance VLSI design and testing. Low power VLSI circuits dissipate more power during testing when compared with that of normal operation. Dynamic power has been the dominant part of power dissipation in CMOS circuits; however, in future technologies the static portion of power dissipation will outreach the dynamic portion. The proposed approach is based on a reordering of test vectors in the test sequence to minimize the switching activity of the circuit using test application. In this paper weighted switching activity is derived based on the average power consumed in the logic gates during all possible event conditions. Since this weighted switching activity is based on the power, which gives more accurate results. The proposed algorithm is implemented and verified using ISCAS85 benchmark circuits. Power is estimated for the circuits using Tanner EDA tool. The results show that power is reduced significantly over the existing methods
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Sahruday, Gaje, Anumula Srikanth, and Karne Harikrishna. "The Power Optimization and an Area Efficient of Static RAM 1-Bit Cell using CMOS Novel Technologies." June 2023 5, no. 2 (June 2023): 104–23. http://dx.doi.org/10.36548/jei.2023.2.001.
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In order to meet all the expectations of consumers, today's technology is all equipped with large capacity memories. Additional factors include power consumption and delay, all of which are crucial in determining how well a gadget performs. Memory is an important factor of many widgets, and as devices get smaller, their size likewise gets less. Every computerized device, as a result, uses little power, and speed is of utmost importance. Since 6T Static Random Access Memory (SRAM) cells have advantages over other cells, the current scenario suggests that they are frequently employed for SRAM-based memory systems. Today's electronics businesses are primarily concerned with minimizing power consumption, with static and dynamic power dissipation being the two key considerations. Meeting customer demands, high bandwidth, low power, and fast-consuming storages are also required. The major objective of this research is to decrease the power dissipation of the SRAM. The main problem faced by the digital industry is the decrease of power and delay. By connecting two Complementary MOSFET inverters back-to-back, an SRAM cell can be set up in an easy and beneficial manner. This setup offers good noise immunity.
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Whig, Pawan, and Syed Naseem Ahmad. "A Novel Pseudo-PMOS Integrated ISFET Device for Water Quality Monitoring." Active and Passive Electronic Components 2013 (2013): 1–6. http://dx.doi.org/10.1155/2013/258970.
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The paper presents a performance analysis of novel CMOS Integrated pseudo-PMOS ISFET (PP-ISFET) having zero static power dissipation. The main focus is on simulation of power and performance analysis along with the comparison with existing devices, which is used for water quality monitoring. The conventional devices, generally used, consume high power and are not stable for long term monitoring. The conventional device has the drawbacks of low value of slew rate, high power consumption, and nonlinear characteristics, but in this novel design, due to zero static power, less load capacitance on input signals, faster switching, fewer transistors, and higher circuit density, the device exhibits a better slew rate and piecewise linear characteristics and is seen consuming low power of the order of 30 mW. The proposed circuit reduces total power consumption per cycle, increases the speed of operation, is fairly linear, and is simple to implement.
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Mahmoud, Rana, Narayanan Madathumpadical, and Hasan Al-Nashash. "TCAD Simulation and Analysis of Selective Buried Oxide MOSFET Dynamic Power." Journal of Low Power Electronics and Applications 9, no. 4 (September 22, 2019): 29. http://dx.doi.org/10.3390/jlpea9040029.
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Low power consumption has become one of the major requirements for most microelectronic devices and systems. Increasing power dissipation may lead to decreasing system efficiency and lifetime. The BULK metal oxide semiconductor field-effect transistor (MOSFET) has relatively high power dissipation and low frequency response due to its internal capacitances. Although the silicon-on-insulator (SOI) MOSFET was introduced to resolve these limitations, other challenges were introduced including the kink effect in the current-voltage characteristics. The selective buried oxide (SELBOX) MOSFET was then suggested to resolve the problem of the kink effect. The authors have previously investigated and reported the characteristics of the SELBOX structure in terms of kink effect, frequency, thermal and static power characteristics. In this paper, we continue our investigation by presenting the dynamic power characteristics of the SELBOX structure and compare that with the BULK and SOI structures. The simulated fabrication of the three devices was conducted using Silvaco TCAD tools in 90 nm complementary metal oxide semiconductor (CMOS) technology. Simulation results show that the average dynamic power dissipation of the CMOS BULK, SOI and SELBOX are compatible at high frequencies with approximately 54.5 µW. At low frequencies, the SOI and SELBOX showed comparable dynamic power dissipation but with lower values than the BULK structure. The difference in power dissipation between the SELBOX and BULK is in the order of nano watts. This power difference becomes significant at the chip level. For instance, at 1 MHz, SOI and SELBOX exhibit an average dynamic power consumption of 0.0026 µW less than that of the BULK structure. This value cannot be ignored when a chip operates using thousands or millions of SOI or SELBOX MOSFETs.
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Moghaddam, Majid, Mohammad Hossein Moaiyeri, Mohammad Eshghi, and Ali Jalali. "A Low-Power Multiplier Using an Efficient Single-Supply Voltage Level Converter." Journal of Circuits, Systems and Computers 24, no. 08 (August 12, 2015): 1550124. http://dx.doi.org/10.1142/s0218126615501248.
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This paper presents a new high-performance and low-power single-supply voltage level converter (SSLC) and a new carry save array multiplier based on clustered-voltage scaling (CVS) technique for ultra-low-power applications. The multiplier operates with low and high supply voltage (V DDL , V DDH ) and at its end stage, the proposed low-power SSLC is utilized to prevent static power dissipation at the next stage working with V DDH and to enhance the output driving capability. In the proposed SSLC, dynamically-controlled source-body voltage, reduced drain induced barrier lowering (DIBL) effect and diode-connected transistor with body-biasing have been utilized properly in order to reduce the power consumption significantly without considerable speed degradation. The results of the simulations conducted using Cadence with standard 90-nm CMOS technology demonstrate the superiority of the proposed multiplier utilizing the proposed LC in terms of static and total power consumptions as well as power-delay product (PDP) as compared to the multipliers utilizing the previous level converters (LCs) and the single supply multiplier. It is worth mentioning that the static power, total power and PDP of the proposed low-power multiplier are on average 75%, 73% and 16%, respectively lower than the single-supply multiplier.
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., Priyanka, and Dr Kiran V. "Leakage Power Reduction in CMOS Logic Circuit Using Various Techniques." International Journal of Research and Review 9, no. 11 (November 3, 2022): 79–85. http://dx.doi.org/10.52403/ijrr.20221113.
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Low power nowadays High-power consumption has turned into a crucial design criterion for VLSI an emerging field. When it comes to energy efficiency, high power dissipation is not thought to be beneficial to battery life in the case of battery-powered applications. It reduces the efficiency, dependability, and cooling expenses of battery life. The high-frequency dynamic variation of inputs is heavily influenced by switching and short-circuit leakage power. There are several common methods for reducing the power consumption of circuits. The average power consumption consists of static and dynamic power consumption. The power consumption comparison of LECT0R, LCNT, Stack 0N0FIC, and SAP0N of various low-power techniques. These circuits are simulated in the cadence tool. Keywords: LECT0R, LCNT, Stack 0N0FIC, and SAP0N Techniques, cadence tool (90nm).
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LIU, YUYU, JINGUO QUAN, HUAZHONG YANG, and HUI WANG. "MOS CURRENT MODE LOGIC CIRCUITS: DESIGN CONSIDERATION IN HIGH-SPEED LOW-POWER APPLICATIONS AND ITS FUTURE TREND, A TUTORIAL." International Journal of High Speed Electronics and Systems 15, no. 03 (September 2005): 599–614. http://dx.doi.org/10.1142/s0129156405003351.
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In this paper, a logic style that is becoming increasingly popular is presented, which is called MOS Current Mode Logic (MCML). MCML is a novel and useful logic style for high-speed, low-power and mixed-signal applications. Its high-speed switching, low supply voltage and reduced output voltage swing contribute to its high performance, low power dissipation, and low noise features. MCML circuits are compared to several other logic styles, such as conventional static CMOS, dynamic logic, and traditional emitter coupled logic (ECL) in terms of power, delay and common mode noise immunity. MCML circuits seem to be very promising in high-speed, low-power and mixed-signal digital circuit applications, such as portable electronic devices, gigahertz microprocessors, and optical transceivers.
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Reddy, M. Madhusudhan, M. Sailaja, and K. Babulu. "Energy optimization of 6T SRAM cell using low-voltage and high-performance inverter structures." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 3 (June 1, 2019): 1606. http://dx.doi.org/10.11591/ijece.v9i3.pp1606-1619.
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The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.
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Gangineni, Manaswini, Jaime Ramirez-Angulo, Héctor Vázquez-Leal, Jesús Huerta-Chua, Antonio J. Lopez-Martin, and Ramon Gonzalez Carvajal. "±0.3V Bulk-Driven Fully Differential Buffer with High Figures of Merit." Journal of Low Power Electronics and Applications 12, no. 3 (June 22, 2022): 35. http://dx.doi.org/10.3390/jlpea12030035.
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A high performance bulk-driven rail-to-rail fully differential buffer operating from ±0.3V supplies in 180 nm CMOS technology is reported. It has a differential–difference input stage and common mode feedback circuits implemented with no-tail, high CMRR bulk-driven pseudo-differential cells. It operates in subthreshold, has infinite input impedance, low output impedance (1.4 kΩ), 86.77 dB DC open-loop gain, 172.91 kHz bandwidth and 0.684 μW static power dissipation with a 50-pF load capacitance. The buffer has power efficient class AB operation, a small signal figure of merit FOMSS = 12.69 MHzpFμW−1, a large signal figure of merit FOMLS = 34.89 (V/μs) pFμW−1, CMRR = 102 dB, PSRR+ = 109 dB, PSRR− = 100 dB, 1.1 μV/√Hz input noise spectral density, 0.3 mVrms input noise and 3.5 mV input DC offset voltage.
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Whig, Pawan, and Syed Naseem Ahmad. "A Novel Pseudo NMOS Integrated CC -ISFET Device for Water Quality Monitoring." Journal of Integrated Circuits and Systems 8, no. 2 (December 28, 2013): 98–103. http://dx.doi.org/10.29292/jics.v8i2.379.
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The paper presents a performance analysis of Novel CMOS Integrated Pseudo NMOS CC –ISFET (PNCC-ISFET) having zero static power dissipation. The main focus is on simulation of power and performance analysis along with the comparison with existing devices, which are used for water quality monitoring. This approach can improve calibration of device to a fairly wide range without the use of a high speed digital processor. The conventional devices generally used, consume high power and are not stable for long term monitoring. The conventional devices have a drawback of low value of slew rate, high power consumption, and non linear characteristics. In the proposed design(PNCC-ISFET) due to zero static power, low value of load capacitance on input signals, faster switching, use of fewer transistors and higher circuit density the device exhibits a better slew rate, piece-wise linear characteristic, and is seen consuming low power of the order of 30mW. The functionality of the circuit is tested using Tanner simulator version 15 for a 70nm CMOS process model. The proposed circuit reduces total power consumption per cycle, increases speed of operation, is fairly linear and simple to implement. This device has a simple architecture, and hence is very suitable for water quality monitoring applications.
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Maryan, Mohammad Moradinezhad, Seyed Javad Azhari, Mehdi Ayat, and Reza Rezaei Siahrood. "Compact Design of High-Speed Low-Error Four-Quadrant Current Multiplier with Reduced Power Dissipation." Journal of Circuits, Systems and Computers 29, no. 03 (May 24, 2019): 2050038. http://dx.doi.org/10.1142/s0218126620500383.
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In this paper, a compact low-power, high-speed, low-error four-quadrant analog multiplier is proposed using a new simple current squarer circuit. The new squarer circuit consists of an NMOS transistor, which operates in saturation region, plus a resistor. The proposed multiplier has a balanced structure composed of four squarer cells and a simple current mirror. This multiplier also has the important property of not using bias currents which results in greatly reduced power. The performance of the proposed design (for passive and active realization of the resistors) has been simulated using HSPICE software in 0.18[Formula: see text][Formula: see text]m TSMC (level-49) CMOS technology. Simulation results with [Formula: see text]-V DC supply voltages show (for passive realization) that the maximum linearity error is 0.35%, the [Formula: see text][Formula: see text]dB bandwidth (BW) is 903[Formula: see text]MHz, the total harmonic distortion (THD) is 0.3% (at 1[Formula: see text]MHz), and the maximum and static power consumption are [Formula: see text]W and [Formula: see text]W, respectively. Also, post-layout simulation results are extracted, which give the maximum linearity error as 0.4%, the [Formula: see text][Formula: see text]dB BW as 657[Formula: see text]MHz and the THD as 0.35%, as well. Moreover, Monte Carlo analysis are performed to verify the satisfactory robustness and reliability of the proposed work’s performance.
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Ghadiri, Zahra, Ali Aghamohammadi, Abdollah Refaei, and Haidar Sheikhahmadi. "Constraints on warm power-law inflation in light of Planck results." Modern Physics Letters A 35, no. 11 (January 17, 2020): 2050078. http://dx.doi.org/10.1142/s0217732320500789.
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The constraints on a general form of the power-law potential and the dissipation coefficient in the framework of warm single field inflation imposed by Planck data will be investigated. By considering a quasi-static Universe, besides a slow-roll condition, the suitable regions in which a pair of theoretical free parameters are in good agreement with Planck results will be estimated. In this method, instead of a set of free parameters, we can visualize a region of free parameters that can satisfy the precision limits on theoretical results. On the other side, when we consider the preformed quantity for the amplitude of scalar perturbations, the conflict between obtained results for free parameters in different steps will be dramatically decreased. As done in prominent literature, based on the friction of the environment, we can divide the primordial Universe into two different epochs, namely weak and strong dissipative regimes. For the aforementioned eras, the free parameters of the model will be constrained and the best regions will be obtained. To do so, the main inflationary observables such as tensor-to-scalar ratio, power-spectra of density perturbations and gravitational waves, scalar and tensor spectral indices, running spectral index and the number of e-folds in both weak and strong regimes will be obtained. Ultimately, it can be visualized, this model can make concord between theoretical results and data originated from cosmic microwave background and Planck 2013, 2015 and 2018.
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Nagulapalli, Rajasekhar, Khaled Hayatleh, and Steve Barker. "A Positive Feedback-Based Op-Amp Gain Enhancement Technique for High-Precision Applications." Journal of Circuits, Systems and Computers 29, no. 14 (March 20, 2020): 2050220. http://dx.doi.org/10.1142/s0218126620502205.
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A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65[Formula: see text]nm CMOS technology. It results in 81[Formula: see text]dB voltage gain, which is 21[Formula: see text]dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8[Formula: see text]V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1[Formula: see text]V supply. The circuit draws a total static current of 295[Formula: see text][Formula: see text]A and occupies 5000[Formula: see text][Formula: see text]m2 of silicon area.
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Jiang, Zhan Peng, Rui Xu, Hai Huang, and Chang Chun Dong. "Design of a Rail-to-Rail Operational Amplifier with Low Supply Voltage and Low Power Dissipation." Applied Mechanics and Materials 380-384 (August 2013): 3275–78. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3275.
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An rail-to-rail operational amplifier is presented in this paper, which is designed by with two op amp, the first level of the structure is the complementary differential structure which will providing input for the operational amplifier, the second level is designed with the structure of folding cascode to get a high gain. The operational amplifier is designed with the TSMC 0.35u m3.3VCMOS mixed analog-digital technology library. The simulated results show that the operational amplifier has a DC gain of 110dB,a GBW of 9.5MHz,a static power dissipation of 0.95mW,a phase margin of 73°,a voltage slew rate of 8.2V/μS,an input and output range of 0-3.3V,when operating at 3.3V power supply and a 20pF output load.
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Roy, Suvajit, Tapas Kumar Paul, and Radha Raman Pal. "Simple Current-Mode Squaring and Square-Rooting Circuits: Applications of MO-CCCCTA." Trends in Sciences 18, no. 23 (November 15, 2021): 721. http://dx.doi.org/10.48048/tis.2021.721.
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This work provides new designs of simple current-mode squaring and square-rooting circuits using multiple-output current controlled current conveyor transconductance amplifier (MO-CCCCTA) as an active building block. Since the proposed circuits need no other external components, they are capable of high-frequency operation and well fitted for IC fabrication. Furthermore, they are insensitive to ambient temperature and their gains can be controlled easily by adjusting the bias currents of MO-CCCCTA. Additionally, the effects of MO-CCCCTA non-idealities on the designed circuits have also been investigated and discussed. Simulation results generated through PSPICE software using TSMC 0.18 µm CMOS process parameters have been presented to justify the theoretical analysis. The static power consumption, bandwidth, and maximum linearity error in dc transfer characteristic measurement for the square-rooting circuit are found to be 0.17 mW, 445.63 MHz and 1.12 %, while for the squaring circuit they are 0.326 mW, 61.15 MHz and 2.38 %, respectively. The application of the reported circuits as a 2-input vector summation circuit has also been included to strengthen the design ideas.
HIGHLIGHTS
Simple structures of fully integrable current-mode squarers and square-rooters with low component count and lower power dissipation
The circuits are insensitive to temperature drift and their gains can be controlled easily by adjusting the bias currents of MO-CCCCTA
Bandwidth, static power dissipation, linearity error of square-rooter are 445.63 MHz, 0.17 mW & ≤ 1.12 %; and for the squarer 61.15 MHz, 0.326 mW & 2.38 %, respectively
GRAPHICAL ABSTRACT
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Myderrizi, Indrit, and Ali Zeki. "A Tunable Swing-Reduced Driver in 0.13-μm MTCMOS Technology." Journal of Circuits, Systems and Computers 26, no. 11 (April 17, 2017): 1750182. http://dx.doi.org/10.1142/s0218126617501821.
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With the increase in demand for high-speed and low-power integrated circuits as technology scales down, low-swing signaling circuit techniques are critical for providing high-speed low-power communications. However, existing low-swing circuits comprise complex designs, power issues (static and dynamic), output voltage swing restrictions or nonadjustable voltage swing levels, leading to lower operation speeds and even larger area footprints. In this paper, a tunable swing-reduced driver (SRD) circuit featuring the mentioned design challenges is presented. The SRD enables low-swing signals with fully controllable output voltage swing that is useful to reduce the power dissipation and delay in the signaling paths. Implemented in UMC 0.13-[Formula: see text][Formula: see text]m multi-threshold CMOS process, the SRD achieves 26 ps propagation delay at 200[Formula: see text]mV output swing for a pulse signal input at 1[Formula: see text]GHz. Post-layout simulations of the proposed SRD and a DAC application circuit, incorporating the SRD, operating at 1[Formula: see text]GHz, validate the design.
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A. Jyotsna, K., P. Satish Kumar, B. K. Madhavi, and I. Swaroopa. "Implementation of 16 Bit SAR ADC in CMOS and sub threshold cml techniques." International Journal of Engineering & Technology 7, no. 2.12 (April 3, 2018): 257. http://dx.doi.org/10.14419/ijet.v7i2.12.11298.
Full textAbstract:
The trends of the VLSI technology is advancing, due to this majority of the industry players are showing interest in development of the devices with ultra low power applications. Analog-to-Digital converters are getting extensively used in Medical implant machines and in lots of Sensor machines, because it is serving an imperative role in interfacing between analog signal and digital signal. This paper presents a modernistic technique called as Sub threshold Current Mode Logic (CML) for ultra low power digital components. Here 16 bit SAR ADC is designed and compared with the techniques like CMOS and STCML for power consumption and delay. Schematics are materialized with Cadence Virtuoso tool using 45nm process. The transistors in these CML and CMOS operate at threshold voltages and Sub-threshold voltages where the executable design is done using 1V to 0.5V power supply (VDD). The comparator dissipates aggrandized power, so most of the intension is converged on forming this chunk. The CML logic procedure operates primarily with the current domain, due to this the performance can be constitutionally high. This approach decreases static power dissipation.
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Geng, Yeliang, Jianping Hu, and Kaiyu Zou. "A Power-Gating Scheme for MCML Circuits with Separable-Sizing Sleep Transistors." Open Electrical & Electronic Engineering Journal 8, no. 1 (December 31, 2014): 306–15. http://dx.doi.org/10.2174/1874129001408010306.
Full textAbstract:
Power-efficient designs are essential for micro-power sensor systems. This paper presents a power-gating scheme for MCML (MOS Current Mode Logic) circuits with separable-sizing sleep transistors. In the proposed scheme, two high-threshold power-gating transistors are inserted between load transistors and outputs of the MCML circuits. The widths and lengths of sleep transistors in power-gated blocks are separately adjusted, which are independent of the bias circuit. Basic cells and a 1-bit full adder are used to verify the correctness of the proposed scheme. The power consuming comparisons between conventional MCML and proposed power-gating MCML circuits are carried out. The 1-bit MCML full adder based on the proposed scheme nearly saves 36% of energy dissipations with respect to no-power-gating MCML one, for a power-gating activity of 0.6. Moreover, the proposed power-gating MCML circuit also has a great advantage in power dissipations in high frequency regions compared with the power-gating static CMOS ones. The power consumption of the MCML 1-bit full adder based on the proposed scheme is 63.2%, 44.8%, and 36.97% compared with the powergating static CMOS one when the operating frequency is 1GHz, 1.5GHz, and 2GHz, respectively.
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LAO, Z., M. LANG, V. HURM, Z. WANG, A. THIEDE, M. SCHLECHTWEG, W. BRONNER, et al. "20–40 Gbit/s GaAs-HEMT CHIP SET FOR OPTICAL DATA RECEIVER." International Journal of High Speed Electronics and Systems 09, no. 02 (June 1998): 437–72. http://dx.doi.org/10.1142/s0129156498000208.
Full textAbstract:
Using our 0.2 and 0.3 μm AlGaAs/GaAs/AlGaAs quantum well HEMT technology, we have developed a chip set for 20–40 Gbit/s fiber-optical digital transmission systems. In this paper we describe nine analog and digital receiver ICs: a 22 GHz high-gain transimpedance amplifier, a 20 Gbit/s OEIC front-end optical receiver, a 25 Gbit/s automatic-gain-control amplifier, a limiting amplifier with a differential gain of 26 dB and a bandwidth of 27.7 GHz, a 20–40 Gbit/s clock recovery, a 20 Gbit/s low-power Master-Slave-D-Flipflop with 24 mW power dissipation, a parallel data decision and a 1:4 demultiplexer, both for bit rates of 40 Gbit/s, and a 30 GHz static frequency divider, respectively. All chips were characterized on wafers with 50 Ω coplanar test probes.
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Upadhyay, Rahul Mani. "High Performance Energy-Efficient Leakage-Tolerant Dual Keeper Pseudo Domino Logic." International Journal on Applied Physics and Engineering 2 (May 31, 2023): 35–43. http://dx.doi.org/10.37394/232030.2023.2.6.
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In this paper, an improved high performance energy-efficient leakage-tolerant dual keeper pseudo domino logic circuit is proposed. Circuit design methodologies such as pseudo domino, stacking effect and inverted clock-controlled dual keeper are used in the proposed work for significant reduction of the circuit’s propagation delay and leakage current. Using pseudo-domino logic voltage swing at the output is reduced, stacking effect reduces the leakage current and charge sharing issues in the circuit are reduced by an inverted clock-controlled dual keeper circuit. Leakage current in the proposed circuit is decreased by 21.9%, 20.8%, 71.6%, 52.4% and 57.5% to the conventional logic, DOIND logic, DVT DOIND logic, DFD logic and C3D domino logic, respectively at a 27°C temperature and 1GHz clock frequency. Similarly, delay in the proposed circuit is reduced by 83.3%, 80.1%, 89.8%, 81.3% and 81.5% in comparison to conventional logic, DOIND logic, DVT DOIND logic, DFD logic and C3D domino logic circuit, respectively. Performance metrics like power dissipation, delay, PDP, leakage current, static power, and EDP of the proposed circuit are analysed and compared with the existing domino logics. Monte-Carlo simulation is performed using 1000 samples to analyse the performance of the proposed circuit. The proposed logic circuit is also tested against temperature and process variations. The median values of the proposed buffer circuit’s power and delay are 5.6µW and 1.28ps, respectively and the standard deviation of average power and propagation delay are 633.62nW and 84.37fs, respectively at 27°C and 1GHz clock frequency.
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Li, Yulan. "Preparation and Optical Properties of Compound Nanopowder Art Ceramics." International Journal of Analytical Chemistry 2022 (May 30, 2022): 1–6. http://dx.doi.org/10.1155/2022/5415922.
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The fluorescent glass of white LEDs has high physical and chemical stabilities, good heat dissipation performance, and can maintain an excellent performance of fluorescent powder itself. In order to realize luminescent materials such as white LED lighting, laser lighting, and long-term lighting, this study proposes the preparation of a compound nanopowder art ceramic and its optical properties. In order to play the role of nanoparticles in optoelectronic or photonic devices, it is necessary to explore the preparation process and performance research of dielectric ceramics. This study uses high-purity aluminate (MgAl2O4) powder for transparent ceramics, doped with yellow nanophosphor as raw materials, through a sintering process in oxygen atmosphere, sintering combined with heat treatment, and isostatic pressing to prepare transparent ceramics. The ceramic sample is placed in a high-temperature and high-pressure environment for heat and other static pressure, and fluorescent samples are obtained. The results show that under 350 mA driving current, high-power white LEDs in the fluorescent ceramic package have almost no attenuation after 700 h, and the average attenuation of the LED package of the phosphor package is about 10%. The use of fluorescent ceramics can be packaged not only to improve the LED device’s light efficiency but also to increase the life of the white LED device.
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Joo, Ji-Eun, Myung-Jae Lee, and Sung Min Park. "A CMOS Optoelectronic Receiver IC with an On-Chip Avalanche Photodiode for Home-Monitoring LiDAR Sensors." Sensors 21, no. 13 (June 25, 2021): 4364. http://dx.doi.org/10.3390/s21134364.
Full textAbstract:
This paper presents an optoelectronic receiver (Rx) IC with an on-chip avalanche photodiode (APD) realized in a 0.18-mm CMOS process for the applications of home-monitoring light detection and ranging (LiDAR) sensors, where the on-chip CMOS P+/N-well APD was implemented to avoid the unwanted signal distortion from bondwires and electro-static discharge (ESD) protection diodes. Various circuit techniques are exploited in this work, such as the feedforward transimpedance amplifier for high gain, and a limiting amplifier with negative impedance compensation for wide bandwidth. Measured results demonstrate 93.4-dBW transimpedance gain, 790-MHz bandwidth, 12-pA/√Hz noise current spectral density, 6.74-mApp minimum detectable signal that corresponds to the maximum detection range of 10 m, and 56.5-mW power dissipation from a 1.8-V supply. This optoelectronic Rx IC provides a potential for a low-cost low-power solution in the applications of home-monitoring LiDAR sensors.
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Priya, Nadendla Bindu, and Muralidharan Jayabhalan. "A 5 Bit 600MS/S Asynchronous Digital Slope ADC with Modified Strong Arm Comparator." International Journal of Engineering and Advanced Technology 9, no. 1s5 (December 30, 2019): 41–43. http://dx.doi.org/10.35940/ijeat.a1012.1291s519.
Full textAbstract:
Strong arm comparator has some characteristics like it devours zero static power and yields rail to rail swing. It acquires a positive feedback allowed by two cross coupled pairs of comparators and results a low offset voltage in input differential stage. We modified a strong arm Comparator for high speed without relying on complex calibration Schemes. a 5-bit 600MS/s asynchronous digital slope analog to digital converter (ADS-ADC) with modified strong arm comparator designed in cadence virtuoso at 180nm CMOS technology. The design of SR-Latch using Pseudo NMOS NOR Gate optimizes the speed. Thus delay reduced in select signal generation block. Power dissipation is minimized with lesser transistor count in Strong arm comparator and SR-Latch with maximum sampling speed. The speed of the converter can be improved by resolution. The proposed circuit is 5-bit ADC containing a delay cell, Sample and hold, continuous time comparator, strong arm comparator, Pseudo NMOS SR-Latch and Multiplexer. This 5-bit ADC operates voltage at 1.8 volts and consumes an average power.
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Chu, Tengfei, Guoliang Bai, and Jiarui Li. "Experimental study on seismic performance of steel-concrete connection section of receiver tower of CSP station." Advances in Engineering Technology Research 1, no. 2 (September 22, 2022): 31. http://dx.doi.org/10.56028/aetr.1.2.31.
Full textAbstract:
Taking the actual structure of the solarreceiver tower of a 243m high optical thermal power station as the prototype, and fully considering the influence range of structural quality and stiffness mutation, the 180-221m steel-concrete connection section structure is selected as the research object. The equivalent scale model is designed and manufactured according to the scale ratio of 1:8, and the quasi-static test under low cyclic reciprocating load is carried out. The failure characteristics, hysteretic performance, skeleton curve, stiffness and strength degradation, energy dissipation capacity, ductility and bearing capacity of the connection section structure are studied. The results show that the ultimate failure of the connection section structure is the overall bending yield of the upper steel frame and the local failure of the steel-concrete connection joint; The stiffness and strength of the connection section degenerate seriously when the structure is damaged. The equivalent viscous damping coefficient is 0.261 and the displacement ductility coefficient is 9.2, indicating that the specimen has good energy dissipation capacity and ductility under earthquake; The special joint structure can ensure the reliable connection between the upper steel frame and the lower concrete and meet the safety requirements.
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Chu, Tengfei, Guoliang Bai, and Jiarui Li. "Experimental study on seismic performance of steel-concrete connection section of receiver tower of CSP station." Advances in Engineering Technology Research 2, no. 1 (September 22, 2022): 31. http://dx.doi.org/10.56028/aetr.2.1.31.
Full textAbstract:
Taking the actual structure of the solarreceiver tower of a 243m high optical thermal power station as the prototype, and fully considering the influence range of structural quality and stiffness mutation, the 180-221m steel-concrete connection section structure is selected as the research object. The equivalent scale model is designed and manufactured according to the scale ratio of 1:8, and the quasi-static test under low cyclic reciprocating load is carried out. The failure characteristics, hysteretic performance, skeleton curve, stiffness and strength degradation, energy dissipation capacity, ductility and bearing capacity of the connection section structure are studied. The results show that the ultimate failure of the connection section structure is the overall bending yield of the upper steel frame and the local failure of the steel-concrete connection joint; The stiffness and strength of the connection section degenerate seriously when the structure is damaged. The equivalent viscous damping coefficient is 0.261 and the displacement ductility coefficient is 9.2, indicating that the specimen has good energy dissipation capacity and ductility under earthquake; The special joint structure can ensure the reliable connection between the upper steel frame and the lower concrete and meet the safety requirements.
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Saggese, Gerardo, and Antonio Giuseppe Maria Strollo. "Low-Power Energy-Based Spike Detector ASIC for Implantable Multichannel BMIs." Electronics 11, no. 18 (September 16, 2022): 2943. http://dx.doi.org/10.3390/electronics11182943.
Full textAbstract:
Advances in microtechnology have enabled an exponential increase in the number of neurons that can be simultaneously recorded. To meet high-channel count and implantability demands, emerging applications require new methods for local real-time processing to reduce the data to transmit. Nonlinear energy operators are widely used to distinguish neural spikes from background noise featuring a good tradeoff between hardware resources and accuracy. However, they require an additional smoothing filter, which affects both area occupation and power dissipation. In this paper, we investigate a spike detector, based on a series of two nonlinear energy operators, and a simple and adaptive threshold, based on a three-point median operator. We show that our proposal provides good accuracy compared to other energy-based detectors on a synthetic dataset at different noise levels. Based on the proposed technique, a 1024-channel neural signal processor was designed in a 28 nm TSMC CMOS process by using latch-based static random-access memory (SRAM), demonstrating a total power consumption of 1.4 μW/ch and a silicon area occupation of 230 μm2/ch. These features, together with a comparison with the state of the art, demonstrate that our proposal constitutes an alternative for the development of next-generation multichannel neural interfaces.
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ChunXiang, Huang, Henadiy Pavlov, Mykhailo Pokrovskyi, Andriy Obrubov, and Iryna Vinnychenko. "DEVELOPMENT OF A FAST WIRELESS BATTERY CHARGING TECHNOLOGY FOR ACCUMULATORS USED IN CLEAN ENERGY TRANSPORT VEHICLES. STATIC CHARACTERISTICS OF A SERIES-TO-SERIES RESONANT CONVERTER FOR CONTACTLESS INDUCTIVE ENERGY TRANSMISSION." Science Journal Innovation Technologies Transfer, no. 2019-4 (September 1, 2019): 56–61. http://dx.doi.org/10.36381/iamsti.4.2019.56-61.
Full textAbstract:
The research object is the electromagnetic processes in the semiconductor power converters based on the schemes with circuit commutation and containing resonant circuits of reactive elements and transformers with a small coupling coefficient. The research aim is to develop a technology for a fast wireless battery charging for the use in clean energy vehicles, which would be based on a resonant converter with a pulse-count adjustment with a phase shift control. The latter provides a high energy performance in a wide range of regulation and a low sensitivity to changes in the magnetic system parameters. This is a final report. The report presents the results of the work performed in accordance with the Terms of Reference for the second stage of the scientific and research work. The following theoretical problems have been solved: development of a mathematical model of a series resonant converter with a pulse-count adjustment for contactless inductive energy transmission, which provided a high accuracy for the studies of the electromagnetic processes in the power section of multi-circuit resonant converters for contactless energy transmission, as well as an opportunity to assess the energy parameters of multi-circuit converters at pulse-count adjustment; compilation of mathematical dependencies of the average input and output current values on the number of half-cycles of resonant oscillations during energy transmission to the circuit and energy dissipation, the supply voltage and the resonant circuit’s parameters, which allowed assessing the converter’s energy parameters over a wide control range; compilation of the dependencies of the converter’s output power and coefficient of efficiency on the number of halfcycles of resonant oscillations during energy transmission to the circuit and energy dissipation, on supply voltage and on the resonant circuit’s parameters, which made it possible to evaluate the efficiency of the pulse-count adjustment of resonant converters for contactless energy transmission; realization of a dynamic model of a resonant converter for contactless energy transmission in the form of transfer functions for small disturbances caused by fluctuations in supply voltage, which made it possible to estimate the effect of its instability on the quality of output current stabilization.
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Prasad, Dilip, and Jinzhang Feng. "Propagation and Decay of Shock Waves in Turbofan Engine Inlets." Journal of Turbomachinery 127, no. 1 (January 1, 2005): 118–27. http://dx.doi.org/10.1115/1.1811102.
Full textAbstract:
Numerical experiments are carried out to investigate the tone noise radiated from a turbofan engine inlet under conditions at which the relative flow past the rotor tip is supersonic. Under these conditions, the inlet tone noise is generated by the upstream-propagating rotor-locked shock wave field. The spatial evolution of this shock system is studied numerically for flows through two basic hard-walled configurations: a slender nacelle with large throat area and a thick nacelle with reduced throat area. With the flight Mach number set to 0.25, the spatial evolution of the acoustic power through the two inlets reveals that the reduced throat area inlet provides superior attenuation. This is attributed to the greater mean flow acceleration through its throat and is qualitatively in accord with one-dimensional theory, which shows that shock dissipation is enhanced at high Mach numbers. The insertion of a uniform extension upstream of the fan is shown to yield greater attenuation for the inlet with large throat area, while the acoustic performance of the reduced throat area inlet is degraded. This occurs because the interaction of the nacelle and spinner potential fields is weakened, resulting in a lower throat Mach number. The effect of forward flight on the acoustic power radiated from the two inlets is also investigated by examining a simulated static condition. It is shown that the slender nacelle radiates significantly less power at the static condition than in flight, whereas the power levels at the two conditions are comparable for the thick nacelle. The reason for this behavior is revealed to be a drastic overspeed near the leading edge of the slender nacelle, which occurs to a lesser degree in the case of the thick inlet. This has implications for ground acoustic testing of aircraft engines, which are discussed.
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Yang, D., J. Hu, and X. Xiang. "Modeling and Sizing of Power-Gating Single-Rail MOS Current Mode Logic." Open Electrical & Electronic Engineering Journal 8, no. 1 (December 31, 2014): 286–97. http://dx.doi.org/10.2174/1874129001408010286.
Full textAbstract:
Almost all power-gating circuits used in MOS current-mode circuits were realized with dual-rail schemes. In this paper, a power-gating scheme for single-rail MOS current mode logic (SRMCML) is presented. The modeling of the sleep transistor in power-gating circuits is constructed and analyzed. The optimization methods for sizing sleep transistors of power-gating circuits are addressed in terms of energy dissipations. The design methods of the power-gating SRMCML circuits are presented. The effectiveness of the proposed power-gating structure is verified by using HSPICE simulations with a SMIC 130nm technology. From the outcomes of simulations, the energy loss of the power-gating SRMCML circuits is smaller than corresponding static CMOS alternatives in high frequencies.
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BEKIARIS, DIMITRIS, SOTIRIOS XYDIS, and GEORGE ECONOMAKOS. "SYSTEMATIC DESIGN AND EVALUATION OF RECONFIGURABLE ARITHMETIC COMPONENTS IN THE DEEP SUBMICRON DOMAIN." Journal of Circuits, Systems and Computers 23, no. 10 (October 14, 2014): 1450140. http://dx.doi.org/10.1142/s0218126614501400.
Full textAbstract:
In the era of deep submicron integration, digital design complexity is increasing with rates that are hard to follow. On one hand, market demand for newer, faster and reliable applications never stops. On the other hand, fabrication technology can not cover this demand with frequency increase and dimension shrinking only, as it has been done in the past. Reconfigurable computing is a new design paradigm that takes advantage of idle components or shared functionality between different algorithms, to maximize utilization and improve performance, based on efficient circuit switching interconnections. However, dense and fast switching interconnections bring power dissipation problems, which are more clear in the deep submicron domain. This paper, presents a systematic design methodology, handling performance, area and both dynamic and static power reduction optimizations in the ASIC domain, for a class of reconfigurable arithmetic components, which can be used as IPs in register-transfer level (RTL) and above RTL synthesis methodologies (electronic system level — ESL, high-level synthesis — HLS, IP-based). Both operand bitwidth and technology scaling are explored, showing that the overall proposed architecture offers clear advantages as device dimensions shrink.
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R.Nirmal, P.Nithila, K.Jayasudha, P.Velumani, M.Barkavi, and Dr D. F. Jingle Jabha. "DESIGN OF A 6T SRAM CELL WITH MINIMAL POWER USING CADENCE VIRTUOSO." Dogo Rangsang Research Journal 13, no. 03 (2023): 97–105. http://dx.doi.org/10.36893/drsr.2023.v13i03n03.097-105.
Full textAbstract:
It has proven challenging for VLSI designers to lower leakage power at the nanoscale level. This is because high- end gadgets, battery-operated portable pads, and other communication tools are in high demand. Memories are made up of static RAM and dynamic RAM. SRAM has had a significant impact on the worldwide VLSI market sinceit is preferred over DRAM because to its rapid read and write access times. Using a 6T static random access memory cell, this study's novel approach to lowering leakage current at various technologies has been put forth. To reduce the 6T SRAM cell leaking power, three source biasing techniques are used. At 45 nanometer and 90 nm technology nodes, the three techniques are NMOS diode clamping, PMOS diode clamping, and NMOS-PMOS diode clamping. The implementation of a 6T SRAM cell using the Multiple Threshold CMOS (MTCMOS) technique at 45nm technology is also emphasised in this article. Using the cadence virtuoso tool, the simulation is completed and different power dissipations are examined for 45 nm and 90 nm technologies, respectively, at supply voltages of 0.45 V and 0.9 V. Comparing PMOS clamping to the other two suggested techniques, an average power reduction of 82.19% was observed.
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J A, Akshay. "Design and VLSI implementation of SRAM memory array using Application-specific Integrated circuits design flow." International Journal for Research in Applied Science and Engineering Technology 11, no. 5 (May 31, 2023): 4047–58. http://dx.doi.org/10.22214/ijraset.2023.52570.
Full textAbstract:
Abstract Static Random-access memory (SRAM) are useful structure blocks in operations like data storage, embedded operations, cache recollections, microprocessors. The circuits should retain larger impunity to noise voltages. So, the Stationary Noise Margin (SNM) of the circuits should be veritably high. Large SRAM arrays that are extensively used as cache memory in microprocessors and operation-specific integrated circuits can absorb a big portion of the chip area. Highly compact circuits like SRAM arrays are estimated to cover relatively 90% of the System on chip area within the coming years. To optimize the performance of similar chips, large arrays of fast SRAM help to speed up the system performance. As a result, numerous minimal-size SRAM cells are tightly packed making SRAM arrays the compact circuitry on a chip. In this work an attempt is made to design a 8 X 8 SRAM memory array along with different components like Write driver circuit, Pre-charge circuit, Row and Column Decoder. Different SRAM architectures such as 6T, 7T and 8T are designed and different parameters such as Static Noise Margin and power dissipated are measured and the best performing memory design has been selected. 8T design has been resulted with least power dissipation. Hence this cell is selected for designing the memory array. A schematic of 8 x 8 array is designed and the layout of single SRAM 8T is created and to complete the ASIC design flow, DRC is done and the pre and post simulation are compared and verified. The integrated SRAM is operated with an input voltage of 0 to 1.8V.
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Sharifi, Mohammad Javad, and Davoud Bahrepour. "A New XOR Structure Based on Resonant-Tunneling High Electron Mobility Transistor." VLSI Design 2009 (August 19, 2009): 1–9. http://dx.doi.org/10.1155/2009/803974.
Full textAbstract:
A new structure for an exclusive-OR (XOR) gate based on the resonant-tunneling high electron mobility transistor (RTHEMT) is introduced which comprises only an RTHEMT and two FETs. Calculations are done by utilizing a new subcircuit model for simulating the RTHEMT in the SPICE simulator. Details of the design, input, and output values and margins, delay of each transition, maximum operating frequency, static and dynamic power dissipations of the new structure are discussed and calculated and the performance is compared with other XOR gates which confirm that the presented structure has a high performance. Furthermore, to the best of authors' knowledge, it has the least component count in comparison to the existing structures.
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WANG, K. L., and P. KHALILI AMIRI. "NONVOLATILE SPINTRONICS: PERSPECTIVES ON INSTANT-ON NONVOLATILE NANOELECTRONIC SYSTEMS." SPIN 02, no. 02 (June 2012): 1250009. http://dx.doi.org/10.1142/s2010324712500099.
Full textAbstract:
Instant-on nonvolatile electronics, which can be powered on/off instantaneously without the loss of information, represents a new and emerging paradigm in electronics. Nonvolatile circuits consisting of volatile CMOS, combined with nonvolatile nanoscale magnetic memory, can make electronics nonvolatile at the gate, circuit and system levels. When high speed magnetic memory is embedded in CMOS logic circuits, it may help resolve the two major challenges faced in continuing CMOS scaling: Power dissipation and variability of devices. We will give a brief overview of the current challenges of CMOS in terms of energy dissipation and variability. Then, we describe emerging nonvolatile memory (NVM) options, particularly those spintronic solutions such as magnetoresistive random access memory (MRAM) based on spin transfer torque (STT) and voltage-controlled magnetoelectric (ME) write mechanisms. We will then discuss the use of STT memory for embedded application, e.g., replacing volatile CMOS Static RAM (SRAM), followed by discussion of integration of CMOS reconfigurable circuits with STT-RAM. We will then present the scaling limits of the STT memory and discuss its critical performance parameters, particularly related to switching energy. To further reduce the switching energy, we present the concept of electric field control of magnetism, and discuss approaches to realize this new mechanism in realizing low switching energy, allowing for implementation of nonvolatility at the logic gate level, and eventually at the transistor level with a magnetoelectric gate (MeGate). For nonvolatile logic (NVL), we present and discuss as an example an approach using interference of spin waves, which will have NVL operations remembering the state of computation. Finally, we will discuss the potential impact and implications of this new paradigm on low energy dissipation instant-on nonvolatile systems.
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Banu, Sufia, and Shweta Gupta. "Design and Leakage Power Optimization of 6T Static Random Access Memory Cell Using Cadence Virtuoso." International Journal of Electrical and Electronics Research 10, no. 2 (June 30, 2022): 341–46. http://dx.doi.org/10.37391/ijeer.100246.
Full textAbstract:
Reduction of Leakage power at nano meter regime has become a challenging factor for VLSI designers. This is owing to the need for low-power, battery-powered portable pads, high-end gadgets and various communication devices. Memories are made up of Static RAM and Dynamic RAM. SRAM has had a tremendous impact on the global VLSI industry and is preferred over DRAM because of its low read and write access time. This research study proposes a new method has been proposed of 6T Static Random Access Memory cell to decrease the leakage current at various technologies. Three source biasing methods are used to minimize the 6T SRAM cell leakage power. The three methods are NMOS diode clamping, PMOS diode clamping and NMOS-PMOS diode clamping at 45 nm and 90 nm technology nodes. This paper also emphasizes on the implementation of 6T SRAM cell using Multiple Threshold CMOS (MTCMOS) technique at 45nm technology. The simulation is achieved and various power dissipations are analyzed at supply voltage of 0.9 V and 0.45 V for 90 nm and 45 nm technology respectively using cadence virtuoso tool. PMOS clamping has shown the reduction in an average power by 82.19% than compared to other two proposed techniques.
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Pandit, Shiv Kumar, and Ashish Shrivastava. "A Review on the Performance Analysis of Engine Bracket." SMART MOVES JOURNAL IJOSCIENCE 5, no. 9 (September 14, 2019): 8–11. http://dx.doi.org/10.24113/ijoscience.v5i9.223.
Full textAbstract:
Engine mounts have an important function of containing firmly the power-train components of a vehicle. Correct geometry and positioning of the mount brackets on the chassis ensure a good ride quality and performance. As an FSAE car intends to be a high performance vehicle, the brackets on the frame that support the engine undergo high static and dynamic stresses as well as huge amount of vibrations. Hence, dissipating the vibrational energy and keeping the stresses under a pre-determined level of safety have been achieved by careful designing and analysis of the mount brackets.
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Pathan, F. R. "Kinetic Energy Harvesting from Human Hand Movement by Mounting micro Electromagnetic Generator." E3S Web of Conferences 115 (2019): 02005. http://dx.doi.org/10.1051/e3sconf/201911502005.
Full textAbstract:
A comprehensive review of design and experimentation is presented in this research paper on sustainable renewable energy scavenging from Human body movement using Micro electromagnetic kinetic energy harvester to powering wearable, portable electronics, implantable medical devices etc. The body location which is chosen as the harvester is human hand between elbow and shoulder. Human body harvest energy in two ways i,e, mechanical energy and thermal energy. Mechanical energy is of two kinds one is static energy and the other one is kinetic energy. Due to motion or displacement or enforcement excitation the kinetic energy is extracted. The electric charges which remains imbalance on the surface or within a material is static energy. Thermal energy is extracted from the dissipation of heat from human body. Human body parts and organs generate energy through two types of activities are voluntary and involuntary. The energy which are produced by voluntary activities are high as people intentionally does work by body motion, walk, run. The generated energy by involuntary organs like heart, breathing, artery are smaller compare to voluntary energy harvesting. One process of energy harvesting is by use of micro electromagnetic generator, flexible and stretchable piezoelectric, triboelectric, electromagnetic induction, PVDF cantilever mounting on human body. The harvester prototype is cylindrical magnet L40xD10 mm size which is mounted on human hand for energy harvesting. While in movement of hand the produced wave forms by magnetic generator are measured and recorded for calculation. Analyzing the received data it has been found that the generated power by micro electromagnetic vibration generator from movement of human hand are 319 RMS μW and 2.48 RMS mV with a frequency of 0.25 Hz and power density of about 2.48μW/cm³.
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Singh, Sanskar, Vandana Singh, and Kajol Kumari. "Design of Engine Mount Bracket for a FSAE Car for Deferent Loading Condition." SMART MOVES JOURNAL IJOSCIENCE 5, no. 9 (October 16, 2019): 28–30. http://dx.doi.org/10.24113/ijoscience.v5i9.238.
Full textAbstract:
Engine mounts have an important function of containing firmly the power-train components of a vehicle. Correct geometry and positioning of the mount brackets on the chassis ensures a good ride quality and performance. As an FSAE car intends to be a high performance vehicle, the brackets on the frame that support the engine undergo high static and dynamic stresses as well as huge amount of vibrations. Hence, dissipating the vibrational energy and keeping the stresses under a pre-determined level of safety should be achieved by careful designing and analysis of the mount brackets. Keeping this in mind the current paper discusses the modeling, Finite Element Analysis, Modal analysis and mass optimization of engine mount brackets for a FSAE car. As the brackets tend to undergo continuous vibrations and varying stresses, the fatigue strength and durability calculations also have been done to ensure engine safety. Keywords: FEA; Modal Analysis; Static Analysis; Optimization; Mounting Bracket
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Arena, Maurizio, Christof Nagel, Rosario Pecora, Oliver Schorsch, Antonio Concilio, and Ignazio Dimino. "Static and Dynamic Performance of a Morphing Trailing Edge Concept with High-Damping Elastomeric Skin." Aerospace 6, no. 2 (February 19, 2019): 22. http://dx.doi.org/10.3390/aerospace6020022.
Full textAbstract:
Nature has many striking examples of adaptive structures: the emulation of birds’ flight is the true challenge of a morphing wing. The integration of increasingly innovative technologies, such as reliable kinematic mechanisms, embedded servo-actuation and smart materials systems, enables us to realize new structural systems fully compatible with the more and more stringent airworthiness requirements. In this paper, the authors describe the characterization of an adaptive structure, representative of a wing trailing edge, consisting of a finger-like rib mechanism with a highly deformable skin, which comprises both soft and stiff parts. The morphing skin is able to follow the trailing edge movement under repeated cycles, while being stiff enough to preserve its shape under aerodynamic loads and adequately pliable to minimize the actuation power required for morphing. In order to properly characterize the system, a mock-up was manufactured whose structural properties, in particular the ability to carry out loads, were also guaranteed by the elastic skin. A numerical sensitivity analysis with respect to the mechanical properties of the multi-segment skin was performed to investigate their influence on the modal response of the whole system. Experimental dynamic tests were then carried out and the obtained results were critically analysed to prove the adequacy of the adopted design approaches as well as to quantify the dissipative (high-damping) effects induced by the rubber foam on the dynamic response of the morphing architecture.
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Maiellaro, Giorgio, Giovanni Caruso, Salvatore Scaccianoce, Mauro Giacomini, and Angelo Scuderi. "40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors." Electronics 10, no. 17 (August 31, 2021): 2114. http://dx.doi.org/10.3390/electronics10172114.
Full textAbstract:
This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38 GHz carrier frequency is −94.3 and −118 dBc/Hz at 1 and 10 MHz frequency offset, respectively. The high-frequency dividers, from 40 to 5 GHz, are made using three static CMOS current-mode logic (CML) Master-Slave D-type Flip-Flop stages. The whole divider factor is 2048. A CMOS toggle flip-flop architecture working at 5 GHz was adopted for low frequency dividers. The power dissipation of the VCO core and frequency divider chain are 18 and 27.8 mW from 1.8 and 1 V supply voltages, respectively. Circuit functionality and performance were proved at three junction temperatures (i.e., −40, 25, and 125 °C) using a thermal chamber.