Relevant bibliographies by topics / High static power dissipation

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Academic literature on the topic 'High static power dissipation'

Author: Grafiati
Published: 6 September 2023

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Journal articles on the topic "High static power dissipation"

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J. Raut, Ketan, Abhijit V. Chitre, Minal S. Deshmukh, and Kiran Magar. "Low Power VLSI Design Techniques: A Review." Journal of University of Shanghai for Science and Technology 23, no. 11 (November 9, 2021): 172–83. http://dx.doi.org/10.51201/jusst/21/11881.

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Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.
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Di Meo, Gennaro, Davide De Caro, Nicola Petra, and Antonio G. M. Strollo. "A Novel Low-Power High-Precision Implementation for Sign–Magnitude DLMS Adaptive Filters." Electronics 11, no. 7 (March 24, 2022): 1007. http://dx.doi.org/10.3390/electronics11071007.

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This paper investigates the use of approximate fixed-width and static segment multipliers in the design of Delayed Least Mean Square (DLMS) adaptive filters based on the sign–magnitude representation for the error signal. The fixed-width approximation discards part of the partial product matrix and introduces a compensation function for minimizing the approximation error, whereas the static segmented multipliers reduce the bit-width of the multiplicands at runtime. The use of sign–magnitude representation for the error signal reduces the switching activity in the filter learning section, minimizing power dissipation. Simulation results reveal that, by properly sizing the two approaches, a steady state mean square error practically unchanged with respect to the exact DLMS can be achieved. The hardware syntheses in a 28 nm CMOS technology reveal that the static segmented multipliers perform better in the learning section of the filter and are the most efficient approach to reduce area occupation, while the fixed-width multipliers offer the best performances in the finite impulse response section and provide the lowest power dissipation. The investigated adaptive filters overcome the state-of-the-art, exhibiting an area and power reduction with respect to the standard implementation up to −18.0% and −64.1%, respectively, while preserving the learning capabilities.
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Bhargavi, K. Manju. "Design of Linear Feedback Shift Register for Low Power Applications." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 31, 2021): 3912–18. http://dx.doi.org/10.22214/ijraset.2021.37251.

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This paper presents the design & implementation of the Linear Feedback Shift Register (LFSR) using the Mentor Graphics tool in 90nm technology. LFSR’s have a wide variety of applications. They are used in pseudo-random variety generation, whitening sequences and pseudo-noise sequences. MOS current-mode logic (MCML) and Dynamic current-mode logic (DYCML) are employed to design an LFSR. MCML is widely used in high-speed applications and these MCML circuits are based on current steering logic. The advantages of the MCML method are that they have high noise immunity due to their differential nature of inputs. The disadvantage of MCML approach is static power dissipation. To overcome these issues of MCML logic, Dynamic CML logic is used. Its advantages include low static power dissipation and high performance. This paper shows the comparison results of CMOS, Dynamic CML and MCML designs in terms of delay, power and transistor count.
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Patel, Ambresh, and Ritesh Sadiwala. "Optimizing and Recuperating the Leakages in Low Voltage CMOS Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 14, no. 02 (June 30, 2022): 202–5. http://dx.doi.org/10.18090/samriddhi.v14i02.13.

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With the advancement of technology, small and handy electronic devices are built with low supply voltage and lower power dissipation in designing deep submicron static CMOS circuits. Small devices scaling down with burst-mode type integrated circuits have two major challenges: area and power dissipation. This paper presents a method for decreasing dynamic power, area, and leakage of application-specific integrated circuits without sacrificing performance. The High Threshold Leakage Control Transistor, TG-Based Technique, Supply Voltage Scaling, Sleep Transistor approaches are covered, and a dynamic CMOS architecture with stack transistor. With certain area and delay considerations, these strategies are utilized to diminish both types of power dissipation in the CMOS logic designs.
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Zhang, Liang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, and Paul D. Franzon. "A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 9 (September 2009): 1267–74. http://dx.doi.org/10.1109/tvlsi.2008.2002682.

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This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5-10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5-48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80-1.52 pJ/b. This work demonstrates a 15.0%-67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.
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Bansal, Deepika, Brahmadeo Prasad Singh, and Ajay Kumar. "Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic." Bulletin of Electrical Engineering and Informatics 6, no. 2 (June 1, 2017): 122–32. http://dx.doi.org/10.11591/eei.v6i2.597.

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The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.
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Wang, Yue, Aiying Guo, Shiwei Qin, Jianghua Zhang, Fei Wang, and Feng Ran. "A Single-Ended 9T SRAM Cell With Improved Noise Margin for Low-Power Applications Used in LEDoS." Journal of Physics: Conference Series 2524, no. 1 (June 1, 2023): 012024. http://dx.doi.org/10.1088/1742-6596/2524/1/012024.

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Abstract As a silicon-based microdisplay for Augment reality (AR), the high power dissipation of digital CMOS driver is a significant barrier to approaching the higher performance of microdisplay. In this paper, a new low-power SRAM cell with a single bitline is proposed to reduce the power dissipation of digital CMOS drivers. Compared with conventional differential 6T SRAM cell, the proposed 9T uses the single-ended read/write and read/write separation technology by reducing bitline and adding word lines, and write/read static noise margin (WSNM/RSNM) has been improved while the power dissipation is reduced effectively by stacking effect. When VDD is 0.8 V, the proposed cell achieves 1.4× and 2.2× improvement in WSNM and RSNM compared to D6T. Besides, the proposed cell consumes 1.4× less power during hold mode compared to D6T at VDD=0.8 V.
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Krishna, B. T., and Shaik mohaseena Salma. "A Flux Controlled Memristor using 90nm Technology." Indian Journal of Signal Processing 1, no. 2 (May 10, 2021): 1–6. http://dx.doi.org/10.54105/ijsp.b1004.051221.

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A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.
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Patel, Ambresh, and Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, no. 01 (January 30, 2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.

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The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits because it requires fewer transistors, has lower parasitic capacitance, is faster, and enables pipelinedsystem architecture with glitch-free circuits. It has, however, increased power dissipation. Both types of CMOS circuits withlow power dissipation overcome their own shortcomings.This paper discusses dynamic CMOS logic circuits and their structures. Various logics are also discussed and on the basisof the results obtained, logic which is best suited for designing CMOS logic circuit will be found out. The logic on the basisof structure layout and design which gives best results for high-speed VLSI circuits, is found out.
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Faghih Mirzaee, Reza, Keivan Navi, and Nader Bagherzadeh. "High-Efficient Circuits for Ternary Addition." VLSI Design 2014 (September 1, 2014): 1–15. http://dx.doi.org/10.1155/2014/534587.

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New ternary adders, which are fundamental components of ternary addition, are presented in this paper. They are on the basis of a logic style which mostly generates binary signals. Therefore, static power dissipation reaches its minimum extent. Extensive different analyses are carried out to examine how efficient the new designs are. For instance, the ternary ripple adder constructed by the proposed ternary half and full adders consumes 2.33 μW less power than the one implemented by the previous adder cells. It is almost twice faster as well. Due to their unique superior characteristics for ternary circuitry, carbon nanotube field-effect transistors are used to form the novel circuits, which are entirely suitable for practical applications.
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Dissertations / Theses on the topic "High static power dissipation"

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Yu, Henry Hon-Kit. "Computer aided design of static reactive compensation for high voltage power systems." Thesis, University of Sunderland, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.293552.

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This thesis describes the development of a detailed set of step-by-step SVC system design procedures which allow manufacturers and operators to plan and develop optimum SVC systems for a given a.c. power transmission system. The validity of a typical svc system designed using the suggested procedures is investigated. The internationally recognised software package EMTP has been used as the primary Research tool, and principal features of this software, including those observed in the Research study also forms part of the discussion in the thesis. Previous conventional approaches to SVC simUlation have been restricted to simplified system models, and have only provided partial solutions to the design problem. In contrast, a detailed representation of three phase SVC systems using a time-domain approach is used in this research study in order to formulate a comprehensive design methodology. The SVC considered is for high voltage transmission applications, and is the TSC-TCR-FC type. A new optimisation program termed "OPTI-SVC" has also been developed to assist the SVC system design process. The system compensation limits must first be derived, and then for given equipment costs and system harmonic constraints, the program evaluates the optimum arrangement of the SVC primary system. Although certain simplifying assumptions are made and only those factors that can be taken into account analytically are considered, the program uses a worst case design philosophy in order to ensure acceptable performanceIn particular, Cost of the the program can minimise either the total svc system or the total harmonic voltage produced in the transmission system. In order to derive optimum control system settings, in particular for the SVC regulator, a structured trial and error approach has been developed. wi th the aid of the Astrom relay tuning technique, a good first estimation on optimum regulator settings for a given a.c. system condition can be obtained. The results are then systematically trimmed until a satisfactory system response is achieved. A three phase SVC system has been designed using the suggested approaches and applied to a generator fed transmission system. Realistic system data has been supplied by NEI Reyrolle Technology Limited. Simulated performance tests carried out demonstrate the correct functioning of the svc system against general accepted criteria, and hence the validity of the design procedure is established. As a primary research tool, the software EMTP has been proved to be very versatile although not user-friendly. Significant observations regarding the use of EMTP that are necessary to assist general users of the software package, are also revealed in the research study.
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RELE, SIDDHARTH N. "COMPILER OPTIMIZATIONS FOR POWER ON HIGH PERFORMANCE PROCESSORS." University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin982010436.

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Etminan, S. "Simulation of high-speed static reactive compensation for suppression of power system disturbances." Thesis, University of Sunderland, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.253748.

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Mauck, Lisa D. "The role of rate dependence and dissipation in the constitutive behavior of ferroelectric ceramics for high power applications." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15864.

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Qi, Yangjie. "FPGA Based High Throughput Low Power Multi-core Neuromorphic Processor." University of Dayton / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449526140.

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Cebrián, González Juan Manuel. "Diseño de Mecanismos de Grano Fino para la Gestión Eficiente de Consumo y Temperatura en Procesadores Multinúcleo." Doctoral thesis, Universidad de Murcia, 2011. http://hdl.handle.net/10803/38362.

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En la última década los ingenieros informáticos se han enfrentado a profundos cambios en el modo en que se diseñan y fabrican los microprocesadores. Los nuevos procesadores no solo deben ser más rápidos que los anteriores, también deben ser factibles en términos de energía y disipación térmica, sobre todo en dispositivos que trabajan con baterías. Los problemas relacionados con consumo y temperatura son muy comunes en estos procesadores. En esta Tesis analizamos el rendimiento, consumo energético y precisión de diferentes mecanismos de reducción de consumo y descubrimos que no son suficientemente buenos para adaptarse a un límite de consumo con una penalización de rendimiento razonable. Para solucionar este problema proponemos diversas técnicas a nivel de microarquitectura que combinan de manera dinámica varios mecanismos de reducción de consumo para obtener una aproximación al límite de consumo mucho más precisa con una penalización de rendimiento mínima.
In the last decade computer engineers have faced changes in the way microprocessors are designed. New microprocessors do not only need to be faster than the previous generation, but also be feasible in terms of energy consumption and thermal dissipation, especially in battery operated devices. In this Thesis we worked in the design, implementation and testing of microarchitecture techniques for accurately adapting the processor performance to power constraints in the single core scenario, multi-core scenario and 3D die-stacked core scenario. We first designed “Power-Tokens”,to approximate the power being consumed by the processor in real time. Later we proposed different mechanisms based on pipeline throttling, confidence estimation, instruction criticality information, to adapt the processor to a predefined power budget . We also propose some layout optimizations for 3D die-stacked vertical designs.
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Malan, Frederich T. "Reduction of the antenna coupling in a bi-static, FM-CW radar system." Thesis, Stellenbosch : Stellenbosch University, 2011. http://hdl.handle.net/10019.1/18029.

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Thesis (MScEng)--Stellenbosch University, 2011.
ENGLISH ABSTRACT: A well-known problem with FM-CW radar systems is the leakage of transmitter power into the receiver which leads to the making of close-in targets, and can severely limit the system dynamic range performance. This thesis considers two solutions to this radar system problem for a low frequency radar operating in the VHF band. The first method to suppress coupling is using separate transmit and receive antennas designed in such a way as to reduce coupling between them. The second is to design a negative feedback loop as part of the radar receiver where the feedback loop adaptively reduces the amount of transmitter leakage through to the receiver. This project details the realisation of these two solutions. A number of antenna designs are modelled in software and simulated to determine their characteristics of which the transmit-to-receive coupling is the key parameter. As no low coupling configuration could be found a simple configuration is chosen and practical measurements are taken. These antennas are then used in the radar system that is to be built. An FM-CW radar system is designed and simulated using software with a negative feedback loop being designed and implemented into the radar simulation. A practical radar system is then made inclusive of the feedback loop. Measurements are then taken to determine the efficacy of the feedback loop.
AFRIKAANSE OPSOMMING: ʼn Bekende probleem met FM-CW radar stelsels is die lekkasie van versender krag tot in die ontvanger wat lei tot die maak van nabye teikens en kan die stelsel se dinamiese sendbereik steng beperk. Hierdie tesis oorweeg twee oplossings tot hierdie probleem vir ʼn lae frekwensie radar wat in die VHF band werk. Die eerste metode wat na gekyk word om die koppeling te onderdruk is om die twee antennas van die radar stelsel so te ontwerp sodat die hoeveelheid koppeling tussen hulle verminder is. Die tweede is om ʼn negatiewe terugvoerlus as deel van die ontvanger te ontwerp. Hierdie terugvoerlus sal die versender lekkasie sein aanpassend in die ontvanger verminder. In hierdie projek word die realisering van bogenoemde oplossings uiteengeset. ʼn Paar verskillende antenna ontwerpe word gemodelleer in sagteware en word gesimuleer om hul karakteristieke te bepaal. Die belangrikste van hierdie faktore is die versender na ontvanger koppeling. Sienend dat geen ontwerp met ʼn lae genoeg koppeling gevind kon word nie, is ʼn eenvoudige ontwerp gekies en praktiese metings daarvan geneem. Hierdie antennas word dan gebruik in die radar stelsel wat gebou sal word. ʼn FM-CW radar stelsel word ontwerp en gesimuleer in sagteware. Die negatiewe terugvoerlus word ook ontwerp en geïmplementeer in die radar simulasie. ʼn Praktiese radar stelsel word dan gemaak insluitend die terugvoerlus. Metings word dan geneem om die effektiwiteit daarvan te bepaal.
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Hadjikypris, Melios. "Supervisory control scheme for FACTS and HVDC based damping of inter-area power oscillations in hybrid AC-DC power systems." Thesis, University of Manchester, 2016. https://www.research.manchester.ac.uk/portal/en/theses/supervisory-control-scheme-for-facts-and-hvdc-based-damping-of-interarea-power-oscillations-in-hybrid-acdc-power-systems(cc03b44a-97f9-44ec-839f-5dcbcf2801f1).html.

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Modern interconnected power systems are becoming highly complex and sophisticated, while increasing energy penetrations through congested inter-tie lines causing the operating point approaching stability margins. This as a result, exposes the overall system to potential low frequency power oscillation phenomena following disturbances. This in turn can lead to cascading events and blackouts. Recent approaches to counteract this phenomenon are based on utilization of wide area monitoring systems (WAMS) and power electronics based devices, such as flexible AC transmission systems (FACTS) and HVDC links for advanced power oscillation damping provision. The rise of hybrid AC-DC power systems is therefore sought as a viable solution in overcoming this challenge and securing wide-area stability. If multiple FACTS devices and HVDC links are integrated in a scheme with no supervising control actions considered amongst them, the overall system response might not be optimal. Each device might attempt to individually damp power oscillations ignoring the control status of the rest. This introduces an increasing chance of destabilizing interactions taking place between them, leading to under-utilized performance, increased costs and system wide-area stability deterioration. This research investigates the development of a novel supervisory control scheme that optimally coordinates a parallel operation of multiple FACTS devices and an HVDC link distributed across a power system. The control system is based on Linear Quadratic Gaussian (LQG) modern optimal control theory. The proposed new control scheme provides coordinating control signals to WAMS based FACTS devices and HVDC link, to optimally and coherently counteract inter-area modes of low frequency power oscillations inherent in the system. The thesis makes a thorough review of the existing and well-established improved stability practises a power system benefits from through the implementation of a single FACTS device or HVDC link, and compares the case –and hence raises the issue–when all active components are integrated simultaneously and uncoordinatedly. System identification approaches are also in the core of this research, serving as means of reaching a linear state space model representative of the non-linear power system, which is a pre-requisite for LQG control design methodology.
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Escamez, Guillaume. "AC losses in superconductors : a multi-scale approach for the design of high current cables." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT087/document.

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Le travail de cette thèse porte sur l'étude des pertes AC dans les supraconducteurs pour des applications tels que les câbles ou les aimants. Les modélisations numériques rapportées sont de type éléments-finis et méthode intégrale. Toutes ces méthodes visent à résoudre à calculer les distributions de densité de courant et de champ magnétique en prenant en compte différents loi de comportement pour le supraconducteur. Deux conducteurs sont introduits dans ce mémoire. Tout d'abord, les supraconducteurs à haute température critiques sont étudiées avec l'introduction d'une nouvelle forme de conducteur (fils cylindriques) et sont envisagés pour des câbles fort courant de 3~kA. Dans un second temps, des simulations numériques 3-D sont réalisés sur un conducteur MgB2. Le chapitre suivant traite des contraintes de calculs des pertes dans le but de dimensionner l'ensemble des pertes d'un câble complet. Enfin, les modèles numériques développés précédemment sont utilisé sur un exemple concret : le démonstrateur 10~kA fait à l'aide du conducteur MgB2 dans le projet BEST-PATHS
The work reported in this PhD deals with AC losses in superconducting material for large scale applications such as cables or magnets. Numerical models involving FEM and integral methods have been developed to solve the time transient electromagnetic distributions of field and current density with the peculiarity of the superconducting constitutive E-J equation. Two main conductors have been investigated for two ranges of superconducting cables. First, REBCO superconductors working at 77 K are studied and a new architecture of conductor (round wires) for 3~kA cables. Secondly, for very high current cables, 3-D simulations on MgB2 wires are approach and solved using FEM modeling. The following chapter introduced new development used for the calculation of AC losses in DC cables. The thesis ends with the use of the developed numerical model on a practical example in the BEST-PATHS project: a 10 kA MgB2 demonstrator
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Kirsten, André Luís. "Reator eletrônico para lâmpadas de descarga em alta pressão baseado no conversor biflyback inversor." Universidade Federal de Santa Maria, 2011. http://repositorio.ufsm.br/handle/1/8494.

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Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
The study of the best utilization of high intensity discharge lamps deals with the great global concern with energy efficiency. Electronic ballasts are the current devices that can make the good use of high luminous efficacy and the long useful life of these lamps. This work aims to develop an electronic ballast to supply high intensity discharge lamps. In order to avoid the acoustic resonance phenomenon occurrence, the lamp is supplied with low frequency square waveform. Power control and voltage inversion stage in the lamp are developed by the biflyback inverter topology. The analysis and design of this topology were performed, as well as the development of resonant inversion methodology of the lamp voltage. It is proposed one study, qualitative and quantitative, of active converters to provide the power factor correction, and their integration with the biflyback inverter topology. Buck biflyback inverter topology is chosen to the implementation of practical experiments, in order to validate the present work. The converter modeling, considering the lamp dynamic, such as the stability analysis and theoretical control strategy of current and lamp power are presented. Experimental results show that the proposed electronic ballast has the follow characteristics: high power factor (0.97), low input current harmonic distortion, high efficiency (88%) and not visible occurrence of acoustic resonance phenomenon.
O estudo do melhor aproveitamento das características das lâmpadas de descarga em alta pressão vem ao encontro da grande preocupação mundial com a eficientização energética. Reatores eletrônicos são os dispositivos atuais que melhor aproveitam a alta eficácia luminosa e longa vida útil dessas lâmpadas. Este trabalho visa o desenvolvimento de um reator eletrônico para a alimentação de lâmpadas de descarga em alta pressão. De modo a não excitar a ocorrência do fenômeno de ressonância acústica, a alimentação da lâmpada é realizada através de forma de onda de corrente quadrada em baixa frequência. Os estágios de controle de potência e inversão da tensão na lâmpada são realizados pela topologia biflyback inversora. A análise e projeto desta topologia foram realizados, assim como o desenvolvimento de uma metodologia de inversão ressonante da tensão da lâmpada. É proposto um estudo, qualitativo e quantitativo, dos conversores ativos para correção do fator de potência, e a integração destes, com a topologia biflyback inversora. A topologia buck biflyback inversora foi escolhida para a realização de experimentos práticos para a validação do trabalho. A modelagem do conversor, considerando a dinâmica de uma lâmpada de descarga em alta pressão de sódio foi realizada. Assim como a análise da estabilidade e estratégias de controle da corrente e da potência na lâmpada. Os resultados experimentais comprovam que o reator eletrônico proposto apresenta as características desejadas de: alto fator de potência (0,97), atendimento da norma IEC61000-3-2 para o nível das harmônicas da corrente de entrada, elevado rendimento (88%) e não excitação visível do fenômeno de ressonância acústica.
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Books on the topic "High static power dissipation"

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Sood, Vijay K. HVDC and FACTS controllers: Applications of static converters in power systems. Boston, MA: Kluwer Academic, 2003.

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HVDC and FACTS controllers: Applications of static converters in power systems. Boston: Kluwer Academic, 2004.

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Low, Tim D. Low power, high performance pseudo-static D flip-flop. 1999.

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Sood, Vijay K. HVDC and FACTS Controllers: Applications of Static Converters in Power Systems (Power Electronics and Power Systems). Springer, 2004.

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Sood, Vijay K. HVDC and FACTS Controllers: Applications of Static Converters in Power Systems. Springer, 2013.

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Noack, Christian, ed. Politics of the Russian Language Beyond Russia. Edinburgh University Press, 2021. http://dx.doi.org/10.3366/edinburgh/9781474463799.001.0001.

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Russia increasingly emphasises the importance of ‘soft power’ for securing its foreign policy interests. Recent research has paid more attention to Russia’s intentions rather than to the receiving end of its cultural and public diplomacy. This volume addresses this gap and explores the specifics of both Russian language promotion and its acceptance in a number of case and country studies, including Ukraine, Germany and Ireland. The authors discuss the legal status and the practical use of Russian for communication or media use, both in the ‘near’ and the ‘far abroad’, examining the politics of the Russian language, the role of the Russian Federation in influencing these politics and the challenges that the promotion of Russian faces in particular contexts across the globe. They discern a fairly instrumental approach towards Russian language promotion. With its strong focus on the former Soviet space, language promotion aims at preserving cohorts of Russian heritage speakers, who are conceived as quasi-natural agents of Russian influence in the neighbourhood. By contrast, the willingness to engage with Russia’s language promotion is seriously diminished by the ideological loading of culture and language in Russian discourses, like those on the ‘compatriots’ and the ‘Russian World’. By declaring the active use of Russian as an expression of political loyalty, Russia almost excludes utilitarian approaches to the learning of the language. Moreover, the book documents a rather traditional understanding of culture with essentialist and static features. Instead of seeing culture as an autonomous free space for negotiation of political possibilities, Russia’s culture and language promotion rests on narrowly codified high culture.
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Book chapters on the topic "High static power dissipation"

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Wu, Keng C. "High-Stress Part and Power Dissipation." In Pulse Width Modulated DC-DC Converters, 116–23. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-6021-0_9.

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Haj-Yahya, Jawad, Avi Mendelson, Yosi Ben Asher, and Anupam Chattopadhyay. "Static Power Modeling for Modern Processor." In Energy Efficient High Performance Processors, 135–65. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8554-3_5.

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Rele, Siddharth, Santosh Pande, Soner Onder, and Rajiv Gupta. "Optimizing Static Power Dissipation by Functional Units in Superscalar Processors." In Lecture Notes in Computer Science, 261–75. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45937-5_19.

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Sharma, Sameer, and L. G. Johnson. "First Order, Quasi-Static, SOI Charge Conserving Power Dissipation Model." In VLSI-SoC: Advanced Topics on Systems on a Chip, 1–23. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-89558-1_16.

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Millan, Alejandro, Jorge Juan, Manuel J. Bellido, David Guerrero, Paulino Ruiz-de-Clavijo, and Julian Viejo. "Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates." In Lecture Notes in Computer Science, 389–98. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-95948-9_39.

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Ge, Jiawei, Dayuan Jin, and Zhiwei Qian. "Research on Heat Dissipation Technology of the High-Power Array Antenna." In Lecture Notes in Electrical Engineering, 400–412. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9441-7_41.

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Satoh, A., Y. Kobayashi, H. Niijima, N. Ooba, S. Munetoh, and S. Sone. "A high-speed small RSA encryption LSI with low power dissipation." In Lecture Notes in Computer Science, 174–87. Berlin, Heidelberg: Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/bfb0030419.

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Kumbhare, Praful P., Akhilesh A. Nimje, and Pankaj R. Sawarkar. "Application of Distributed Static Series Compensator for Improvement of Power System Stability." In Silicon Photonics & High Performance Computing, 27–34. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7656-5_4.

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Srikantam, Vamsi, and Mario Martinez. "Comparative Analysis of Flip-Flops and Application of Data-Gating in Dynamic Flip-Flops for High Speed, Low Active and Low Leakage Power Dissipation." In Power Aware Computing, 3–17. Boston, MA: Springer US, 2002. http://dx.doi.org/10.1007/978-1-4757-6217-4_1.

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Bharathsimha Reddy, A., S. N. Mahato, and Nilanjan Tewari. "Static and Dynamic Analysis of IGBT Power Modules for Low and High-Power Range Electric Drives." In Recent Advances in Power Electronics and Drives, 119–36. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-7728-2_9.

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Conference papers on the topic "High static power dissipation"

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Lu, Jianhua. "Heat dissipation analysis of high power LED package." In 2017 14th China International Forum on Solid State Lighting: International Forum on Wide Bandgap Semiconductors China (SSLChina: IFWS). IEEE, 2017. http://dx.doi.org/10.1109/ifws.2017.8246007.

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Jahanian, Shahriar, and Z. J. Delalic. "Temperature Distribution in a VLSI Chip due to Dynamic Power Density." In ASME 1999 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 1999. http://dx.doi.org/10.1115/imece1999-1183.

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Abstract High speed computation is driving VLSI custom chips into smaller micron sizes and scale down power supplies. To accomplish very high speed, industry is developing shut down methods and short channel devices. Going below 0.5 micron technology speed is accomplished but hot spots, power density, and die failure are increased. Failure accumulated knowledge has not yet established a classic theory. In this paper, the STEPS method is used to determine the power dissipation in a CMOS circuit The experiment demonstrates dynamic power dissipation and assumes that static power dissipation is negligible in the CMOS devices. Each node is examined individually as signals are propagated through the chip. At each node the power distribution in the form of heat is determined.
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Raju, Uthaman, Praveen Pandojirao-S., Niraja Sivakumar, and Dereje Agonafer. "Static Power Consumption: Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistor." In ASME 2007 International Mechanical Engineering Congress and Exposition. ASMEDC, 2007. http://dx.doi.org/10.1115/imece2007-44059.

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The static power consumption due to leakage current plays a significant part in semiconductor devices, as the device dimensions continue to shrink. Low power dissipation is one of the critical factors needed to achieve high performance in a chip. New methods are continuously being implemented for reduction of leakage current in deep sub micron ultra thin SOI MOSFET using device simulator tools. In this paper, an 18nm gate length ultra thin SOI MOSFET is simulated for different silicon body thicknesses and the leakage current is determined by using the device simulator, MEDICITM. It is demonstrated that MEDICI™ device simulations is a good tool that can effectively be used for ultra thin SOI MOSFET devices to study the effect of design parameters on the leakage current. Ultra thin SOI MOSFET with 18nm gate length of different Silicon body thickness is simulated and the leakage current as determined by using MEDICI™ shows that the leakage current decreases by 10–15% as the silicon body thickness reduces by 2 nm.
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Hurst, Adam M., Anthony D. Kurtz, and Boaz Kochman. "High Temperature Static and Dynamic Pressure Transducer for Combustion Instability Control Using Acoustic Low-Pass Filter Structures." In ASME Turbo Expo 2008: Power for Land, Sea, and Air. ASMEDC, 2008. http://dx.doi.org/10.1115/gt2008-51522.

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There is a need to measure static and dynamic conditions in many gas turbine applications, in particular for combustion instabilities, such as those in the afterburner. The DC and low frequency components are typically used for conventional engine control, while the high frequency data is essential for acoustic screech and rumble diagnostics and control. This paper presents a static-dynamic piezoresistive pressure transducer that measures low amplitude, dynamic pressure perturbations superimposed on top of a high pressure through the implementation of low pass mechanical structures. The transducer, which is capable of operating at ultra-high temperatures and in harsh environments, consists of a static piezoresistive pressure transducer, which measures the large pressures on the order of 200psi and greater, and an ultrasensitive, dynamic piezoresistive pressure transducer which captures small, high frequency pressure oscillations on the order of a few psi. The heightened sensitivity in high pressure environments is achieved by filtering the measured pressure of high frequency content through an innovative low pass mechanical filter structure. The large static pressures passed by the low-pass mechanical filter structures are routed to the backside of the dynamic pressure sensor, which results in both the front and the back of the dynamic sensor being exposed to the large pressures within the environment. Therefore, the large static pressures cancel out, and the dynamic sensor only senses the low magnitude, high frequency pressure perturbations. This dual sensor, static-dynamic pressure transducer reproduces pressure signals with sensitivity far higher than any single high pressure transducer available today. The dual sensor, static-dynamic transducer meets the pressure sensing specification of numerous applications including, but not limited to, the following: the optimization of turbine operation, turbine design and testing, the detection of the onset of rotating stall and surge in turbine compressors, and combustion instabilities. This paper describes a six element model of the static-dynamic transducer’s low-pass mechanical filtering structures. The paradigm is derived from first-principles of fluid motion in acoustic ducts with viscous dissipation. A dynamic pressure source is used to verify the model and its operation. Finally, a transfer function characterization of a fully operational static-dynamic pressure transducer over a wide bandwidth is presented. Based upon the analytical and experimental results, the static-dynamic pressure transducer will make it possible for turbine users and manufacturers to implement ultra-sensitive pressure monitoring to reduce compressor and combustion instabilities [1] [2].
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Hassanvand, Mohsen, Wang Song Tao, Feng Guo Tai, and Wang Zhong Qi. "Unsteady Simulation and Investigation of Tip Leakage Flow Based on Dissipation Function." In ASME Turbo Expo 2004: Power for Land, Sea, and Air. ASMEDC, 2004. http://dx.doi.org/10.1115/gt2004-54283.

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Further improvements of flow in tip clearance demand a better understanding of its complex structure and this would not be possible if we are not able to provide an interpretative or a more realistic presentation of its main effects, i.e., viscous dissipation and mixing. To do so and to gain further insights into the details and distribution of viscous dissipation, a commercial N-S solver has been employed for simulation and investigation of the unsteady flow field inside the tip clearance of a turbine rotor in first stage. The main objective of this paper is to introduce the direct implementation of dissipation function for viscous dissipation assessment in tip leakage flow. This idea seems to be the simplest and at the same time, the most straightforward approach to simulate and calculate the viscous dissipation caused by viscous effects. It is shown that the dissipation function can be employed as a strong and convenient tool in direct identification and assessment of regions of high viscous dissipation. It has been found that in tip leakage flow, regions of high viscous effects are located near casing rather than blade tip. Near casing, leakage flow creates a source point in pressure side and a sink point in suction side on rotor blade tip projection on the casing. It is shown that the time-averaged viscous dissipation in tip leakage flow is dissimilar for rotor blades. This result, which is caused by flow unsteadiness, is a helpful hint that can be taken by blade designers to design non-uniform rotor blades, that is, to design blades with different geometries and aerodynamic loads, both circumferentially and radially, to minimize the viscous dissipation. The casing passage vortex, the end wall boundary layers, and the wakes from the upstream stator significantly enhance the unsteadiness of the flow to the tip region of rotor blades. Results indicate that there exists a strong interaction between leakage flow and annulus-wall boundary layer.
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Kameyama, Atushi, Yasuo Ikawa, Katsue Kawakyu, Takamaro Mizoguchi, Toshiyuki Terada, and Nobuyuki Toyoda. "An SLCF Circuit: A Large Noise Margin, High-Speed and Moderate Power Dissipation Circuit for Reliable GaAs LSI Operation." In 1986 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1986. http://dx.doi.org/10.7567/ssdm.1986.c-6-4.

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Kim, Tae Ho, and Luis San Andre´s. "Heavily Loaded Gas Foil Bearings: A Model Anchored to Test Data." In ASME Turbo Expo 2005: Power for Land, Sea, and Air. ASMEDC, 2005. http://dx.doi.org/10.1115/gt2005-68486.

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Widespread usage of gas foil bearings (FBs) into micro turbomachinery to midsize gas turbine engines requires accurate performance predictions anchored to reliable test data. The paper presents a simple yet accurate model predicting the static and dynamic force characteristics of gas FBs. The analysis couples the Reynolds equation for a thin gas film to a simple elastic foundation model for the top foil and bump strip layer. An exact flow advection model is adopted to solve the partial differential equations for the zeroth- and first- order pressure fields that render the FB load capacity and frequency dependent force coefficients. As the static load imposed on the foil bearing increases, predictions show the journal center displaces to eccentricities exceeding the bearing nominal clearance. A nearly constant FB static stiffness, independent of journal speed, is estimated for operation with large loads; and approaching closely the structural stiffness derived from contact operation at null rotor speed. Predicted minimum film thickness and journal attitude angle demonstrate good agreement with archival test data for a first-generation gas FB. The bump-foil strip structural loss factor, exemplifying a dry-friction dissipation mechanism, aids to largely enhance the bearing direct damping force coefficients. At high loads, the bump-foil structure influences most the stiffness and damping coefficients. The FB whirl frequency ratio (WFR) is examined to ensure its dynamically stable operation. The predictions demonstrate that FBs have greatly different static and dynamic force characteristics when operating at journal eccentricities in excess of the bearing clearance from those obtained for operation at low loads, i.e. small journal eccentricities.
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Hassan Vand, Mohsen, and Songtao Wang. "Numerical Study of the Effects of Bowed Blades on Aerodynamic Characteristics in a High Pressure Turbine." In ASME Turbo Expo 2005: Power for Land, Sea, and Air. ASMEDC, 2005. http://dx.doi.org/10.1115/gt2005-68214.

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A commercial N-S solver has been employed for simulating the unsteady flow field and analyzing aerodynamic characteristics in a steam turbine stage with low aspect ratio in two cases, one with straight and the other with bowed stator blades. The stator and rotor trailing edge wakes have been studied and compared for two cases. In blade-to-blade view, it was observed that the strength, position and the width or range of influence of wakes in bowed stator blades are bigger than those of straight blades. This effect causes remarkable changes in rotor flow and rotor trailing edge wakes. By analyzing the wake-induced turbulence, it was found that there is a periodic distribution for stator trailing wakes along the radial direction in straight blades, while for bowed blades; the distribution is concentrated towards the midspan. The bowing of stator blades causes the rotor trailing wakes to be greatly strengthened near the hub and casing. The blade loading distribution, viscous dissipation and rotor tip leakage flow for straight and bowed blades are compared in detail to show the aerodynamic performance of stator blade bowing.
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Altman, David H., Anurag Gupta, Thomas E. Dubrowski, Darin J. Sharar, Nicholas R. Jankowski, and Mark T. North. "Analysis and Characterization of Thermal Expansion-Matched Wick-Based Multi-Chip Passive Heat Spreaders in Static and Dynamic Environments." In ASME 2013 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2013. http://dx.doi.org/10.1115/ipack2013-73087.

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Ensuring adequate spreading of heat dissipated by high power density devices is a critical part of many electronics packaging designs. In many cases, passive wick-based heat spreaders can offer improved heat spreading performance relative to solid conductor alternatives. However, concerns related to performance degradation in high-inertial force environments frequently limit their use to static or near-static applications. In this work we investigate the performance of low coefficient of thermal expansion (CTE) wick-based heat spreaders cooling multiple high heat flux devices in static and high-g environments. Two high-power devices are simulated using custom-manufactured resistor-thermometer chips, enabling dissipation of die average heat fluxes in excess of 150W/cm2. Comparative thermal performance is evaluated for wick-based heat spreaders and solid CuMo heat spreaders of equivalent CTE affixed with interface materials typical of those used when attaching a low CTE package to a high CTE cold plate (e.g., Al or Cu). Thermal performance is characterized as a function of heat input during exposure to increasing g-forces applied using a custom-built centrifuge. Experimental observations are interpreted through detailed modeling of fluid flow patterns within the wick structure of the passive heat spreader. Results from these experiments demonstrate that properly designed wick-based heat spreaders have utility in both static and dynamic environments, exhibiting effective conductivities in excess of that obtainable with competitive low-expansion composites.
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Schuepbach, P., R. S. Abhari, M. G. Rose, T. Germain, I. Raab, and J. Gier. "Improving Efficiency of a High Work Turbine Using Non-Axisymmetric Endwalls: Part II—Time-Resolved Flow Physics." In ASME Turbo Expo 2008: Power for Land, Sea, and Air. ASMEDC, 2008. http://dx.doi.org/10.1115/gt2008-50470.

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This paper is the second part of a two part paper that reports on the improvement of efficiency of a one-and-half stage high work axial flow turbine. The first part covered the design of the endwall profiling as well as a comparison with steady probe data, this part covers the analysis of the time-resolved flow physics. The focus is on the time-resolved flow physics that lead to a total-to-total stage efficiency improvement of Δηtt = 1.0% ± 0.4%. The investigated geometry is a model of a high work (Δh/U2 = 2.36), axial shroudless HP turbine. The time-resolved measurements have been acquired upstream and downstream of the rotor using a Fast Response Aerodynamic Probe (FRAP). The paper contains a detailed analysis of the secondary flow field that is changed between the axisymmetric and the non-axisymmetric endwall profiling cases. The flowfield at exit of the first stator is improved considerably due to non-axisymmetric endwall profiling and results in reduced secondary flow and a reduction of loss at both hub and tip, as well as a reduced trailing shed vorticity. The rotor has reduced losses and a reduction of secondary flows mainly at the hub. At the rotor exit the flow field with non-axisymmetric endwalls is more homogenous due to the reduction of secondary flows in the two rows upstream of the measurement plane. This confirms that non-axisymmetric endwall profiling is an effective tool for reducing secondary losses in axial turbines. Using a frozen flow assumption the time-resolved data is used to estimate the axial velocity gradients, which are then used to evaluate the streamwise vorticity and dissipation. The non-axisymmetric endwall profiling of the first nozzle guide vane show reductions of dissipation and streamwise vorticity due to reduced trailing shed vorticity. This smaller vorticity explains the reduction of loss at mid-span, which is shown in the first part of the two part paper. This leads to the conclusion that non-axisymmetric endwall profiling also has the potential of reducing trailing shed vorticity.
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Reports on the topic "High static power dissipation"

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Nelson, Thomas, Donald Agresta, and James Ehret. Heat Dissipation for High Power Optically Pumped Semiconductor Vertical External Cavity Surface Emitting Lasers. Fort Belvoir, VA: Defense Technical Information Center, October 2003. http://dx.doi.org/10.21236/ada419156.

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Bell, Jason R., Robert Anthony Joseph III, Joanna McFarlane, and A. L. Qualls. Phenylnaphthalene as a Heat Transfer Fluid for Concentrating Solar Power: High-Temperature Static Experiments. Office of Scientific and Technical Information (OSTI), May 2012. http://dx.doi.org/10.2172/1039630.

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EXPERIMENTAL STUDY ON MECHANICAL PERFORMANCE OF BUCKLING-RESTRAINED BRACE ON FRAMES WITH HIGH-STRENGTH CONCRETE-FILLED SQUARE STEEL TUBE COLUMNS. The Hong Kong Institute of Steel Construction, September 2023. http://dx.doi.org/10.18057/ijasc.2023.19.3.9.

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Using buckling-restrained braces (BRBs) in frames with high-strength concrete-filled square steel tube columns(HSCFSSTC) can solve issues such as brittle failure and low lateral stiffness. To investigate the mechanical performance of buckling-restrained brace frames(BRBFs), an experiment study was conducted. The investigation involved the design and analysis of a frame system composed of BRBs, HSCFSSTC and H-shaped steel beams. Sub-structures at a 1/3 scale with two types of connections, welded and pin connections, were subjected to pseudo-static tests. The influence of BRBF connection types on the plastic hinge formation mechanism, load-bearing capacity, energy dissipation capacity and stress magnitude of the connection gusset plates was examined. After the test, ABAQUS software was used for finite element analysis of the specimen, and the simulation results were in good agreement with the experimental results.Based on the results, both the welded and pin-connected specimens formed plastic hinges at column bases and the beam ends, which ensured the energy dissipation performance of BRBs. Pin connections were found to exhibit noticeable slippage during loading due to the presence of holes. However, the study found that the plastic hinge formation mechanism, load-bearing capacity, and lateral stiffness of the frames with the two connection types were similar. Furthermore, there was no significant difference in the load-bearing capacity, stress distribution, and magnitude between the two connection types. Nevertheless, welded connections demonstrated a greater potential for broader application as they allowed the BRB to resist horizontal seismic forces earlier than pin connections.
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