Dissertations / Theses: 'High speed converters'

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Sculley, Terry Lee. "Achieving high speed, high precision A/D conversion using nonlinearity correction." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/13424.

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Chan, Kok Lim. "High-speed, high-resolution digital-to-analog converters." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2007. http://wwwlib.umi.com/cr/ucsd/fullcit?p3294746.

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Thesis (Ph. D.)--University of California, San Diego, 2007.
Title from first page of PDF file (viewed March 14, 2008). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references.

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Robinson, Dirk J. "High speed data converter circuits in SI-GE." Pullman, Wash. : Washington State University, 2008. http://www.dissertations.wsu.edu/Dissertations/Fall2008/d_robinson_121008.pdf.

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Thesis (Ph. D.)--Washington State University, December 2008.
Title from PDF title page (viewed on Jan. 15, 2009). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 60-61).

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Hsu, M. S. "Aspects of designing a high speed analog to digital converter /." Title page, contents and abstract only, 1992. http://web4.library.adelaide.edu.au/theses/09ENS/09ensh873.pdf.

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Figueiredo, Michael. "Reference-free high-speed cmos pipeline analog-to-digital converters." Doctoral thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8776.

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Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering of the Faculdade de Ciências e Tecnologia of Universidade Nova de Lisboa
More and more signal processing is being transferred to the digital domain to profit from the technological enhancement of digital circuits. Where technology scaling enhances the capabilities of digital circuits, it degrades the performance of analog circuits. However, it is important to note that the impact that technology scaling has on digital circuits is becoming smaller and smaller, which means that, in nanotechnologies, to enhance energy and area efficiency, we can not simply depend on the benefits of this scaling. Although, a share of the efficiency can be obtained from the technology, new circuit architectures and techniques have to be developed to really push the limits of efficiency. In data converters, more specifically analog-to-digital converters (ADCs), a decision can be made: research energy and area efficient analog circuit techniques and architectures that cope with technological scaling issues, or design algorithms that use digital circuitry to assist the poor analog technological performance. The former option is the premise for the work developed in this thesis. The work reported in this thesis explores various design techniques with the purpose of enhancing the power and area efficiency of building blocks mainly to be used in multiplying digital-to-analog converter based ADCs. Therefore, novel analog techniques are developed for the three main blocks of an MDAC-based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. These techniques include self-biasing and inverter-based design for the flash quantizer and amplifier. Regarding the MDAC, it combines three techniques: unity feedback factor, insensitivity to capacitor mismatch, and current-mode reference shifting. In the second part of this work, the designed amplifier is implemented and experimentally characterized demonstrating its practical feasibility and performance. The final part of this work explores the design and implementation of a medium-low resolution high speed pipeline ADC incorporating all the developed circuits. Experimental results validate the feasibility of the techniques and demonstrate the attractiveness in terms of power dissipation and reduced area.

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Li, Xiangtao. "High-speed analog-to-digital conversion in SiGe HBT technology." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24652.

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Thesis (Ph.D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Committee Chair: Cressler, John D.; Committee Member: Laskar, Joy; Committee Member: Lee, Chin-Hui; Committee Member: Morley, Thomas; Committee Member: Papapolymerou, John

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Karanicolas, Andrew N. (Andrew Nicholas). "Digital self-calibration techniques for high-accuracy, high speed analog-to-digital converters." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/12010.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
Includes bibliographical references (leaves 219-224).
by Andrew Nicholas Karanicolas.
Ph.D.

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Lu, Dongtian. "High speed CMOS ADC for UWB receiver /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LUD.

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Gupta, Amit Kumar. "Design techniques for low noise and high speed A/D converters." [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1666.

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Sundström, Timmy. "Design of High‐Speed, Low‐Power, Nyquist Analog‐to‐Digital Converters." Licentiate thesis, Linköping University, Linköping University, Electronic Devices, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-51375.

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The scaling of CMOS technologies has increased the performance of general purposeprocessors and DSPs while analog circuits designed in the same process have not been ableto utilize the process scaling to the same extent, suffering from reduced voltage headroom and reduced analog gain. In order to design efficient analog‐to‐digital converters in nanoscale CMOS there is a need to both understand the physical limitations as well as to develop new architectures and circuits that take full advantage of what the process has tooffer.

This thesis explores the power dissipation of Nyquist rate analog‐to‐digital converters andtheir lower bounds, set by both the thermal noise limit and the minimum device and feature sizes offered by the process. The use of digital error correction, which allows for lowaccuracy analog components leads to a power dissipation reduction. Developing the bounds for power dissipation based on this concept, it is seen that the power of low‐to‐medium resolution converters is reduced when going to more modern CMOS processes, something which is supported by published results.

The design of comparators is studied in detail and a new topology is proposed which reduces the kickback by 6x compared to conventional topologies. This comparator is used in two flash ADCs, the first employing redundancy in the comparator array, allowing for the use of small sized, low‐power, low‐accuracy comparators to achieve an overall low‐power solution. The flash ADC achieves 4 effective bits at 2.5 GS/s while dissipating 30 mW of power.

The concept of low‐accuracy components is taken to its edge in the second ADC which oes not include a reference network, instead relying on the process variations to generate the reference levels based on the mismatch induced comparator offsets. The reference‐free ADC achieves a resolution of 3.69 bits at 1.5 GS/s while dissipation 23 mW showing that process variations not necessarily must be seen as detrimental to circuit performance but rather can be seen as a source of diversity.

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Macedo, Marco. "Calibration and high speed techniques for CMOS analog-to- digital converters." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=110482.

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The main focus of the work carried in this dissertation is to find the best design solution for an ultra high-speed Analog-to-Digital converter. Designing CMOS Analog-to-Digital converters in the gigahertz range for a good resolution is a challenge due to a lower power supply and smaller transistors. As a result, critical analog components (e.g., comparator, pre-amplifiers, band-gap) become more susceptible to process variation and make it hard to achieve a good resolution (e.g., higher than 6-bit). The traditional approach to design Analog-to-Digital converters does not work well with current CMOS technology and yields unpractical designs since it does not take advantage of the technology scaling down. For these reasons, this work investigates new designs topologies for the track-and-hold circuits needed at the front-end of ultra high-speed Analog-to- Digital converters and also investigates a digital foreground technique aimed at reducing the impact of process mismatch. For this purpose, two chips have been designed to investigate the best track-and-hold architecture based on a differential switch source-follower and to validate a proposed digital foreground calibration technique using resistive loads.
L'objectif de cette dissertation est de trouver la meilleure méthode de conception pour les convertisseurs de type analogique à digital. La conception de convertisseurs de type analogique à digital en CMOS qui soient capables de fournir une résolution élevée est un défi de taille à des fréquences très élevées comme les gigahertz, car en CMOS les sources de voltages sont très petites et les dimensions des transistors rendent les composantes analogues (e.g., comparateur, amplicateur, et references de voltage) de plus en plus susceptibles aux variations physiques et chimiques qui se produisent durant la fabrication des puces microélectroniques.Les méthodes traditionnelles de conception pour les convertisseurs de type analogique à digital ne sont plus a la hauteur pour fournir des convertisseurs capables d'une bonne resolution, car elles ne prennent pas avantage des percés technologiques qui ont été réalisées avec la diminution de la taille physique des transistors en CMOS. Par conséquent, le travail de recherche éffectué dans cette thèse consiste à étudier des nouvelles structures de circuits pour faire la conception de track-and-hold qui est necessaire au bon fonctionnement de convertisseurs analogique à digital de très hautes fréquences. De plus, une méthode de calibration digitale qui a pour objectif de corriger les défectuosités engendrées par la fabrication des puces microélectroniques est aussi proposée afin d'ameliorer la performance et la résolution des convertisseurs analogique à digital. Finalement, deux puces microélectroniques ont été fabriquées a des fins expérimentales pour démontrer la performance d'un nouveau track-and-hold ainsi que valider une nouvelle technique de calibration digitale de type foreground qui utilise des résistances.

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Bhide, Ameya. "Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters." Doctoral thesis, Linköpings universitet, Elektroniska Kretsar och System, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-120626.

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Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for highdata-ate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconguration for multiple radio standards. ΔΣ DACs can t very well into this trend of digital architectures as they contain a large digital signal processing component and oer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction lter order is reduced. Achieving a large bandwidth from ΔΣ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ΔΣ DAC architectures, even in nanometer CMOS processes. Time-interleaved ΔΣ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs. The rst work is an 8-GS/s interleaved ΔΣ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the nal multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, –57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to be limited by the testing setup for sending high-speed digital data into the prototype. The performance of a two-channel interleaved ΔΣ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this eect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 — z—1)n. It is shown that a low-order FIR lter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this lter is also developed. These expressions are useful for choosing a suitable modulator and lter order for an interleaved ΔΣ DAC in the early stage of the design process. A comparison between the FIR lter and compensation techniques for DCE mitigation is also presented. The nal work is a 11 GS/s 1.1 GHz bandwidth time-interleaved DAC prototype IC in 65-nm CMOS for the 60-GHz radio baseband. The high sampling rate is again achieved by using a two-channel interleaved MASH 1-1 architecture with a 4-bit output i.e only fteen analog current cells. The single clock architecture for the logic and the multiplexing requires each channel to operate at 5.5 GHz. To enable this, a new look-ahead technique is proposed that decouples the two channels within the modulator feedback path thereby improving the speed as compared to conventional loop-unrolling. Full speed DAC testing is enabled by an on-chip 1 Kb memory whose read path also operates at 5.5 GHz. Measurement results from the prototype show that the ΔΣ DAC achieves >53 dB SFDR, < —49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. The proposed ΔΣ DAC can satisfy the spectral mask of the 60-GHz radio IEEE 802.11ad WiGig standard with a second order reconstruction lter.

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Rebold, Thomas Arthur. "Dynamic error correction method for high-speed analog-to-digital converters." Thesis, Massachusetts Institute of Technology, 1987. http://hdl.handle.net/1721.1/14623.

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Kapusta, Ronald A. (Ronald Alan) 1979. "A delay line architecture for high-speed analog-to-digital converters." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/87228.

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Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
Includes bibliographical references (p. 95-97).
by Ronald A. Kapusta, Jr.
M.Eng.

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Wu, Jian-Yi. "Roundtrip design strategy of high-speed delta-sigma A/D Converters /." The Ohio State University, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=osu148647407805097.

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Shoaei, Omid Carleton University Dissertation Engineering Electronics. "Continuous-time Delta-Sigma A/D converters for high speed applications." Ottawa, 1995.

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17

Sundström, Timmy. "Design of high-speed, low-power, Nyquist analog-to-digital converters /." Linköping : Department of Electrical Engineering, Linköping University, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-51375.

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Lee, Choong Hoon. "Design of high speed low voltage data converters for UWB communication systems." Texas A&M University, 2005. http://hdl.handle.net/1969.1/3798.

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For A/D converters in ultra-wideband (UWB) communication systems, the flash A/D type is commonly used because of its fast speed and simple architecture. However, the number of comparators in a flash A/D converter exponentially increases with an increase in resolution; therefore, an interpolating technique is proposed in this thesis to mitigate the exponential increase of comparators in a flash converter. The proposed structure is designed to improve the system bandwidth degradation by replacing the buffers and resistors of a typical interpolating technique with a pair of transistors. This replacement mitigates the bandwidth degradation problem, which is the main drawback of a typical interpolating A/D converter. With the proposed 4-bit interpolating structure, 3.75 of effective number of bits (ENOB) and 31.52dB of spurious-free dynamic range (SFDR) are achieved at Nyquist frequency of 264MHz with 6.93mW of power consumption. In addition, a 4-bit D/A converter is also designed for the transmitter part of the UWB communication system. The proposed D/A converter is based on the charge division reference generator topology due to its full swing output range, which is attractive for low-voltage operation. To avoid the degradation of system bandwidth, resistors are replaced with capacitors in the charge division topology. With the proposed D/A converter, 0.26 LSB of DNL and 0.06 LSB of INL is obtained for the minimum input data stream width of 1.88ns. A 130 Âµm Ã286 Âµm chip area is required for the proposed D/A converter with 19.04mW of power consumption. The proposed A/D and D/A converter are realized in a TSMC 0.18 Âµm CMOS process with a 1.8 supply voltage for the 528MHz system frequency.

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Shu, Yun-Shiang. "Background digital calibration techniques for high-speed, high resolution analog-to-digital data converters." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2008. http://wwwlib.umi.com/cr/ucsd/fullcit?p3289085.

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Thesis (Ph. D.)--University of California, San Diego, 2008.
Title from first page of PDF file (viewed Feb. 5, 2008). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 106-111).

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Tang, Tze Kwan Andrew. "Accuracy enhancement techniques for high speed A/D and D/A converters." Thesis, Imperial College London, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.266583.

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Sundström, Timmy. "Design of High-Speed Analog-to-Digital Converters using Low-Accuracy Components." Doctoral thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-67624.

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The scaling of CMOS technologies has increased the performance of general purpose processors and DSPs. However, analog circuits designed in the same process have not been able to utilize the scaling to the same extent, suffering from reduced voltage headroom and reduced analog gain. Integration of the system components on the same die means that the analog-to-digital converters (ADCs) needs to be implemented in the newest technologies in order to utilize the digital capabilities at these process nodes. To design efficient ADCs in nanoscale CMOS technologies, there is a need to both understand the physical limitations as well as to develop new architectures and circuits that take full advantage of the potential that process has to offer. As the technology scales to smaller feature sizes, the possible sample-rate of ADCs can be increased. This thesis explores the design of high-speed ADCs and investigates architectural and circuit concepts that address the problems associated with lower supply voltage and analog gain. The power dissipation of Nyquist rate ADCs is investigated and lower bounds, as set by both thermal noise and minimum feature sizes are formulated. Utilizing the increasing digital performance, low-accuracy analog components can be used, assisted by digital correction or calibration, which leads to a reduction in power dissipation. Through the aid of new techniques and concepts, the power dissipation of low-to-medium resolution ADCs benefit from going to more modern CMOS processes, which is supported by both theory and published results. New architectures and circuits of high-speed ADCs are explored in test-chips based on the flash and pipeline ADC architectures. Two flash ADCs were developed, both based on a new comparator that suppresses common-mode kick-back by a factor of 6x compared to conventional topologies. The first flash ADC is based on redundancy in the comparator array, allowing the use of low-accuracy, small-sized and low-power comparators to achieve an overall low-power solution. The flash ADC achieves 4.0 effective bits at 2.5 GS/s while dissipating 30 mW of power. The second Flash ADC further explores the use of low-accuracy components, relying on the process variations to generate the reference levels based on the mismatch induced comparator offsets. The reference-free ADC achieves a resolution of 3.7 bits at 1.5 GS/s and dissipates 23 mW of power, showing that process variations does not necessarily has to be seen as detrimental to circuit performance, but rather can be seen as a source of diversity. In two implemented pipeline ADCs, the potential of very high sample-rates and energy efficiency is explored. The first pipeline ADC utilizes a new high-speed currentmode amplifier in open-loop configuration in order to reach a sample-rate of 2.4 GS/s in a single-channel pipeline ADC, a speed which is significantly faster than previous stateof-the-art The ADC achieved above 4.7 bits throughout the Nyquist range while dissipating 318 mW. The second pipeline ADC relies on an inverter-based amplifier, used in switched-capacitor feedback in order to keep the amplifier biased at a poweroptimal point. The amplifier uses asymmetrically biased transistors in order to better match the p- and n-type transistors, which increases linearity and allows for fully symmetrical layout. Operating at 1.0 GS/s, the effective resolution of the ADC was 7.5 bits and the power dissipation was 73 mW. This shows that it is possible to achieve low power dissipation while maintaining both high sample-rates and medium resolution.

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Safi-Harab, Mouna. "Low-power low-voltage high-speed delta-sigma analog-to-digital converters." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79258.

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The increasingly stringent requirements of today's communication systems and portable devices are imposing two challenges on the design of Analog-to-Digital Converters (ADC) and delta-sigma modulators (DeltaSigmaM) architecture in particular.
The first is the extension of the input frequency range to include applications where the input bandwidth exceeds the 1 MHz range.
This challenge in extending the operational speed of DeltaSigmaM is further rendered more complicated by the ever shrinking transistor dimension. As predicted by the Semiconductor Industry Association (SIA) Roadmap for CMOS technology, the transistor dimension will reach 0.05 mum in 2011. With this dramatic shrink in the transistor length, and as a result in the supply voltage, device modelling becomes ambiguous and circuit non-idealities more pronounced. The design of the main analog building blocks that minimize the time-to-market is therefore becoming very complicated.
These two issues will be addressed in this thesis, namely a new design method that will minimize the design cycle of delta-sigma analog-to-digital converters (DeltaSigma ADCs) intended for high-speed applications. This method will be demonstrated efficient in the implementation of two state-of-the-art modulators in terms of performance using a widely adopted figure of merit.
The validity of the top-down design methodology was verified through the fabrication of two prototype integrated circuits (ICs), both in TSMC 0.18 mum CMOS technology. In the first chip, a single-bit, fourth-order DeltaSigma ADC was implemented achieving more than 12-bit resolution. The second chip further validated the methodology to include higher resolution, in the range of 13 bits, multi-bit DeltaSigma ADCs. The experimental results from both prototype ICs closely mimic the system-level behavior of the designed modulator.

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Chen, Po-Hsin. "Analysis and design of high-speed A/D converters in SiGe technology." College Park, Md.: University of Maryland, 2007. http://hdl.handle.net/1903/7653.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2007.
Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

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Sadeghifar, Mohammad Reza. "On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters." Licentiate thesis, Linköpings universitet, Elektroniska Kretsar och System, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-114274.

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High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency up-conversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element. In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatory pulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work. ΣΔ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal’s number of bits, still maintain the same resolution. By utilizing the ΣΔ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing ΣΔ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the ΣΔ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement. Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with ΣΔ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only two output levels available in the DAC, the static transfer function, regardless of the mismatch errors, is always given by a straight line. In this work, the design of SDFIR filter is done through an optimization procedure where the ΣΔ noise transfer function is also taken into account. Different constraints are defined for different applications in formulation of the SDFIR optimization problem. For a given radio transmitter application the objective function can be defined as, e.g., the hardware cost for SDFIR implementation while the constraint can be set to fulfill the radio transmitter spectral emission mask.

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Katyal, Vipul. "Low power high speed and high accuracy design methodologies for pipeline Analog-to-Digital Converters." [Ames, Iowa : Iowa State University], 2008.

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Lau, Yanlok Charlotte 1979. "A high-speed cascaded folding and interpolating A/D converter." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/29683.

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Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
Includes bibliographical references (p. 85-86).
The folding and interpolating technique has been introduced to CMOS analog-to- digital converter (ADC) in the 1980's. It has successfully reduced the number of comparators required while preserving the benefits of a flash ADC. However, similar to flash ADC, folding and interpolating ADC is also limited to low resolution, due to its complication in the folding operation. Cascaded folding and interpolating architecture is then adopted to alleviate the problem. The design of a 10-bit, 55MSPS ADC is presented to illustrate the merits of the architecture. Data conversion is conducted in two parallel blocks, the MSB and LSB sections. The MSB section is responsible for computing the four MSBs while the LSB section computes the remaining six LSBs. The folding and interpolation preprocessing, completed in three cascaded stages, is employed in the LSB section. The circuit functions are designed in 0.35[mu]m CMOS process with a 3.3V supply. The analog circuitry dissipates 54m W while achieving < 1 /2 LSB DNL performance in simulation.
by Yanlok Charlotte Lau.
M.Eng.

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Zhong, Jian Yu. "Design of high-speed power-efficient SAR-type ADCs." Thesis, University of Macau, 2017. http://umaclib3.umac.mo/record=b3691882.

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Balasubramanian, Sidharth. "STUDIES ON HIGH-SPEED DIGITAL-TO-ANALOG CONVERSION." The Ohio State University, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=osu1376333781.

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Ren, Saiyu Dr. "BROAD BANDWIDTH HIGH RESOLUTION ANALOG TO DIGITAL CONVERTERS: THEORY, ARCHITECTURE AND IMPLEMENTATION." Wright State University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=wright1205948819.

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Swindlehurst, Eric Lee. "High-Speed and Low-Power Techniques for Successive-Approximation-Register Analog-to-Digital Converters." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8923.

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Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power efficiency of the SAR architecture and demonstrates them in a low-power 10-GHz SAR ADC suitable for broadband wireless communications. The proposed 8-bit, 10-GHz, 8× time-interleaved SAR ADC utilizes a constant-matching DAC with symmetrically grouped unit finger capacitors to maximize speed by reducing the total DAC capacitance to 32 fF and minimizing the bottom plate parasitic capacitance. The capacitance reduction also saves power as both the DAC size and the driving logic size are reduced. An optimized asynchronous comparator loop and smaller driver logic push the single channel speed of the SAR ADC to 1.25 GHz, thus minimizing the total number of timeinterleaved channels to 8 to reach 10 GHz. A dual-path bootstrapped switch improves the spurious-free dynamic range (SFDR) of the sampling by creating an auxiliary path to drive the non-linear N-well capacitance apart from the main signal path. Using these techniques, the ADC achieves a measured signal-to-noise-and-distortion ratio (SNDR) and SFDR of 36.9 dB and 59 dB, respectively with a Nyquist input while consuming 21 mW of power. The ADC demonstrates a record-breaking figure-of-merit of 37 fJ/conv.-step, which is more than 2× better than the next best published design, among reported ADCs of similar speeds and resolutions.

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Dinc, Huseyin. "A high-speed two-step analog-to-digital converter with an open-loop residue amplifier." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39572.

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It is well known that feedback is a very valuable tool for analog designers to improve linearity, and desensitize various parameters affected by process, temperature and supply variations. However, using strong global feedback limits the operation speed of analog circuits due to stability requirements. The circuits and techniques explored in this research avoid the usage of strong-global-feedback circuits to achieve high conversion rates in a two-stage analog-to-digital converter (ADC). A two-step, 9-bit, complementary-metal-oxide-semiconductor (CMOS) ADC utilizing an open-loop residue-amplifier is demonstrated. A background-calibration technique was proposed to generate the reference voltage to be used in the second stage of the ADC. This technique alleviates the gain variation in the residue amplifier, and allows an open-loop residue amplifier topology. Even though the proposed calibration idea can be extended to multistage topologies, this design was limited to two stages. Further, the ADC exploits a high-performance double-switching frontend sample-and-hold amplifier (SHA). The proposed double-switching SHA architecture results in exceptional hold-mode isolation. Therefore, the SHA maintains the desired linearity performance over the entire Nyquist bandwidth.

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Cha, Han Ju. "Analysis and design of matrix converters for adjustable speed drives and distributed power sources." Diss., Texas A&M University, 2004. http://hdl.handle.net/1969.1/1048.

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Recently, matrix converter has received considerable interest as a viable alternative to the conventional back-to-back PWM (Pulse Width Modulation) converter in the ac/ac conversion. This direct ac/ac converter provides some attractive characteristics such as: inherent four-quadrant operation; absence of bulky dc-link electrolytic capacitors; clean input power characteristics and increased power density. However, industrial application of the converter is still limited because of some practical issues such as common mode voltage effects, high susceptibility to input power disturbances and low voltage transfer ratio. This dissertation proposes several new matrix converter topologies together with control strategies to provide a solution about the above issues. In this dissertation, a new modulation method which reduces the common mode voltage at the matrix converter is first proposed. The new method utilizes the proper zero vector selection and placement within a sampling period and results in the reduction of the common mode voltage, square rms of ripple components of input current and switching losses. Due to the absence of a dc-link, matrix converter powered ac drivers suffer from input voltage disturbances. This dissertation proposes a new ride-through approach to improve robustness for input voltage disturbances. The conventional matrix converter is modified with the addition of ride-through module and the add-on module provides ride-through capability for matrix converter fed adjustable speed drivers. In order to increase the inherent low voltage transfer ratio of the matrix converter, a new three-phase high-frequency link matrix converter is proposed, where a dual bridge matrix converter is modified by adding a high-frequency transformer into dc-link. The new converter provides flexible voltage transfer ratio and galvanic isolation between input and output ac sources. Finally, the matrix converter concept is extended to dc/ac conversion from ac/ac conversion. The new dc/ac direct converter consists of soft switching full bridge dc/dc converter and three phase voltage source inverter without dc link capacitors. Both converters are synchronized for zero current/voltage switching and result in higher efficiency and lower EMI (Electro Magnetic Interference) throughout the whole load range. Analysis, design example and experimental results are detailed for each proposed topology.

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Rahmatian, Farnoosh. "High-speed guided-wave electro-optic modulators and polarization converters in III-V compound semiconductors." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/nq25142.pdf.

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Löwenborg, Per. "Asymmetric filter banks for mitigation of mismatch errors in high-speed analog-to-digital converters /." Linköping : Univ, 2002. http://www.bibl.liu.se/liupubl/disp/disp2002/tek787s.pdf.

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Lim, Han Wei. "FPGA implementation of robust symmetrical number system in high-speed folding analog-to-digital converters." Thesis, Monterey, California. Naval Postgraduate School, 2010. http://hdl.handle.net/10945/5062.

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Approved for public release; distribution is unlimited
Analog-To-Digital Converters (ADCs) are integral building blocks of most sensor and communication systems today. As the need for ADCs with faster conversion speeds and lower power dissipation increases, there is a growing motivation to reduce the number of power-consuming components by employing folding circuits to fold the input analog signal symmetrically prior to quantization by high-speed comparators. These properties of low-power consumption, compactness, high-resolution and fast conversion speeds make folding ADCs an attractive concept to be used for defense applications, such as unmanned systems, direction-finding antenna architectures and system-on-a-chip applications. In this thesis, a prototype of an optical folding ADC was implemented using the Robust Symmetrical Number System (RSNS). The architecture employs a three-modulus (Moduli 7, 8, 9) scheme to preprocess the antenna signal. This thesis focuses on the simulation and hardware implementation of this ADC architecture, including the bank of comparators and the RSNS-to-Binary Conversion within a Field Programmable Gate Array (FPGA), to achieve an eight-bit dynamic range of 133. This is then integrated with the front-end photonics implementation (designed under a separate thesis). Low frequency analyses of the results using a 1-kHz input signal indicate a 5.39 Effective Number of Bits (ENOB), a Signal-to-Noise Ratio plus Distortion (SINAD) of 34.21 dB, and a Total Harmonic Distortion (THD) of -61.68 dB.

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Ritter, Philipp. "Design and optimization of high speed flash analog-to-digital converters in SiGe BiCMOS technologies." Thesis, Lyon, INSA, 2013. http://www.theses.fr/2013ISAL0052.

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Le Convertisseur Analogique Numérique (CAN) est une brique essentielle de la ré- ception et du traitement des données à très haut débit. L’architecture de type "flash" effectue la quantification en comparant simultanément le signal analogique d’entrée à l’ensemble des références du codeur, ce qui en fait, par construction, l’architecture la plus rapide de CAN. Par le passé, cette architecture a démontré des capacités de codage supérieures à 20GS/s dans les conditions de Nyquist. Cependant, cette capac- ité à travailler à très haute vitesse a donné le jour à des réalisations très consommantes (plusieurs Watts) donc peu efficaces énergétiquement. Cette thèse explore différentes approches d’optimisation de l’efficacité énergétique des CAN "flash". Afin de min- imiser la consommation du CAN, il n’y a pas d’Echantillonneur-Bloqueur (EB) en tête du circuit. Les étages d’entrée du codeur sont ainsi exposés à la pleine bande passante du signal, à savoir DC-10GHz. Ceci impose des contraintes très strictes sur la précision temporelle de la détection et de la quantification du signal. L’essentiel de cette thèse est donc concentré sur l’analyse des effets hautes frèquences impactant la conception des éléments frontaux du CAN. La validité et l’efficacité des méthodes présentées sont démontrées par des mesures autour d’un CAN 6 bit 20 GS/s. En em- pruntant les techniques de conception des circuits ultra-rapides et en exploitant le po- tentiel haute-fréquence de la technologie à l’état de l’art SiGe BiCMOS, un circuit complètement analogique a ainsi pu être réalisé. Ce CAN est mono-voie et n’a besoin d’aucune calibration ou correction, ni d’assistance digitale. Avec à peine 1W, ce cir- cuit atteint un record d’efficacité énergétique dans l’état de l’art des CAN rapides non entrelacés
High speed Analog-to-Digital Converters (ADC) are essential building blocks for the reception and processing in high data rate reception circuits. The flash ADC archi- tecture performs the digitization by comparing the analog input signal to all refer- ence levels of the quantization range simultaneously and is thus the fastest architecture available. In the past the flash architecture has been employed successfully to digitize signals at Nyquist rates beyond 20 GS/s. However the inherent high speed operation has led to power consumptions of several watts and hence to poor energy efficien- cies. This thesis explores approaches to optimize the energy efficiency of flash ADCs. In particular, no dedicated track-and-hold stage is used at the high speed data input. This imposes very stringent requirements on the timing accuracy and level accuracy in the high speed signal distribution to the comparators. The comparators need to ex- hibit a very high speed capability to correctly perform the quantization of the signal against the reference levels. The main focus of this thesis is hence the investigation of design relevant high frequency effects in the analog ADC frontend, such as the bandwidth requirement of overdriven comparators, the data signal distribution over a passive transmission line tree and the dynamic linearity of emitter followers. The correctness and efficacy of the presented methods is demonstrated by measurement results of a 6 bit 20 GS/s Nyquist rate flash ADC fabricated within the context of this work. The demonstrator ADC operates without time interleaving, no calibration or correction whatsoever is needed. By employing design techniques borrowed from high speed analog circuits engineering and by exhausting the high speed potential of a state-of-the-art SiGe BiCMOS production technology, a flash ADC with a record energy efficiency could be realized

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McDonald, Alasdair Stewart. "Structural analysis of low speed, high torque electrical generators for direct drive renewable energy converters." Thesis, University of Edinburgh, 2008. http://hdl.handle.net/1842/12608.

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Direct drive renewable energy converters provide a low speed, high torque input to the electrical generator. As a result these generators must be larger than their high speed counterparts. Because of this size and the large airgap-closing force, the structural design must be stiff and robust. This typically results in heavy generators, with structural (‘inactive’) material dominating the electromagnetically ‘active’ material. Design tools are set out, validated and used to model the inactive material in high torque axial-flux and radial-flux type machines. Simple optimisations on generator aspect ratios are carried out to find lighter designs. Axial-flux and radial-flux permanent magnet synchronous machines for wind turbines are compared in terms of mass and a cost criterion, with and without the inactive mass. Some machines are designed in such a way that the normal force is nonexistent or significantly smaller than in conventional electrical generators. The design and modelling of a speed air-cored permanent magnetic machine is described. Discussions and conclusions highlight impacts on direct drive design philosophy.

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Jalali, Farahani Bahar. "Adaptive digital calibration techniques for high speed, high resolution SIGMA DELTA ADCs for broadband wireless applications." Columbus, Ohio : Ohio State University, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1133192371.

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Bair, Shyh-Shyong. "A high speed microprocessor-based data acquisition system." Ohio : Ohio University, 1985. http://www.ohiolink.edu/etd/view.cgi?ohiou1183748292.

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Kim, Seokjin. "High-speed analog-to-digital converters for modern satellite receivers design verification test and sensitivity analysis /." College Park, Md.: University of Maryland, 2008. http://hdl.handle.net/1903/7864.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2008.
Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

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Chen, Zheng. "Very large scaled integrated circuit (VLSI) implementation of a high-speed delta-sigma analog to digital converter." Ohio : Ohio University, 1997. http://www.ohiolink.edu/etd/view.cgi?ohiou1177445405.

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Zhao, Shaohua. "The design of transmitter/receiver and high speed analog to digital converters in wireless communication systems : a convex programming approach /." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B41290525.

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Wei, He Gong. "High speed power/area optimized multi-bit/cycle SAR ADCs." Thesis, University of Macau, 2011. http://umaclib3.umac.mo/record=b2489844.

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Jalili, Kamran. "Investigation of Control Concepts for High-Speed Induction Machine Drives and Grid Side Pulse-Width Modulation Voltage Source Converters." Doctoral thesis, Technische Universität Dresden, 2008. https://tud.qucosa.de/id/qucosa%3A25053.

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Control of a low voltage ac/dc/ac converter for high-speed induction machine drive applications has been investigated. Such a configuration can be applied, for example, in microturbines and high-speed spindles. Scalar control is usually applied for the control of high-speed drives especially in the case of very high-speed drives. Indirect rotor-flux-oriented control and direct torque control are designed and compared for the control of an exemplary high-speed induction machine drive. The 2L VSC is the most widely applied converter for high-speed drives. However, the 3L-NPC VSC is an attractive topology if drastically increased switching frequencies are required. A detailed comparison between a 2L VSC and a 3L-NPC VSC as the machine side converter of the exemplary high-speed induction machine drive is carried out. Voltage-oriented control is applied for the control of the grid side PWM active front end converter. In several industrial applications PWM active front end converters commonly operate in parallel to thyristor converter fed dc drives. Behavior of the voltage-oriented controlled active front end converter with L-filter in the presence of a parallel thyristor converter is investigated. The design of the LCL-filter components according to the given maximum grid current harmonics (e.g. IEEE-519) is a complex task. So far a precise and clear design procedure has not been presented. A new procedure to design the grid side filter (L- and LCL-filter) is proposed using the analytical expression of the converter voltage harmonics based on Bessel functions to achieve the compliance with the grid standard of IEEE-519. Voltage-oriented control with active damping is used to control the active front end converter with LCL-filter. A simple method is proposed to design the required lead-lag compensator in the active damping loop.

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Jalili, Kamran. "Investigation of control concepts for high speed induction machine drives and grid side pulse width modulation voltage source converters." Doctoral thesis, Berlin mbv, 2009. http://d-nb.info/995880107/04.

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Powell, I. A. (Ian Allan). "The design and simulation of a superconductive, COSL compatible comparator and high-speed superconductive analog-to-digital converter." Thesis, Stellenbosch : Stellenbosch University, 2004. http://hdl.handle.net/10019.1/53765.

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Thesis (PhD)--University of Stellenbosch, 2004.
ENGLISH ABSTRACT: Analog-to-digital converters (ADCs) are an integral part of the interface between the analog and digital realms. This dissertation presents the design and simulation of a Complementary Output Switching-Logic (COSL) compatible, voltage state, switching logic comparator and a flash ADC for high speed applications with multi-GHz input bandwidth. Josephson technology and the COSL family of gates were utilized for this purpose. A detailed design for the switching logic comparator is first provided. The design is verified with simulations to obtain a functional comparator. The comparator is then optimized utilizing an optimization tool developed using the scripting facilities of WRSpice. Incorporated in this tool is a Monte Carlo capability to randomly vary the component values according to Gaussian distributions, and trimming facilities to be able to trim a non-functional comparator to restore functionality. The design component values are then optimized by maximizing the yield of a comparator. The optimized comparator is incorporated into the construction of a4-bit quantizer of an ADC. The output from the quantizer section yields a switching-logic Gray-code output. A Gray-to- Binary converter is designed with COSL gates to convert the Gray output from the quantizer into Binary code for further processing. The functionality, linearity, maximum input bandwidth and dynamic range of the 4-bit ADC is verified by simulation. A number of special input waveforms are used for this purpose. The performance of the comparator and the 4-bit ADC is also evaluated with thermal noise incorporated into simulation. Beat frequency simulations and Fourier spectra were also used in the evaluation of the ADC performance. A fully functional 4-bit ADC, with a maximum input bandwidth of 10 GHz for a clock speed of 20 GHz was achieved through simulations. Beat frequency simulations revealed that the comparators have an input bandwidth greater than 19 GHz with sufficient dynamic range for an ADC of greater than 6 bits of resolution. Due to the fact that the aperture time for the ADC is dependant on the rise time of the sampling pulse and not the width of the pulse, a much smaller aperture time is obtained which directly translates to higher input bandwidth. Finally, a layout of a 4-bit sampler circuit was done according to the Hypres manufacturing process to enable the high-speed testing of the comparator circuits.
AFRIKAANSE OPSOMMING: Analoog-na-Digitale Omsetters (ADOs) vorm 'n integrale deel van die koppelvlak tussen die analoog en digitale wêrelde. Hiedie proefskrif stel die ontwerp en simulasie van 'n Komplementêre Uittree Geskakelde Logika (COSL) aanpasbare, spanningstoestand, geskakelde logika vergelyker en ADO bekend. Hierdie ADO kan vir hoë spoed toepassings waar multi-GHz intree-bandwydte benodig word, aangewend word. Josephson tegnologie en die Komplementêre Uittree Geskakelde Logika (COSL) familie van hekke word vir hierdie doel gebruik. Die volledige ontwerp vir die geskakelde logika vergelyker word eerstens gegee. Die ontwerp word met behulp van simulasies bevestig om sodoende 'n ten volle funksionele vergelyker te verkry. Die vergelyker word verder geëptimeer deur middel van 'n proses wat met behulp van programmering in WRSpice ontwikkel is. Hierdie optimeringsproses sluit 'n Monte Carlo proses in wat die komponentwaardes van die vergelyker onwillekeurig volgens 'n Gaussiese verspreiding verander, sowel as 'n verstellingsmeganisme waarmee 'n nie-funksionerende vergelyker verstel kan word totdat dit weer ten volle funksioneer. Die komponentwaardes word dan geëptimeer vir maksimale opbrengs van 'n vergelyker. Die geëptimeerde vergelyker word gebruik in die konstruksie van 'n 4-bis kwantifiseerder vir 'n ADO. Die uittree van die 4-bis kwantifiseerder is in Gray kode. 'n Gray-na-Binêre kode omsetter word vir hierdie doelontwerp deur van COSL hekke gebruik te maak. Die volle ADO word voorts gesimuleer om die funksionalitet, lineariteit, maksimum intreebandwydte en dinamiese bereik te verifieer. 'n Verskeidenheid van intreeseine is vir hierdie doel gebruik. Die vergelyker en die 4-bis ADO is ook gesimuleer met termiese ruis om die effek daarvan te bepaal. Fourier spektra en ''verskilfrekwensie'' (Beat Frequency) simulasies word ook gebruik in die evaluering van die vergelyker en die ADO. Die korrekte werking van 'n 4-bis ADO met intreebandwydte van 10 GHz met 'n klokspoed van 20 GHz is deur simulasie bevestig. Verskilfrekwensie simulasies dui aan dat die vergelykers 'n intreebandwydte van groter as 19 GHz het, met voldoende dinamiese bereik vir 6 bis resolusie. Aangesien die vergelykers se venstertydperk bepaal word deur die stygende helling van die monsterpuls en nie deur die pulswydte nie, maak dit voorsiening vir 'n baie klein venstertydperk. 'n Klein venstertydperk is essensieel vir 'n hoë intreebandwydte. 'n Uitleg van 'n 4-bis vergelyker stadium is gedoen vir die Hypres vervaardigingsproses om die vergelyker teen hoë spoed te kan toets.

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Zhao, Shaohua, and 趙少華. "The design of transmitter/receiver and high speed analog to digital converters in wireless communication systems: a convex programming approach." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2008. http://hub.hku.hk/bib/B41290525.

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Kotte, Hari Babu. "High Speed (MHz) Switch Mode Power Supplies (SMPS) using Coreless PCB Transformer Technology." Licentiate thesis, Mittuniversitetet, Institutionen för informationsteknologi och medier, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-13964.

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The most essential unit required for all the electronic devices is the Power Supply Unit (PSU). The main objective of power supply designers is to reduce the size, cost and weight, and to increase the power density of the converter. There is also a requirement to have a lower loss in the circuit and hence in the improvement of energy efficiency of the converter circuit. Operating the converter circuits at higher switching frequencies reduces the size of the passive components such as transformers, inductors, and capacitors, which results in a compact size, weight, and increased power density of the converter. At present the switching frequency of the converter circuit is limited due to the increased switching losses in the existing semiconductor devices and in the magnetic area, because of increased hysteresis and eddy current loss in the core based transformer. Based on continuous efforts to improve the new semi conductor materials such as GaN/SiC and with recently developed high frequency multi-layered coreless PCB step down power transformers, it is now feasible to design ultra-low profile, high power density isolated DC/DC and AC/DC power converters. This thesis is focussed on the design, analysis and evaluation of the converters operating in the MHz frequency region with the latest semi conductor devices and multi-layered coreless PCB step-down power and signal transformers. An isolated flyback DC-DC converter operated in the MHz frequency with multi-layered coreless PCB step down 2:1 power transformer has been designed and evaluated. Soft switching techniques have been incorporated in order to reduce the switching loss of the circuit. The flyback converter has been successfully tested up to a power level of 10W, in the switching frequency range of 2.7-4 MHz. The energy efficiency of the quasi resonant flyback converter was found to be in the range of 72-84% under zero voltage switching conditions (ZVS). The output voltage of the converter was regulated by implementing the constant off-time frequency modulation technique. Because of the theoretical limitations of the Si material MOSFETs, new materials such as GaN and SiC are being introduced into the market and these are showing promising results in the converter circuits as described in this thesis. Comparative parameters of the semi conductor materials such as the vi energy band gap, field strengths and figure of merit have been discussed. In this case, the comparison of an existing Si MOSFET with that of a GaN MOSFET has been evaluated using a multi-layered coreless PCB step-down power transformer for the given input/output specifications of the flyback converter circuit. It has been determined that the energy efficiency of the 45 to 15V regulated converter using GaN was improved by 8-10% compared to the converter using the Si MOSFET due to the gate drive power consumption, lower conduction losses and improved rise/fall times of the switch. For some of the AC/DC and DC/DC applications such as laptop adapters, set-top-box, and telecom applications, high voltage power MOSFETs used in converter circuits possess higher gate charges as compared to that of the low voltage rating MOSFETs. In addition, by operating them at higher switching frequencies, the gate drive power consumption, which is a function of frequency, increases. The switching speeds are also reduced due to the increased capacitance. In order to minimize this gate drive power consumption and to increase the frequency of the converter, a cascode flyback converter was built up using a multi-layered coreless PCB transformer and this was then evaluated. Both simulation and experimental results have shown that with the assistance of the cascode flyback converter the switching speeds of the converter were increased including the significant improvement in the energy efficiency compared to that of the single switch flyback converter. In order to further maximize the utilization of the transformer, to reduce the voltage stress on MOSFETs and to obtain the maximum power density from the power converter, double ended topologies were chosen. For this purpose, a gate drive circuitry utilising the multi-layered coreless PCB gate drive transformer was designed and evaluated in both a Half-bridge and a Series resonant converter. It was found that the gate drive power consumption using this transformer was less than 0.8W for the frequency range of 1.5-3.5MHz. In addition, by using this gate drive circuitry, the maximum energy efficiency of the series resonant converter was found to be 86.5% with an output power of 36.5W.

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Wang, Xian. "Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53521.

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Low-cost test and tuning methods for difficult-to-measure specifications are presented in this research from the following perspectives: 1)"Safe" test and self-tuning for power converters: To avoid the risk of device under test (DUT) damage during conventional load/line regulation measurement on power converter, a "safe" alternate test structure is developed where the power converter (boost/buck converter) is placed in a different mode of operation during alternative test (light switching load) as opposed to standard test (heavy switching load) to prevent damage to the DUT during manufacturing test. Based on the alternative test structure, self-tuning methods for both boost and buck converters are also developed in this thesis. In addition, to make these test structures suitable for on-chip built-in self-test (BIST) application, a special sensing circuit has been designed and implemented. Stability analysis filters and appropriate models are also implemented to predict the DUT’s electrical stability condition during test and to further predict the values of tuning knobs needed for the tuning process. 2) High bandwidth RF signal generation: Up-convertion has been widely used in high frequency RF signal generation but mixer nonlinearity results in signal distortion that is difficult to eliminate with such methods. To address this problem, a framework for low-cost high-fidelity wideband RF signal generation is developed in this thesis. Depending on the band-limited target waveform, the input data for two interleaved DACs (digital-to-analog converters) system is optimized by a matrix-model-based algorithm in such a way that it minimizes the distortion between one of its image replicas in the frequency domain and the target RF waveform within a specified signal bandwidth. The approach is used to demonstrate how interferers with specified frequency characteristics can be synthesized at low cost for interference testing of RF communications systems. The frameworks presented in this thesis have a significant impact in enabling low-cost test and tuning of difficult-to-measure device specifications for power converter and high-speed devices.

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Krune, Edgar Verfasser], Klaus [Akademischer Betreuer] Petermann, Franz X. [Gutachter] [Kärtner, Lars [Gutachter] Zimmermann, and Klaus [Gutachter] Petermann. "Performance analysis of low jitter high-speed photonic analog-to-digital converters in silicon photonics / Edgar Krune ; Gutachter: Franz X. Kärtner, Lars Zimmermann, Klaus Petermann ; Betreuer: Klaus Petermann." Berlin : Technische Universität Berlin, 2017. http://d-nb.info/1155929489/34.

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Dissertations / Theses on the topic 'High speed converters'

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