Relevant bibliographies by topics / High speed converters

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'High speed converters'

Author: Grafiati
Published: 10 January 2023
Last updated: 28 January 2023

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Journal articles on the topic "High speed converters"

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GHARBIYA, AHMED, TREVOR C. CALDWELL, and D. A. JOHNS. "HIGH-SPEED OVERSAMPLING ANALOG-TO-DIGITAL CONVERTERS." International Journal of High Speed Electronics and Systems 15, no. 02 (June 2005): 297–317. http://dx.doi.org/10.1142/s0129156405003211.

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This paper is mainly tutorial in nature and discusses architectures for oversampling converters with a particular emphasis on those which are well suited for high frequency input signal bandwidths. The first part of the paper looks at various architectures for discrete-time modulators and looks at their performance when attempting high speed operation. The second part of this paper presents some recent advancements in time-interleaved oversampling converters. The next section describes the design and challenges in continuous-time modulators. Finally, conclusions are made and a brief summary of the recent state of the art of high-speed converters is presented.
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Maloberti, F. "High-speed data converters for communication systems." IEEE Circuits and Systems Magazine 1, no. 1 (2001): 26–36. http://dx.doi.org/10.1109/7384.928307.

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Foster, M. P., H. I. Sewell, C. M. Bingham, D. A. Stone, D. Hente, and D. Howe. "High-speed analysis of resonant power converters." IEE Proceedings - Electric Power Applications 150, no. 1 (2003): 62. http://dx.doi.org/10.1049/ip-epa:20030057.

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Hsu, H. "High speed A/D converters: understanding data converters through spice [Book Review]." IEEE Circuits and Devices Magazine 18, no. 1 (January 2002): 26. http://dx.doi.org/10.1109/mcd.2002.981297.

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Jain, Ankesh, and Shanthi Pavan. "Characterization Techniques for High Speed Oversampled Data Converters." IEEE Transactions on Circuits and Systems I: Regular Papers 61, no. 5 (May 2014): 1313–20. http://dx.doi.org/10.1109/tcsi.2014.2309895.

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Liberali, Valentino, Simona Brigati, Fabrizio Francesconi, and Franco Maloberti. "Progress in high-speed and high-resolution CMOS data converters." Microelectronics Reliability 37, no. 9 (September 1997): 1411–20. http://dx.doi.org/10.1016/s0026-2714(97)00013-9.

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Shukla, Mohit. "A 13.42ps Resolution, Low-Power Time-to-Digital Converter and 0.519fJ Energy-Efficient Novel Voltage-to-Time Converter for High-Speed Time-Based ADC Application." Journal of University of Shanghai for Science and Technology 24, no. 02 (February 19, 2022): 1020–30. http://dx.doi.org/10.51201/jusst/21/10878.

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Voltage domain ADC architectures require high gain and high bandwidth opamps to amplify the signal for successive stages. The opamp design gets a bit challenging due to noise, small gain and lower overdrive voltage. Due to these limitations, the inclination shifted towards high-speed converters which don’t require opamps. Time based Analog to Digital Converters (TBADC) is one such category of circuits. TBADCs are constituted from VTC followed by TDC with an encoder in the end. This work is concerned around the design of a high-resolution time to digital converter (TDC) and proposing a novel high-speed, low power consuming voltage to time converter (VTC) circuit. Both the circuits were implemented in Cadence Virtuoso EDA tool version 6.1.7 and Spectre was employed for running the simulations. TDC circuits had resolution of 13.425 ps and consume power of 1.873 μW. Process corner analysis and Monte Carlo analysis were performed on VTC design to determine worst possible deviations in performance. The proposed VTC exhibited delay of 23.79 ps with power consumption of 21.83 μW at 1 Volt. The presented TDC and VTC circuits can be used to design high-speed time-based Analog to Digital Converters.
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Bruha, Martin, Kai Pietiläinen, and Axel Rauber. "High Speed Electrical Drives – Perspective of VFD Manufacturer." E3S Web of Conferences 178 (2020): 01006. http://dx.doi.org/10.1051/e3sconf/202017801006.

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This paper deals with high-speed electrical drives utilizing power electronic converters (commonly abbreviated as ASD, VFD or VSD). Existing solutions vary mainly on the motor side while the power electronic converter is very similar for all cases. Various advantages as well as technical challenges are discussed and illustrated. At certain stages comparisons between conventional and high-speed drives are made. The paper summarizes the experience of a VFD manufacturer based on state of the art technology in medium voltage and multi-megawatt power range. The authors believe that main complexity around high-speed drives is the motor design while the VFD requires only small adaptations or can sometimes be used directly without any modifications of standard design. The technology readiness is evaluated to be on a medium to high level.
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Takahashi, Tomomi, Takashi Oshima, and Taizo Yamawaki. "Novel Digitally Assisted High-Speed High-Resolution Analog-to-Digital Converters." Journal of The Institute of Image Information and Television Engineers 64, no. 2 (2010): 241–43. http://dx.doi.org/10.3169/itej.64.241.

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Boni, A., and C. Morandi. "Harmonic distortion in high-speed differential A/D converters." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 45, no. 3 (March 1998): 403–6. http://dx.doi.org/10.1109/82.664250.

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Dissertations / Theses on the topic "High speed converters"

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Sculley, Terry Lee. "Achieving high speed, high precision A/D conversion using nonlinearity correction." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/13424.

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Chan, Kok Lim. "High-speed, high-resolution digital-to-analog converters." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2007. http://wwwlib.umi.com/cr/ucsd/fullcit?p3294746.

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Thesis (Ph. D.)--University of California, San Diego, 2007.
Title from first page of PDF file (viewed March 14, 2008). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references.
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Robinson, Dirk J. "High speed data converter circuits in SI-GE." Pullman, Wash. : Washington State University, 2008. http://www.dissertations.wsu.edu/Dissertations/Fall2008/d_robinson_121008.pdf.

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Thesis (Ph. D.)--Washington State University, December 2008.
Title from PDF title page (viewed on Jan. 15, 2009). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 60-61).
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Hsu, M. S. "Aspects of designing a high speed analog to digital converter /." Title page, contents and abstract only, 1992. http://web4.library.adelaide.edu.au/theses/09ENS/09ensh873.pdf.

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Figueiredo, Michael. "Reference-free high-speed cmos pipeline analog-to-digital converters." Doctoral thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8776.

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Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering of the Faculdade de Ciências e Tecnologia of Universidade Nova de Lisboa
More and more signal processing is being transferred to the digital domain to profit from the technological enhancement of digital circuits. Where technology scaling enhances the capabilities of digital circuits, it degrades the performance of analog circuits. However, it is important to note that the impact that technology scaling has on digital circuits is becoming smaller and smaller, which means that, in nanotechnologies, to enhance energy and area efficiency, we can not simply depend on the benefits of this scaling. Although, a share of the efficiency can be obtained from the technology, new circuit architectures and techniques have to be developed to really push the limits of efficiency. In data converters, more specifically analog-to-digital converters (ADCs), a decision can be made: research energy and area efficient analog circuit techniques and architectures that cope with technological scaling issues, or design algorithms that use digital circuitry to assist the poor analog technological performance. The former option is the premise for the work developed in this thesis. The work reported in this thesis explores various design techniques with the purpose of enhancing the power and area efficiency of building blocks mainly to be used in multiplying digital-to-analog converter based ADCs. Therefore, novel analog techniques are developed for the three main blocks of an MDAC-based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. These techniques include self-biasing and inverter-based design for the flash quantizer and amplifier. Regarding the MDAC, it combines three techniques: unity feedback factor, insensitivity to capacitor mismatch, and current-mode reference shifting. In the second part of this work, the designed amplifier is implemented and experimentally characterized demonstrating its practical feasibility and performance. The final part of this work explores the design and implementation of a medium-low resolution high speed pipeline ADC incorporating all the developed circuits. Experimental results validate the feasibility of the techniques and demonstrate the attractiveness in terms of power dissipation and reduced area.
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Li, Xiangtao. "High-speed analog-to-digital conversion in SiGe HBT technology." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24652.

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Thesis (Ph.D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Committee Chair: Cressler, John D.; Committee Member: Laskar, Joy; Committee Member: Lee, Chin-Hui; Committee Member: Morley, Thomas; Committee Member: Papapolymerou, John
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Karanicolas, Andrew N. (Andrew Nicholas). "Digital self-calibration techniques for high-accuracy, high speed analog-to-digital converters." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/12010.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
Includes bibliographical references (leaves 219-224).
by Andrew Nicholas Karanicolas.
Ph.D.
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Lu, Dongtian. "High speed CMOS ADC for UWB receiver /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LUD.

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Gupta, Amit Kumar. "Design techniques for low noise and high speed A/D converters." [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1666.

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Sundström, Timmy. "Design of High‐Speed, Low‐Power, Nyquist Analog‐to‐Digital Converters." Licentiate thesis, Linköping University, Linköping University, Electronic Devices, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-51375.

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The scaling of CMOS technologies has increased the performance of general purposeprocessors and DSPs while analog circuits designed in the same process have not been ableto utilize the process scaling to the same extent, suffering from reduced voltage headroom and reduced analog gain. In order to design efficient analog‐to‐digital converters in nanoscale CMOS there is a need to both understand the physical limitations as well as to develop new architectures and circuits that take full advantage of what the process has tooffer.

This thesis explores the power dissipation of Nyquist rate analog‐to‐digital converters andtheir lower bounds, set by both the thermal noise limit and the minimum device and feature sizes offered by the process. The use of digital error correction, which allows for lowaccuracy analog components leads to a power dissipation reduction. Developing the bounds for power dissipation based on this concept, it is seen that the power of low‐to‐medium resolution converters is reduced when going to more modern CMOS processes, something which is supported by published results.

The design of comparators is studied in detail and a new topology is proposed which reduces the kickback by 6x compared to conventional topologies. This comparator is used in two flash ADCs, the first employing redundancy in the comparator array, allowing for the use of small sized, low‐power, low‐accuracy comparators to achieve an overall low‐power solution. The flash ADC achieves 4 effective bits at 2.5 GS/s while dissipating 30 mW of power.

The concept of low‐accuracy components is taken to its edge in the second ADC which oes not include a reference network, instead relying on the process variations to generate the reference levels based on the mismatch induced comparator offsets. The reference‐free ADC achieves a resolution of 3.69 bits at 1.5 GS/s while dissipation 23 mW showing that process variations not necessarily must be seen as detrimental to circuit performance but rather can be seen as a source of diversity.

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Books on the topic "High speed converters"

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High speed A/D converters: Understanding data converters through SPICE. Boston: Kluwer Academic Publishers, 2001.

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Moscovici, Alfi. High speed A/D converters: Understanding data converters through SPICE. Boston, MA: Kluwer Academic Publishers, 2001.

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Moscovici, Alfi. High speed A/D converters: Understanding data converters through SPICE. New York: Kluwer Academic, 2002.

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Demler, Michael J. High-speed analog-to-digital conversion. San Diego: Academic Press, 1991.

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Hitachi Electronic Components (UK) Limited. High speed A/D and D/A converters: Datasheets. 2nd ed. Maidenhead: Hitachi, 1991.

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Li, Weitao, Fule Li, and Zhihua Wang. High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-62012-1.

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1959-, Steyaert Michiel, and Sansen Willy M. C, eds. Static and dynamic performance limitations for high speed D/A converters. Boston: Kluwer Academic Publishers, 2004.

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Waltari, Mikko E. Circuit techniques for low-voltage and high-speed A/D converters. New York: Springer, 2011.

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I, Halonen K. A., ed. Circuit techniques for low-voltage and high-speed A/D converters. Boston: Kluwer Academic Publishers, 2002.

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Bosch, Anne, Michiel Steyaert, and Willy Sansen. Static and Dynamic Performance Limitations for High Speed D/A Converters. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4757-6579-3.

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Book chapters on the topic "High speed converters"

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Uyttenhove, Koen, and Michiel Steyaert. "High-Speed Flash ADCs." In CMOS Telecom Data Converters, 213–40. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3724-0_6.

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Plassche, Rudy. "High-speed A/D converters." In CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 107–203. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3768-4_3.

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Plassche, Rudy. "High-speed D/A converters." In CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 205–35. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3768-4_4.

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Plassche, Rudy. "High-speed A/D converters." In Integrated Analog-To-Digital and Digital-To-Analog Converters, 107–87. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2748-0_4.

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Luis González, José, and Eduard Alarcón. "Current-Steering High-Speed D/A Converters for Communications." In CMOS Telecom Data Converters, 93–148. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3724-0_3.

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Wu, Jieh-Tsorng, Chun-Cheng Huang, and Chung-Yi Wang. "CMOS Ultra-High-Speed Time-Interleaved ADCs." In Nyquist AD Converters, Sensor Interfaces, and Robustness, 73–96. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-4587-6_5.

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Louwsma, Simon, Ed van Tuijl, and Bram Nauta. "Implementation of a High-speed Time-interleaved ADC." In Time-interleaved Analog-to-Digital Converters, 71–124. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-90-481-9716-3_4.

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Mandai, Shingo, and Edoardo Charbon. "High Speed Time-Domain Imaging." In High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing, 299–317. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-07938-7_13.

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Bugeja, Alex R. "High Speed Digital-Analog Converters — The Dynamic Linearity Challenge." In Analog Circuit Design, 211–31. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/0-306-47950-8_11.

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Roovers, Raf. "High Speed CMOS DA Converters for Upstream Cable Applications." In Analog Circuit Design, 171–87. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/0-306-47950-8_9.

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Conference papers on the topic "High speed converters"

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Naviasky, Eric, and Mohammad Ranjbar. "High-speed data converters." In 2012 IEEE Custom Integrated Circuits Conference - CICC 2012. IEEE, 2012. http://dx.doi.org/10.1109/cicc.2012.6330606.

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Van de Plassche, R. "High-speed Converters for Telecom Applications." In 32nd European Solid-State Device Research Conference. IEEE, 2002. http://dx.doi.org/10.1109/essderc.2002.194866.

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Venediktov, M. D., Yu A. Krutyakov, and M. I. Plotnikov. "High-sensitivity converters of a TV type." In Twenty-Third International Congress on High-Speed Photography and Photonics, edited by Valentina P. Degtyareva, Mikhail A. Monastyrski, Mikhail Y. Schelev, and Alexander V. Smirnov. SPIE, 1999. http://dx.doi.org/10.1117/12.350478.

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Останин, S. Ostanin, Миляев, and I. Milyaev. "Nano-magnetic materials for rotors of high-speed and of over-high-speed electromechanical energy converters." In XXIV International Conference. Москва: Infra-m, 2016. http://dx.doi.org/10.12737/23122.

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The "Nano-magnetic materials for rotors of high-speed and of over-high-speed electromechanical energy converters" are developed issues of choice and of research of magnetically hard materials and alloys for rotors of the high-speed and of the ultra high-speed hysteretic electromechanical energy converters; impact of heat treatment modes, hot plastic deformation and sintering temperature on the magnetic, hysteretic properties and characteristics of the base class´s alloys.
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Wu, Jieh-Tsorng, and Seung-Tak Ryu. "Session 22 overview: High-speed data converters: Data converters subcommittee." In 2014 IEEE International Solid- State Circuits Conference (ISSCC). IEEE, 2014. http://dx.doi.org/10.1109/isscc.2014.6757568.

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"Session 4 Overview High-speed data converters." In 2009 IEEE International Solid-State Circuits Conference (ISSCC 2009). IEEE, 2009. http://dx.doi.org/10.1109/isscc.2009.4977313.

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"Session 12 - High speed A/D converters." In 2008 IEEE Custom Integrated Circuits Conference. IEEE, 2008. http://dx.doi.org/10.1109/cicc.2008.4672078.

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Dedic, Ian. "High-speed CMOS DSP and data converters." In Optical Fiber Communication Conference. Washington, D.C.: OSA, 2011. http://dx.doi.org/10.1364/ofc.2011.otun1.

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Sobczyk, T. J., and T. Sienko. "Matrix converters control for high speed generators." In International Electric Machines and Drives Conference. IEEE, 2005. http://dx.doi.org/10.1109/iemdc.2005.195990.

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Murmann, Boris, and Tetsuya Iizuka. "Session 26 overview: High-speed data converters." In 2013 IEEE International Solid-State Circuits Conference - (ISSCC). IEEE, 2013. http://dx.doi.org/10.1109/isscc.2013.6487856.

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Reports on the topic "High speed converters"

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Fathimulla, Ayub. Ultra-High-Speed A/D Converter Based on Resonant-Tunneling Diodes. Fort Belvoir, VA: Defense Technical Information Center, January 1995. http://dx.doi.org/10.21236/ada298951.

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Gardner, David W. An Ultra-High Speed Incoherent-to-Coherent Converter for Optical Computing. Fort Belvoir, VA: Defense Technical Information Center, February 1995. http://dx.doi.org/10.21236/ada301033.

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Ruvinsky, Alicia, Timothy Garton, Daniel Chausse, Rajeev Agrawal, Harland Yu, and Ernest Miller. Accelerating the tactical decision process with High-Performance Computing (HPC) on the edge : motivation, framework, and use cases. Engineer Research and Development Center (U.S.), September 2021. http://dx.doi.org/10.21079/11681/42169.

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Managing the ever-growing volume and velocity of data across the battlefield is a critical problem for warfighters. Solving this problem will require a fundamental change in how battlefield analyses are performed. A new approach to making decisions on the battlefield will eliminate data transport delays by moving the analytical capabilities closer to data sources. Decision cycles depend on the speed at which data can be captured and converted to actionable information for decision making. Real-time situational awareness is achieved by locating computational assets at the tactical edge. Accelerating the tactical decision process leverages capabilities in three technology areas: (1) High-Performance Computing (HPC), (2) Machine Learning (ML), and (3) Internet of Things (IoT). Exploiting these areas can reduce network traffic and shorten the time required to transform data into actionable information. Faster decision cycles may revolutionize battlefield operations. Presented is an overview of an artificial intelligence (AI) system design for near-real-time analytics in a tactical operational environment executing on co-located, mobile HPC hardware. The report contains the following sections, (1) an introduction describing motivation, background, and state of technology, (2) descriptions of tactical decision process leveraging HPC problem definition and use case, and (3) HPC tactical data analytics framework design enabling data to decisions.
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