Journal articles: 'High speed ADC/DAC'

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Azarov, O. D., S. V. Bohomolov, and O. Y. Stahov. "MULTICHANNEL SPEED ADC-DAC SYSTEM BASED ON HIGH-LINE CURRENT-CURRENT CONVERTERS." Information technology and computer engineering 50, no. 1 (2021): 69–79. http://dx.doi.org/10.31649/1999-9941-2021-50-1-69-79.

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Cheng, Li, Jiao Xu, Yi Xin Zhang, and Ning Yang. "Design of High-Speed and Low-Power Two-Channel Pipeline ADC." Advanced Materials Research 328-330 (September 2011): 1820–23. http://dx.doi.org/10.4028/www.scientific.net/amr.328-330.1820.

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This paper describes a low-power 1.2 V 8-bit 1Gs/s two-channel pipeline ADC. The novelty of the designed ADC lies in: ameliorating the two-channel pipeline structure that consists of 1.5-bit multiplying DAC (MDAC). In order to reduce the power consumption and improve the sampling speed, the dual-channel pipeline Time Division Multiplexing operation amplifier and double or single channel flash ADC are used; in the front-end Sample-and-Hold circuits, switch-linearization control circuits(SLC) driven by a single clock signal is applied to solve the problem of time-skew and time mismatch between two channels. The pipeline ADC is designed with 90 nm CMOS process. From the simulation results of the designed ADC, we can draw that the SFDR is 42.3 dB; the SNR is 32.7 dB under the usual temperature. The ADC achieves 21 mW power-dissipation, 8 resolution and 1.01 GS/s sampling speed. So the design meets high speed, high precision and low power dissipation at the same time.

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Wang, Li, Wenli Chen, Kai Chen, Renjun He, and Wenjian Zhou. "The Research on the Signal Generation Method and Digital Pre-Processing Based on Time-Interleaved Digital-to-Analog Converter for Analog-to-Digital Converter Testing." Applied Sciences 12, no. 3 (February 7, 2022): 1704. http://dx.doi.org/10.3390/app12031704.

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In the high-resolution analog circuit, the performance of chips is an important part. The performance of the chips needs to be determined by testing. According to the test requirements, stimulus signal with better quality and performance is necessary. The main research direction is how to generate high-resolution and high-speed analog signal when there is no suitable high-resolution and high-speed digital-to-analog converter (DAC) chip available. In this paper, we take the high-resolution analog-to-digital converter (ADC) chips test as an example; this article uses high-resolution DAC chips and multiplexers to generate high-resolution high-speed signals that can be used for testing high-resolution ADC chips based on the principle of time-alternating sampling. This article explains its method, analyzes its error and proposes a digital pre-processing method to reduce the error. Finally, the actual circuit is designed, and the method is verified on the circuit. The test results prove the effectiveness of this method for generating high-resolution ADC test signals.

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Kakarla, Deepti. "An optimized design approach for 8-bit pipelined ADC using high gain amplifier." i-manager’s Journal on Electronics Engineering 12, no. 2 (2022): 23. http://dx.doi.org/10.26634/jele.12.2.18529.

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Demand of high-performance converters with integrated circuits with combined features and specifications of power consumption, resolution and speed have become very dominant in many emerging applications. Pipelined ADC mixed signal system consists of Sample and Hold, Flash ADC, DAC and Gain amplifier in all the stages. In the present work, a pipeline ADC architecture has 3-stages, with each stage of 3-bits with 3-bit flash ADC followed by a 3-bit binary weighted DAC at each stage. A novel approach to design a 8-bit ADC is implemented, and this design offers less number of comparators compared to flash ADC with less circuit complexity, and 8-bit ADC is designed with improvement in resolution. It is simulated first in MATLAB, but applying 1.8Volts sinusoidal and sampling time of 40 MSPS and clock frequency 10MHz the individual blocks are implemented in LT-spice 180 nm technology with bandwidth of 40 MHz. Then a high gain amplifier is implemented by using Diode connected load differential amplifier with 10mv input voltage and 18Mhz input frequency.

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Arafa, Kawther I., Dina M. Ellaithy, Abdelhalim Zekry, Mohamed Abouelatta, and Heba Shawkey. "Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications." Active and Passive Electronic Components 2023 (January 4, 2023): 1–29. http://dx.doi.org/10.1155/2023/3669255.

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

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Ye, Wen Hua, and Huan Li. "Design of Virtex-7 FPGA-Based High-Speed Signal Processor Carrier Board." Applied Mechanics and Materials 719-720 (January 2015): 534–37. http://dx.doi.org/10.4028/www.scientific.net/amm.719-720.534.

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With the development of digital signal processing technology, the demand on the signal processor speed has become increasingly high. This paper describes the hardware design of carrier board in high-speed signal processing module, which using Xilinx's newest Virtex-7 FPGA family XC7VX485T chip, and applying high-speed signal processing interface FMC to transport and communicate high-speed data between carrier board and daughter card with high-speed ADC and DAC. This design provides a hardware implementation and algorithm verification platform for high-speed digital signal processing system.

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Chauhan, Sarita. "Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 31, 2021): 3073–80. http://dx.doi.org/10.22214/ijraset.2021.37002.

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After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.

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Shetty, Chaya, M. Nagabushanam, and Venkatesh Nuthan Prasad. "A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology." International Journal of Circuits, Systems and Signal Processing 15 (June 29, 2021): 556–68. http://dx.doi.org/10.46300/9106.2021.15.62.

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The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.

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Bchir, Mounira, Thouraya Ettaghzouti, and Néjib Hassen. "A Novel High Frequency Low Voltage Low Power Current Mode Analog to Digital Converter Pipeline." Journal of Low Power Electronics 15, no. 4 (December 1, 2019): 368–78. http://dx.doi.org/10.1166/jolpe.2019.1621.

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This paper introduces a novel structure for the realization of a low voltage, low power current-mode analog to the digital converter (ADC) pipeline (12 bits). The proposed structure of the ADC is based on a novel design of a current comparator and Digital to Analog Converter (DAC) structure. This modification allows us to reach a higher speed, lower voltage, and lower power dissipation. ELDO simulators using 0.18 μm, CMOS and TSMC parameters are performed to confirm the workability of this architecture. The proposed ADC is powered with a 1 V supply voltage. It is characterized by wide conversion frequency (350 MHz) and low power consumption that is 2.76 mW.

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Vasudeva, G., and B. V. Uma. "Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET." WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL 17 (January 3, 2022): 1–15. http://dx.doi.org/10.37394/23203.2022.17.1.

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Successive Approximation Register (SAR) Analog to Digital Converter (ADC) architecture comprises of sub modules such as comparator, Digital to Analog Converter and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements and ADC metrics is presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two stage segmented resistive string DAC architecture and low power SAR logic is designed and integrated to form the ADC architecture with maximum sampling rate of 1 GS/s. Circuit schematic is captured in Cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC is evaluated in MATLAB environment. Differential Non Linearity and Integral Non Linearity metrics for the 12-bit ADC is limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency upto 1 GSps is designed in this work with low power dissipation less than 10 mW.

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Idros, Norhamizah, Alia Rosli, Zulfiqar Ali Abdul Aziz, Jagadheswaran Rajendran, and Arjuna Marzuki. "A 1.8 V high-speed 8-bit hybrid DAC with integrated rail-to-rail buffer amplifier in CMOS 180 nm." Microelectronics International 38, no. 2 (May 18, 2021): 46–54. http://dx.doi.org/10.1108/mi-10-2020-0073.

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Purpose The purpose of this paper is to present the performance of an 8-bit hybrid DAC which is suitable for wireless application or part of a built-in test block for ADC. The hybrid architecture used is the combination of thermometer coding and binary-weighted resistor architectures. Design/methodology/approach The conventional DAC topology performance tends to degrade at high-resolution applications. A hybrid topology, which combines an equal number of bits of thermometer coding and binary-weighted resistor architectures operating at higher sampling frequency, was proposed in this work. The die was fabricated in 180 nm CMOS process technology with a supplied voltage of 1.8 V. Findings Measured results showed that the DNL and INL errors are within −1 to +1 LSB and −0.9 to +0.9 LSB, respectively for the input range of 0.9 V at the clock rate of 200 MHz, and this DAC was proven monotonic. This 0.068 mm2 DAC consumed 12.6 mW for the data conversion. Originality/value This paper is of value in showing the equal division of bits from thermometer coding and binary-weighted resistor architectures provides smaller die size and enhances the performance of hybrid DAC, in terms of linearity, which are DNL and INL errors and guarantees monotonicity at higher sampling frequency.

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Reed, Lynn, John Hoenig, and Vema Reddy. "The Design and Characterization of an 8-bit ADC for 250°C Operation." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, HiTEN (January 1, 2015): 000027–32. http://dx.doi.org/10.4071/hiten-session1-paper1_5.

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Many high temperature applications require the measurement of analog voltages. This usually requires the integration of an ADC into the design. While the temperature degradation in performance of digital circuits is well known, the effects of temperature on analog circuitry are much harder to predict. Analog design is often an iterative process in which the characterization knowledge of a fabricated design is used to improve the next iteration of the design. This paper presents the results of the most recent iteration. This paper describes how the design of an existing 8-bit ADC was optimized for the SOI process. It also presents the characterization of the ADC at various temperatures up to 250°C and shows the effects of increased leakage on the ADC parameters of linearity, accuracy, and conversion speed. The ADC discussed is a successive approximation design which uses a resistive DAC. The design was modified to take advantage of the resistive characteristics inherent in the SOI process. Specifically, the DAC resistors were formed using N-type diffusion because of their superior matching as compared to using poly. The analog circuitry in the DAC switching and in the comparator required carefully choosing where to use “A” type versus “H” type transistor geometries to prevent inadvertent SCR failures. The ADC design also included a serial interface circuit that facilitates measurements within an oven by minimizing the number of connections required for operation. The measurements were taken using a 12-bit DAC to generate the analog input voltages to the 8-bit ADC under test. The ADC digital output was compared to the digital input to the DAC. All 4096 measurement points were taken at each voltage and temperature step. The results of these measurements were post-processed to extract the characterization data. There is a discussion of the results, the effects of leakage on those results, and how these effects might be overcome to produce more accurate ADC circuits in the future.

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Jung, Youngho, and Jooyoung Jeon. "Delta-Sigma Modulator with Relaxed Feedback Timing for High Speed Applications." Electronics 8, no. 10 (October 9, 2019): 1138. http://dx.doi.org/10.3390/electronics8101138.

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In this paper, a ΔΣ analog-to-digital converter (ADC) was designed and measured for broadband and high-resolution applications by applying the simple circuit technique to alleviate the feedback timing of input feed-forward architecture. With the proposed technique, a low-speed comparator and dynamic element matching (DEM) logic can be applied even for high-speed implementation, which helps to decrease power dissipation. Two prototypes using slightly different input branch topologies were fabricated with a 0.18 um 2-poly and 4-metal CMOS process, and measured to demonstrate the effectiveness of the proposed circuit technique. The sampling capacitor and feedback DAC capacitors were separated in prototype A, while they were shared in prototype B. The prototypes achieved 81.2 dB and 72.4 dB of SNDR in a 2.1 MHz signal band, respectively.

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ZHU, ZHANGMING, GUANGWEN YU, JINGYU WANG, and YINTANG YANG. "A LOW DISTORTION BOOTSTRAPPED SWITCH FOR 4-BIT MDAC." Journal of Circuits, Systems and Computers 22, no. 01 (January 2013): 1250074. http://dx.doi.org/10.1142/s0218126612500740.

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A novel bootstrapped switch scheme with low distortion and high-speed is presented. Transmission gate (TG) switch is used to implement the switch circuit, which results in a reduction in the effect of charge injection during sampling phase and an improved linearity. The parasitic capacitance connected to the top plate of battery capacitor is minimized for higher output voltage. The switch has been simulated in Spectre using an SMIC 0.18 μm CMOS technology at 3.3 V and been applied to a 4-bit multiplying DAC (MDAC) in a 14-bit 100 MS/s pipelined analog-to-digital converter (ADC). The 4-bit MDAC has shown a satisfying dynamic performance.

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Zahrai, Seyed Alireza, Marina Zlochisti, Nicolas Le Dortz, and Marvin Onabajo. "A Low-Power High-Speed Hybrid ADC With Merged Sample-and-Hold and DAC Functions for Efficient Subranging Time-Interleaved Operation." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 11 (November 2017): 3193–206. http://dx.doi.org/10.1109/tvlsi.2017.2739108.

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Begum, Farhana, Sandeep Mishra, Md Najrul Islam, and Anup Dandapat. "A 10-bit 2.33 fJ/conv. SAR-ADC with high speed capacitive DAC switching using a novel effective asynchronous control circuitry." Analog Integrated Circuits and Signal Processing 100, no. 2 (April 9, 2019): 311–25. http://dx.doi.org/10.1007/s10470-019-01450-w.

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Verma, Deeksha, Khuram Shehzad, Sung Jin Kim, Young Gun Pu, Sang-Sun Yoo, Keum Cheol Hwang, Youngoo Yang, and Kang-Yoon Lee. "A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator." Sensors 22, no. 14 (July 19, 2022): 5393. http://dx.doi.org/10.3390/s22145393.

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A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.

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Yani, Kalfika, Fiky Y. Suratman, and Koredianto Usman. "Design and Implementation Pulse Compression for S-Band Surveillance Radar." Journal of Measurements, Electronics, Communications, and Systems 7, no. 1 (December 30, 2020): 20. http://dx.doi.org/10.25124/jmecs.v7i1.2631.

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The radar air surveillance system consists of 4 main parts, there are antenna, RF front-end, radar signal processing, and radar data processing. Radar signal processing starts from the baseband to IF section. The radar waveform consists of two types of signal, there are continuous wave (CW) radar, and pulse compression radar [1]. Range resolution for a given radar can be significantly improved by using very short pulses. Pulse compression allows us to achieve the average transmitted power of a relatively long pulse, while obtaining the range resolution corresponding to a short pulse. Pulse compression have compression gain. With the same power, pulse compression radar can transmit signal further than CW radar. In the modern radar, waveform is implemented in digital platform. With digital platform, the radar waveform can optimize without develop the new hardware platform. Field Programmable Gate Array (FPGA) is the best platform to implemented radar signal processing, because FPGA have ability to work in high speed data rate and parallel processing. In this research, we design radar signal processing from baseband to IF using Xilinx ML-605 Virtex-6 platform which combined with FMC-150 high speed ADC/DAC.

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Pawase, Ramesh, and N. P. Futane. "MEMS Seismic Sensor with FPAA Based Interface Circuit for Frequency-Drift Compensation using ANN." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 2 (May 28, 2018): 120. http://dx.doi.org/10.11591/ijres.v6.i2.pp120-126.

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<p>Electrochemical MEMS seismic sensor is limited by its non-ideality of frequency dependent characteristics hence interface circuits for compensation is necessary. The conventional compensation circuits are limited by high power consumption, bulky external hardware circuitry. In these methods digital circuits are also limited by inherent analog to digital conversion and vice versa which consumes significant power, acquires more size and limits speed. A Field programmable analog array (FPAA) overcomes these limitations and gives fast, simple and user friendly development platform with less development speed comparable to ASIC. Recently FPAA becoming popular for rapid prototyping. The proposed system presents FPAA (Anadigm AN231E04) based hardware implementation of ANN model. Using this FPAA based compensation circuit, the error in frequency drift have been minimized in the range of 3.68% to about 0.64% as compared to ANN simulated results in the range of 23.07% to 0.99 %. This single neuron consumes of power of 206.62 mW. and has minimum block wise resource utilization. The proposed hardware uses all analog blocks which remove the requirement of ADC and DAC reducing significant power and size of interface circuit. This work gives the SMART MEMS seismic sensor with reliable output and ANN based intelligent interface circuit implemented in FPAA hardware.<strong></strong></p>

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Chhetri, Sujit Rokka, Bikash Poudel, Sandesh Ghimire, Shaswot Shresthamali, and Dinesh Kumar Sharma. "Implementation of Audio Effect Generator in FPGA." Nepal Journal of Science and Technology 15, no. 1 (February 3, 2015): 89–98. http://dx.doi.org/10.3126/njst.v15i1.12022.

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This paper describes the theory and implementation of audio effects such as echo, distortion and pitch-shift in Field Programmable Gate Array (FPGA). At first the mathematical formulation for generation of such effects is explained and then the algorithm is described for its implementation in FPGA using Very high speed integrated circuit hardware descriptive language (VHDL). The digital system being designed, which is synthesizable and reconfigurable, offers a great flexibility and scalability in designing and prototyping in FPGAs. The system is divided into three HDL blocks, each for echo, distortion, and pitch-shift effect generation, which are multiplexed in order to share the common ADC and DAC. The audio effect generator designed in this paper was successfully implemented in Spartan-3E FPGA utilizing the resources available effectively. There has been tremendous research being carried out in the field of IP core. Efficient IP cores designed to carry out digital signal processing are implemented in every modern device using configurable logics. This trend hasn’t yet been realized in Nepal. Through the design and implementation of audio effect generator, this paper also aims at bringing the field of IP core development to limelight among scholars of Nepal.DOI: http://dx.doi.org/10.3126/njst.v15i1.12022 Nepal Journal of Science and TechnologyVol. 15, No.1 (2014) 89-98

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Yang, Yu-Xiang, Shi-Zhan Bai, Hai-Jun Lin, Jian-Min Li, and Fu Zhang. "Design of multi-frequency electrical impedance tomography system based on multisine excitation and integer-period sampling." Acta Physica Sinica 71, no. 5 (2022): 058703. http://dx.doi.org/10.7498/aps.71.20211375.

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Starting from the principle that the integer-period sampling (IPS) of periodic signals is free of spectrum leakage, in this paper we propose the multisine-IPS theory, deduce theoretically the sampling rate setting formula of multisine-IPS condition for the first time, and build its realization method based on field-programmable gate array (FPGA) plus digital-to-analog converter (DAC) plus analog-to-digital converter (ADC). A new multi-frequency electrical impedance tomography (mfEIT) system based on multisine excitation and its IPS theory is developed, and a dual-target imaging model including a carrot stick and a cucumber stick is designed. The experiments of multi-frequency time-difference imaging and frequency-difference imaging are carried out on the mfEIT system. The experimental results show that the newly-designed mfEIT system can achieve full-band impedance measurements on multiple objective tissue boundary at 20 frequency points (2–997 kHz) within one fundamental period (1 ms), and the structure and position of biological tissues with different electrical properties can also be distinguished from the resulting images. The proposed multisine-IPS theory and its implementation method can complete a full-band impedance measurement within one multisine fundamental period, which lays a theoretical and technical foundation for developing high-speed mfEIT system.

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Tsvetkov, A. N., and Doan Ngok Shi. "Hardware-software complex for experimental research of electric drives of asynchronous motors with squirrel-cage rotor with traditional winding and motors with combined winding." Power engineering: research, equipment, technology 23, no. 6 (April 1, 2022): 157–65. http://dx.doi.org/10.30724/1998-9903-2021-23-6-157-165.

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THE PURPOSE. Modern requirements for electric drives impose increasingly stringent conditions for energy efficiency, dimensions and weight. The weight and size parameters are especially noticeable in relation to the rapidly developing electric transport. The achieved technological limits practically do not give tangible results in improving the characteristics of known structures, so there is a struggle for units of percent and fractions of a percent in terms of increasing the efficiency of equipment.MATERIALS. Debugging and fine-tuning of electric drive elements requires numerous tests on research benches using measuring channels and analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), digital-to-digital conversion (DDC).RESULTS. The creation of research stands implies the development of a hardware-software complex (HSC) based on high-speed computing devices. The structure of the HSC included the developed frequency converter with the possibility of adjusting the algorithms for controlling the electric motor and the mathematical model of the electric motor itself. The object of experimental research was prototypes of electric drives based on asynchronous electric motors with a squirrel-cage rotor and a combined stator winding.CONCLUSION. The article discusses ways to organize the measuring and control channels of the measuring and information system of the research stand, which makes it possible to study samples of asynchronous electric motors in idling and under load modes.

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Tsvetkov, A. N., V. Yu Kornilov, A. R. Safin, A. G. Logacheva, T. I. Petrov, and N. E. Kuvshinov. "Control measuring and information system of the experimental stand." Power engineering: research, equipment, technology 22, no. 4 (November 15, 2020): 88–98. http://dx.doi.org/10.30724/1998-9903-2020-22-4-88-98.

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Modern trends in the development of technology are based on the need for experimental studies of the equipment being developed in laboratory conditions with the maximum approximation of the operating modes to real ones. Such studies are impossible without the development of specialized stands with test automation systems. Automation of processes involves the organization of measuring channels as part of a stand using analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), digital-todigital conversion (DDC) and the development of a hardware-software complex (HSC) based on high-speed computing devices. As part of the project to create new high-tech equipment, the specialists of FSBEI HE “KSPEU” and JSC “ChEAZ” developed and created an experimental stand designed to verify and confirm the correctness of the selected structural and circuit solutions used in the design of a synchronous valve electric motor (SVEM) and rod control station borehole pumping unit (RC SBPU). The object of experimental research was the prototype and prototype electric drives of oil pumping units, as well as their components: SVEM and RC SBPU. The article discusses the ways of organizing the measuring and control channels of the measuring and information system of the experimental bench, which allows to study samples of synchronous valve motors and control stations of the sucker rod pump unit in the regimes that are as close as possible to real field conditions simulating the operation of the oil pumping unit of the sucker rod pump unit. Thus, in the experimental stand, analog, discrete and digital control and control channels are implemented.

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Huang, Fu Xiang, Zhi Qiang Gao, and Xiao Wei Liu. "Design of 16 bit 200kHz Feedforward Sigma-Delta ADC Applied in Silicon Gyroscope." Key Engineering Materials 645-646 (May 2015): 548–54. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.548.

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Due to the huge potential applications in military and civil fields, silicon micro mechanical gyro has become the most popular research direction in MEMS field today. Therefore, the corresponding interface circuit of silicon gyroscope has also become a hot topic at home and abroad. Now, integration, digitalization and intelligence has become the focus of future research directions of silicon gyroscope, so the research of analog to digital conversion circuit for gyroscope has become a research priority. Therefore, the conduct of Sigma Delta ADCs research for silicon gyro interface circuit has a very important significance and application prospects.This topic briefly introduces the working principle of Sigma Delta ADC. Based on the requirements of the modulator design, Sigma Delta modulator structures are carefully analyzed and also carried on the comparison and optimization. Hereby, a three order three bits quantization in single-loop with partial feedback of feed-forward summation system structure for modulator is designed in this paper, and then the ideal model of modulator system in Matlab is simulated. In addition, the focus of this topic is mainly on the nonlinear factors analysis and modeling, and the Data Weighted Average (DWA) technique used in multi-bit quantization is introduced as well as modeling in system level. Then, the non-ideal modeling of system is simulated in Matlab.In system level design, this paper adopts feed-forward summation and multi-bit quantization structure to reduce the output of the integrator, increase the noise performance of the modulator, and make it easier for the system stability. Furthermore, the use of partial feedback in the structure for zero-point optimization improves the noise shaping ability in signal bandwidth of modulator. This topic employs the single-loop third-order three-bit quantization structure, with the sampling rate 64, signal bandwidth 200 K Hz and the sampling clock frequency 25.6 MHz. For the ideal modeling, the Signal-to-Noise Ratio (SNR) is 125dB, and the Effective Number of Bits (ENOB) is 20.48. When in consideration of modulator’s nonlinear factors, the nonlinear systems Simulink simulation results obtained SNR of 104dB, and the ENOB is 16.98.In order to reduce the harmonic distortion of the modulator, transistor level is implemented by fully-differential switch capacitor circuit. The structure at all levels of the integrator was optimized. To reduce the influence of flicker noise, the integrator adopts Correlated Double Sampling (CDS) technology, and is improved by the partial feedback circuit. The fully-differential operational amplifier with high slew-rate and high bandwidth is designed, and uses switch capacitor circuit as common-mode feedback. Dynamic comparator and multi-bit quantizer are designed to improve the speed of the quantizer and reduce power consumption. The design the nonlinear compensation feedback DAC module--DWA module circuit--realizes noise shaping of capacitance matching error. The overall circuit was simulated in Cadence by 0.6um process. Transistor-level simulation result shows that the SNR is 101.3dB, and the effective number of bits is 16.54bits. The simulation results are consistent with the established non-ideal model of modulator, which verifies the correction of system level design method.

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Shrestha, Manish Man, Bibek Ropakheti, Uddhav Bhattarai, Ajay Adhikari, and Shreeram Thakur. "Intelligent Wireless Ultrasonic Device for Damage Detection of Metallic Structures." Scientific World 14, no. 14 (February 15, 2021): 31–36. http://dx.doi.org/10.3126/sw.v14i14.34979.

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In today’s world, it is necessary to monitor structures for possible damages. A failure to monitor the structures properly can cause structural catastrophe. Many researchers have worked on the low-power ultrasonic device to monitor the structures. In this research, we present an intelligent ultrasonic device (IUD) to monitor and detect the damages on the structures. The device uses microcontroller, actuator interface circuit, sensor interface circuit and radio frequency (RF) modem. The microcontroller has in-built high-speed analog-to-digital converter (ADC), digital-to-analog converter (DAC) and floating-point unit for signal processing. The controller generates the tone-burst signal and sends it to actuator interface circuit. The actuator interface circuit conditions the received signal from the microcontroller and drives the Piezoelectric Transducer (PZT) actuator. The actuator generates an ultrasonic wave in the structure. The wave is then sensed by PZT sensors. The sensor interface circuit selects the signal from desired PZT sensor and sends it to the microcontroller for further processing. The microcontroller digitizes the signal and computes the damage index and only if the damage is severe, it will send data wirelessly to the nearby PC. To test the device, iron specimen was prepared, PZT actuator and PZT sensor was mounted on it. The artificial crack was then induced on the specimen. The ultrasonic wave was then collected from the structure. By analyzing the ultrasonic wave, the device successfully detected the induced crack in the structure. The future work will be to use GSM modem so that the device can be monitored in the real time from the remote location.

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Rikan, Behnam, Sang-Yun Kim, Hamed Abbasizadeh, Arash Hejazi, Reza Rad, Khuram Shehzad, Keum Hwang, Youngoo Yang, Minjae Lee, and Kang-Yoon Lee. "A 10- and 12-Bit Multi-Channel Hybrid Type Successive Approximation Register Analog-to-Digital Converter for Wireless Power Transfer System." Energies 11, no. 10 (October 8, 2018): 2673. http://dx.doi.org/10.3390/en11102673.

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This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) designed for a wireless power transfer system. This is a four–channel SAR ADC structure with 10-bit resolution for each channel, which can also be applied as a single 12-bit ADC. To reduce the area and the number of the required devices in the ADC module, a hybrid-type structure with capacitor and resistor DACs is applied, in which the resistor DAC is shared between channels and determines the seven least significant bits (LSB)s, while the capacitor DAC determines the three most significant bits (MSBs). For the 12-bit operation mode, and to reduce the number of capacitors required in the capacitor DAC, the capacitors of the four channels are shared to determine the five MSBs. A foreground calibration is applied to the capacitor DAC to remedy the gain and offset errors after fabrication. An additional low resistive path is also implemented in the resistor DAC for error correction. The conversion speed for 10- and 12-bit operations reaches up to 1 and 0.5 MS/s, respectively. The prototype ADC is designed in a 180 nm complementary metal-oxide semiconductor (CMOS) process. For 10- and 12-bit operating modes, this ADC module achieves up to 9.71 and 11.76 effective number of bits (ENOBs), respectively.

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Romashov, V. V., K. A. Yakimenko, and A. N. Doktorov. "Wideband high-speed DAC-based frequency synthesizer." Journal of Physics: Conference Series 2388, no. 1 (December 1, 2022): 012114. http://dx.doi.org/10.1088/1742-6596/2388/1/012114.

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Abstract Wideband hybrid frequency synthesizer with phase-locked loop (PLL) and high-speed direct-to-analog converter (DAC) is presented. The use of special DAC operating modes allows to expand the synthesizer generating frequency band. Presented synthesizer also provides a low phase noise due to using RF mixer in PLL feedback.

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Riewruja *, Vanchai, and Amphawan Chaikla. "A high-speed algorithmic ADC." International Journal of Electronics 91, no. 12 (December 2004): 719–33. http://dx.doi.org/10.1080/00207210412331332862.

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29

Saifutdinov, A. I., and S. S. Sysoev. "Development of a Probe System for Measuring the Plasma Parameters and the High-Energy Part of the Electron-Energy Distribution Function." Instruments and Experimental Techniques 65, no. 1 (February 2022): 75–79. http://dx.doi.org/10.1134/s0020441222010195.

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Abstract— A probe system has been developed on the basis of an external ADC/DAC module (ADC is the analog-to-digital converter and DAC is the digital-to-analog converter). Using this system, it is possible to determine all the main plasma parameters of continuous and pulsed gas discharges. A program for the Windows operating system has been developed in C++ to control the probe system. The probe system can be used for diagnostics of plasma devices and can be included in modern microplasma analyzers of gas mixtures.

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Lee, B. G., and S. G. Lee. "Input-tracking DAC for low-power high-linearity SAR ADC." Electronics Letters 47, no. 16 (2011): 911. http://dx.doi.org/10.1049/el.2011.1642.

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Kristianti, Veronica Ernita, Hamzah Afandi, Eri Prasetyo Wibowo, and Djoko Purnomo. "A 8-Bit DAC Design in AMS 0.35 μm CMOS Process for High-Speed Communication Systems." Advanced Materials Research 646 (January 2013): 178–83. http://dx.doi.org/10.4028/www.scientific.net/amr.646.178.

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DAC architecture that is designed in this research can be applied in high-speed communication systems. DAC architecture that is presented in this research is based on the R2R ladder method. The design requires three main components, namely switches, resistors, and op-amp. This method has been applied to the 8-bit DAC for high-speed communication system using AMS technology 0.35 μm CMOS process. Resistors that are used in R2R DAC is replaced by transistors, so that the size is smaller and easier layout in the manufacturing process. Mentor graphics software is used as a simulator of the design. DAC design with 8-bit resolution in this research can be applied to the speed up to 1000 Msps. In the way the design can be categorized as high-speed DAC that can be used in a communication system.

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32

Li, Donggen. "Comparative Study of High Speed ADCs." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 146–52. http://dx.doi.org/10.54097/hset.v27i.3731.

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With the development of information technology, analog-to-digital converter (ADC) is widely used. In products such as radar, ultra wideband communication system, high-performance digital oscilloscope and so on, the speed performance of analog-to-digital converter is usually the bottleneck of the whole system performance, so the research of high-speed ADC has attracted much attention. ADC is an interface circuit that converts analog signals into digital signals that can be processed by DSP. This paper will start with the basic knowledge of ADC, explain the general working process of ADC, introduce several architectures and working principles suitable for high-speed ADC, and compare and analyze their advantages and disadvantages.

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Nguyen, Cong Luong, Huu Nhan Phan, and Jong-Wook Lee. "A 12-b Subranging SAR ADC Using Detect-and-Skip Switching and Mismatch Calibration for Biopotential Sensing Applications." Sensors 22, no. 9 (May 9, 2022): 3600. http://dx.doi.org/10.3390/s22093600.

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This paper presents a 12-b successive approximation register (SAR) analog-to-digital converter (ADC) for biopotential sensing applications. To reduce the digital-to-analog converter (DAC) switching energy of the high-resolution ADC, we combine merged-capacitor-switching (MCS) and detect-and-skip (DAS) methods, successfully embedded in the subranging structure. The proposed method saves 96.7% of switching energy compared to the conventional method. Without an extra burden on the realization of the calibration circuit, we achieve mismatch calibration by reusing the on-chip DAC. The mismatch data are processed in the digital domain to compensate for the nonlinearity caused by the DAC mismatch. The ADC is realized using a 0.18 μm CMOS process with a core area of 0.7 mm2. At the sampling rate fS = 9 kS/s, the ADC achieves a signal-to-noise ratio and distortion (SINAD) of 67.4 dB. The proposed calibration technique improves the spurious-free dynamic range (SFDR) by 7.2 dB, resulting in 73.5 dB. At an increased fS = 200 kS/s, the ADC achieves a SINAD of 65.9 dB and an SFDR of 68.8 dB with a figure-of-merit (FoM) of 13.2 fJ/conversion-step.

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Olieman, Erik, Anne-Johan Annema, and Bram Nauta. "An Interleaved Full Nyquist High-Speed DAC Technique." IEEE Journal of Solid-State Circuits 50, no. 3 (March 2015): 704–13. http://dx.doi.org/10.1109/jssc.2014.2387946.

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Kiss, P., U. Moon, J. Steensgaard, J. T. Stonick, and G. C. Temes. "High-speed ADC with error correction." Electronics Letters 37, no. 2 (2001): 76. http://dx.doi.org/10.1049/el:20010069.

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Huang, Cheng, You Hui Li, Ya Dan Zhang, and Nan Wang. "Testing of High-Resolution Analog-to-Digital Converters Using Segmentation and Optimized Low-Precision DAC." Applied Mechanics and Materials 333-335 (July 2013): 1669–72. http://dx.doi.org/10.4028/www.scientific.net/amm.333-335.1669.

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The main challenges of high-resolution ADC testing are the huge number of samples and the expensive test equipment, especially the requirement of high linearity signal source. In this paper, the scaling and segmentation algorithm which combines SEIR with windows is introduced for high-resolution ADC test. The new approach is validated by simulation with a 24-bit sigma-delta ADC. INL error of the proposed method is ±0.2LSB, which is less than the SEIR method of ±0.5LSB,and less than the histogram method of ±0.3LSB. About 20 million samples are required in the proposed method, which is about 30 times less than the traditional histogram method.

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37

Bastos, J., A. M. Marques, M. S. J. Steyaert, and W. Sansen. "A 12-bit intrinsic accuracy high-speed CMOS DAC." IEEE Journal of Solid-State Circuits 33, no. 12 (1998): 1959–69. http://dx.doi.org/10.1109/4.735536.

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Jung, Jaejin, Sangho Shin, Shin-Il Lim, Suki Kim, and Sung-Mo Kang. "Power efficient high-speed DAC for wideband communication applications." Analog Integrated Circuits and Signal Processing 70, no. 3 (August 4, 2011): 421–28. http://dx.doi.org/10.1007/s10470-011-9708-4.

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Rohman, Fatkhur, Nurhadi Nurhadi, and Mira Esculenta Martawati. "Unjuk Kerja GPIO, PWM, ADC dan Timer pada Mikrokontroler STM32F103, ESP32S dan ATMega328." JURNAL ELTEK 19, no. 2 (October 29, 2021): 73. http://dx.doi.org/10.33795/eltek.v19i2.295.

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Perangkat embedded system pada masa sekarang memiliki banyak pilihan terhadap jenis mikrokontroler yang sesuai dengan kebutuhan. Hal ini menjadi tantangan tersendiri bagi pengguna ketika diharuskan untuk memilih salah satu jenis mikrokontroler tersebut. Sebagai contoh permasalahan apakah mikrokontroler yang telah dipilih tersebut memiliki sejumlah pin GPIO yang diinginkan, dengan frekuensi switching yang tinggi, berapakah jumlah kanal, resolusi, linieritas dan durasi konversi ADC, bagaimana kemampuan peripheral internal DAC, Timer dan PWM yang bisa dibangkitkan dari mikrokontroler tersebut. Penelitian ini telah membandingkan setidaknya 4 peripheral internal utama yang dimiliki oleh 3 jenis mikrokontroler. Metode yang dilakukan adalah dengan menguji karakteristik GPIO, PWM, TIMER dan ADC pada 3 jenis mikrokontroler yaitu Arduino ATMega328, STM32F103C8 dan ESP32. Eksperiment dilakukan dengan mengevaluasi frekuensi switching digital ouput, mengevaluasi resolusi sinyal hasil konversi ADC, mengevaluasi ketepatan hasil instruksi delay berkaitan dengan timer program dan waktu konversi sinyal DAC semuanya dilakukan pada masing-masing mikrokontroler. Hasil akhir dari penelitian ini menunjukkan, mikrokontroler ESP32 memiliki unjuk kerja GPIO, PWM, TIMER dan ADC terbaik apabila dibandingkan dengan jenis lainnya. Penelitian ini juga membuktikan integrasi FreeRTOS pada Framework Arduino bisa berfungsi dengan optimal meskipun mikrokontroler berjalan pada 2 task yang berbeda di 2 core CPU yang bekerja secara pararel. Frekuensi switching digital output pada ESP32 mampu mencapai 3MHz, waktu konversi ADC hanya 5,7us dan DAC hanya 3,7us. Today's embedded systems have many choices for the type of microcontroller that suits the needs. This is a challenge in itself for users when required to choose one type of microcontroller. For example, the problem of whether the selected microcontroller has the desired number of GPIO pins, with a high switching frequency, what is the number of channels, resolution, linearity, and duration of the ADC conversion, what is the ability of the internal DAC, Timer and PWM peripherals that can be generated from the microcontroller. This study has compared at least 4 main internal peripherals owned by 3 types of microcontrollers. The method used is to test the characteristics of the GPIO, PWM, TIMER, and ADC on 3 types of microcontrollers, namely Arduino ATMega328, STM32F103C8, and ESP32. The experiment was carried out by evaluating the digital output switching frequency, evaluating the signal resolution of the ADC conversion result, evaluating the accuracy of the delay instruction results related to the program timer and DAC signal conversion time, all of which were carried out on each microcontroller. The final results of this study indicate that the ESP32 microcontroller has the best GPIO, PWM, TIMER, and ADC performance when compared to other types. This research also proves that the FreeRTOS integration on the Arduino Framework can function optimally even though the microcontroller runs on 2 different tasks on 2 CPU cores that work in parallel. The digital output switching frequency on the ESP32 is capable of reaching 3MHz, the ADC conversion time is only 5.7us and the DAC is the only 3.7us.

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40

Li, H., J. Eckmueller, S. Sattler, H. Eichfeld, and R. Weigel. "A new BIST scheme for low-power and high-resolution DAC testing." Advances in Radio Science 1 (May 5, 2003): 289–93. http://dx.doi.org/10.5194/ars-1-289-2003.

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Abstract. A BIST scheme for testing on chip DAC is presented in this paper. We discuss the generation of on chip testing stimuli and the measurement of digital signals with a narrow-band digital filter. We validate the scheme with software simulation and point out the possibility of ADC BIST with verified DACicus-journals.

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41

Osipov, Dmitry, Aleksandr Gusev, Vitaly Shumikhin, and Steffen Paul. "Noise shaping in SAR ADC." Facta universitatis - series: Electronics and Energetics 33, no. 1 (2020): 15–26. http://dx.doi.org/10.2298/fuee2001015o.

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The successive approximation register (SAR) analog-to-digital converter (ADC) is currently the most popular type of ADC architecture, owing to its power efficiency. They are also used in multichannel systems, where power efficiency is of high importance because of the large number of simultaneously working channels. However, the SAR ADC architecture is not the most area efficient. In SAR ADCs, the binary weighted capacitive digital-to-analog converter (DAC) is used, which means that one additional bit of resolution costs double the increase of area. Oversampling and noise shaping are methods that allow an increase in resolution without an increase of area. In this paper we present the new SAR ADC architectures with a noise shaping. A first-order noise transfer function (NTF) with zero located nearly at one can be achieved. We propose two modifications of the architecture: with zero-only NTF and with the NTF with additional pole. The additional pole theoretically increases the efficiency of noise shaping to further 3 dB. The architectures were applied to the design of SAR ADCs in a 65 nm complementary metal-oxide semiconductor (CMOS) with OSR equal to 10. A 6-bit capacitive DAC was used. The proposed architectures provide nearly 4 additional bits in ENOB. The equalent input bandwitdth is equal to 200 kHz with the sampling rate equal to 4 MS/s.

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42

Kwon, Chan-Keun, Junil Moon, and Soo-Won Kim. "A 12-Bit 500-MS/s Current Steering CMOS DAC for High-Speed PLC Modems." Journal of Circuits, Systems and Computers 25, no. 10 (July 22, 2016): 1650122. http://dx.doi.org/10.1142/s021812661650122x.

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A 12-bit 500-MS/s current steering digital-to-analog converter (DAC) for high-speed power line communication (PLC) modems is presented in this paper. The performance of current steering DAC is limited by the current cell mismatches and glitch problems caused by switching timing errors. In this paper, the current cell design procedure is presented to minimize random mismatches. Then, a new data-weighted averaging (DWA) technique with fewer glitches and low hardware complexity is proposed to compensate for the gradient mismatch. Spurious-free dynamic range (SFDR) improvement and low complexity are effectively achieved by employing both a row–column structure and a (CSA) structure as the floor plan of the proposed DAC. The proposed DAC is implemented in a standard 0.18-[Formula: see text]m CMOS process with an active area of 2.445[Formula: see text]mm2, which achieves a differential non linearity (DNL) of 0.25[Formula: see text]LSB and an integral non-linearity (INL) of 0.19[Formula: see text]LSB. Additionally, the SFDR increases by 13.2[Formula: see text]dB (on average) when employing the proposed DWA technique. The total power consumption of the proposed DAC is 176[Formula: see text]mW from a 1.8-V supply voltage.

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43

Cidon, Israel, and Inder S. Gopal. "Paris: An approach to integrated high-speed private networks." International Journal of Digital & Analog Cabled Systems 1, no. 2 (April 1988): 77–85. http://dx.doi.org/10.1002/dac.4520010208.

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SHIN, YOUNG SAN, JAE-KYUNG WEE, JONG-CHAN HA, JI-HOON LIM, YONG-JU KIM, and YOUNG-SANG SON. "A SEAMLESS-CONTROLLED DIGITAL PLL USING DUAL LOOPS FOR HIGH SPEED SOCS." Journal of Circuits, Systems and Computers 20, no. 04 (June 2011): 741–56. http://dx.doi.org/10.1142/s021812661100758x.

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A new dual-loop digital phased-locked loop (DPLL) architecture is presented. This novel architecture is designed to provide a wide operating frequency range, high precision, and small jitter, and fits over a relatively small area. To achieve these characteristics, the architecture is implemented using a coarse loop with an UP/DOWN counter and a coarse digital-to-analog converter (DAC) to rapidly reduce the phase error, and a fine loop with a time-to-digital converter (TDC) and a fine DAC to provide more precision. Furthermore, the seamless-frequency tracking architecture based on a code conversion between the coarse cell and the fine cell of the DAC is devised to improve the lock-in stability. The chip is fabricated with Dongbu HiTek 0.18-μm CMOS technology. It has a wide operation range of 0.4–1.4 GHz, and an area of 0.195 mm2. The measured results show 15.64 ps peak-to-peak jitter and 2.22 ps rms jitter, and a power dissipation of 16.2 mW at 1 GHz.

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Zhuang, Yuming, Benjamin Magstadt, Tao Chen, and Degang Chen. "High-Purity Sine Wave Generation Using Nonlinear DAC With Predistortion Based on Low-Cost Accurate DAC–ADC Co-Testing." IEEE Transactions on Instrumentation and Measurement 67, no. 2 (February 2018): 279–87. http://dx.doi.org/10.1109/tim.2017.2769238.

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Kumawat, Mahesh, Abhishek Kumar Upadhyay, Sanjay Sharma, Ravi Kumar, Gaurav Singh, and Santosh Kumar Vishvakarma. "An improved current mode logic latch for high-speed applications." International Journal of Communication Systems 33, no. 13 (July 29, 2019): e4118. http://dx.doi.org/10.1002/dac.4118.

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47

Saito, Hiroshi. "VP dimensioning for high-speed data communication in ATM networks." International Journal of Communication Systems 7, no. 4 (1994): 275–81. http://dx.doi.org/10.1002/dac.4500070404.

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Li, Victor O. K., Jin-Fu Chang, Kuo-Chun Lee, and Tien-Shun Yang. "A survey of research and standards in high-speed networks." International Journal of Digital & Analog Communication Systems 4, no. 4 (October 1991): 269–309. http://dx.doi.org/10.1002/dac.4510040406.

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Nilsson, Arne A., and Fuyung Lai. "Performance evaluation of error recovery schemes in high-speed networks." International Journal of Digital & Analog Communication Systems 5, no. 3 (1992): 177–87. http://dx.doi.org/10.1002/dac.4510050308.

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Dimitrov, D. P., and T. K. Vasileva. "Eight-Bit Semiflash A/D Converter." VLSI Design 2007 (July 12, 2007): 1–7. http://dx.doi.org/10.1155/2007/80389.

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An 8-bit semiflash ADC is reported that uses a single array of 15 comparators for both the coarse and the fine conversion. Conversion is implemented in two steps. First, an estimate is made of the 4 most significant bits, which are then memorized in the output latch. Next, the remaining 4 bits are evaluated by the same array of comparators. The auto-zeroed comparators also perform the function of a sample-and-hold circuit. In the proposed 8-bit semiflash ADC, there are no sample-and-hold circuit, no DAC, no subtraction circuit, and no residue amplifier. As a result, a moderate conversion speed has been combined with a drastically reduced power consumption. The ADC was fabricated in a standard 0.6 μm double-poly, double-metal CMOS process. Experimental results show monotonic conversion with very low integral and differential nonlinearities. These features, combined with the ultra-low power consumption, make the proposed circuit very suitable for low-power mixed-signal applications.

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Journal articles on the topic 'High speed ADC/DAC'

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