Dissertations / Theses on the topic 'High speed ADC/DAC'
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Swindlehurst, Eric Lee. "High-Speed and Low-Power Techniques for Successive-Approximation-Register Analog-to-Digital Converters." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8923.
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Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power efficiency of the SAR architecture and demonstrates them in a low-power 10-GHz SAR ADC suitable for broadband wireless communications. The proposed 8-bit, 10-GHz, 8× time-interleaved SAR ADC utilizes a constant-matching DAC with symmetrically grouped unit finger capacitors to maximize speed by reducing the total DAC capacitance to 32 fF and minimizing the bottom plate parasitic capacitance. The capacitance reduction also saves power as both the DAC size and the driving logic size are reduced. An optimized asynchronous comparator loop and smaller driver logic push the single channel speed of the SAR ADC to 1.25 GHz, thus minimizing the total number of timeinterleaved channels to 8 to reach 10 GHz. A dual-path bootstrapped switch improves the spurious-free dynamic range (SFDR) of the sampling by creating an auxiliary path to drive the non-linear N-well capacitance apart from the main signal path. Using these techniques, the ADC achieves a measured signal-to-noise-and-distortion ratio (SNDR) and SFDR of 36.9 dB and 59 dB, respectively with a Nyquist input while consuming 21 mW of power. The ADC demonstrates a record-breaking figure-of-merit of 37 fJ/conv.-step, which is more than 2× better than the next best published design, among reported ADCs of similar speeds and resolutions.
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Lu, Dongtian. "High speed CMOS ADC for UWB receiver /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LUD.
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Hiremath, Vinayashree. "DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY." Wright State University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=wright1291391500.
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Sivakumar, Balasubramanian. "A 6-Bit Sub-Ranging High Speed Flash Analog To Digital Converter With Digital Speed And Power Control." The Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=osu1229631191.
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Wang, Mingzhen. "High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.
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Kaald, Rune. "Modelling, Simulation and Implementation Considerations of High Speed Continuous Time Sigma Delta ADC." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8942.
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A found state of the art Continuous Time Sigma Delta ADC is modelled and simulated for the presence of nonidealities. A comparison between two Excess Loop Delay compensation techniques is done, the digital differentiation technique was found to have lower swing at the last integrator, and did not need a gain-bandwidth induced delay sensitive summing amplifier. The detrimental influence of clock jitter is shown. Different DAC linearization techniques are discussed, the DWA algorithm was simulated and found to be the best choice for linearizing the DACs. Through high level modeling in Simulink and verification in the Cadence framework specifications for each building block was determined, a final simulation resulted in a SNDR of 76.3 dB.
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Homsi, Mustafa Al. "High speed ADC design targeting the UWB system using TSMC 0.18uM technology process." The Ohio State University, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=osu1399551999.
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Shar, Ahmad. "Design of a High-Speed CMOS Comparator." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10446.
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This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V.
The comparator is designed for time-interleaved bandpass sigma-delta ADC.
Due to the nature of the target application, it should be possible to turn off the components to avoid the static power consumption. The comparator of this design implements the turn off technique when it is not in use. The settling time of the comparator is less than half the clock cycle which means it does not effect the functionality of the bandpass sigma-delta ADC in terms of speed.
The simulation results are derived using Cadence environment. The results show that the comparator has 6-bit resolution and power consumption of 4.13 mW for the worst-case frequency of 250 MHz. It fulfills all the performance requirements, most of them with large margins.
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Figueiredo, Michael. "Reference-free high-speed cmos pipeline analog-to-digital converters." Doctoral thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8776.
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Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering of the Faculdade de Ciências e Tecnologia of Universidade Nova de LisboaMore and more signal processing is being transferred to the digital domain to profit from the technological enhancement of digital circuits. Where technology scaling enhances the capabilities of digital circuits, it degrades the performance of analog circuits. However, it is important to note that the impact that technology scaling has on digital circuits is becoming smaller and smaller, which means that, in nanotechnologies, to enhance energy and area efficiency, we can not simply depend on the benefits of this scaling. Although, a share of the efficiency can be obtained from the technology, new circuit architectures and techniques have to be developed to really push the limits of efficiency. In data converters, more specifically analog-to-digital converters (ADCs), a decision can be made: research energy and area efficient analog circuit techniques and architectures that cope with technological scaling issues, or design algorithms that use digital circuitry to assist the poor analog technological performance. The former option is the premise for the work developed in this thesis. The work reported in this thesis explores various design techniques with the purpose of enhancing the power and area efficiency of building blocks mainly to be used in multiplying digital-to-analog converter based ADCs. Therefore, novel analog techniques are developed for the three main blocks of an MDAC-based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. These techniques include self-biasing and inverter-based design for the flash quantizer and amplifier. Regarding the MDAC, it combines three techniques: unity feedback factor, insensitivity to capacitor mismatch, and current-mode reference shifting. In the second part of this work, the designed amplifier is implemented and experimentally characterized demonstrating its practical feasibility and performance. The final part of this work explores the design and implementation of a medium-low resolution high speed pipeline ADC incorporating all the developed circuits. Experimental results validate the feasibility of the techniques and demonstrate the attractiveness in terms of power dissipation and reduced area.
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Elkafrawy, Abdelrahman [Verfasser]. "Concept and design of a high speed current mode based SAR ADC / Abdelrahman Elkafrawy." Ulm : Universität Ulm, 2016. http://d-nb.info/1108434592/34.
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Ferreira, João Manuel Graça. "An high-speed parametric ADC and a co-designed mixer for CMOS RF receivers." Master's thesis, Faculdade de Ciências e Tecnologia, 2009. http://hdl.handle.net/10362/3933.
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Dissertação apresentada na faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de ComputadoresThe rapid growth of wireless communications and the massive use of wireless end-user equipments have created a demand for low-cost, low-power and low-area devices with tight specifications imposed by standards. The advances in CMOS technology allows, nowadays, designers to implement circuits that work at high-frequencies, thus, allowing the complete implementation of RF front ends in a single chip. In this work, a co-design strategy for the implementation of a fully integrated CMOS receiver for use in the ISM band is presented. The main focus is given to the Mixer and the ADC blocks of the presented architecture. The traditional approach used in RF design requires 50 matching buffers and networks and AC coupling capacitors between Mixer inputs and LNA and LO outputs. The codesign strategy avoids the use of DC choke inductors for Mixer biasing, because it is possible to use the DC level from the output of the LNA and the LO to provide bias to the Mixer. Moreover, since the entire circuit is in the same chip and the Mixer inputs are transistors gates, we should consider voltage instead of power and avoid the 50 matching networks. The proposed ADC architecture relies on a 4-bit flash converter. The main goals are to achieve low-power and high sampling frequency. To meet these goals, parametric amplification based on MOS varactors is applied to reduce the offset voltage of the comparators, avoiding the traditional and power-consuming approach of active pre-amplification gain stages.
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Sadeghifar, Mohammad Reza. "On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters." Licentiate thesis, Linköpings universitet, Elektroniska Kretsar och System, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-114274.
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High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency up-conversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element. In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatory pulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work. ΣΔ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal’s number of bits, still maintain the same resolution. By utilizing the ΣΔ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing ΣΔ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the ΣΔ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement. Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with ΣΔ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only two output levels available in the DAC, the static transfer function, regardless of the mismatch errors, is always given by a straight line. In this work, the design of SDFIR filter is done through an optimization procedure where the ΣΔ noise transfer function is also taken into account. Different constraints are defined for different applications in formulation of the SDFIR optimization problem. For a given radio transmitter application the objective function can be defined as, e.g., the hardware cost for SDFIR implementation while the constraint can be set to fulfill the radio transmitter spectral emission mask.
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Kandala, Veera Raghavendra Sai Mallik. "ENERGY EFFICIENT CIRCUIT TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER ADC." OpenSIUC, 2012. https://opensiuc.lib.siu.edu/dissertations/539.
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Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in the design of low power electronics. Significant portions of CS-SAR ADC power are consumed by CS capacitor arrays and comparator circuits. This Dissertation presents circuit techniques to reduce the power consumption of both CS capacitor array and the latch comparator during ADC operations. The impacts of the proposed techniques on ADC accuracies are analyzed and circuit techniques are presented to address the accuracy concerns. The dissertation also presents techniques to cope with capacitor mismatches, which becomes more significant with the use of very small unit capacitors in the CS array. These techniques rely on a novel programmable CS capacitor array that allow optimally grouping the unit capacitors. Based on a 0.13um CMOS technology the proposed techniques are verified with extensive circuit simulation. Post layout simulations are done to evaluate the proposed techniques for energy efficient CS capacitor array.
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Micheva, Nora Iordanova. "Design port and optimization of a high-speed SAR ADC comparator from 65nm to 0.11[mu]M." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/66446.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2011."May 2011." In title on title page, "[mu]" appears as lower case Greek letter. Cataloged from PDF version of thesis.
Includes bibliographical references (p. 50-51).
As the world continues to do more and more of its signal processing digitally, there is an ever increasing need for high speed high precision signal processors in consumer applications such as digital photography. Technological progress in CMOS fabrication has allowed chips to be made on nano scale processes, but this still comes at a steep price. Especially in chips for which analog components are a priority over digital components, some of the benefits of using nano scale processes diminish, such as smaller area. In these cases, it is worth investigating whether the same performance can be achieved with larger feature size, and therefore, cheaper processes. To that end, a three-stage comparator circuit for use in a digital camera SAR ADC has been ported from its original 65nm process to a 0.11[mu]m process. Its design has been analyzed and performance presented here. Additionally, an alternative latch-only architecture for the comparator has been designed and analyzed. In 0.11[mu]m the three-stage comparator operates at the same speed, 13% lower RMS noise contributing 0.9 bits difference, and 11% higher power than the original in 65nm. More noteworthy, the 0.11[mu]m latch-only comparator operates at 40% higher speed, equivalent noise, and 72% lower power.
by Nora Iordanova Micheva.
M.Eng.
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Baskaran, Balakumaar, and Hari Shankar Elumalai. "High-Speed Hybrid Current mode Sigma-Delta Modulator." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80060.
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The majority of signals, that need to be processed, are analog, which are continuous and can take an infinite number of values at any time instant. Precision of the analog signals are limited due to influence of distortion which leads to the use of digital signals for better performance and cost. Analog to Digital Converter (ADC), converts the continuous time signal to the discrete time signal. Most A/D converters are classified into two categories according to their sampling technique: nyquist rate ADC and oversampled ADC. The nyquist rate ADC operates at the sample frequency equal to twice the base-band frequency, whereas the oversampled ADC operates at the sample frequency greater than the nyquist frequency. The sigma delta ADC using the oversampling technique provides high resolution, low to medium speed, relaxed anti-aliasing requirements and various options for reconfiguration. On the contrary, resolution of the sigma delta ADC can be traded for high speed operation. Data sampling techniques plays a vital role in the sigma delta modulator and can be classified into discrete time sampling and continuous time sampling. Furthermore, the discrete time sampling technique can be implemented using the switched-capacitor (SC) integrator and the switched-current (SI) integrator circuits. The SC integrator technique provides high accuracy but occupies a larger area. Unlike the SC integrator, the SI integrator offers low input impedance and parasitic capacitance. This makes the SI integrator suitable for low supply voltage and high frequency applications. From a detailed literature study on the multi-bit sigma delta modulator, it is analyzed that, theneeds a highly linear digital to analogue converter (DAC) in its feedback path. The sigma delta modulators are very sensitive to linearity of the DAC which can degrade the performance without any attenuation. For this purpose T.C. Leslie and B. Singh proposed a Hybrid architecture using the multi-bit quantizer with a single bit DAC. The most significant bit is fed back to the DAC while the least significant bits are omitted. This omission requires a complex digital calibration to complete the analog to digital conversion process which is a small price to pay compared to the linearity requirements of the DAC. This project work describes the design of High-Speed Hybrid Current modeModulator with a single bit feedback DAC at the speed of 2.56GHz in a state-of-the-art 65 nm CMOS process. It comprises of both the analog and digital processing blocks, using T.C. Leslie and B. Singh architecture with the switched current integrator data sampling technique for low voltage, high speed operation. The whole system is verified mathematically in matlab and implemented using signal flow graphs and verilog a code. The analog blocks like switched current integrator, flash ADC and DAC are implemented in transistor level using a 65 nm CMOS technology and the functionality of each block is verified. Dynamic performance parameters such as SNR, SNDR and SFDR for different levels of abstraction matches the mathematical model performance characteristics.
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Ren, Saiyu Dr. "BROAD BANDWIDTH HIGH RESOLUTION ANALOG TO DIGITAL CONVERTERS: THEORY, ARCHITECTURE AND IMPLEMENTATION." Wright State University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=wright1205948819.
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Li, Xiangtao. "High-speed analog-to-digital conversion in SiGe HBT technology." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24652.
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Thesis (Ph.D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.Committee Chair: Cressler, John D.; Committee Member: Laskar, Joy; Committee Member: Lee, Chin-Hui; Committee Member: Morley, Thomas; Committee Member: Papapolymerou, John
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Öresjö, Per. "A High Speed Sigma Delta A/D-Converter for a General Purpose RF Front End in 90nm-Technology." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8706.
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In this report a transistor-level design of a GHz Sigma-Delta analog-to-digital converter for an RF front end is proposed. The design is current driven, where the integration is done directly over two capacitances and it contains no operational amplifiers.
The clock frequency used for verification was 2.5 GHz and the output band-width was 10 MHz. The system is flexible in that the number of internal bits can be scaled easily and in this report a three-bit system yielding an SNR of 76.5 dB as well as a four-bit system yielding an SNR of 82.5 dB are analyzed.
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Dinc, Huseyin. "A high-speed two-step analog-to-digital converter with an open-loop residue amplifier." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39572.
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It is well known that feedback is a very valuable tool for analog designers to improve linearity, and desensitize various parameters affected by process, temperature and supply variations. However, using strong global feedback limits the operation speed of analog circuits due to stability requirements. The circuits and techniques explored in this research avoid the usage of strong-global-feedback circuits to achieve high conversion rates in a two-stage analog-to-digital converter (ADC). A two-step, 9-bit, complementary-metal-oxide-semiconductor (CMOS) ADC utilizing an open-loop residue-amplifier is demonstrated. A background-calibration technique was proposed to generate the reference voltage to be used in the second stage of the ADC. This technique alleviates the gain variation in the residue amplifier, and allows an open-loop residue amplifier topology. Even though the proposed calibration idea can be extended to multistage topologies, this design was limited to two stages. Further, the ADC exploits a high-performance double-switching frontend sample-and-hold amplifier (SHA). The proposed double-switching SHA architecture results in exceptional hold-mode isolation. Therefore, the SHA maintains the desired linearity performance over the entire Nyquist bandwidth.
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Hedayati, Raheleh. "High-Temperature Analog and Mixed-Signal Integrated Circuits in Bipolar Silicon Carbide Technology." Doctoral thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-213697.
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Silicon carbide (SiC) integrated circuits (ICs) can enable the emergence of robust and reliable systems, including data acquisition and on-site control for extreme environments with high temperature and high radiation such as deep earth drilling, space and aviation, electric and hybrid vehicles, and combustion engines. In particular, SiC ICs provide significant benefit by reducing power dissipation and leakage current at temperatures above 300 °C compared to the Si counterpart. In fact, Si-based ICs have a limited maximum operating temperature which is around 300 °C for silicon on insulator (SOI). Owing to its superior material properties such as wide bandgap, three times larger than Silicon, and low intrinsic carrier concentration, SiC is an excellent candidate for high-temperature applications. In this thesis, analog and mixed-signal circuits have been implemented using SiC bipolar technology, including bandgap references, amplifiers, a master-slave comparator, an 8-bit R-2R ladder-based digital-to-analog converter (DAC), a 4-bit flash analog-to-digital converter (ADC), and a 10-bit successive-approximation-register (SAR) ADC. Spice models were developed at binned temperature points from room temperature to 500 °C, to simulate and predict the circuits’ behavior with temperature variation. The high-temperature performance of the fabricated chips has been investigated and verified over a wide temperature range from 25 °C to 500 °C. A stable gain of 39 dB was measured in the temperature range from 25 °C up to 500 °C for the inverting operational amplifier with ideal closed-loop gain of 40 dB. Although the circuit design in an immature SiC bipolar technology is challenging due to the low current gain of the transistors and lack of complete AC models, various circuit techniques have been applied to mitigate these problems. This thesis details the challenges faced and methods employed for device modeling, integrated circuit design, layout implementation and finally performance verification using on-wafer characterization of the fabricated SiC ICs over a wide temperature range.QC 20170905
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Alfredsson, Jon. "Design of a parallel A/D converter system on PCB : For high-speed sampling and timing error correction." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1201.
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The goals for most of today’s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with"state-of-the-art"components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically.
In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors.
This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system’s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvementsto achieve even higher performance.
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Mariano, André Augusto. "Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications." Thesis, Bordeaux 1, 2008. http://www.theses.fr/2008BOR13644/document.
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La chaîne de réception des téléphones mobiles de dernière génération utilisent au moins deux étages de transposition en fréquence avant d'effectuer la démodulation en quadrature. La transposition en fréquence augmente la complexité du système et engendre de nombreux problèmes tels que la limitation de l'échelle dynamique et l'introduction de bruit issu de l'oscillateur local. Il est alors nécessaire d'envisager une numérisation du signal le plus près possible de l'antenne. Cette dernière permet la conversion directe d'un signal analogique en un signal numérique à des fréquences intermédiaires. Elle simplifie ainsi la conception globale du système et limite les problèmes liés aux mélangeurs. Pour cela, des architectures moins conventionnelles doivent être développées, comme la conversion analogique-numérique utilisant la modulation Sigma-Delta à temps continu. La modélisation comportementale de ce convertisseur analogique-numérique, ainsi que la conception des principaux blocs ont donc été l'objet de cette thèse. L'application d'une méthodologie de conception avancée, permettant la simulation mixte des blocs fonctionnels à différents niveaux d'abstraction, a permis de valider aussi bien la conception des circuits que le système global de conversion. En utilisant une architecture à multiples boucles de retour avec un quantificateur multi-bit, le convertisseur Sigma-Delta passe bande à temps continu atteint un rapport signal sur bruit (SNR) d'environ 76 dB dans une large bande de 20MHzWireless front-end receivers of last generation mobile devices operate at least two frequency translations before I/Q demodulation. Frequency translation increases the system complexity, introducing several problems associated with the mixers (dynamic range limitation, noise injection from the local oscillator, etc.). Herein, the position of the analog-to-digital interface in the receiver chain can play an important role. Moving the analog-to-digital converter (ADC) as near as possible to the antenna, permits to simplify the overall system design and to alleviate requirements associated with analog functions (filters, mixers). These currently requirements have led to a great effort in designing improved architectures as Continuous-Time Delta-Sigma ADCs. The behavioural modeling this converter, although the circuit design of the main blocks has been the subject of this thesis. The use of an advanced design methodology, allowing the mixed simulation at different levels of abstraction, allows to validate both the circuit design and the overall system conversion. Using a multi-feedback architecture associated with a multi-bit quantizer, the continuous-time Bandpass Delta-Sigma converter achieves a SNR of about 76 dB in a wide band of 20MHz
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Anderson, Christopher R. "A Software Defined Ultra Wideband Transceiver Testbed for Communications, Ranging, or Imaging." Diss., Virginia Tech, 2006. http://hdl.handle.net/10919/29026.
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Impulse Ultra Wideband (UWB) communications is an emerging technology that promises a number of benefits over traditional narrowband or broadband signals: extremely high data rates, extremely robust operation in dense multipath environments, low probability of intercept/detection, and the ability to operate concurrently with existing users. Unfortunately, most currently available UWB systems are based on dedicated hardware, preventing researchers from investigating algorithms or architectures that take advantage of some of the unique properties of UWB signals.
This dissertation outlines the development of a general purpose software radio transceiver testbed for UWB signals. The testbed is an enabling technology that provides a development platform for investigating ultra wideband communication algorithms (e.g., acquisition, synchronization, modulation, multiple access), ranging or radar (e.g., precision position location, intrusion detection, heart and respiration rate monitoring), and could potentially be used in the area of ultra wideband based medical imaging or vital signs monitoring. As research into impulse ultra wideband expands, the need is greater now than ever for a platform that will allow researchers to collect real-world performance data to corroborate theoretical and simulation results.
Additionally, this dissertation outlines the development of the Time-Interleaved Analog to Digital Converter array which served as the core of the testbed, along with a comprehensive theoretical and simulation-based analysis on the effects of Analog to Digital Converter mismatches in a Time-Interleaved Sampling array when the input signal is an ultra wideband Gaussian Monocycle. Included in the discussion is a thorough overview of the implementation of both a scaled-down prototype as well as the final version of the testbed. This dissertation concludes by evaluating the of the transceiver testbed in terms of the narrowband dynamic range, the accuracy with which it can sample and reconstruct a UWB pulse, and the bit error rate performance of the overall system.Ph. D.
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Raymundo, Luyo Fernando Rodolfo. "Apport de la technologie d’intégration 3D à forte densité d’interconnexions pour les capteurs d'images CMOS." Thesis, Toulouse, ISAE, 2016. http://www.theses.fr/2016ESAE0018.
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Ce travail a montré que l’apport de la technologie d’intégration 3D, permet de surmonter les limites imposées par la technologie monolithique sur les performances électriques (« coupling » et consommation) et sur l’implémentation physique (aire du pixel) des imageurs. Grâce à l’analyse approfondie sur la technologie d’intégration 3D, nous avons pu voir que les technologies d’intégration 3D les plus adaptées pour l’intégration des circuits dans le pixel sont : 3D wafer level et 3D construction séquentielle. La technologie choisie pour cette étude, est la technologie d'intégration 3D wafer level. Cela nous a permis de connecter 2 wafers par thermocompression et d’avoir une interconnexion par pixel entre wafers. L’étude de l’architecture CAN dans le pixel a montré qu’il existe deux limites dans le pixel : l’espace de construction et le couplage entre la partie analogique et numérique « digital coupling ». Son implémentation dans la technologie 3D autorise l’augmentation de 100% l’aire de construction et la réduction du « digital coupling » de 70%. Il a été implémenté un outil de calcul des éléments parasites des structures 3D. L’étude des imageurs rapides, a permis d’étendre l’utilisation de cette technologie. L’imageur rapide type « burst » a été étudié principalement. Cet imageur permet de dissocier la partie d’acquisition des images de la sortie. La limite principale, dans la technologie monolithique, est la taille des colonnes (pixels vers mémoires). Pour une haute cadence d’acquisition des images, il faut une grande consommation de courant. Son implémentation dans la technologie 3D a autorisé à mettre les mémoires au-dessous des pixels. Les études effectuées pour ce changement (réduction de la colonne à une interconnexion entre wafers), ont réduit la consommation totale de 90% et augmenté le temps d’acquisition des images de 184%, en comparaison à son pair monolithiqueThis work has shown that the contribution of 3D integration technology allows to overcome the limitations imposed by monolithic technology on the electrical performances (coupling and consumption) and on the physical implementation (area of the pixel) of imagers. An in-depth analysis of the 3D integration technology has shown that the most suitable 3D integration technologies for the integration of the circuits at the pixel level are: 3D wafer level and 3D sequential construction. The technology chosen for this study is the 3D wafer level integration technology. This allows us to connect 2 wafers by thermocompression bonding and to have an interconnection or “bonding point” par pixel between wafers. The study of the architecture CAN at the pixel level showed that there are two limits in the pixel: the construction area and the coupling between the analog and digital part «digital coupling». Its implementation in 3D technology allows the construction area to be increased by 100% and the digital coupling reduced by 70%. It has been implemented a tool for computing the parasitic elements of 3D structures. The study of high speed imagers has allowed the use of this technology to be extended. The "burst" imager was mainly studied. This kind of imager’s architecture can dissociate the image acquisition from the output part. The main limit, in monolithic technology, is the size of the columns (pixels to memories). For a high rate of image acquisition, a high current consumption is required. Its implementation in 3D technology allowed to put the memories below the pixels. The studies carried out for this change (reduction of the column to an interconnection between wafers) reduced the total consumption by 90% and increased the acquisition time of the images by 184%, compared to its monolithic peer
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Zeman, Pavel. "Návrh a realizace pěti-úrovňového kvantovacího obvodu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218776.
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The work deals with design and realisation of the five-levels high-speed quantizer using switched-current technique (SI). The main aim is to use an advantage of switched-current technique like potential of the high-speed operation and to minimize disadvantages at all. Flash structure of the quantizer is used to ensure high-speed operation. It is supposed that the quantizer will be part of greater integrated systems such as higher-order delta-sigma modulators. Simulations are performed in CADENCE simulation tool using AMIS CMOS 0,7 µm technologic process.
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Nouman, Ziad. "Užití programovatelných hradlových polí v systémech průmyslové automatizace." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-234615.
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Tato disertační práce se zabývá využitím programovatelných hradlových polí (FPGA) v diagnostice měničů, využívajících spínaných IGBT tranzistorů. Je zaměřena na budiče těchto výkonových tranzistorů a jejich struktury. Přechodné jevy veličin, jako jsou IG, VGE, VCE během procesu přepínání (zapnutí, vypnutí), mohou poukazovat na degradaci IGBT. Pro měření a monitorování těchto veličin byla navržena nová architektura budiče IGBT. Rychlé měření a monitorování během přepínacího děje vyžaduje vysokou vzorkovací frekvenci. Proto jsou navrhovány paralelní vysokorychlostní AD převodníky (> 50 MSPS). Práce je zaměřena převážně na návrh zařízení s FPGA včetně hardware a software. Byla navržena nová deska plošných spojů s FPGA, která plní požadované funkce, jako je řízení IGBT pomocí vícenásobných paralelních koncových stupňů, monitorování a diagnostiku, a propojení s řídicí jednotkou měniče.
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Hsu, Chia-Hao, and 許家豪. "A 10-bit High-Speed Subrange ADC." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/74555666386339650556.
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碩士國立臺灣大學
電子工程學研究所
102
A low-noise phase-detector-based (PD-based) comparator is proposed for subrange analog-to-digital converters (ADCs) in this thesis. It can reduce the thermal-induced noise as well as the probability of the metastability. The 10-bit subrange ADC is composed of a 3.9-bit flash ADC and a 7-bit SAR ADC. The proposed ADC was fabricated in a 40-nm LP CMOS technology. The ADC achieves 54.41-dB SNDR at 160MS/s under a 1.1V supply voltage and consumes 2.7mW. The figure-of-merit (FOM) is 39.4 fJ/conversion-step. The active area is 0.0475 mm2.
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Huang, Wei-Chia, and 黃維家. "A High-Speed Time-Interleaved SAR ADC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/48851480069020999338.
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碩士國立臺灣大學
電子工程學研究所
104
Analog-to-digital converter (ADC) has to operate at ultra-high speed with low to medium resolution in the next-generation wireless communication systems. A 6-bit 4.5 GS/s time-interleaved SAR ADC in 40 nm CMOS general–process (GP) technology is proposed. By combining the front-end input buffers and the grouping technique into the time-interleaved architecture, the input capacitance effectively decreases and the available settling of input buffers increases. The proposed 16-channel time-interleaved SAR ADC achieves the performance of high-speed sampling rate and high input bandwidth. A zero-crossing detection technique is employed to correct timing skew among sub-ADCs. Gain and offset mismatches between sub-ADCs are calibrated in the digital domain. Asynchronous processing and monotonic capacitor switching technique used in the single-channel SAR ADC make the sub-ADC high speed and power-efficiency. Furthermore, AWCA technique solves the dynamic offset problem of the comparator in the sub-ADC. The measurement results show that ADC exhibits DNL of +0.17/-0.29 LSB and INL of +0.20/-0.18 LSB at 4 GS/s with Fin of 50 MHz. SNDR and SFDR are 32.15 dB and 41.04 dB at 4.5 GS/s with Fin of 1 GHz. The power consumption is 24.9 mW at 1.2 V supply voltage. As a result, the FoM (Power/2ENOB/FS) is 159 fJ/conversion-step. The whole chip including pads occupies 1.275 mm2 while area of core circuit is 0.195 mm2.
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Tseng, Huan-Chieh, and 曾煥傑. "A 1.2V 10-bit High-Speed Pipelined ADC." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/92358876564535883847.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
96
This thesis presents a 1.2V 10-bit CMOS two-channel time-interleaved pipelined ADC in a standard 0.13-μm CMOS process. For high conversion speed, the first stage with divided residue gain is proposed to increase the feedback factor of the MDAC. In order to reduce the mismatch-effects, opamp-sharing technique is applied between two channels, and the proposed clock generator is designed to suppress the sampling-time mismatch. According to the measurement results, the prototype ADC exhibits a DNL of -0.49/+0.43LSB and an INL of -1.05/+0.86LSB at the sampling rate of 50MS/s. For 1MHz input frequency, the SNDR and SFDR achieve 56.53dB and 68.38dB at 50MS/s. The SNDR and SFDR are reduced to 37.63dB and 41.61dB at 250MS/s for 1MHz input. The power consumption is 106mW at the conversion rate of 250MS/s. The chip with pads occupies 1.3mm2. Chapter 1 introduces the pipelined ADC architecture. Chapter 2 discusses the channel mismatch effects in the time-interleaved ADC system. A proposed architecture to increase conversion speed and to reduce mismatch effects is given in Chapter 3. Detail circuit implementation and simulation result are shown in Chapter 4. Chapter 5 presents the test setup and measurement results. Finally, conclusions are summarized in Chapter 6.
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Huang, Cheng-Chieh, and 黃政傑. "Study on High-speed Low-power SAR ADC." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/65587942319732896750.
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碩士國立暨南國際大學
電機工程學系
98
This research proposes a high-speed and low-power DAC, which is apply to Successive Approximation ADC. Compared with general redistribution capacitor DAC which has to charge each capacitor under sampling condition, DAC proposed in this research charges only one capacitor and effectively promotes the speed. As to the reference voltage, DAC takes only half of the general one, and obviously reduces the power consumption. According to the simulation result, the designed SAR ADC can operate at 2MHz. The Signal-to-Noise and Distortion Ratio is 59.95dB when the input frequency is 100KMz and the effective number of bit is 9.67 bit. The Integral Nonlinearity is 0.7LSB. The Differential Nonlinearity is 0.4LSB. The power dissipation is 1.8mW. The chip layout area is 1030um*1030um.
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Tseng, Huan-Chieh. "A 1.2V 10-bit High-Speed Pipelined ADC." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2707200820291300.
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Luo, Shih-Fen, and 羅世分. "A New Approach for Nonlinearity Test of High Speed DAC." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/91272931626500865944.
Full textAbstract:
碩士雲林科技大學
電子與資訊工程研究所
96
In this work, we propose a novel test scheme for high speed digital-to-analog converter (DAC) based on under-sampling technique. The under-sampling technique is constructed by a pulse-width-modulation (PWM) modulator. The DAC output signal is modulated through a low frequency sinusoidal carrier and converted to low speed pulse signal. The pulse width of low speed pulse signal can be measured using conventional logic analyzer and the nonlinearity error of DAC can be estimated by analyzing the variation of pulse width. An experiment an 8-bit 50~300MS/s DAC has shown very good results and only requires a set of instruments which have sample rate lower than that of the circuit-under-test (CUT).
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Cheng, Wei-Sheng, and 程韋盛. "A High Speed Current-Steering DAC for Powerline Communication System." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/84476907365301286957.
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碩士國立臺灣大學
電子工程學研究所
101
A 10-bit current-steering digital-to-analog converter (DAC) has been proposed for high speed communication systems. This study is used for the transmitter (Tx) of the powerline communication (PLC) analog-front-end (AFE), and it reaches the standard of the HomePlug AV2. And the DAC has also been combined with the line driver as the transmitter of the whole system. In order to improve static performance, we use 6-4 segmented decoding architecture to get good matching and reduce the glitch. Furthermore, we implemented our current source array as common centroid type and adding dummy current sources around the array to reduce the mismatch between edge and center. For dynamic performance consideration, the proposed DAC uses a technique as digital random-return-to-zero (DRRZ) [10][11] to achieve good performance for high speed sampling frequency. The test chip was fabricated in TSMC 90 nm CMOS technology and occupied 0.42 mm2 for active area. The supplies for the analog and digital circuits are 2.5V and 1.2V. The maximum INL and DNL are 0.8 LSB and 0.3 LSB respectively. The SFDR is up to 40.09 dB for 1.25GS/s of Nyquist-rate sampling. The power consumption is 58mW.
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Wu, Shih-Wei, and 吳世偉. "High-Speed and Energy-Efficient Time-Interleaved SAR ADC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/p7975n.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
105
Recently, hundreds MS/s to 1GS/s medium resolution Analog-to-Digital Convertors (ADCs) are used extensively in applications, for the purpose to replace the front end of the receiver. This thesis proposed a high-speed and energy-efficient time-interleaved subranging SAR ADC that utilizing settling time relief technique [1] to improve overall circuit arrangement by using two 5-bit coarse ADCs to assist 10-bit four channels fine SAR ADC architecture. To solve the problem that skew mismatch within sub-ADCs in subranging architecture, we propose a low-skew bootstrap circuit without additional calibration circuit. This time-interleaved SAR ADC can achieve the conversion rate of 1GS/s with near 220 MHz input frequency, and 500MS/s with Nyquist rate, SNDR are 49.51 dB and 51.45 dB, respectively. The power consumption is 5.899mW and 3.0245mW, respectively. And, getting the good FoM of 24.15 fJ/c.-s. and 19.83 fJ/c.-s. The active area is 0.0459 mm2. It is suitable for the energy-efficient wireless communication and Ethernet network application.
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Cheng, Li-Hsin, and 鄭立新. "An Area Efficient High Speed SAR ADC in 0.18um." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/66346500161548759558.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
102
SAR ADC, with simple structure and energy efficiency becomes one of the recent choices in battery-endurance concerned devices and data acquisition systems. In this thesis, we propose a “voltage-jumping” SAR architecture operating at 50MS/s in 0.18um that is area efficient and achieves high speed. The circuit solves the MSB DAC settling error physically and hence uses only 1/4 of total capacitor array area compared to the conventional structure without shrinking the size of unit capacitor. Also, the switching energy is smallest because the most critical MSB switching does not consume power and the rest of bits are switched monotonically with smaller capacitance. As for measurement results, 0.1MHz input sinusoidal signal is fed into the ADC operating at 50MS/s, 40MS/s and 25MS/s, and the SNDR, SFDR and ENOB of the ADC are 35.31 dB, 45.81 and 5.57 bits for 50MS/s, 33.90 dB, 41.58 and 5.34 bits for 40MS/s and 33.82 dB, 39.71 and 5.33 bits for 25MS/s. The post-sim power consumption and the FoM of the ADC in 0.18um at 50MS/s are 2.3mW and 63 fJ/convstep; whereas the power consumption and the FoM of the measured circuit are 2.5mW and 1 pJ/convstep. In future works, the problems for unsatisfied measurement in this 0.18um chip discovered are all rectified in 90nm. The post-sim 90nm “voltage-jumping” SAR ADC operating at 100MS/s with 1.3mW is present. Also, in order to accelerate the speed of ADC, a new idea of two-stage pipelined SAR ADC is launched to prevent the use of OP-amp to deliver signal to the next stage.
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Wang, Yu-Chun, and 王玉君. "8-BIT TWO-STEP ADC FOR HIGH SPEED APPLICATIONS." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/71186879580444649840.
Full textAbstract:
碩士大同大學
通訊工程研究所
94
A two-step ADC is proposed for high speed application. The architecture of the coarse ADC is a flash-type ADC, and the fine ADC is an interpolation ADC. The 8-bit resolution of the ADC is divided into 3.36-bit in coarse ADC and 5-bit in fine ADC with 12% overlap. Comparing with conventional method, this work reduces 6 transition points in coarse ADC to decrease the loading of T/H and improve speed. However, less offset tolerance is required in coarse ADC comparators. Although offset cancellation techniques can be employed to relax the requirement, large parasitic capacitance would reduce the cancellation effectiveness. Detailed analysis for differential mode and single ended offset compensation methods will be given to predict the compensation error and to achieve the required offset constraint without over-designing.
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Chiou, Cheng-Yi, and 邱承毅. "High Speed ADC Design for MB-OFDM UWB Application." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/10943357968498760245.
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碩士中原大學
電子工程研究所
95
This thesis proposes a 6-bit high speed and low power flash ADC with sampling period of 900ps and this circuit is utilized in the receiver of MB-OFDM UWB system. In low power circuit design, the design method proposed in this thesis has three effects: (1)reduce the charge current of dynamic regenerative comparator and dynamic logic circuit, (2)lower down the load capacitance of each circuit, (3)reduce the number of output logic transitions in digital circuits. The circuits proposed in this thesis can largely reduce the power consumption of flash ADC in the condition of not seriously affect the circuit operation speed. In the subcircuits of flash ADC, this thesis improves the performance of comparator array and thermometer code to binary code encoder. For comparator array, the proposed method is to apply a lower supply voltage to reduce the power consumption of comparator array. In the circuit of encoder, in addition to apply a lower supply voltage, an inverter array is also utilized to lower down the load capacitance of comparator array and reduce the number of output logic transitions in 1-of-N encoder. The circuit simulations in this thesis are based on TSMC CMOS 0.18µm process, and the simulation tool is Spectre. The simulation result shows that the proposed flash ADC can operate correctly in the sampling period of 900ps. As this circuit is operated in the sampling frequency of 1GHz, its power consumption is only 18.28mW.
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Lee, Chien-Wei, and 李建緯. "A 12-bit High Speed DAC with Novel Self-Calibrated Technique." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/88294442353421270077.
Full textAbstract:
碩士國立中正大學
電機工程所
95
We design the Digital-to-Analog Converter (DAC) with Current-Steering architecture to achieve high-speed specification and propose a novel calibration technique in this thesis. The technique could directly suppress the differential nonlinearity (DNL) and integral nonlinearity (INL) and furthermore lift up dynamic performance to increase the linearity of whole DAC effectively. By this technique, we have attained the destination of high speed, high resolution and low power consumption because of successfully improving the drawback caused by requiring large scale area of unit source to drop random error. The high-speed 12-bit Digital-to-Analog Converter, whose maximum sampling rate is 400MS/s, is implemented in TSMC CMOS process. New digital calibration circuit can keep the performance in an outstanding level even with a dramatically slight unit source area and lack of specific output stage [17][18].
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Lin, Sheng-feng, and 林聖峯. "Design of low thermal sensitivity BIST circuits for high speed DAC." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/85404519105617439782.
Full textAbstract:
博士國立雲林科技大學
工程科技研究所博士班
101
Along with the advance in consumer electronics and communication technologies, high speed data converters were applied to many applications. The data converter testing is one of the most challenging problems in the area of analog and mixed-signal testing. As an interface between digital systems and analog world, the digital to analog converter (DAC) is one of the most widely used mixed-signal integrated circuits. Conventional DAC test methods require measurement equipments with higher speed than the circuit under test to sample and characterize the performance of the circuit accurately. Consequently, the design and manufacturing of instruments is really a challenge and extremely difficult for those high speed DACs. In addition, even worse, interference and noise in test environment also make test result distortedly. To enhance the testability, built-in self-test (BIST) is the promising way to measure analog signal in chip accurately. However, due to the heat originated from continuous high speed operation of the circuit under test, the characteristics and functions of BIST circuit may drift according to the temperature variation of chip. For advanced fabrication process with shorter transistor channel length, the temperature dependence is more serious because of acute impact on carrier mobility and threshold voltage. The BIST circuit could be out of controlled or unavailable for the worst. For this reason, this dissertation presents a BIST scheme for estimating the nonlinearity errors of DAC and employs well-developed low thermal sensitivity processing circuits to enhance the reliability of testing results as well. Through applying dual-under-sampling approach and pulse-width-modulation (PWM), the DAC output signal is modulated into low-speed narrow-width pulse streams. The nonlinearity errors of DAC are proportional to pulse width of modulated signal which can be quantified as digital representation. To enhance the accuracy of modulators for PWM, a current-mode comparator is proposed instead of voltage-mode comparator. A cyclic time-to-digital converter (TDC) is also proposed to measure the pulse width of signal on chip. All of the crucial circuits are designed with temperature compensation technique, so that the measurement error can be reduced when the temperature varies with continuous operation of DAC at high speed test.
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Castro, Scorsi Rafael. "A data interface for ultra high speed ADC integrated circuits." 2011. http://hdl.handle.net/2152/22769.
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Analog-to-Digital (ADC) converters have been an essential building block of electronic design for years. As ADC components get faster, new data interfaces are required in order to keep up with the faster data rates while providing very high data integrity. The objective of this project was to design an inter-IC ADC interface for converters with data bandwidths as high as 56 Gigabytes per second. The main goal for this project was to create a mechanism for interfacing a general-purpose high-speed ADC integrated circuit with an FPGA. This will enable applications that can benefit from the reprogrammability offered by FPGAs as well as those that could not justify a monolithic integrated solution for cost reasons. The interface presented is based on the physical layer of the IEEE 10GBASE-KR specification for 10 Gigabit Ethernet (10GE). Leveraging this specification provides significant benefits as it defines most of the services required by the interface, such as effcient encoding and forward error correction. Furthermore, using an interface as widely used as 10GBASE-KR leverages significant validation work as well as widespread support in mainstream FPGAs and by IP providers. The report will provide an analysis of the requirements of the ADC interface and a description of the architecture proposed. One key aspect of the design of the system was the analysis of the e ects of random bit errors in the channel and how to deal with them while making a robust interface. The causes of error are described and the critical sections of the system were simulated to validate the choice of Forward Error Correction solution. Finally, the report describes the working prototype system built in an FPGA board and provides a description of the performance achieved.text
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Chang, Chun-Hao, and 張峻豪. "A High Effective Resolution Bandwidth High Speed Asynchronous Successive Approximation Register ADC." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/54170690466820934535.
Full textAbstract:
碩士國立中興大學
電機工程學系所
103
This thesis presents a high effective resolution bandwidth (ERBW) high speed asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with differential input signals. This ADC is designed as the sub-ADC that constructs a time-interleaved ADC. Therefore, the range of ERBW is much considered. In addition, parallel signal paths are used in the control logic circuit to decrease the delay time of producing triggering signals, which enlarges the room for speeding up the sampling rate of the ADC compared with the conventional design. Chip sarf2_32 that was fabricated under TSMC 90nm RF process was measured 6.7 bits at low frequency while it was measured 3.8 bits at high frequency. As the input frequency goes higher, the ADC''s performance gets worse. This problem can be solved with the use of cross-couple MOS in the sample and hold circuit. The measured power consumption is 4.5mW, and the FOM is 321fJ/conversion-step. Fabricated under TSMC 90nm GUTM process, chip sarf2_33 was measured 5.6 bits at low frequency and it was measured around 4.8 bits at high frequency. The results of measurement are similar to that of FF corner simulation. The measured power consumption is 5.61mW, and the FOM is 692fJ/conversion-step. Source followers are used at the input as input buffers for sarf2_34. Above 7 bits of ENOB were simulated under SS, TT, and FF corner from low frequency to high frequency. The simulated power consumption is 5.8mW, and the FOM is 206fJ/conversion-step. This chip has been taped out under TSMC 90nm GUTM process.
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Chien-Kai, Hung. "High-speed flash ADC with new averaging network termination method." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2507200618535100.
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Tyshchenko, Oleksiy. "Clock and Data Recovery for High-speed ADC-based Receivers." Thesis, 2011. http://hdl.handle.net/1807/27606.
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This thesis explores the clock and data recovery (CDR) for the high-speed blind-sampling ADC-based receivers. This exploration results in two new CDR architectures that reduce the receiver complexity and save the ADC power and area compared to the previous work. The two proposed CDR architectures constitute the primary contributions of this thesis. The first proposed architecture, a 2x feed-forward CDR architecture, eliminates the interpolating feedback loop, used in the previously reported CDRs, in order to reduce the CDR circuit complexity. Instead of the feedback loop, the proposed architecture uses a feed-forward topology to recover the phase and data directly from the blind digital samples of the received signal. The 2x feed-forward CDR architecture was implemented and characterized in a 5 Gb/s receiver test-chip in 65 nm CMOS. The test-chip measurements confirm that the CDR successfully recovers the data with bit error rate (BER) < 10e-12 in the presence of jitter. The second proposed architecture, a fractional-sampling-rate (FSR) CDR architecture, reduces the receiver sampling rate from the typical integer rate of 2x the baud rate to a fractional rate between 2x and 1x in order to reduce the ADC power and area. This architecture employs the feed-forward topology of the first contribution of this thesis to recover the phase and data from the fractionally-spaced digital samples of the signal. To verify the proposed FSR CDR architecture, a 1.45x receiver test-chip was implemented and characterized in 65 nm CMOS. This test-chip recovers 6.875 Gb/s data from the ADC samples taken at 10 GS/s. The measurements confirm a successful data recovery in the presence of jitter with BER < 10e-12. With sampling at 1.45x, the FSR CDR architecture reduces the ADC power and area by 27.3% compared to the 2x feed-forward CDR architecture, while the overall receiver power and area are reduced by 12.5%.
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Hung, Chien-Kai, and 洪健凱. "High-speed flash ADC with new averaging network termination method." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/01756134253596784517.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
94
A 1.6 GS/s 6-bit CMOS flash ADC using reversed-reference dummy method is demonstrated in a standard 0.18-μm CMOS process. The proposed method improves linearity error at the boundary of offset averaging networks. The prototype circuit exhibits an INL of +0.32/-0.28 LSB and a DNL of +0.28/-0.28 LSB. The SNDR and SFDR achieve 32 and 44 dB at 1.6 GS/s for Nyquist input frequency. The ADC consumes 350 mW at 1.8 V supply and occupies an active chip area of 0.56 mm2.
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Hu, Ting-Wei, and 胡庭維. "Input Buffer Improved High Speed Asynchronous Successive Approximation Register ADC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/70012398542253459114.
Full textAbstract:
碩士國立中興大學
電機工程學系所
104
This thesis presents an input buffer improved high speed Asynchronous successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The application is as a sub-ADC of a time-interleaved ADC. In order to enhance the converter’s effective number of bits, the input buffer is added. The frist design, Sarf2_34 ,has oscillations found during measurement. Thus a second design Sarf2_35 improve the input buffer circuit to solve, the output waveform oscillation issue. With TSMC 90nm GUTM manufacturing process, and sampling frequency as 166MHZ, measurement results of Sarf2_35 chip is obtained. When input frequency is 10MHZ ,the effective number of bits is 6.09bit.When input frequency is 1GHZ, the effective number of bits is 3.48bit.
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Chen, Hongbo. "Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters." Thesis, 2011. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10522.
Full textAbstract:
Nowadays, the multi-standard wireless receivers and multi-format video processors have created a great demand for integrating multiple standards into a single chip. The multiple standards usually require several Analog to Digital Converters (ADCs) with different specifications. A promising solution is adopting a power and area efficient reconfigurable ADC with tunable bandwidth and dynamic range. The advantage of the reconfigurable ADC over customized ADCs is that its power consumption can be scaled at different specifications, enabling optimized power consumption over a wide range of sampling rates and resulting in a more power efficient design. Moreover, the reconfigurable ADC provides IP reuse, which reduces design efforts, development costs and time to market.
On the other hand, software radio transceiver has been introduced to minimize RF blocks and support multiple standards in the same chip. The basic idea is to perform the analog to digital (A/D) and digital to analog (D/A) conversion as close to the antenna as possible. Then the backend digital signal processor (DSP) can be programmed to deal with the digital data. The continuous time (CT) bandpass (BP) sigma-delta ADC with good SNR and low power consumption is a good choice for the software radio transceiver.
In this work, a proposed 10-bit reconfigurable ADC is presented and the non-overlapping clock generator and state machine are implemented in UMC 90nm CMOS technology. The state machine generates control signals for each MDAC stage so that the speed can be reconfigured, while the power consumption can be scaled. The measurement results show that the reconfigurable ADC achieved 0.6-200 MSPS speed with 1.9-27 mW power consumption. The ENOB is about 8 bit over the whole speed range.
In the second part, a 2-bit quantizer with tunable delay circuit and 2-bit DACs are implemented in TSMC 0.13um CMOS technology for the 4th order CT BP sigma-delta ADC. The 2-bit quantizer and 2-bit DACs have 6dB SNR improvement and better stability over the single bit quantizer and DACs. The penalty is that the linearity of the feedback DACs should be considered carefully so that the nonlinearity doesn't deteriorate the ADC performance. The tunable delay circuit in the quantizer is designed to adjust the excess loop delay up to +/- 10% to achieve stability and optimal performance.
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Lin, Yu-Hong, and 林育弘. "A 16-bit, High-Speed DAC with Random Multiple Data-Weighted Averaging Algorithm." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/72nnnu.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
90
Current-steering DACs have intrinsic high-speed characteristics and are commonly used in wide-band communication systems today. However, element mismatch will cause harmonic distortion and thus limits their performance. This thesis proposes a new algorithm called Random Multiple Data Weighted Averaging (RMDWA) to reduce harmonic distortions due to element mismatch. RMDWA can be used to randomize tones such that spurious-free dynamic range (SFDR) and multi-tone power tone (MPTR) are increased. In addition, low-complexity digital circuit used to implement RMDWA algorithm is presented in this thesis. Performance equations and quantitative performance analyses of RMDWA are also derived. A 16-bit high-speed current-steering DAC is implemented in this thesis. The DAC includes a 6-bit thermometer-decoded MSB with RMDWA algorithm, a 5-bit thermometer-decoded upper LSB (ULSB) and a 5-bit binary-decoded lower LSB (LLSB). The new QN rotated-walk switching scheme is also proposed to obtain high accuracy without trimming or tuning. QN rotated-walk switching scheme can effectively compensate 1st–order and 2nd–order errors caused by current sources mismatch. In addition, a new latch is designed to increase conversion speed and reduce noise. The post-layout simulation shows that it can achieve 102/94/84dBc SFDRs under a 40-MHz clock rate with 780KHz/5MHz/18MHz signal frequencies, respectively. With 2.7V analog and 2.2V digital supplies, it has power consumption of 112mW for a clock rate of 40 MHz. The DAC is fabricated with TSMC 0.25um single-poly, five-metal process. The active die area is 1.9mm x 0.9mm.
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Li, Jipeng. "Accuracy enhancement techniques in low-voltage high-speed pipelined ADC design." Thesis, 2003. http://hdl.handle.net/1957/28872.
Full textAbstract:
Pipelined analog to digital converters (ADCs) are very important building
blocks in many electronic systems such as high quality video systems, high
performance digital communication systems and high speed data acquisition systems.
The rapid development of these applications is driving the design of pipeline ADCs
towards higher speed, higher dynamic range, lower power consumption and lower
power supply voltage with the CMOS technology scaling. This trend poses great
challenges to conventional pipelined ADC designs which rely on high-gain
operational amplifiers (opamps) and well matched capacitors to achieve high accuracy. In this thesis, two novel accuracy improvement techniques to overcome the
accuracy limit set by analog building blocks (opamps and capacitors) in the context of
low-voltage and high-speed pipelined ADC design are presented. One is the time-shifted
correlated double sampling (CDS) technique which addresses the finite opamp
gain effect and the other is the radix-based background digital calibration technique
which can take care of both finite opamp gain and capacitor mismatch. These methods
are simple, easy to implement and power efficient. The effectiveness of the proposed
techniques is demonstrated in simulation as well as in experiment.
Two prototype ADCs have been designed and fabricated in 0.18μm CMOS
technology as the experimental verification of the proposed techniques. The first ADC
is a 1.8V 10-bit pipeline ADC which incorporated the time-shifted CDS technique to
boost the effective gain of the amplifiers. Much better gain-bandwidth tradeoff in
amplifier design is achieved with this gain boosting. Measurement results show total
power consumption of 67mW at 1.8V when operating at 100MSPS. The SNR, SNDR
and SFDR are 55dB, 54dB and 65dB respectively given a 1MHz input signal. The
second one is a 0.9V 12-bit two-stage cyclic ADC which employed a novel
correlation-based background calibration to enhance the linearity. The linearity limit
set by the capacitor mismatches, finite opamp gain effects is exceeded. After
calibration, the SFDR is improved by about 33dB and exceeds 80dB. The power
consumption is 12mW from 0.9V supply when operating at 2MSPS.Graduation date: 2004
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Wang, Po-Tsang, and 王柏蒼. "A Metal Density Improved High Speed Asynchronous Successive Approximation Register ADC." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/77v7sk.
Full textAbstract:
碩士國立中興大學
電機工程學系所
105
This thesis presents a high speed successive approximation register (SAR) analog to digital converter (ADC) with input buffer and the study of non-ideal situation. The design purpose of this SAR ADC is to use it as one of sub ADCs for a Time-Interleaved ADC. The sample rate of this SAR ADC is 166MS/s, and the highest input frequency is 1.2GHz. In order to strengthen the driving power, we add a buffer to the front end. Last, but not least, considering the characteristic impedance in the high frequency will affect the input signal, we improved the PCB layout design. On the other hand, for minimizing the delay time after the signal triggered, the ADC’s control logic path is designed as parallel, which can improve the performance. Fabricated under TSMC 90nm GUTM process, sarf_35 has the ENOB of 6.09 bit when the input frequency is 10MHz and 3.48 bit when input frequency is 1.2GHz. After the improvement, sarf_36 has a higher ENOB at 10MHz, which is 7.028bit, and 5.25bit at 1.2GHz.
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Chung, Meng-hsun, and 鍾孟勳. "A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/n6jsr8.
Full textAbstract:
碩士國立中山大學
資訊工程學系研究所
103
In this thesis, a 10-bit binary search assisted time-interleaved SAR ADC operating in 250Ms/s sampling rate with 1.2 supply voltage is presented. The ADC adopt TSMC 90nm process and can be used for receiving in front-end chip of wireless communication system. In circuit design, we take BS-ADC and SAR-ADC’s advantage for the requirement of high sampling rate and low power consumption and separate ADC in two stages. The first stage is Binary-search ADC which converts high five bit at 250Ms/s sampling rate. Due to additional switching circuit to select correct reference voltage, the need of comparators in BS-ADC can be substantially reduced. The second stage is two-channel SAR ADCs which convert low five bit. Each channel operates at 125Ms/s. In binary-weight capacitor array, we give half-reference voltage for LSB capacitor switching with monotonic switching method. Compared to conventional binary-weight capacitor array, the proposed architecture can reduce total capacitance by 75%. The entire architecture is designed in fully-differential circuit to reduce common mode noise and improve the linearity of the circuit.