Relevant bibliographies by topics / High speed ADC/DAC

Academic literature on the topic 'High speed ADC/DAC'

Author: Grafiati
Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "High speed ADC/DAC"

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Azarov, O. D., S. V. Bohomolov, and O. Y. Stahov. "MULTICHANNEL SPEED ADC-DAC SYSTEM BASED ON HIGH-LINE CURRENT-CURRENT CONVERTERS." Information technology and computer engineering 50, no. 1 (2021): 69–79. http://dx.doi.org/10.31649/1999-9941-2021-50-1-69-79.

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Cheng, Li, Jiao Xu, Yi Xin Zhang, and Ning Yang. "Design of High-Speed and Low-Power Two-Channel Pipeline ADC." Advanced Materials Research 328-330 (September 2011): 1820–23. http://dx.doi.org/10.4028/www.scientific.net/amr.328-330.1820.

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This paper describes a low-power 1.2 V 8-bit 1Gs/s two-channel pipeline ADC. The novelty of the designed ADC lies in: ameliorating the two-channel pipeline structure that consists of 1.5-bit multiplying DAC (MDAC). In order to reduce the power consumption and improve the sampling speed, the dual-channel pipeline Time Division Multiplexing operation amplifier and double or single channel flash ADC are used; in the front-end Sample-and-Hold circuits, switch-linearization control circuits(SLC) driven by a single clock signal is applied to solve the problem of time-skew and time mismatch between two channels. The pipeline ADC is designed with 90 nm CMOS process. From the simulation results of the designed ADC, we can draw that the SFDR is 42.3 dB; the SNR is 32.7 dB under the usual temperature. The ADC achieves 21 mW power-dissipation, 8 resolution and 1.01 GS/s sampling speed. So the design meets high speed, high precision and low power dissipation at the same time.
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Wang, Li, Wenli Chen, Kai Chen, Renjun He, and Wenjian Zhou. "The Research on the Signal Generation Method and Digital Pre-Processing Based on Time-Interleaved Digital-to-Analog Converter for Analog-to-Digital Converter Testing." Applied Sciences 12, no. 3 (February 7, 2022): 1704. http://dx.doi.org/10.3390/app12031704.

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In the high-resolution analog circuit, the performance of chips is an important part. The performance of the chips needs to be determined by testing. According to the test requirements, stimulus signal with better quality and performance is necessary. The main research direction is how to generate high-resolution and high-speed analog signal when there is no suitable high-resolution and high-speed digital-to-analog converter (DAC) chip available. In this paper, we take the high-resolution analog-to-digital converter (ADC) chips test as an example; this article uses high-resolution DAC chips and multiplexers to generate high-resolution high-speed signals that can be used for testing high-resolution ADC chips based on the principle of time-alternating sampling. This article explains its method, analyzes its error and proposes a digital pre-processing method to reduce the error. Finally, the actual circuit is designed, and the method is verified on the circuit. The test results prove the effectiveness of this method for generating high-resolution ADC test signals.
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Kakarla, Deepti. "An optimized design approach for 8-bit pipelined ADC using high gain amplifier." i-manager’s Journal on Electronics Engineering 12, no. 2 (2022): 23. http://dx.doi.org/10.26634/jele.12.2.18529.

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Demand of high-performance converters with integrated circuits with combined features and specifications of power consumption, resolution and speed have become very dominant in many emerging applications. Pipelined ADC mixed signal system consists of Sample and Hold, Flash ADC, DAC and Gain amplifier in all the stages. In the present work, a pipeline ADC architecture has 3-stages, with each stage of 3-bits with 3-bit flash ADC followed by a 3-bit binary weighted DAC at each stage. A novel approach to design a 8-bit ADC is implemented, and this design offers less number of comparators compared to flash ADC with less circuit complexity, and 8-bit ADC is designed with improvement in resolution. It is simulated first in MATLAB, but applying 1.8Volts sinusoidal and sampling time of 40 MSPS and clock frequency 10MHz the individual blocks are implemented in LT-spice 180 nm technology with bandwidth of 40 MHz. Then a high gain amplifier is implemented by using Diode connected load differential amplifier with 10mv input voltage and 18Mhz input frequency.
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Arafa, Kawther I., Dina M. Ellaithy, Abdelhalim Zekry, Mohamed Abouelatta, and Heba Shawkey. "Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications." Active and Passive Electronic Components 2023 (January 4, 2023): 1–29. http://dx.doi.org/10.1155/2023/3669255.

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.
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Ye, Wen Hua, and Huan Li. "Design of Virtex-7 FPGA-Based High-Speed Signal Processor Carrier Board." Applied Mechanics and Materials 719-720 (January 2015): 534–37. http://dx.doi.org/10.4028/www.scientific.net/amm.719-720.534.

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With the development of digital signal processing technology, the demand on the signal processor speed has become increasingly high. This paper describes the hardware design of carrier board in high-speed signal processing module, which using Xilinx's newest Virtex-7 FPGA family XC7VX485T chip, and applying high-speed signal processing interface FMC to transport and communicate high-speed data between carrier board and daughter card with high-speed ADC and DAC. This design provides a hardware implementation and algorithm verification platform for high-speed digital signal processing system.
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Chauhan, Sarita. "Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 9, no. VII (July 31, 2021): 3073–80. http://dx.doi.org/10.22214/ijraset.2021.37002.

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After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.
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Shetty, Chaya, M. Nagabushanam, and Venkatesh Nuthan Prasad. "A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology." International Journal of Circuits, Systems and Signal Processing 15 (June 29, 2021): 556–68. http://dx.doi.org/10.46300/9106.2021.15.62.

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The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.
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Bchir, Mounira, Thouraya Ettaghzouti, and Néjib Hassen. "A Novel High Frequency Low Voltage Low Power Current Mode Analog to Digital Converter Pipeline." Journal of Low Power Electronics 15, no. 4 (December 1, 2019): 368–78. http://dx.doi.org/10.1166/jolpe.2019.1621.

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This paper introduces a novel structure for the realization of a low voltage, low power current-mode analog to the digital converter (ADC) pipeline (12 bits). The proposed structure of the ADC is based on a novel design of a current comparator and Digital to Analog Converter (DAC) structure. This modification allows us to reach a higher speed, lower voltage, and lower power dissipation. ELDO simulators using 0.18 μm, CMOS and TSMC parameters are performed to confirm the workability of this architecture. The proposed ADC is powered with a 1 V supply voltage. It is characterized by wide conversion frequency (350 MHz) and low power consumption that is 2.76 mW.
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Vasudeva, G., and B. V. Uma. "Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET." WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL 17 (January 3, 2022): 1–15. http://dx.doi.org/10.37394/23203.2022.17.1.

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Successive Approximation Register (SAR) Analog to Digital Converter (ADC) architecture comprises of sub modules such as comparator, Digital to Analog Converter and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements and ADC metrics is presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two stage segmented resistive string DAC architecture and low power SAR logic is designed and integrated to form the ADC architecture with maximum sampling rate of 1 GS/s. Circuit schematic is captured in Cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC is evaluated in MATLAB environment. Differential Non Linearity and Integral Non Linearity metrics for the 12-bit ADC is limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency upto 1 GSps is designed in this work with low power dissipation less than 10 mW.
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Dissertations / Theses on the topic "High speed ADC/DAC"

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Swindlehurst, Eric Lee. "High-Speed and Low-Power Techniques for Successive-Approximation-Register Analog-to-Digital Converters." BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8923.

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Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power efficiency of the SAR architecture and demonstrates them in a low-power 10-GHz SAR ADC suitable for broadband wireless communications. The proposed 8-bit, 10-GHz, 8× time-interleaved SAR ADC utilizes a constant-matching DAC with symmetrically grouped unit finger capacitors to maximize speed by reducing the total DAC capacitance to 32 fF and minimizing the bottom plate parasitic capacitance. The capacitance reduction also saves power as both the DAC size and the driving logic size are reduced. An optimized asynchronous comparator loop and smaller driver logic push the single channel speed of the SAR ADC to 1.25 GHz, thus minimizing the total number of timeinterleaved channels to 8 to reach 10 GHz. A dual-path bootstrapped switch improves the spurious-free dynamic range (SFDR) of the sampling by creating an auxiliary path to drive the non-linear N-well capacitance apart from the main signal path. Using these techniques, the ADC achieves a measured signal-to-noise-and-distortion ratio (SNDR) and SFDR of 36.9 dB and 59 dB, respectively with a Nyquist input while consuming 21 mW of power. The ADC demonstrates a record-breaking figure-of-merit of 37 fJ/conv.-step, which is more than 2× better than the next best published design, among reported ADCs of similar speeds and resolutions.
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Lu, Dongtian. "High speed CMOS ADC for UWB receiver /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LUD.

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Hiremath, Vinayashree. "DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY." Wright State University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=wright1291391500.

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Sivakumar, Balasubramanian. "A 6-Bit Sub-Ranging High Speed Flash Analog To Digital Converter With Digital Speed And Power Control." The Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=osu1229631191.

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Wang, Mingzhen. "High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.

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Kaald, Rune. "Modelling, Simulation and Implementation Considerations of High Speed Continuous Time Sigma Delta ADC." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8942.

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A found state of the art Continuous Time Sigma Delta ADC is modelled and simulated for the presence of nonidealities. A comparison between two Excess Loop Delay compensation techniques is done, the digital differentiation technique was found to have lower swing at the last integrator, and did not need a gain-bandwidth induced delay sensitive summing amplifier. The detrimental influence of clock jitter is shown. Different DAC linearization techniques are discussed, the DWA algorithm was simulated and found to be the best choice for linearizing the DACs. Through high level modeling in Simulink and verification in the Cadence framework specifications for each building block was determined, a final simulation resulted in a SNDR of 76.3 dB.

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Homsi, Mustafa Al. "High speed ADC design targeting the UWB system using TSMC 0.18uM technology process." The Ohio State University, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=osu1399551999.

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Shar, Ahmad. "Design of a High-Speed CMOS Comparator." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10446.

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This master thesis describes the design of high-speed latched comparator with 6-bit resolution, full scale voltage of 1.6 V and the sampling frequency of 250 MHz. The comparator is designed in a 0.35 9m CMOS process with a supply voltage of 3.3 V.

The comparator is designed for time-interleaved bandpass sigma-delta ADC.

Due to the nature of the target application, it should be possible to turn off the components to avoid the static power consumption. The comparator of this design implements the turn off technique when it is not in use. The settling time of the comparator is less than half the clock cycle which means it does not effect the functionality of the bandpass sigma-delta ADC in terms of speed.

The simulation results are derived using Cadence environment. The results show that the comparator has 6-bit resolution and power consumption of 4.13 mW for the worst-case frequency of 250 MHz. It fulfills all the performance requirements, most of them with large margins.

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Figueiredo, Michael. "Reference-free high-speed cmos pipeline analog-to-digital converters." Doctoral thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8776.

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Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering of the Faculdade de Ciências e Tecnologia of Universidade Nova de Lisboa
More and more signal processing is being transferred to the digital domain to profit from the technological enhancement of digital circuits. Where technology scaling enhances the capabilities of digital circuits, it degrades the performance of analog circuits. However, it is important to note that the impact that technology scaling has on digital circuits is becoming smaller and smaller, which means that, in nanotechnologies, to enhance energy and area efficiency, we can not simply depend on the benefits of this scaling. Although, a share of the efficiency can be obtained from the technology, new circuit architectures and techniques have to be developed to really push the limits of efficiency. In data converters, more specifically analog-to-digital converters (ADCs), a decision can be made: research energy and area efficient analog circuit techniques and architectures that cope with technological scaling issues, or design algorithms that use digital circuitry to assist the poor analog technological performance. The former option is the premise for the work developed in this thesis. The work reported in this thesis explores various design techniques with the purpose of enhancing the power and area efficiency of building blocks mainly to be used in multiplying digital-to-analog converter based ADCs. Therefore, novel analog techniques are developed for the three main blocks of an MDAC-based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. These techniques include self-biasing and inverter-based design for the flash quantizer and amplifier. Regarding the MDAC, it combines three techniques: unity feedback factor, insensitivity to capacitor mismatch, and current-mode reference shifting. In the second part of this work, the designed amplifier is implemented and experimentally characterized demonstrating its practical feasibility and performance. The final part of this work explores the design and implementation of a medium-low resolution high speed pipeline ADC incorporating all the developed circuits. Experimental results validate the feasibility of the techniques and demonstrate the attractiveness in terms of power dissipation and reduced area.
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Elkafrawy, Abdelrahman [Verfasser]. "Concept and design of a high speed current mode based SAR ADC / Abdelrahman Elkafrawy." Ulm : Universität Ulm, 2016. http://d-nb.info/1108434592/34.

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Books on the topic "High speed ADC/DAC"

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Gottardo, Marco. FPGA to High Speed Adc Data Streaming. Lulu Press, Inc., 2018.

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Takenaka, Norio. PIC32 FRM, Section 22 High-Speed SAR ADC. Microchip Technology Incorporated, 2016.

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Zhou, Clarence. Designing Digital RF Receiver Using MCP37DXX High-Speed ADC. Microchip Technology Incorporated, 2020.

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Takenaka, Norio. AN2497 - Designing Digital RF Receiver Using MCP37DXX High-Speed ADC. Microchip Technology Incorporated, 2020.

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Lee, Jade. 12-Bit High-Speed, Multiple SARs a/d Converter (ADC). Microchip Technology Incorporated, 2015.

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Boles, Melanie. AN2497, Designing Digital RF Receiver Using MCP37DXX High-Speed ADC. Microchip Technology Incorporated, 2018.

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Jiang, Linda. 12-Bit High-Speed, Multiple SARs a/d Converter (ADC). Microchip Technology Incorporated, 2017.

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Jiang, Linda. 12-Bit High-Speed, Multiple SARs a/d Converter (ADC). Microchip Technology Incorporated, 2018.

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Jiang, Linda. SPIC33/PIC24 FRM - High-Speed Analog Comparator with Slope Compensation DAC. Microchip Technology Incorporated, 2020.

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Boles, Melanie. DsPIC33/PIC24 FRM, High-Speed Analog Comparator with Slope Compensation DAC. Microchip Technology Incorporated, 2019.

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Book chapters on the topic "High speed ADC/DAC"

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Zhang, Feng. "ADC, DAC Data Transmission Based on JESD204 Protocol." In High-speed Serial Buses in Embedded Systems, 85–130. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-1868-3_3.

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Zheng, Yong, Xiao-han Guan, and Wen-jia Li. "Design and Implementation of High-Speed ADC and DAC Based on SPI Technology in TMS320F2808DSP Control System." In 2011 International Conference in Electrics, Communication and Automatic Control Proceedings, 1697–704. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-8849-2_220.

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Krishna, K. Lokesh, Yahya Mohammed Ali Al-Naamani, and K. Anuradha. "A High Speed Two Step Flash ADC." In Soft Computing Systems, 826–36. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1936-5_84.

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Chaudhary, Kapil, B. K. Kaushik, and Kirat Pal. "Design of High Speed Optimized Flash ADC." In Computer Networks and Information Technologies, 260–63. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19542-6_42.

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Louwsma, Simon, Ed van Tuijl, and Bram Nauta. "Implementation of a High-speed Time-interleaved ADC." In Time-interleaved Analog-to-Digital Converters, 71–124. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-90-481-9716-3_4.

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Ramkaj, Athanasios T., Marcel J. M. Pelgrom, Michiel S. J. Steyaert, and Filip Tavernier. "High-Speed Wide-Bandwidth Single-Channel SAR ADC." In Analog Circuits and Signal Processing, 149–81. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-22709-7_5.

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Palermo, Samuel, Sebastian Hoyos, Shiva Kiran, Shengchang Cai, and Yuanming Zhu. "ADC/DSP-Based Receivers for High-Speed Serial Links." In Analog Circuits for Machine Learning, Current/Voltage/Temperature Sensors, and High-speed Communication, 247–67. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-91741-8_14.

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Sin, Sai-Weng, Seng-Pan U, and Rui Paulo Martins. "Time-Interleaving: Multiplying the Speed of the ADC." In Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters, 55–74. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9710-1_4.

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Kull, Lukas, Thomas Toifl, Martin Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel Kossel, Thomas Morf, Toke Meyer Andersen, and Yusuf Leblebici. "Energy-Efficient High-Speed SAR ADCs in CMOS." In High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing, 45–63. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-07938-7_3.

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Zhuang, Yuming, and Degang Chen. "High-Purity Sine Wave Generation Using Nonlinear DAC with Pre-distortion Based on Low-Cost Accurate DAC-ADC Co-testing." In Accurate and Robust Spectral Testing with Relaxed Instrumentation Requirements, 59–78. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-77718-4_4.

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Conference papers on the topic "High speed ADC/DAC"

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Bedi, R. "Low-power, high-speed, ADC/DAC design for satellite communications." In 5th IEE International Conference on ADDA 2005. Advanced A/D and D/A Conversion Techniques and their Applications. IEE, 2005. http://dx.doi.org/10.1049/cp:20050133.

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Kilic, Mustafa, and Yusuf Leblebici. "A DAC assisted speed enhancement technique for high resolution SAR ADC." In 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME). IEEE, 2017. http://dx.doi.org/10.1109/prime.2017.7974155.

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Heikkinen, Veli, Eveliina Juntunen, Mikko Karppinen, Kari Kautio, Aila Sitomaniemi, Antti Tanskanen, Hélène Gachon, et al. "High-speed ADC and DAC modules with fibre optic interconnections for telecom satellites." In International Conference on Space Optics 2008, edited by Josiane Costeraste, Errico Armandillo, and Nikos Karafolas. SPIE, 2017. http://dx.doi.org/10.1117/12.2308251.

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Elkafrawy, Abdelrahman, Jens Anders, Timon Bruckner, and Maurits Ortmanns. "Design of a current steering DAC for a high speed current mode SAR ADC." In 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS). IEEE, 2013. http://dx.doi.org/10.1109/icecs.2013.6815449.

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Chun, Ji Hwan (Paul), Hak-soo Yu, and Jacob A. Abraham. "An efficient linearity test for on-chip high speed ADC and DAC using loop-back." In Proceedins of the 14th ACM Great Lakes symposium. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/988952.989031.

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Varughese, S., T. Richter, S. Tibuleac, and S. E. Ralph. "Joint optimization of DAC and ADC based on frequency dependent ENOB analysis for high speed optical systems." In 45th European Conference on Optical Communication (ECOC 2019). Institution of Engineering and Technology, 2019. http://dx.doi.org/10.1049/cp.2019.0928.

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G, Naveen I., Ramachandra A. C, and Manohara H. T. "A Low Power High-Speed 12-Bit SAR ADC using Split Capacitor Based DAC at 45 nm CMOS Technology." In 2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon). IEEE, 2022. http://dx.doi.org/10.1109/mysurucon55714.2022.9972699.

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Wang, Xiaoyang, Xiong Zhou, and Qiang Li. "A energy-efficient high speed segmented prequantize and bypass DAC for SAR ADCs." In 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2014. http://dx.doi.org/10.1109/mwscas.2014.6908361.

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9

"Very high-speed ADCs and DACs." In 2006 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. IEEE, 2006. http://dx.doi.org/10.1109/isscc.2006.1696293.

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Grozing, Markus, Damir Ferenci, Felix Lang, Thomas Alpert, Hao Huang, Jochen Briem, Thomas Veigel, and Manfred Berroth. "High-speed CMOS DACs and ADCs for broadband communication." In 2013 IEEE/MTT-S International Microwave Symposium - MTT 2013. IEEE, 2013. http://dx.doi.org/10.1109/mwsym.2013.6697601.

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