Dissertations / Theses on the topic 'HIGH GAIN LOW POWER'
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Li, Lisha. "High Gain Low Power Operational Amplifier Design and Compensation Techniques." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd1701.pdf.
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Saidev, Sriram. "Design of a Digitally Enhanced, Low Power, High Gain, High Linearity CMOS Mixer and CppSim Evaluation." The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1461262622.
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Chen, Lin. "A low power, high dynamic-range, broadband variable gain amplifier for an ultra wideband receiver." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5843.
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A fully differential Complementary Metal-Oxide Semiconductor (CMOS) Variable
Gain Amplifier (VGA) consisting of complementary differential pairs with source
degeneration, a current gain stage with programmable current mirror, and resistor loads is
designed for high frequency and low power communication applications, such as an Ultra
Wideband (UWB) receiver system. The gain can be programmed from 0dB to 42dB in 2dB
increments with -3dB bandwidth greater than 425MHz for the entire range of gain. The 3rd-order
intercept point (IIP3) is above -13.6dBm for 1Vpp differential input and output
voltages. These low distortion broadband features benefit from the large linear range of the
differential pair with source degeneration and the low impedance internal nodes in the
current gain stages. In addition, common-mode feedback is not required because of these
low impedance nodes. Due to the power efficient complementary differential pairs in the
input stage, power consumption is minimized (9.5mW) for all gain steps. The gain control
scheme includes fine tuning (2dB/step) by changing the bias voltage of the proposed
programmable current mirror, and coarse tuning (14dB/step) by switching on/off the source degeneration resistors in the differential pairs. A capacitive frequency compensation
scheme is used to further extend the VGA bandwidth.
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Singh, Rishi Pratap. "A High-Gain, Low-Power CMOS Operational Amplifier Using Composite Cascode Stage in the Subthreshold Region." BYU ScholarsArchive, 2011. https://scholarsarchive.byu.edu/etd/2510.
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This thesis demonstrates that the composite cascode differential stage, operating in the subthreshold region, can form the basis of a high gain (113 dB) and low-power op amp (28.1 µW). The circuit can be fabricated without adding a compensation capacitance. The advantages of this architecture include high voltage gain, low bandwidth, low harmonic distortion, low quiescent current and power, and small chip area. These advantages suggest that this design might be well-suited for biomedical applications where low power, low noise bio-signal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range is required.
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Cahill, Kurtis Daniel. "Subthreshold Op Amp Design Based on the Conventional Cascode Stage." BYU ScholarsArchive, 2013. https://scholarsarchive.byu.edu/etd/3611.
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Op amps are among the most-used components in electronic design. Their performance is important and is often measured in terms of gain, bandwidth, power consumption, and chip area. Although BJT amplifiers can achieve high gains and bandwidths, they tend to consume a lot of power. CMOS amplifiers utilizing the strong inversion region alone use less power than BJT amplifiers, but generally have lower gains and bandwidths. When CMOS SPICE models were improved to accurately simulate all regions of inversion, researchers began to test the performance of amplifiers operating in the weak and moderate inversion regions. Previous work had dealt with exploring the parameters of composite cascode stages, including inversion coefficients. This thesis extends the work to include conventional cascode stages and presents an efficient method for exploring design parameters. A high-gain (137.7 dB), low power (4.347 µW) operational amplifier based on the conventional cascode stage is presented.
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Saini, Kanika. "Linearity Enhancement of High Power GaN HEMT Amplifier Circuits." Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/94361.
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Gallium Nitride (GaN) technology is capable of very high power levels but suffers from high non-linearity. With the advent of 5G technologies, high linearity is in greater demand due to complex modulation schemes and crowded RF (Radio Frequency) spectrum. Because of the non-linearity issue, GaN power amplifiers have to be operated at back-off input power levels. Operating at back-off reduces the efficiency of the power amplifier along-with the output power. This research presents a technique to linearize GaN amplifiers. The linearity can be improved by splitting a large device into multiple smaller devices and biasing them individually. This leads to the cancellation of the IMD3 (Third-order Intermodulation Distortion) components at the output of the FETs and hence higher linearity performance.
This technique has been demonstrated in Silicon technology but has not been previously implemented in GaN. This research work presents for the first time the implementation of this technique in GaN Technology.
By the application of this technique, improvement in IMD3 of 4 dBc has been shown for a 0.8-1.0 GHz PA (Power Amplifier), and 9.5 dBm in OIP3 (Third-order Intercept Point) for an S-Band GaN LNA, with linearity FOM (IP3/DC power) reaching up to 20.
Large-signal simulation and analysis have been done to demonstrate linearity improvement for two parallel and four parallel FETs. A simulation methodology has been discussed in
detail using commercial CAD software. A power sampler element is used to compute the IMD3 currents coming out of various FETs due to various bias currents. Simulation results show by biasing one device in Class AB and others in deep Class AB, IMD3 components of parallel FETs can be made out of phase of each other, leading to cancellation and improvement in linearity. Improvement up to 20 dBc in IMD3 has been reported through large-signal simulation when four parallel FETs with optimum bias were used.
This technique has also been demonstrated in simulation for an X-Band MMIC PA from 8-10 GHz in GaN technology. Improvements up to 25-30 dBc were shown using the technique of biasing one device with Class AB and other with deep class AB/class B. The proposed amplifier achieves broadband linearization over the entire frequency compared to state-of-the-art PA's. The linearization technique demonstrated is simple, straight forward, and low cost to implement. No additional circuitry is needed. This technique finds its application in high dynamic range RF amplifier circuits for communications and sensing applications.Doctor of Philosophy
Power amplifiers (PAs) and Low Noise Amplifiers (LNAs) form the front end of the Radio Frequency (RF) transceiver systems. With the advent of complex modulation schemes, it is becoming imperative to improve their linearity. Through this dissertation, we propose a technique for improving the linearity of amplifier circuits used for communication systems. Meanwhile, Gallium Nitride (GaN) is becoming a technology of choice for high-power amplifier circuits due to its higher power handling capability and higher breakdown voltage compared with Gallium Arsenide (GaAs), Silicon Germanium (SiGe) and Complementary Metal-Oxide-Semiconductor (CMOS) technologies. A circuit design technique of using multiple parallel GaN FETs is presented. In this technique, the multiple parallel FETs have independently controllable gate voltages. Compared to a large single FET, using multiple FETs and biasing them individually helps to improve the linearity through the cancellation of nonlinear distortion components. Experimental results show the highest linearity improvement compared with the other state-of-the-art linearization schemes. The technique demonstrated is the first time implementation in GaN technology. The technique is a simple and cost-effective solution for improving the linearity of the amplifier circuits. Applications include base station amplifiers, mobile handsets, radars, satellite communication, etc.
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Säll, Erik. "Design of a Low Power, High Performance Track-and-Hold Circuit in a 0.18µm CMOS Technology." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1353.
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This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter.
A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type.
The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase.
The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins.
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Waddel, Taylor Matt. "A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions." BYU ScholarsArchive, 2012. https://scholarsarchive.byu.edu/etd/2934.
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Composite cascode stages have been used in operational amplifier designs to achieve ultra-high gain at very low power. The flexibility and simplicity of the stage makes it an appealing choice for low power op-amp designs. Op-amp design using the composite cascode stage is often made more difficult through the lack of a design process. A design process to aid in the selection of the MOSFET dimensions is provided in this thesis. This process includes a table-based method for selection of the widths and lengths of the MOSFETs used in the composite cascode stage. Equations are also derived for the gain, bandwidth, and noise of the composite cascode stage with each of the devices operating in the various regions of inversion.
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Ciarkowski, Timothy A. "Low Impurity Content GaN Prepared via OMVPE for Use in Power Electronic Devices: Connection Between Growth Rate, Ammonia Flow, and Impurity Incorporation." Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/94551.
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GaN has the potential to revolutionize the high power electronics industry, enabling high voltage applications and better power conversion efficiency due to its intrinsic material properties and newly available high purity bulk substrates. However, unintentional impurity incorporation needs to be reduced. This reduction can be accomplished by reducing the source of contamination and exploration of extreme growth conditions which reduce the incorporation of these contaminants. Newly available bulk substrates with low threading dislocations allow for better study of material properties, as opposed to material whose properties are dominated by structural and chemical defects. In addition, very thick films can be grown without cracking due to exact lattice and thermal expansion coefficient match. Through chemical and electrical measurements, this work aims to find growth conditions which reduces contamination without a severe impact on growth rate, which is an important factor from an industry standpoint. The proposed thicknesses of these devices are on the order of one hundred microns and requires tight control of the intentional dopants.Doctor of Philosophy
GaN is a compound semiconductor which has the potential to revolutionize the high power electronics industry, enabling new applications and energy savings due to its inherent material properties. However, material quality and purity requires improvement. This improvement can be accomplished by reducing contamination and growing under extreme conditions. Newly available bulk substrates with low defects allow for better study of material properties. In addition, very thick films can be grown without cracking on these substrates due to exact lattice and thermal expansion coefficient match. Through chemical and electrical measurements, this work aims to find optimal growth conditions for high purity GaN without a severe impact on growth rate, which is an important factor from an industry standpoint. The proposed thicknesses of these devices are on the order of one hundred microns and requires tight control of impurities.
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Hasegawa, Naoki. "Integral Study of GaN Amplifiers and Antenna Technique for High Power Microwave Transmission." Kyoto University, 2018. http://hdl.handle.net/2433/232041.
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Park, Jung-Hyun. "High-gain, high-power free electron lasers." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/30964.
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The Paladin FEL experiment is shown to exhibit clear and dramatic effects governed by the electron beam velocity distribution for the first time. The FEL integral equation is used to show that there is significant broadening of the gain spectrum due to the Gaussian velocity distribution, and also shows a plateau in the gain evolution along the undulator due to a triangular-shaped velocity distribution. The gain spectra and power evolution from simple, single- mode simulations are compared to the ELF experiments. The microwave power evolution along the undulator is compared as well for both the tapered and untapered undulators. In all cases, the agreement is found to be good.
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Iqbal, Rashid. "Low Power Gain Cell Arrays: Voltage Scaling and Leakage Reduction." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73970.
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In this thesis, a fully logic - compatible Gain - Cell (GC) based Dynamic - Random - Access (DRAM) with a storage capacity of 2048 bit is designed in UMC – 180 nm technology. The GC used is a two transistor PMOS (2PMOS) cell. This thesis aims at building the foundation for further research on the effects of supply voltage ff scaling on retention time, leakage and power consumption. Different techniques are used to reduce leakage current for longer retention time and ultimately low power. Different types of decoders are analyzed for low power. First, general concepts of memories are presented. Furthermore, the topic of leakage and its effect on retention time and power consumption is introduced. Two memories are designed, first one is single port memory with improved retention time. Finally, a Two port memory with all peripherals, which consists of he GC array, Decoder, Drivers, Registers, Pulse generators is designed. All the simulations for voltage scaling and retention time are shown.
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De, Souza Marcelo. "Conception d'amplificateur faible bruit reconfigurable en technologie CMOS pour applications de type radio adaptative." Thesis, Bordeaux, 2016. http://www.theses.fr/2016BORD0295/document.
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Les systèmes de communication mobiles permettent l’utilisation de l’information en environnements complexes grâce à des dispositifs portables qui ont comme principale restriction la durée de leurs batteries. Des nombreux efforts se sont focalisés sur la réduction de la consommation d’énergie des circuits électroniques de ces systèmes, une fois que le développent des technologies des batteries ne avance pas au rythme nécessaire. En outre, les systèmes RF sont généralement conçus pour fonctionner de manière fixe, spécifiés pour le pire cas du lien de communication. Toutefois, ce scénario peut se produire dans une petite partie du temps, entraînant ainsi en perte d’énergie dans le reste du temps. La recherche des circuits RF adaptatifs, pour adapter le niveau du signal d'entrée pour réduire la consommation d'énergie est donc d'un grand intérêt et de l'importance. Dans la chaîne de réception radiofréquence, l'amplificateur à faible bruit (LNA) se montre un composant essentiel, autant pour les performances de la chaîne que pour la consommation d'énergie. Au cours des dernières décennies, des techniques pour la conception de LNAs reconfigurables ont été proposées et mises en oeuvre. Cependant, la plupart d'entre elles s’applique seulement au contrôle du gain, sans exploiter Le réglage de la linéarité et du bruit envisageant l'économie d'énergie. De plus,ces circuits occupent une grande surface de silicium, ce qui entraîne un coût élevé, ou NE correspondent pas aux nouvelles technologies CMOS à faible coût. L'objectif de cette étude est de démontrer la faisabilité et les avantages de l'utilisation d'un LNA reconfigurable numériquement dans une chaîne de réception radiofréquence, du point de vue de la consommation d'énergie et de coût de fabricationMobile communication systems allow exploring information in complex environments by means of portable devices, whose main restriction is battery life. Once battery development does not follow market expectations, several efforts have been made in order to reduce energy consumption of those systems. Furthermore, radio-frequency systems are generally designed to operate as fixed circuits, specified for RF link worst-case scenario. However, this scenario may occur in a small amount of time, leading to energy waste in the remaining periods. The research of adaptive radio-frequency circuits and systems, which can configure themselves in response to input signal level in order to reduce power consumption, is of interest and importance. In a RF receiver chain, Low Noise Amplifier (LNA) stand as critical elements, both on the chain performance or power consumption. In the past some techniques for reconfigurable LNA design were proposed and applied. Nevertheless, the majority of them are applied to gain control, ignoring the possibility of linearity and noise figure adjustment, in order to save power. In addition, those circuits consume great area, resulting in high production costs, or they do not scale well with CMOS. The goal of this work is demonstrate the feasibility and advantages in using a digitally controlled LNA in a receiver chain in order to save area and power
Os sistemas de comunicação móveis permitem a exploração da informação em ambientes complexos através dos dispositivos portáteis que possuem como principal restrição a duração de suas baterias. Como o desenvolvimento da tecnologia de baterias não ocorre na velocidade esperada pelo mercado, muitos esforços se voltam à redução do consumo de energia dos circuitos eletrônicos destes sistemas. Além disso, os sistemas de radiofrequência são em geral projetados para funcionarem de forma fixa, especificados para o cenário de pior caso do link de comunicação. No entanto, este cenário pode ocorrer em uma pequena porção de tempo, resultando assim no restante do tempo em desperdício de energia. A investigação de sistemas e circuitos de radiofrequência adaptativos, que se ajustem ao nível de sinal de entrada a fim de reduzir o consumo de energia é assim de grande interesse e importância. Dentro de cadeia de recepção de radiofrequência, os Amplificadores de Baixo Ruído (LNA) se destacam como elementos críticos, tanto para o desempenho da cadeia como para o consumo de potência. No passado algumas técnicas para o projeto de LNA reconfiguráveis foram propostas e aplicadas. Contudo, a maioria delas só se aplica ao controle do ganho, deixando de explorar o ajuste da linearidade e da figura de ruído com fins de economia de energia. Além disso, estes circuitos ocupam grande área de silício, resultando em alto custo, ou então não se adaptam as novas tecnologias CMOS de baixo custo. O objetivo deste trabalho é demonstrar a viabilidade e as vantagens do uso de um LNA digitalmente configurável em uma cadeia de recepção de radiofrequência do ponto de vista de custo e consumo de potência
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Zhu, Haikun. "High-performance low-power VLSI design." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2007. http://wwwlib.umi.com/cr/ucsd/fullcit?p3250072.
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Thesis (Ph. D.)--University of California, San Diego, 2007.Title from first page of PDF file (viewed April 4, 2007). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 97-101).
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Saadallah, Nisrine. "High-speed low-power asynchronous circuits." Thesis, McGill University, 2004. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=80140.
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This thesis presents several design experiments for high-performance power-efficient asynchronous circuits.In Chapter two we present a new asynchronous pipeline logic family with improved latency and throughput compared to several other asynchronous pipeline circuits. The channels between pipeline stages use data encoding and a small set of minimum-delay timing constraints that permit modular design with few dependencies on technology and layout. We develop circuit blocks that implement linear pipelines as well as forking, joining and data-dependent decisions. An implementation in 0.18mum CMOS exhibits a latency of 56ps per pipeline stage and throughput of 4.8-giga data item per second (GDI/s) in Hspice simulation.
We also present the design of a low-control-overhead asynchronous microprocessor integrated with a high-speed sampling FIFO. This is an experiment in exploring the benefits of asynchronous design in high-speed embedded DSP applications. It reports on the design approach, implementation and performance, including a comparison with the synchronous version of the microprocessor.
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Guo, Haidong. "A low power low noise high accuracy sensor IC." Online access for everyone, 2006. http://www.dissertations.wsu.edu/Dissertations/Fall2006/h_guo_111406.pdf.
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Ibrahim, Sameh Ahmed Assem Mostafa. "High-speed low-power equalizers for high-loss channels." Diss., Restricted to subscribing institutions, 2009. http://proquest.umi.com/pqdweb?did=2026920921&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Worapishet, Apisak. "High frequency low power switched-current techniques." Thesis, Imperial College London, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.392911.
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Burrow, Stephen George. "Low power, high efficiency Class D amplifiers." Thesis, University of Bristol, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.271779.
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Li, Wei Ph D. Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science. "Very-high-frequency low-voltage power delivery." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/82352.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 217-223).
Power conversion for the myriad low-voltage electronic circuits in use today, including portable electronic devices, digital electronics, sensors and communication circuits, is becoming increasingly challenging due to the desire for lower voltages, higher conversion ratios and higher bandwidth. Future computation systems also pose a major challenge in energy delivery that is difficult to meet with existing devices and design strategies. To reduce interconnect bottlenecks and enable more flexible energy utilization, it is desired to deliver power across interconnects at high voltage and low current with on- or over-die transformation to low voltage and high current, while providing localized voltage regulation in numerous zones. This thesis introduces elements for hybrid GaN-Si dc-de power converters operating at very high frequencies (VHF, 30-300 MHz) for low-voltage applications. Contributions include development of a new VHF frequency multiplier inverter suitable for step-down power conversion, and a Si CMOS switched-capacitor step-down rectifier. These are applied to develop a prototype GaN-Si hybrid dc-dc converter operating at 50 MHz. Additionally, this thesis exploits these elements to propose an ac power delivery architecture for low-voltage electronics in which power is delivered across the interconnect to the load at VHF ac, with local on-die transformation and rectification to dc. With the proposed technologies and emerging passives, it is predicted that the ac power delivery system can achieve over 90 % efficiency with greater than 1 W/mm² power density and 5:1 voltage conversion ratio. A prototype system has been designed and fabricated using a TSMC 0.25 [mu]m CMOS process to validate the concept. It operates at 50 MHz with output power of 4 W. The prototype converter has 8:1 voltage conversion ratio with input voltage of 20 V and output voltage of 2.5 V. To the author's best knowledge, this is the first ac power delivery architecture for low-voltage electronics ever built and tested.
by Wei Li.
Ph.D.
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Lee, Sunghyuk. "Techniques for low-power high-performance ADCs." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/87928.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 127-133).
Analog-to-digital converters (ADCs) are essential building blocks in many electronic systems which require digital signal processing and storage of analog signals. Traditionally, ADCs are considered a power hungry circuit. This thesis investigates ADC design techniques to achieve high-performance with low power consumption. Two designs are demonstrated. The first design is a voltage scalable zero-crossing based pipelined ADC. The zero-crossing based circuit technique is modified and optimized to improve the limited ADC resolution in nano-scaled CMOS technology. The proposed unidirectional charge transfer scheme allows faster and more energy efficient operation by eliminating unnecessary charging and discharging of the capacitors. Furthermore, the reduced transient disturbance at the beginning of the fine charge transfer phase improves the accuracy of operation. Power supply scaling enhances power efficiency at low sampling rates much like in digital circuits and widens the conversion frequency range where the ADC operates with highest efficiency. The second design is a high speed time-interleaved (TI) SAR ADC with background timing-skew calibration. A time-interleaved structure is employed to improve the effective sampling rate without sacrificing energy efficiency. SAR ADCs are used for each channel to make good use of device scaling. The proposed ADC architecture incorporates a flash ADC operating at the full sampling rate of the TI ADC. The flash ADC output is multiplexed to resolve MSBs of the SAR channels. Because the full-speed flash ADC does not suffer from timing-skew errors, the flash ADC output is also used as the timing reference to estimate the timing-skew of the SAR ADCs.
by Sunghyuk Lee.
Ph. D.
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Amoêdo, David Jorge Tiago. "A 1.2 V low noise amplifier with double feedback for high gain and low noise figure." Master's thesis, Faculdade de Ciências e Tecnologia, 2013. http://hdl.handle.net/10362/11040.
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Dissertação para obtenção do Grau de Mestre em
Engenharia Eletrotécnica e de ComputadoresIn this thesis we present a balun low noise amplifier (LNA) in which the gain is boosted using a double feedback structure. The circuit is based in a Balun LNA with noise and distortion cancellation. The LNA is based in two basic stages: common-gate (CG) and common-source (CS). We propose to replace the resistors by active loads, which have two inputs that will be used to provide the feedback (in the CG and CS stages). This proposed methodology will boost the gain and reduce the NF (Noise Figure). Simulation results, with a 130 nm CMOS technology, show that the gain is 19.65 dB and the NF is less than 2.17 dB. The total power dissipation is only 5 mW (since no extra blocks are required), leading to an FOM (Figure of Merit) of 3.13 mW-1 from a nominal 1.2 supply.
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Azmat, Rehan. "Design and implementation of a low-noise high-linearity variable gain amplifier for high speed transceivers." Thesis, Linköpings universitet, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73449.
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The variable gain amplifier (VGA) is utilized in various applications of remote sensing and communication equipments. Applications of the variable gain amplifier (VGA) include radar, ultrasound, wireless communication and even speech analysis. These applications use the variable gain amplifier (VGA) to enhance dynamic performance. The purpose of the thesis work is to implement a high linearity and low noise variable gain amplifier in 150 nm CMOS technology, for an analog-front-end of a transceiver. Two different amplifier architectures are designed and compared. First architecture is an amplifier with diode connected load and second architecture is a source degenerative amplifier. The performance of the amplifier with diode connected load is lower than the source degenerative amplifier in terms of gain, power, linearity, noise and bandwidth. So, the source degenerative amplifier is selected for implementation. The three stage variable gain differential amplifier is implemented with selected architecture. The implemented three stage variable gain differential amplifier have gain range of -541.5 mdB to 22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The -3 dB bandwidth achieved is 953.3 MHz. The third harmonic distortion (HD3) is -45 dBc at 250 mV and the power is 35 mW at 1.8 V supply source.
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Bystrøm, Vebjørn. "Low power/high performance dynamic reconfigurable filter-design." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8899.
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The main idea behind this thesis was to optimize the multipliers in a finite impulse response (FIR) filter. The project was chosen because digital filters are very common in digital signal processing and is an exciting area to work with. The first part of the text describes some theory behind the digital filter and how to optimize the multipliers that are a part of digital filters. The substantial thing to emphasize here is the use of Canonical Signed Digits (CSD) encoding. CSD representation for FIR filters can reduce the delay and complexity of the hardware implementation. CSD-encoding reduces the amount of non-zero digits and will by this reduce the multiplication process to a few additions/subtractions and shifts. In this thesis it was designed 4 versions of the same filter, that was implemented on an FPGA, where the substantial and most interesting results were the differences between coefficients that was CSD-encoded and coefficients that was represented with 2's complement. It was shown that the filter version that had CSD-encoded coefficients used almost 20% less area then the filter version with 2's complement coefficients. The CSD-encoded filter could run on a maximum frequency of 504,032 MHz compared the other filter that could run on a maximum frequency of 249,123 MHz. One of the filters that was designed was designed using the * operator in VHDL, that proved to be the most efficient when it came to the use of number of slices and speed. The reason for this was because an FPGA has built-in multipliers, so if one has the opportunity to use the multiplier they will give the best result instead of using logic blocks on the FPGA It was also discussed a filter that has the ability to change the coefficients at run-time without starting the design from the beginning. This is an advantage because a constant coefficient multiplier requires the FPGA to be reconfigured and the whole design cycle to be re-implemented. The drawback with the dynamic multiplier is that is uses more hardware resources.
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Li, Nan. "Improvements in High-Coverage and Low-Power LBIST." Doctoral thesis, KTH, Elektroniksystem, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-165463.
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Testing cost is one of the major contributors to the manufacturing cost of integrated circuits. Logic Built-In Self Test (LBIST) offers test cost reduction in terms of using smaller and cheaper ATE, test data volume reduction due to on-chip test pattern generation, test time reduction due to at-speed test pattern application. However, it is difficult to reach a sufficient test coverage with affordable area overhead using LBIST. Also, excessive power dissipation during test due to the random nature of LBIST patterns causes yield-decreasing problems such as IR-drop and overheating. In this dissertation, we present techniques and algorithms addressing these problems. In order to increase test coverage of LBIST, we propose to use on-chip circuitry to store and generate the "top-off" deterministic test patterns. First, we study the synthesis of Registers with Non-Linear Update (RNLUs) as on-chip sequence generators. We present algorithms constructing RNLUs which generate completely and incompletely specified sequences. Then, we evaluate the effectiveness of RNLUs generating deterministic test patterns on-chip. Our experimental results show that we are able to achieve higher test coverage with less area overhead compared to test point insertion. Finally, we investigate the possibilities of integrating the presented on-chip deterministic test pattern generator with existing Design-For-Testability (DFT) techniques with a case study. The problem of excessive test power dissipation is addressed with a scan partitioning algorithm which reduces capture power for delay-fault LBIST. The traditional S-graph model for scan partitioning does not quantify the dependency between scan cells. We present an algorithm using a novel weighted S-graph model in which the weights are scan cell dependencies determined by signal probability analysis. Our experimental results show that, on average, the presented method reduces average capture power by 50% and peak capture power by 39% with less than 2% drop in the transition fault coverage. By comparing the proposed algorithm to the original scan partitioning, we show that the proposed method is able to achieve higher capture power reduction with less fault coverage drop.QC 20150508
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Ma, Albert. "Circuits for high-performance low-power VLSI logic." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37906.
Full textAbstract:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 85-88).
The demands of future computing, as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and variation. We propose a new family of logic styles called Preset Skewed Static Logic (PSSL). PSSL bridges the gap between the two main logic styles, static CMOS logic and domino logic, occupying an intermediate region in the energy-delay-robustness space between the two. PSSL is better than domino in terms of energy and robustness, and is better than static CMOS in terms of delay. PSSL works by partially overlapping the execution of consecutive iterations through speculative evaluation. This is accomplished by presetting nodes at register boundaries before input arrival.
by Albert Ma.
Ph.D.
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Hirst, Peter Frank. "Low pressure plasmas for high power microwave sources." Thesis, University of St Andrews, 1992. http://hdl.handle.net/10023/13613.
Full textAbstract:
This thesis describes an investigation of the use of low pressure plasmas for the generation of high power microwaves. Previous research has shown that the efficiency of a high power microwave ("HPM") source such as a BWO is enhanced by the introduction of a low pressure plasma into the oscillator cavity. The principle aim of this thesis is to extend the use of low pressure plasmas to the whole HPM system. Electron beams with current densities of the order of 20 A cm-2 can be generated in a cold cathode glow discharge at low gas pressures. Results are presented which show the effects of magnetic fields and electrode spacing on the I-V characteristics of a DC glow discharge electron gun. A glow discharge electron gun with an operating voltage of 350 kV has been designed and tested. A new kind of RP plasma cathode is proposed in which electrons are drawn from an RF discharge in a low pressure gas. An analysis of the production of an annular RF plasma cathode using a microwave-excited helical slow-wave structure is presented. Experimental results show that the RF plasma cathode yields electron current densities an order of magnitude higher than does a solid cathode. Examples of the implementation of the RF plasma cathode in a number of components of an HPM system are given. The propagation of electromagnetic waves in plasma-loaded waveguides of circular cross-section has been modelled. Numerical solutions are presented for the case of slow-waves in a longitudinally-magnetised plasma waveguide. Propagation below the cut-off frequency of the waveguide is generally possible and, according to the configuration, the propagating waves may be used for plasma generation or for RF power transmission. A new kind of high power microwave waveguide switch, based on the properties of plasma waveguides, is proposed. The design of new kind of magnetron, the "Glow Discharge Inverted Magnetron" ("GDIM"), is presented. The GDIM is an inverted magnetron with the resonant structure located on the cathode. The resonant cavities are used as a source of glow discharge electron beams, which gives high power operation without requiring relativistic voltages.
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Zhang, Ling. "Low power high performance interconnect design and optimization." Diss., [La Jolla] : University of California, San Diego, 2009. http://wwwlib.umi.com/cr/ucsd/fullcit?p3368979.
Full textAbstract:
Thesis (Ph. D.)--University of California, San Diego, 2009.Title from first page of PDF file (viewed September 17, 2009). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 113-118).
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Nho, Hyunwoo. "A high-speed, low-power 3D-SRAM architecture /." May be available electronically:, 2008. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
Full text
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Liu, Yushi. "Low Profile, High Power Density and High Efficiency DC-DC Converters." Thesis, University of Colorado at Boulder, 2019. http://pqdtopen.proquest.com/#viewpdf?dispub=10980034.
Full textAbstract:
Due to the ever decreasing thickness and increasing battery size of modern cellphones, battery chargers inside cellphones are required to meet increasingly stringent power density requirements, including small printed circuit board (PCB) area and component height. This thesis is focused on low-profile, high-power-density, and high-efficiency dc-dc converters for battery charging applications.
This thesis investigates five topologies, including ZVS-QSW buck converter, three-level buck converter, four-level buck converter, a resonant switched capacitor converter, and a new reconfigurable hybrid switched capacitor converter. The operation principle of each topology is described, and the advantages and disadvantages of each topology are analyzed and compared in terms of efficiency and power density. To accurately evaluate the performance of each topology, this thesis utilizes the augmented state-space modeling method that efficiently calculates the steady-state waveforms of a converter. To accurately predict losses, the dynamic on-resistance of GaN transistors and core loss of inductors have been modeled. Furthermore, a comprehensive optimization methodology is utilized to select circuit and component parameters.
For 2:1 conversation ratio application scenario, two prototypes using GaN transistors and low-voltage Silicon MOSFET have been designed, built and tested for an input voltage range of 5 V to 20 V, an output voltage range of 3 V to 4.2 V, and a maximum output current of 10 A. The prototype with GaN transistors (EPC2023) occupies a PCB area of 358 mm2 with component height of 1 mm. To maximize efficiency, the converter is designed to achieve ZVS at light-to-medium loads, while sacrificing ZVS to reduce transistor conduction and inductor losses. This prototype converter achieves a peak efficiency of 98.5%. The prototype using low-voltage Silicon MOSFET (CPF03433) occupies a PCB area of 310 mm2. A prototype of four-level buck converter with a PCB area of 410 mm2, optimized for 3:1 conversion ratio, has also been built and tested. For extreme-power-density application, a prototype with a PCB area of 79.6 mm2 and component height of 1 mm is built and tested. The prototype converter achieves a peak efficiency of 96.7% and a power density of 3230 W/in3.
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OJHA, RAM MOHAN. "DESIGN OF HIGH GAIN LOW POWER AMPLIFIER." Thesis, 2012. http://dspace.dtu.ac.in:8080/jspui/handle/repository/14145.
Full textAbstract:
The analog electronics circuits have been developed much better from the past few decades. The design of analog amplifier has become the field of attraction due to various changes in technology. Amplifier circuits are analog circuit which can be used anywhere in houses like in electronic appliances. A variety of these devices such as Operational Amplifier, Fully Differential Amplifier, Current Feedback and Current Conveyors are spread all over in the integration of such electronic devices. In analog processing system Operational Amplifier is considered as a key element.
A CMOS single output two stage operational amplifier is presented which operates at 1.8 V power supply. It is designed to meet a set of provided specifications. The unique behavior of MOS transistor in sub-threshold region allows designer to work at both low input bias current and also at low voltage. This op-amp has very low standby power consumption with a high driving capability and operates at low voltage so that the circuit operates at low power. The op-amp provides a gain of 95.2 dB, -3db bandwidth of 80 Hz, phase margin of 64.60 and a unity gain bandwidth of 1.49 MHz for a load of 1 pF capacitor. This op-amp has a PSRR of 148.2 dB. It has a CMRR (dc) of 99.1 dB, and an output slew rate of 11.9 V/μs. The power consumption for the op-amp is 54.2 μW. The presented op-amp has Input Common Mode Range (ICMR) of 0.2V to 1.3V. The op-amp is designed in the 180 nm technology using the 180 nm technology library.
The described op-amp is a simple two stage single ended op-amp which employs composite cascode technique. The input stage of the op-amp is a differential amplifier with an NMOS pair. The second stage of the operational amplifier is a simple PMOS common source amplifier. The second stage is used to increase the voltage swing at the output. The schematic of the operational amplifier has been designed and simulation is done using PSPICE simulator thereafter results are compared with the previous reported design.
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Huang, Kuo Ching, and 黃國清. "24GHz High Gain Low Power Low Noise Amplifier and Low Power Down-Conversion Mixer." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/57178811540405199796.
Full textAbstract:
碩士長庚大學
電子工程學系
98
This thesis presents the development of RF CMOS circuits for 24GHz transceivers including high gain, low power, low noise amplifier and low power down-conversion mixer with TSMC 90nm RF CMOS standard process and 0.13µm RF CMOS standard process. All circuits were simulated and designed by Agilent ADS (Advanced Design System) software. The CMOS RF receiver is focused on low power consumption, and operated at frequency of 24GHz. This work includes low-noise amplifier and down-conversion mixer. The operating radio frequency is 24GHz, and the supply voltage is 1.2V. In this thesis, the low-noise amplifier has a power gain of 18.212dB and noise figure of about 2.977dB. Input and output return losses are smaller than -15dB and power consumption of 2.87mW and chip area of 0.796x0.703mm2. Low power down conversion mixer shows a conversion gain of 7.237dB and the return loss of RF Port is smaller than -12dB. Power consumption is 8.07mW, and IIP3 of -3.7dBm. The LO to BB isolation and RF to BB isolation are -30dB and -30dB, respectively. The chip area is 0.89407x0.58mm2.
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Yeh, Yu-Ying, and 葉又穎. "Design of Low Power High Gain Low Noise Amplifiers for Wideband Application." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/m3dcj6.
Full textAbstract:
碩士國立東華大學
電機工程學系
104
Receiver design is one of the most challenging aspects in the implementation wireless communication systems. Low noise amplifiers (LNAs) are the key blocks of receivers for amplifying weak signals from antenna. The design goal of LNAs are high gain, low noise figure (NF), good input and output matching, high linearity, small die area and low power consumption. In this thesis, two LNAs are proposed with low power and high gain for different wireless communication system applications. The first chip is an ultra-wide band (UWB) LNA with wireless local area network (WLAN) band rejection. UWB systems are operated at frequency band from 3.1 to 10.6GHz with very low transmission power. Within UWB band, there are signals of 5.725-5.825GHz from WLAN systems, which the signal strength is larger than the transmission power of UWB systems. Such signals are called in-band interference. The designed UWB LNA with 5.8GHz notch filter can avoid interference signal from WLAN system. The input stage is based on common gate amplifier. Also, the proposed UWB LNA uses the stagger tuning technique for extending the bandwidth with a flat gain. The notch filter with extremely high quality factor provides high band rejection ratio. The second chip is a low power high gain low noise amplifier for Long Term Evolution (LTE) system application. The complementary feedback amplifier is used in the first stage. A body-biased architecture is added to lower supply voltage so as to save the power consumption. The second stage is a cascade amplifier which provides high gain. The output stage is common-drain amplifier to achieve output impedance matching. The proposed LNAs were simulated and fabrication by using 0.18m CMOS process technology which is provided by Chip Implementation Center of National Applied Research Laboratory. The simulation results show that the proposed low power UWB LNA with WLAN band rejection. The power consumption is 9.6mW at 1V supply voltage. The maximum power gain and minimum noise figure is 15.4 and 4.9dB, respectively. The input reflection coefficient and output reflection coefficient are both less than -10dB. The maximum interference rejection (IRR) is 40.5dB. The chip size is 1.164×0.905mm2. The second chip is a low power high gain LNA for LTE application. The simulation results of the second chip are obtained by the same process as that of the first one. The power consumption is 4.87mW at 1V supply voltage. The maximum power gain is 19.9dB. The minimum noise figure is 2.55dB. The input reflection coefficient and the output reflection coefficient are both less than -10dB. The chip size is 1.185×0.776mm2. ¬The EM simulation results show that both LNAs achieved characteristics of low power and high gain.
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He, Jheng-Jie, and 何政杰. "Design of High Gain Low Power Mixers for Vehicle Systems Application." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/nxp53r.
Full textAbstract:
碩士國立東華大學
電機工程學系
106
In recent years, due to the rapid development of wireless communication systems and advances of CMOS process technology, Transceiver design is an important key in wireless communication systems. The mixer at the front end of the transceiver needs to mix the signal of the previous low-noise amplifier with the signal of the local oscillator to deliver the mixed-signal signal. In the thesis ,both two mixers are based on architecture of a traditional Single-balanced Mixer. Useing current-bleeding technology improve conversion gain and power consumption performance ,The first mixer chip is designed within 24GHz of FMCW operation. The load stage utilizes a common-mode feedback circuit to improve performance. Under the supply voltage of 1.2 V , circuit performances are achieved with a gain 14.4 dB. Noise figure is 11.3 dB. IIP3 is -9dBm The core power consumption is 4.47 mW. The chip size is 0.944×0.744mm2 The second mixer chip with high conversion gain and low power consumption is proposed for 20-28 GHz of UWB pulse wave a operation. The load stage utilizes cross-coupled pair to improve conversion gain performance. Under the supply voltage of 1.2V, performances are achieved with a gain of 14.3dB.Noise figure is 11.6dB. IIP3 is -3dBm The core power consumption is 5.25 mW. The chip size is 0.722×0.869mm2 The proposed mixer chips were fabricated using tsmc 0.18m 1P6M CMOS processes technology.The circuit verification and simulation are done by using advanced design system (ADS). Especially, The proposed chips was obtained by using a cloud server which is provided by National Chip Implementation Center.
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Yen, Wei-de, and 顏維德. "Design of a 24 GHz High Gain and Low Power Consumption Low Noise Amplifier." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/s5ys89.
Full textAbstract:
碩士國立中山大學
電機工程學系研究所
102
Due to the increasing percentages of traffic accidents in our society, many automobile manufacturers devote to develop various automotive anti-collision radar warning systems. Utilizing these radar warning systems, drivers can make some responses for preventing accident occurring within few seconds. However, for the automotive collision avoidance radar receivers, low-noise amplifiers must have the abilities of highly stable and amplify the signal to ensure the messages are shown perfectly and accurately, which give motorists attentions of traffic accident. To achieve the above characteristics, the traditional low-noise amplifiers consume greater power to meet the high-gain and stable functions. Therefore, this thesis employs the TSMC 0.18 μm CMOS process to develop low-noise amplifiers designs with both high gain and low power consumption which can be implemented in automotive anti-collision radars. This thesis utilizes dual stage to simplify complexity of the circuit without sacrificing the power consumption. In order to effectively increase the gain and stability, the proposed low-noise amplifiers comprises a negative resistance of a gm-boosted technology, the concept of zero-pole point, the paralleled RC structure, a source follower buffer and a source-degeneration structure employed into the input stage improving input matching. The proposed low noise amplifier with 1.4 mm × 0.7 mm chip size and its 24 GHz operating frequency is well suited for automotive radar (22-29 GHz) application. This low noise amplifier shows a very high-gain of 21.2 dB. Moreover, the amplifier presemts input return loss of -18.1 dB, very good output return loss of -28.1 dB and excellent isolation of -65.6 dB. Finally, a moderate consuming power are 15.8 mW of low noise amplifier from 1.5 V supply voltage.
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Hou, Han-Jiun, and 侯鈞瀚. "A 4.15mW Low-Power High-Gain Current-Reuse Low Noise Amplifier Design Working in 5.2GHz Band." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/60798995005364215973.
Full textAbstract:
碩士國立高雄應用科技大學
電機工程系
98
A current-reuse low noise amplifier using standard 0.18μm RFCMOS technology is proposed in this paper. The low noise amplifier is applicable on IEEE 802.11a 5.2 GHz at 0.8 V supply. The core circuit of the low noise amplifier has been designed based on current-reuse architecture and uses a source follower method for output impedance to 50Ω. Firstly, this thesis briefly introduces the fundamental theory of different kinds of low noise amplifier circuit. Secondly, we focus on low power consumption as the starting point to compared and benchmark several kinds of circuitries to achieve the low supply voltage technology of low noise amplifier circuit. The fundamental design guide line of low noise amplifier circuit is analyzed in this paper. Thirdly, the design procedures and optimization schemes of low noise amplifier circuit are presented. In order to achieve both the high gain and low voltage operation, the proposed low noise amplifier circuit uses a low Vt mos and an source follower. Agilent Advanced Design System (ADS) RF simulator and TSMC 0.18μm device model are adopted to prevail the low noise amplifier integrated circuit design. Low supply voltage and low power consumption are considered for low noise amplifier circuit as the key performance indexes in order to optimize and fine-tune low noise amplifier circuit. The low noise amplifier design is fabricated by using TSMC 0.18μm standard CMOS process via National Chip Implement Center (CIC) foundry chip service. The gain of this low noise amplifier achieves as high as 21.7 dB at 5.2 GHz under the supply voltage of 0.8 V. The low noise amplifier exhibits a noise figure of 2.8 dB and the isolation is greater than 47 dB. The DC power consumption of this low noise amplifier is only 5.2 mW. The chip area is 0.99 × 0.76 mm2. The figure of merit (FoM) of this low noise amplifier reaches 2.8 dB.
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Chang, Ke-Wei, and 張克瑋. "Low-Power, Low-Noise, and High-Gain Analog Front-End Amplifier for Parkinson\'s Disease Treatment." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/v7r2xg.
Full textAbstract:
碩士國立交通大學
電機工程學系
107
With the help of levodopa and other medications, Parkinson patients have had their Parkinson symptoms improved in the recent years. However, continuous and periodic levodopa dosage increases the chance of developing other side effects, such as involuntary movements as well as compulsive withdrawal syndrome. This is where a more technological approach is introduced, the “Deep Brain Stimulation”, whose operating principle is stimulating the patient’s brain through the buried electrodes when necessary. This thesis is to propose a fully differential preamplifier circuit to amplify the cell’s local field potential signal related to Parkinson’s disease, so that the acquired signals can be processed by the ADC, and DSP that follows. Knowing that the signals are miniature, the preamplifier must achieve high gain and low noise. To accomplish low input referred noise in the transistor level, the input pairs in the first stage fully differential operational amplifier have to be large in size and operate in the weak inversion region. The high gain characteristic is stacked up using the ratio of the input and feedback capacitors and resistors in three stages while reducing corner variations. The preamplifier achieves a bandwidth of 0.5Hz to 100Hz, a programmable gain of 70dB, 80dB, and 90dB, and a noise of 2.4uVrms in TSMC 0.18um standard CMOS 1P6M process with a power supply of 1.8V.
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Yiu, Chun-Chee Francis. "Gain-reconfigurable Current-sensing Circuit for High-frequencey Low-power DC-DC Converters." Thesis, 2010. http://hdl.handle.net/1807/24290.
Full textAbstract:
A novel current-sensing circuit that can operate from 1MHz to 4MHz has been designed and implemented for high-frequency low-power dc-dc power converter applications. The design is based on SenseFET concept with embedded SenseFETs in the main switch (MS) and synchronous rectifier (SR). An intermediate RC filter merges outputs from the MS and SR SenseFETs and supplies a smooth voltage signal to an op-amp. This reduces the need for a very high gain-bandwidth op-amp circuit and improves the efficiency of the power converter. The circuit has configurable feedback gain in order to increase current sensing accuracy when the average inductor current is small.
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Ranganathan, Sachin. "Design of a variable gain, high linearity, low power baseband filter for WLAN transmitters." Thesis, 2003. http://hdl.handle.net/1957/32350.
Full textAbstract:
A variable gain, high linearity, low power baseband filter for WLAN applications
is implemented in a 1.5 V 3 V 0.15 ��m CMOS process. This fourth-order
low-pass filter, which is introduced in the transmit channel as a reconstruction filter
between the D/A converter and the mixer, has a measured cut-off frequency of
9 MHz. The active-RC configuration has single amplifier biquads (SABs) to save
power and is implemented using three-stage opamps with nested-Miller compensation
for better linearity. It also features a special ��-to-Tee transformation network
for the resistor arrays, used for frequency or gain trimming, in order to obtain higher
linearity than conventional Sallen-Key circuits. The measured THD for a 2 V [subscript p-p]
signal at 1 MHz is -72 dB.Graduation date: 2004
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Fang, Wei-Hsien, and 方偉憲. "Low-Power Operational Amplifier with High-Gain Rail-to-Rail Input and Output Ranges." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/70004757408515675928.
Full textAbstract:
碩士淡江大學
電機工程學系碩士在職專班
98
A low-power high-gain CMOS operational amplifier with rail-to-rail input/output ranges is presented in this paper. A constant-gm controller is employed in the input stage to achieve an optimum bandwidth and settling response in a wide operational range. A differential-input single-output gain-boosting amplifier without common-mode feedback is applied to minimize the power consumption and increase the dc gain of opamp. The floating current sources are also introduced to the cascode stage to provide proper bias levels for the class AB output stage. The proposed opamp can load with a large capacitance or a small resistance loads without losing the gain and unity-gain bandwidth. It has been fabricated in a 0.35 μm 2P4M CMOS process. With a 50 pF of the output capacitance load, a 123dB of dc gain and a 1.52MHz of unity-gain frequency can be achieved in the proposed opamp. The total power dissipation is only 0.36 mW at a 3.3 V of supply voltage.
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Chen, Ting-Chun, and 陳亭君. "Design and Analysis of 24GHz Low Power and High Gain Receiver Front-End Structure." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/65352360093279126647.
Full textAbstract:
碩士國立交通大學
電信工程研究所
103
This thesis consists of three parts. All the proposed circuit were implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology. Part I present a three-stage wideband LNA design in k-band. This LNA design use two-stage common-source and one-stage cascode structure. The simulation result shows the noise and power of the proposed circuit is low while the gain is high. The measurement result, however, is not as good as the simulation result owing to the oscillation occurring on certain frequency. According to the 3-dB bandwidth is 23 – 26 GHz and the peak gain is 8 dB at 21 GHz. The input return loss and output return loss are below -10 dB. The noise figure is 5.5 – 6.8 over the frequency band. The P1dB is -7dBm and IIP3 is -1.15 dBm at 24GHz. Total power dissipation is 23.4mW. The measured FOM of the proposed LNA is 0.227. Part II proposed a high gain down-conversion mixer with capacitance cross-coupled technique. The first stage of the proposed design is a differential LNA with cross-coupled design; the switching stage uses the current bleeding technique; these ensure high gain and low power dissipation. Due to the imperfect post-simulation, the measurement oscillates at the IF frequency. The simulated gain of the mixer reaches 19.53 dB and the 3-dB BW is 9GHz; the double-side band minimum noise figure is 7.5 dB; the P1dB is -13.7 dBm and the IIP3 is -9dBm at 24GHz. The power dissipation excludes the output buffer is 4.79mW. Part III presents a 24GHz high gain low power receiver front-end. In this chapter a new LNA and balun is implemented and the mixer is reused in last chapter. The conversion gain is 31dB and the noise figure is 5.45 dB; IIP3 is -11 dBm and the P1dB is -25 dBm at 24GHz. The LO-IF leakage is less than -50 dB; the LO-RF leakage is less than -50dB; the RF-IF leakage is less than -35dB. Total power consumption excluded output buffer is 24.59 mW.
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Chiu, Po-Ju, and 邱柏儒. "Design of Low Phase Noise Current-Reused VCO and Double-Balanced Mixer with Low Power and High Gain." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/77699149475831248901.
Full textAbstract:
碩士國立交通大學
電信工程研究所
100
This thesis consists of three parts. All the proposed circuits were implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology. Part I presents a low phase noise current-reused VCO (CR-VCO). Owning to the conventional current-reused VCO (CR-VCO) needs a high capacitance external capacitor (Cgnd) to connect the source terminals of the transistors (20PF up). By connecting the Cgnd with an inductance in series, the capacitance of Cgnd will not only largely decrease from 20PF to 1PF, but also it could fully integrate in a single chip without adding an external capacitor. According to the measured results, the oscillation frequency is 4.78 - 5.33GHz, and the power consumption is about 5.76mW at the supply voltage of 1.8V. The phase noise at 1MHz offset is -117.8dBc/Hz and the figure-of-merit (FOM) of the proposed VCO is about -183.78dBc/Hz. Part II presents a back-gate coupled current-reused quadrature VCO (CR-QVCO) which use double feedback mechanism to accomplish modified spontaneous transconductance match (M-STM) technique. This method is able to eliminate the transconductance difference between NMOS and PMOS transistors so that high output amplitude balance can be achieved. According to the measured results, the oscillation frequency is 4.84 - 5.17 GHz, and the power consumption is about 5.04mW at the supply voltage of 1.3V. The phase noise at 1MHz offset is -117.4dBc/Hz and the figure-of-merit (FOM) of the proposed QVCO is about -184.07dBc/Hz. Part III proposes a double-balanced mixer with low power and high gain. In general, active mixer could provide better conversion gain. Gilbert-cell mixer could provide better LO-IF isolation comparison with single-balanced mixer, but it needs to pay the cost of larger power consumption and noise figure. Therefore, we try to design a mixer topology with high gain and low power in this part. By adding coupling capacitors to increase the transconductance, it could enhance the conversion gain instead of increasing RL. According to the simulated results: The conversion gain of the 15GHz double-balanced mixer is 17.0dB, increasing about 4.7dB compared with the mixer without coupling capacitors. The noise figure (NF) is about 21.0 dB. And the power consumption is about 3.6 mW at the supply voltage of 1.8V
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Hsu, Yuan-Wen, and 許媛雯. "Design of Low-Power High-Gain Operational Amplifier with Rail-to-Rail Input and Output Ranges." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/10397192373285911996.
Full textAbstract:
碩士淡江大學
電機工程學系碩士在職專班
102
This thesis presents an operational amplifier which function could meet the new requirement of nowadays. Following the improvement of VLSI (Very Large Scale Integrated Circuits) design and CMOS (Complementary Metal Oxide Semiconductor) process, the design of OPA (Operational Amplifier) has many choices for different applications and purposes. The new tendency of OPA applications would be high gain, low power consumption, rail-to-rail input/output range, better stability, better driving capability and low cost, etc., which would be the goal of this proposed OPA to be designed. The architecture of this proposed OPA includes 3 major stages: the first stage is the differential inputs stage combined with constant-gm controller; the second stage is the folded-cascode amplifier stage constructed of cascode, floating current source and gain boosting amplifiers; the third stage is the single-ended output stage consisted of a class AB push-pull amplifier. The goal of this OPA is to achieve that gain equals over 120dB, phase margin equals around 60°~63°, unity-gain frequency equals 1.5MHz, power consumption equals 0.37mW, the input/output range reaches the maximum, and the driving load is up to 50pF capacitor or lowest to 10kΩ resistor, etc. The fabrication of this proposed OPA is implemented by the 0.35μm 2P4M CMOS process of CIC (Chip Implementation Center). The final result of this OPA is that gain equals 123dB, phase margin 61.4°, unity-gain frequency 1.52MHz, power consumption equals 0.37mW, the input/output range reaches from 0V to 3.3V, and the driving load is stable up to 50pF capacitor or lowest to 10kΩ resistor.
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Liu, Yen-Jen, and 劉晏任. "A Low Power and High Dynamic Range Automatic Gain Control Amplifier in 0.35um 1P4M CMOS Technology." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/41355215088960817117.
Full textAbstract:
碩士國立清華大學
電子工程研究所
91
In this project, an automatic gain control(AGC) amplifier is analyzed and designed. It was fabricated with TSMC 0.35um 1P4M CMOS technology and the size of the chip is 0.928um×0.67895um. We use a V-V Converter to decrease the power consumption and increase dynamic range. We simulate all circuits by Hspice. The supply voltage is 3V. The dynamic range is 57dB and the noise figure is 11.2338dB. The total power consumption is 6.2664mW and the gain range of VGA is 84dB.
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Dai, Yu-Hsiu, and 戴瑜秀. "A High Gain Low Noise Mixer with Low Power Consumption for WLAN Application and A Triple Band Circularly Polarized Antenna." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/32868316067013888375.
Full textAbstract:
碩士國立交通大學
電信工程研究所
101
This paper consists of three parts. All the proposed circuits were implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology; and the antenna design is fabricated on an FR4 substrate. Part I, It’s a design of low noise mixer, the trans-conductance stage is implemented with low-noise amplifier cascade structure, a cross capacitance was connected between the terminal gate and source of the input stage transistor, and the input differential pair was combined together by a current source transistor, the function of this transistor is not only as a current controller but also effects the input impedance to achieve a suitable value. The trans-conductance cause the noise cancelling, in addition to this, the first stage consist of cascade architecture and it provide a high power gain to reduce the noise factor in the overall system; for switching pairs, the parasitic capacitance resulting frequency response is cancelled by an additional inductive peaking, the conversion gain versus operation frequencies will become flat; in other words, overall 3dB bandwidth will not be compressed; the following techniques gives us an excellent FOM values. According to the measurement results showed that: The S parameter are blow to -10 dB for operation frequency band 5~6GHz, and it has high conversion gain from 26.7dB to 27dB, a flat DSB noise figure 7.3~8dB, at the frequency 5.2GHz with the maximum conversion gain, the IIP3 is -12dBm, and the power consumption is 11.32mW. The FOM is 15.5 dB. Part II, the mixer design is expected to maintain a high gain and low noise. In addition, low power consumption is an important aim, with the consideration, in order create a high conversion gain but not to increase the current on the DC path, using the CG configuration as the input stage and an additional signal path is used to increase the equivalent value of trans-conductance, it implement by a negative feedback path to turn down the noise comes from gate leakage through the input parasitic capacitance path to source; to make up the low input impedance value caused by the negative feedback path, use positive feedback path to increase the input impedance value and increase the overall gain value, switch-pairs implement with PMOS transistors, instead of the traditional NMOS architecture; in this way, it can reduce the voltage headroom, and the noise source caused by the switching pairs will not leakage from parasitic to affect the trans-conductance stage. As above-mentioned improve techniques, measurement results can be obtained as the following: S parameter in the operating frequency 5 ~ 6GHz bands is below to -10dB, and it has high power gain 25dB, noise figure of 3.9 ~ 4.2dB, in the case of the highest gain IIP3 is measured as-8dBm, and the overall power consumption is reduced to 3.92mW, available FOM value increased to 23.67dB. Part III, In this proposed antenna architecture, the triple-band printed monopole antenna with triple band circular polarization is presented. The antenna generates circular polarization by two circular patches and a L shape strip. The proposed antenna can provide impedance bandwidths of 33% for 2.5GHz band, 25% for 3.5GHz band, and the 9.79% for 5.2GHz band, respectively. The axial-ratio bandwidths achieved 11.4% for 2.5GHz, 6.2% for 3.5GHz, and the 11.8% for 5.2GHz, respectively. The proposed antenna is fabricated on FR4 substrate. The operating triple frequencies cover 2.5GHz, 3.5GHz and 5.2GHz, so that the antenna could be used in WiMax and WLAN application.
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Luo, Ren-wu, and 羅仁武. "Design of a High Conversion Gain and Low Power ConsumptionRF Front-end Receiver for 4G Mobile Network System." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/28445410855443826264.
Full textAbstract:
碩士國立中山大學
電機工程學系研究所
103
Since the global mobile communication systems and the wireless multimedia markets are increasing rapidly, various innovative electronic devices or circuits with higher transmission bandwidth, lower delay time and high-speed data rate are developed for matching the requirements of the new-generation global mobile communication products (Long Term Evolution, LTE). However, for providing higher power conversion gain, the new-generation receiver chip will consume larger power than that of 3G products. In this thesis, a wide-band (0.5~2.8 GHz) front-end receiver with high power conversion gain (≥ 15 dB), high linearity (≥ -10 dBm), low input insertion loss (≤ -15 dB), low noise figure (≤ 10 dB) and low power consumption (≤ 40 mW) are developed utilizing TSMC 0.18 μm CMOS technology and which can be used in 4G mobile network system. The proposed receiver chip is including a low noise amplifier (LNA), a variable gain amplifier (VGA) and a down-conversion mixer. The conversion gain, power consumption and bandwidth of the receiver can be improved by using self-biasing inverter and feedback resistor architectures. In addition, a source degeneration technique and RC-tank load are adopted in the proposed mixer to enhance the linearity and suppress high frequency signal, respectively. The chip size and operation frequency of the implemented receiver were 1.2 × 1.0 mm2 and 0.5~2.8 GHz, respectively. Under the optimized conditions, a high conversion gain (31.2 dB), high linearity (the Input third-order Intercept Point, IIP3 =-6.1 dBm), low input return loss (-20.1 dB), high reverse isolation (-72 dB) and low noise figure ranges (4.2 dB) and low power consumption (20 mW, at 1.8 V supply voltage) of the presented receiver chip can be demonstrated in this research and such characteristics are well suitable for 4G mobile communications system applications.
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Yu, Chih-Chieh, and 尤致捷. "Ultra Low-power VCO Designed with Body-biased Technology and High Conversion Gain Mixer Designed with Body-injected Technology." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/26686782675382937801.
Full textAbstract:
碩士龍華科技大學
電子工程研究所
97
An ultra low-power voltage control oscillator (VCO) designed with body-bias technology and high conversion gain mixer designed with body-inject technology are studied of this thesis. The oscillator portion uses a pMOS cross-coupled structure, while the mixer modifies from Gilbert Cell topology with local oscillator (LO) signal inject into body of MOS. The ultra low-power VCO designed is operating in 5GHz band. The proposed VCO is implemented in TSMC 0.18-μm 1P6M CMOS technology. With 0.49-V supply, it achieves a phase noise of -114.8 dBc/Hz at 1-MHz offset. Tuning range is 340MHz with control voltage from -1V to 1.5V. Figure-of-Merit (FoM) is -188.5dB, and the total power consumption is 0.99mW. The high-gain mixer is designed to be used in 5.2GHz U-NII band. The proposed mixer is implemented in TSMC 0.18-μm 1P6M CMOS technology. The down-converted intermediate frequency (IF) is 55MHz. With 0.8-V supply, it achieves conversion gain of 13.22 dB and SSB noise figure of 18.747 dB. The 1dB compression point is -25.16 dBm. Input Third-order Intercept Point(IIP3) is -14.998 dBm. Isolation of RF to IF is 86.8 dB and isolation of LO to RF is 59.7 dB. The total power consumption is 0.698 mW.
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Chen, Wen-Sheng, and 陳文生. "Design and Analysis of 3.1-10.6 GHz UWB LNA and 24-GHz Low-Power High-Gain Receiver Front-End Circuit." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/76027471132284029500.
Full textAbstract:
碩士國立交通大學
電信工程研究所
103
This thesis consists of two parts. All the proposed circuits were implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology. Part I presents an ultra-wide band low-noise amplifier applied to WPAN (Wireless Personal Area Network.), and a common gate architecture and noise-cancelling technique are employed in this amplifier. Using these techniques can not only suppress the total noise contribution in the output but increase the total gain with an excellent input wideband matching. According to the measured results, the LNA achieves the small signal gain of 9.7~11.6 dB, a noise figure of 4.54~4.85 dB, the input P1dB of -19 dBm, and the input IP3 of -9.5 dBm over the whole working range. The power consumption is about 16.9 mW at the supply voltage of 1.8V. Part II proposes a low-power high-gain receiver front-end applied to 24-GHz ISM band. The receiver front-end contains a low-noise amplifier, a transformer balun, a down-conversion mixer and an intermediate frequency amplifier. In LNA design, using two stage common source structure cascaded with common gate structure realizes performance of high gain and low-noise with the limited power dissipation; in down-conversion mixer design, making use of cross-coupling and current-bleeding techniques obtains high gain and low power consumption. Furthermore, an intermediate frequency amplifier is added after the down-conversion mixer so the whole conversion gain increases once more. Therefore, the proposed receiver front-end has advantage of low power and high gain compared to other researches. This circuit achieves a conversion gain of 37.1 dB and a double-side band noise figure of 5.65 dB with the input P1dB of -33.5 dBm, output P1dB of 2.1 dBm, and input IP3 of -23 dBm consuming 37.1 mW.
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(7043102), Sami Saleh Alghamdi. "Electrical Characterization of Emerging Devices For Low and High-Power Applications." Thesis, 2019.
Find full textAbstract:
In this thesis, an
interface passivation by a lattice matched atomic layer deposition (ALD)
epitaxial magnesium calcium oxide (MgCaO) on wide-bandgap gallium nitride (GaN)
has been applied for the first time and expensively studied via various
characterization methods (including AC conductance methods, pulsed
current-voltage, and single pulse charge pumping). Also, beta-Ga2O3 with a monoclinic crystal
structure that offers several surface oriented channels has been demonstrated
as potential beta-Ga2O3 FET. On the other hand,
low frequency noise studies in 2-D MoS2 NC-FETs was reported for the first
time. Low frequency noise of the devices is systematically studied depending on
various interfacial oxides, different thicknesses of interfacial oxide, and ferroelectric
hafnium zirconium oxide. Interestingly enough,
the low frequency noise is found to decrease with thicker ferroelectric HZO in
the subthreshold regime of the MoS2 NC-FETs, in stark contrast to the
conventional high-k transistors. Also, the
ferroelectric switching speed is found to be related with the maximum electric
field applied during the fast gate voltage sweep, suggesting the internal
ferroelectric switching speed can be even faster depending on the device’s
electrical bias conditions and promises a high speed performance in our
ferroelectric HZO
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Hu, Yun-Chung, and 胡運忠. "Low Power Variable Gain Amplifier for UWB systems." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/13040808438308906179.
Full textAbstract:
碩士中原大學
電子工程研究所
95
The booming development of the wireless communication technology in recent years make the relevant products, such as GSM, CDMA, Bluetooth, 802.11 (Wi-Fi), ZigBee and Ultra wide band (UWB) widely used in our daily life and became important research topics. This thesis proposes a Variable Gain Amplifier (VGA) that is suitable for UWB system. It consists of a main amplifier, gain control circuit, and a common mode feedback loop. The main amplifier is realized by a folded cascode amplifier with feedback and the gain control function is utilized by a source-coupled pair to realize controllable gain. A modified pseudo-exponential equation is proposed to improve the linearity of the proposed VGA. The circuit is designed and simulated in TSMC 0.18um CMOS process. The gain range of 18dB and the 3dB frequency of 610MHz at the maximum gain that meets the specification of UWB system is obtained. The power dissipation is less then 2mW at 1.8V supply voltage.