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Journal articles on the topic 'Heterogeneous embedded systems'

Author: Grafiati

Published: 22 October 2022

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1

Berrahou, Aissam, Nassim Sefrioui, Ouafaa Diouri, and Mohsine Eleuldj. "Exploration of Heterogeneous Resources in Embedded Systems." International Review on Computers and Software (IRECOS) 9, no. 9 (September 30, 2014): 1597. http://dx.doi.org/10.15866/irecos.v9i9.3160.

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2

Grimm, Christoph, Axel Jantsch, Sandeep Shukla, and Eugenio Villar. "C-Based Design of Heterogeneous Embedded Systems." EURASIP Journal on Embedded Systems 2008, no. 1 (2008): 243890. http://dx.doi.org/10.1155/2008/243890.

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3

Syschikov, Alexey, Yuriy Sheynin, Boris Sedov, and Vera Ivanova. "Domain-Specific Programming Environment for Heterogeneous Multicore Embedded Systems." International Journal of Embedded and Real-Time Communication Systems 5, no. 4 (October 2014): 1–23. http://dx.doi.org/10.4018/ijertcs.2014100101.

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Nowadays embedded systems are used in a broad range of domains such as avionics, space, automotive, mobile, domestic appliances etc. Sophisticated software determines the quality of embedded systems and requires high-qualified experts for software development. Software becomes the main assert of embedded systems that is valuable to retain in changing computing platforms in embedded systems evolution. Computing platforms for embedded systems became multicore processors and SoC, they can change in the embedded system lifetime that could be long (dozen of years for an automobile and airplane). It requires software porting to new platforms as a regular process. Many tools and approaches allow developing of software for domain area experts, but mainly for general-purpose computing systems. In this paper the authors present the complex technology and tools that allows involving domain experts in software development for embedded systems. The proposed technology has various aspects and abilities that can be used to build verifiable and portable software for a wide range of embedded platforms.

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Latif, Rachid, and Amine Saddik. "Embedded implementation of biomedical applications in heterogeneous systems." Biomedical Spectroscopy and Imaging 8, no. 3-4 (January 27, 2020): 73–80. http://dx.doi.org/10.3233/bsi-200192.

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5

Edwards, S. A., and O. Tardieu. "SHIM: a deterministic model for heterogeneous embedded systems." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, no. 8 (August 2006): 854–67. http://dx.doi.org/10.1109/tvlsi.2006.878473.

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6

Radojevic, Ivan, Zoran Salcic, and Partha Roop. "Design of Distributed Heterogeneous Embedded Systems in DDFCharts." IEEE Transactions on Parallel and Distributed Systems 22, no. 2 (February 2011): 296–308. http://dx.doi.org/10.1109/tpds.2010.69.

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7

Josko, Bernhard, Qin Ma, and Alexander Metzner. "5.1.2 Designing Embedded Systems using Heterogeneous Rich Components1." INCOSE International Symposium 18, no. 1 (June 2008): 558–76. http://dx.doi.org/10.1002/j.2334-5837.2008.tb00827.x.

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8

Monjau, D., and M. Sporer. "Semantic Modelling and Simulation of Heterogeneous Embedded Systems." International Journal of Modelling and Simulation 26, no. 3 (January 2006): 201–11. http://dx.doi.org/10.1080/02286203.2006.11442369.

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9

Jammalamadaka, Sastry Kodanda Rama, Valluru Sai Kumar Reddy, and Smt J Sasi Bhanu. "Networking Heterogeneous Microcontroller based Systems through Universal Serial Bus." International Journal of Electrical and Computer Engineering (IJECE) 5, no. 5 (October 1, 2015): 992. http://dx.doi.org/10.11591/ijece.v5i5.pp992-1002.

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Networking heterogeneous embedded systems is a challenge. Every distributed embedded systems requires that the network is designed specifically considering the heterogeneity that exits among different Microcontroller based systems that are used in developing a distributed embedded system. Communication architecture, which considers the addressing of the individual systems, arbitration, synchronisation, error detection and control etc., needs to be designed considering a specific application. The issue of configuring the slaves has to be addressed. It is also important that the messages, flow of the messages across the individual ES systems must be designed. Every distributed embedded system is different and needs to be dealt with separately. This paper presents an approach that addresses various issues related to networking distributed embedded systems through use of universal serial bus communication protocol (USB). The approach has been applied to design a distributed embedded that monitors and controls temperatures within a Nuclear reactor system.

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10

Garbo, Alessandro, and Stefano Quer. "Moving Object Detection in Heterogeneous Conditions in Embedded Systems." Sensors 17, no. 7 (July 1, 2017): 1546. http://dx.doi.org/10.3390/s17071546.

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Salcic, Zoran, Dong Hui, Partha S. Roop, and Morteza Biglari-Abhari. "HiDRA—A reactive multiprocessor architecture for heterogeneous embedded systems." Microprocessors and Microsystems 30, no. 2 (March 2006): 72–85. http://dx.doi.org/10.1016/j.micpro.2005.05.001.

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12

Pop, P., P. Eles, and Z. Peng. "Analysis and optimisation of heterogeneous real-time embedded systems." IEE Proceedings - Computers and Digital Techniques 152, no. 2 (2005): 130. http://dx.doi.org/10.1049/ip-cdt:20045069.

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13

Taylor, Ben, Vicent Sanz Marco, and Zheng Wang. "Adaptive optimization for OpenCL programs on embedded heterogeneous systems." ACM SIGPLAN Notices 52, no. 5 (September 14, 2017): 11–20. http://dx.doi.org/10.1145/3140582.3081040.

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14

Huang, Jing, Renfa Li, Jiyao An, Derrick Ntalasha, Fan Yang, and Keqin Li. "Energy-Efficient Resource Utilization for Heterogeneous Embedded Computing Systems." IEEE Transactions on Computers 66, no. 9 (September 1, 2017): 1518–31. http://dx.doi.org/10.1109/tc.2017.2693186.

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15

Maity, Srijeeta, Anirban Ghose, Soumyajit Dey, and Swarnendu Biswas. "Thermal-aware Adaptive Platform Management for Heterogeneous Embedded Systems." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–28. http://dx.doi.org/10.1145/3477028.

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Recent trends in real-time applications have raised the demand for high-throughput embedded platforms with integrated CPU-GPU based Systems-On-Chip (SoCs). The enhanced performance of such SoCs, however, comes at the cost of increased power consumption, resulting in significant heat dissipation and high on-chip temperatures. The prolonged occurrences of high on-chip temperature can cause accelerated in-circuit ageing, which severely degrades the long-term performance and reliability of the chip. Violation of thermal constraints leads to on-board dynamic thermal management kicking-in, which may result in timing unpredictability for real-time tasks due to transient performance degradation. Recent work in adaptive software design have explored this issue from a control theoretic stand-point, striving for smooth thermal envelopes by tuning the core frequency. Existing techniques do not handle thermal violations for periodic real-time task sets in the presence of dynamic events like change of task periodicity, more so in the context of heterogeneous SoCs with integrated CPU-GPUs. This work presents an OpenCL runtime extension for thermal-aware scheduling of periodic, real-time tasks on heterogeneous multi-core platforms. Our framework mitigates dynamic thermal violations by adaptively tuning task mapping parameters, with the eventual control objective of satisfying both platform-level thermal constraints and task-level deadline constraints. We consider multiple platform-level control actions like task migration, frequency tuning and idle slot insertion as the task mapping parameters. To the best of our knowledge, this is the first work that considers such a variety of task mapping control actions in the context of heterogeneous embedded platforms. We evaluate the proposed framework on an Odroid-XU4 board using OpenCL benchmarks and demonstrate its effectiveness in reducing thermal violations.

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Syschikov, A. Yu, B. N. Sedov, and Yu E. Sheynin. "INTEGRATED DOMAIN-SPECIFIC PROGRAMMING ENVIRONMENT FOR HETEROGENEOUS MANYCORE PLATFORMS." Issues of radio electronics, no. 8 (August 20, 2018): 133–44. http://dx.doi.org/10.21778/2218-5453-2018-8-133-144.

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Different classes of problems on the embedded systems market and its needs make manufacturers of embedded systems to design heterogeneous many/multi core hardware platforms. Such platforms includes dozens of different cores: CPU, GPU, DSP, FPGA etc. That makes them incredibly hard to program, especially in case when domain experts are involved in the development process. Usually, domain expert has knowledge in his domain area, but does not fully understand the specificity of programming for heterogeneous manycore platforms. In this article, we propose the complex technology and tools that allows involving domain experts in software development for embedded systems. The proposed technology has various aspects and abilities that can be used to build verifiable and portable software for a wide range of heterogeneous embedded platforms.

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17

Valente, Giacomo, Tiziana Fanni, Carlo Sau, Tania Di Mascio, Luigi Pomante, and Francesca Palumbo. "A Composable Monitoring System for Heterogeneous Embedded Platforms." ACM Transactions on Embedded Computing Systems 20, no. 5 (July 2021): 1–34. http://dx.doi.org/10.1145/3461647.

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Advanced computations on embedded devices are nowadays a must in any application field. Often, to cope with such a need, embedded systems designers leverage on complex heterogeneous reconfigurable platforms that offer high performance, thanks to the possibility of specializing/customizing some computing elements on board, and are usually flexible enough to be optimized at runtime. In this context, monitoring the system has gained increasing interest. Ideally, monitoring systems should be non-intrusive, serve several purposes, and provide aggregated information about the behavior of the different system components. However, current literature is not close to such ideality: For example, existing monitoring systems lack in being applicable to modern heterogeneous platforms. This work presents a hardware monitoring system that is intended to be minimally invasive on system performance and resources, composable, and capable of providing to the user homogeneous observability and transparent access to the different components of a heterogeneous computing platform, so system metrics can be easily computed from the aggregation of the collected information. Building on a previous work, this article is primarily focused on the extension of an existing hardware monitoring system to cover also specialized coprocessing units, and the assessment is done on a Xilinx FPGA-based System on Programmable Chip. Different explorations are presented to explain the level of customizability of the proposed hardware monitoring system, the tradeoffs available to the user, and the benefits with respect to standard de facto monitoring support made available by the targeted FPGA vendor.

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18

Campeanu, Gabriel, and Mehrdad Saadatmand. "A Two-Layer Component-Based Allocation for Embedded Systems with GPUs." Designs 3, no. 1 (January 19, 2019): 6. http://dx.doi.org/10.3390/designs3010006.

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Component-based development is a software engineering paradigm that can facilitate the construction of embedded systems and tackle its complexities. The modern embedded systems have more and more demanding requirements. One way to cope with such a versatile and growing set of requirements is to employ heterogeneous processing power, i.e., CPU–GPU architectures. The new CPU–GPU embedded boards deliver an increased performance but also introduce additional complexity and challenges. In this work, we address the component-to-hardware allocation for CPU–GPU embedded systems. The allocation for such systems is much complex due to the increased amount of GPU-related information. For example, while in traditional embedded systems the allocation mechanism may consider only the CPU memory usage of components to find an appropriate allocation scheme, in heterogeneous systems, the GPU memory usage needs also to be taken into account in the allocation process. This paper aims at decreasing the component-to-hardware allocation complexity by introducing a two-layer component-based architecture for heterogeneous embedded systems. The detailed CPU–GPU information of the system is abstracted at a high-layer by compacting connected components into single units that behave as regular components. The allocator, based on the compacted information received from the high-level layer, computes, with a decreased complexity, feasible allocation schemes. In the last part of the paper, the two-layer allocation method is evaluated using an existing embedded system demonstrator; namely, an underwater robot.

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19

Prongnuch, Sethakarn, Suchada Sitjongsataporn, and Theerayod Wiangtong. "A Heuristic Approach for Scheduling in Heterogeneous Distributed Embedded Systems." International Journal of Intelligent Engineering and Systems 13, no. 1 (February 29, 2020): 135–45. http://dx.doi.org/10.22266/ijies2020.0229.13.

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20

Attarzadeh-Niaki, Seyed-Hosein, and Ingo Sander. "Heterogeneous co-simulation for embedded and cyber-physical systems design." SIMULATION 96, no. 9 (June 1, 2020): 753–65. http://dx.doi.org/10.1177/0037549720921945.

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The growing complexity of embedded and cyber-physical systems makes the design of all system components from scratch increasingly impractical. Consequently, already from early stages of a design flow, designers rely on prior experience, which comes in the form of legacy code or third-party intellectual property (IP) blocks. Current approaches partly address the co-simulation problem for specific scenarios in an ad hoc style. This work suggests a general method for co-simulation of heterogeneous IPs with a system modeling and simulation framework. The external IPs can be integrated as high-level models running in an external simulator or as software- and hardware-in-the-loop simulation with minimal effort. Examples of co-simulation scenarios for wrapping models with different semantics are presented together with their practical usage in two case studies. The presented method is also used to formulate a refinement-by-replacement workflow for IP-based system design.

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21

Luo, Jiong, and Niraj K. Jha. "Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, no. 6 (June 2007): 1161–70. http://dx.doi.org/10.1109/tcad.2006.885736.

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22

Dave, B. P., and N. K. Jha. "COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, no. 10 (1998): 900–919. http://dx.doi.org/10.1109/43.728913.

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23

Xu, Hongzhi, Renfa Li, Chen Pan, and Keqin Li. "Minimizing energy consumption with reliability goal on heterogeneous embedded systems." Journal of Parallel and Distributed Computing 127 (May 2019): 44–57. http://dx.doi.org/10.1016/j.jpdc.2019.01.006.

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24

Persson, Anna, Henrik Gustavsson, Brian Lings, Björn Lundell, Anders Mattsson, and Ulf Ärlig. "OSS tools in a heterogeneous environment for embedded systems modelling." ACM SIGSOFT Software Engineering Notes 30, no. 4 (July 2005): 1–4. http://dx.doi.org/10.1145/1082983.1083267.

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25

Liu, Jing, Kenli Li, Dakai Zhu, Jianjun Han, and Keqin Li. "Minimizing Cost of Scheduling Tasks on Heterogeneous Multicore Embedded Systems." ACM Transactions on Embedded Computing Systems 16, no. 2 (April 14, 2017): 1–25. http://dx.doi.org/10.1145/2935749.

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26

Ansari, Mohsen, Mostafa Pasandideh, Javad Saber-Latibari, and Alireza Ejlali. "Meeting Thermal Safe Power in Fault-Tolerant Heterogeneous Embedded Systems." IEEE Embedded Systems Letters 12, no. 1 (March 2020): 29–32. http://dx.doi.org/10.1109/les.2019.2931882.

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27

Shatnawi, A., J. Ghanim, and M. N. S. Swamy. "Memory Optimization on Heterogeneous Multiprocessor Embedded Systems for DSP Applications." International Journal of Modelling and Simulation 23, no. 4 (January 2003): 240–50. http://dx.doi.org/10.1080/02286203.2003.11442278.

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28

Dave, B. P., G. Lakshminarayana, and N. K. Jha. "COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7, no. 1 (March 1999): 92–104. http://dx.doi.org/10.1109/92.748204.

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29

Pérez, Ignacio, and Miguel Figueroa. "A Heterogeneous Hardware Accelerator for Image Classification in Embedded Systems." Sensors 21, no. 8 (April 9, 2021): 2637. http://dx.doi.org/10.3390/s21082637.

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Convolutional neural networks (CNN) have been extensively employed for image classification due to their high accuracy. However, inference is a computationally-intensive process that often requires hardware acceleration to operate in real time. For mobile devices, the power consumption of graphics processors (GPUs) is frequently prohibitive, and field-programmable gate arrays (FPGA) become a solution to perform inference at high speed. Although previous works have implemented CNN inference on FPGAs, their high utilization of on-chip memory and arithmetic resources complicate their application on resource-constrained edge devices. In this paper, we present a scalable, low power, low resource-utilization accelerator architecture for inference on the MobileNet V2 CNN. The architecture uses a heterogeneous system with an embedded processor as the main controller, external memory to store network data, and dedicated hardware implemented on reconfigurable logic with a scalable number of processing elements (PE). Implemented on a XCZU7EV FPGA running at 200 MHz and using four PEs, the accelerator infers with 87% top-5 accuracy and processes an image of 224×224 pixels in 220 ms. It consumes 7.35 W of power and uses less than 30% of the logic and arithmetic resources used by other MobileNet FPGA accelerators.

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30

Herrera, Fernando, and Eugenio Villar. "A framework for heterogeneous specification and design of electronic embedded systems in SystemC." ACM Transactions on Design Automation of Electronic Systems 12, no. 3 (August 17, 2007): 1–31. http://dx.doi.org/10.1145/1255456.1255459.

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31

Zhang, Huafeng, Hehua Zhang, Ming Gu, and Jiaguang Sun. "Modeling a Heterogeneous Embedded System in Coloured Petri Nets." Journal of Applied Mathematics 2014 (2014): 1–8. http://dx.doi.org/10.1155/2014/943094.

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Embedded devices are everywhere now and, unlike personal computers, their systems differ in implementation languages and behaviors. Interactions of different devices require programmers to master programming paradigms in all related languages. So, a defect may occur if differences in systems' behaviors are ignored. In this paper, a heterogeneous system which is composed of two subsystems is introduced and we point out a potential defect in this system caused by an interface mismatch. Then, a state based approach is applied to verify our analysis of the system.

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32

RADOJEVIC, IVAN, ZORAN SALCIC, and PARTHA ROOP. "A NEW MODEL FOR HETEROGENEOUS EMBEDDED SYSTEMS — What Esterel and SyncCharts Need to Become a Suitable Specification Platform." International Journal of Software Engineering and Knowledge Engineering 15, no. 02 (April 2005): 405–10. http://dx.doi.org/10.1142/s0218194005001963.

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Specification of embedded systems based on formal models of computation is gaining importance. The behavior of an increasing number of embedded systems is heterogeneous, consisting of a mixture of control-dominated and data-dominated parts. While models of computations suitable to control-dominated systems and data-dominated systems are well developed, there are only a limited number of models catering to both systems. In this paper, we present informally a new model for heterogeneous embedded systems, called HEMOC, which combines three common models of computation, synchronous reactive, hierarchical finite state machines and synchronous data flow. Then, the languages Esterel and SyncCharts are used for system specification following the new model in order to determine what they need to become suitable specification platform.

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33

Liang, Quanyi, and Zhikun She. "Constraint consensus of heterogeneous multi-agent systems." International Journal of Modern Physics C 29, no. 05 (May 2018): 1840005. http://dx.doi.org/10.1142/s0129183118400053.

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In this brief paper, we study the constraint consensus problem of heterogeneous multi-agent systems. First, we provide an invariant set, which can be exactly obtained by solving linear equations. Then, a virtual system is defined on this invariant set such that it is the largest common embedded system of all the individual agents. Afterwards, a linear consensus protocol is proposed with the corresponding constraint consensus criterion. In particular, the above virtual system can reveal all the asymptotic dynamical behaviors if heterogeneous multi-agent systems achieve consensus. Finally, an example with numerical simulations is given to illustrate the validity of our criterion.

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34

Leu, Jenq-Shiou, Wei-Hsiang Lin, Wen-Bin Hsieh, and Chien-Chih Lo. "Design and Implementation of a VoIP Broadcasting Service over Embedded Systems in a Heterogeneous Network Environment." Scientific World Journal 2014 (2014): 1–10. http://dx.doi.org/10.1155/2014/917060.

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As the digitization is integrated into daily life, media including video and audio are heavily transferred over the Internet nowadays. Voice-over-Internet Protocol (VoIP), the most popular and mature technology, becomes the focus attracting many researches and investments. However, most of the existing studies focused on a one-to-one communication model in a homogeneous network, instead of one-to-many broadcasting model among diverse embedded devices in a heterogeneous network. In this paper, we present the implementation of a VoIP broadcasting service on the open source—Linphone—in a heterogeneous network environment, including WiFi, 3G, and LAN networks. The proposed system featuring VoIP broadcasting over heterogeneous networks can be integrated with heterogeneous agile devices, such as embedded devices or mobile phones. VoIP broadcasting over heterogeneous networks can be integrated into modern smartphones or other embedded devices; thus when users run in a traditional AM/FM signal unreachable area, they still can receive the broadcast voice through the IP network. Also, comprehensive evaluations are conducted to verify the effectiveness of the proposed implementation.

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35

Kilaru, Chaitanya, Dr JKR Sastry, and Dr K RajaSekhara Rao. "Testing distributed embedded systems through logic analyzer." International Journal of Engineering & Technology 7, no. 2.7 (March 18, 2018): 297. http://dx.doi.org/10.14419/ijet.v7i2.7.10601.

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Testing distributed embedded systems is complex as the individual systems connected on to the network are heterogeneous in nature.The communication system that is used for establishing the networking also varies greatly leading to different testing requirements. Testing of embedded systems can be carried using different methods that include Scaffolding, assert macros, instruction set simulators. In-circuit emulators, logic analyzers each requiring establishment of different testing environment required for undertaking actual testing. Testing of any embedded systems involves testing hardware, testing hardware dependent code, and testing hardware independent code. Logic analyzers are generally used for testing proper working of the Hardware.In this paper, a framework is presented using which testing of hardware distributed across the distributed embedded system using logic analyzer is presented.

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36

Nam, Hyunsuk, and Roman Lysecky. "Mixed Cryptography Constrained Optimization for Heterogeneous, Multicore, and Distributed Embedded Systems." Computers 7, no. 2 (April 24, 2018): 29. http://dx.doi.org/10.3390/computers7020029.

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37

Xu, Cheng, and Tao Li. "Chemical Reaction Optimization for Task Mapping in Heterogeneous Embedded Multiprocessor Systems." Advanced Materials Research 712-715 (June 2013): 2604–10. http://dx.doi.org/10.4028/www.scientific.net/amr.712-715.2604.

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With different task mapping and scheduling will lead to different time consumption and energy consumption on heterogeneous multiprocessor systems, using appropriate task mapping and scheduling algorithms can save more energy. In this paper, we propose a new method to solve the task mapping problem. The algorithm consists of two elements: An intelligent approach to assign the execution orders of tasks by task level, and an allocation algorithm based on chemical-reaction-inspired metaheuristic called Chemical Reaction Optimization (CRO) to map processors to tasks. The results show that it can use less time to reduce more energy consumption.

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38

Gaspar, Francisco, Luis Taniça, Pedro Tomás, Aleksandar Ilic, and Leonel Sousa. "A Framework for Application-Guided Task Management on Heterogeneous Embedded Systems." ACM Transactions on Architecture and Code Optimization 12, no. 4 (January 7, 2016): 1–25. http://dx.doi.org/10.1145/2835177.

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39

Hamann, Arne, Marek Jersak, Kai Richter, and Rolf Ernst. "A framework for modular analysis and exploration of heterogeneous embedded systems." Real-Time Systems 33, no. 1-3 (July 2006): 101–37. http://dx.doi.org/10.1007/s11241-006-6884-x.

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40

Taheri, Golnaz, Ahmad Khonsari, Reza Entezari-Maleki, and Leonel Sousa. "A hybrid algorithm for task scheduling on heterogeneous multiprocessor embedded systems." Applied Soft Computing 91 (June 2020): 106202. http://dx.doi.org/10.1016/j.asoc.2020.106202.

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41

Perri, Stefania, Cristian Sestito, Fanny Spagnolo, and Pasquale Corsonello. "Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip." Journal of Imaging 6, no. 9 (August 25, 2020): 85. http://dx.doi.org/10.3390/jimaging6090085.

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Today, convolutional and deconvolutional neural network models are exceptionally popular thanks to the impressive accuracies they have been proven in several computer-vision applications. To speed up the overall tasks of these neural networks, purpose-designed accelerators are highly desirable. Unfortunately, the high computational complexity and the huge memory demand make the design of efficient hardware architectures, as well as their deployment in resource- and power-constrained embedded systems, still quite challenging. This paper presents a novel purpose-designed hardware accelerator to perform 2D deconvolutions. The proposed structure applies a hardware-oriented computational approach that overcomes the issues of traditional deconvolution methods, and it is suitable for being implemented within any virtually system-on-chip based on field-programmable gate array devices. In fact, the novel accelerator is simply scalable to comply with resources available within both high- and low-end devices by adequately scaling the adopted parallelism. As an example, when exploited to accelerate the Deep Convolutional Generative Adversarial Network model, the novel accelerator, running as a standalone unit implemented within the Xilinx Zynq XC7Z020 System-on-Chip (SoC) device, performs up to 72 GOPs. Moreover, it dissipates less than 500mW@200MHz and occupies 5.6%, 4.1%, 17%, and 96%, respectively, of the look-up tables, flip-flops, random access memory, and digital signal processors available on-chip. When accommodated within the same device, the whole embedded system equipped with the novel accelerator performs up to 54 GOPs and dissipates less than 1.8W@150MHz. Thanks to the increased parallelism exploitable, more than 900 GOPs can be executed when the high-end Virtex-7 XC7VX690T device is used as the implementation platform. Moreover, in comparison with state-of-the-art competitors implemented within the Zynq XC7Z045 device, the system proposed here reaches a computational capability up to 20% higher, and saves more than 60% and 80% of power consumption and logic resources requirement, respectively, using 5.7× fewer on-chip memory resources.

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42

ZHONG, ZHAOQIAN. "Model-Based Parallelizer for Embedded Control Systems on Single-ISA Heterogeneous Multicore." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 19 (February 28, 2019): 7470–84. http://dx.doi.org/10.24297/ijct.v19i0.8123.

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This paper presents a model-based parallelization approach to parallelize embedded systems on single-ISA heterogeneous multicore processors, especially processors with the ARM big.LITTLE architecture, wherein the core assignment of the Simulink blocks is determined based on the control design constraints and characteristics of the big.LITTLE architecture. The proposed approach uses a hierarchical clustering method on Simulink blocks to reduce the problem scale, and an integer linear programming (ILP) formulation to determine the core assignment solution, considering load balancing and minimization of inter-core communication across cores with different performances. Finally, we generate the parallel code of the model based on the core assignment solution for execution on the processors. We evaluate the proposed approach by comparing it with existing methods and generating the parallel code on a single-board computer with the big.LITTLE architecture to determine its effectiveness.

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43

Xie, Guoqi, Yuekun Chen, Yan Liu, Yehua Wei, Renfa Li, and Keqin Li. "Resource Consumption Cost Minimization of Reliable Parallel Applications on Heterogeneous Embedded Systems." IEEE Transactions on Industrial Informatics 13, no. 4 (August 2017): 1629–40. http://dx.doi.org/10.1109/tii.2016.2641473.

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Ansari, Mohsen, Javad Saber-Latibari, Mostafa Pasandideh, and Alireza Ejlali. "Simultaneous Management of Peak-Power and Reliability in Heterogeneous Multicore Embedded Systems." IEEE Transactions on Parallel and Distributed Systems 31, no. 3 (March 1, 2020): 623–33. http://dx.doi.org/10.1109/tpds.2019.2940631.

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Peón-quirós, Miguel, Alexandros Bartzas, Stylianos Mamagkakis, Francky Catthoor, José Manuel Mendías, and Dimitrios Soudris. "Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems." ACM Transactions on Embedded Computing Systems 14, no. 2 (March 25, 2015): 1–30. http://dx.doi.org/10.1145/2656208.

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Qiu, Meikang, and Edwin H. M. Sha. "Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems." ACM Transactions on Design Automation of Electronic Systems 14, no. 2 (March 2009): 1–30. http://dx.doi.org/10.1145/1497561.1497568.

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Deniziak, Stanisław, and Leszek Ciopiński. "Synthesis of self-adaptable energy aware software for heterogeneous multicore embedded systems." Microelectronics Reliability 123 (August 2021): 114184. http://dx.doi.org/10.1016/j.microrel.2021.114184.

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Spagnolo, Fanny, Stefania Perri, Fabio Frustaci, and Pasquale Corsonello. "Energy-Efficient Architecture for CNNs Inference on Heterogeneous FPGA." Journal of Low Power Electronics and Applications 10, no. 1 (December 24, 2019): 1. http://dx.doi.org/10.3390/jlpea10010001.

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Due to the huge requirements in terms of both computational and memory capabilities, implementing energy-efficient and high-performance Convolutional Neural Networks (CNNs) by exploiting embedded systems still represents a major challenge for hardware designers. This paper presents the complete design of a heterogeneous embedded system realized by using a Field-Programmable Gate Array Systems-on-Chip (SoC) and suitable to accelerate the inference of Convolutional Neural Networks in power-constrained environments, such as those related to IoT applications. The proposed architecture is validated through its exploitation in large-scale CNNs on low-cost devices. The prototype realized on a Zynq XC7Z045 device achieves a power efficiency up to 135 Gops/W. When the VGG-16 model is inferred, a frame rate up to 11.8 fps is reached.

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CAI, XIA, MICHAEL R. LYU, and KAM-FAI WONG. "COMPONENT-BASED EMBEDDED SOFTWARE ENGINEERING: DEVELOPMENT FRAMEWORK, QUALITY ASSURANCE AND A GENERIC ASSESSMENT ENVIRONMENT." International Journal of Software Engineering and Knowledge Engineering 12, no. 02 (April 2002): 107–33. http://dx.doi.org/10.1142/s0218194002000846.

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Embedded software is used to control the functions of mechanical and physical devices by dedicated digital signal processor and computers. Nowadays, heterogeneous and collaborative embedded software systems are widely adopted to engage the physical world. To make such software extremely reliable, very efficient and highly flexible, component-based embedded software development can be employed for the complex embedded systems, especially those based on object-oriented (OO) approaches. In this paper, we introduce a component-based embedded software framework and the features it inherits. We propose a quality assurance (QA) model for component-based embedded software development, which covers both the component QA and the system QA as well as their interactions. Furthermore, we propose a generic quality assessment environment for component-based embedded systems: ComPARE. ComPARE can be used to assess real-life off-the-shelf components and to evaluate and validate the models selected for their evaluation. The overall component-based embedded systems can then be composed and analyzed seamlessly.

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Gao, Fang, Zhangqin Huang, Shulong Wang, and Xinrong Ji. "Optimized Parallel Implementation of Face Detection Based on Embedded Heterogeneous Many-Core Architecture." International Journal of Pattern Recognition and Artificial Intelligence 31, no. 07 (April 10, 2017): 1756011. http://dx.doi.org/10.1142/s0218001417560110.

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Computing performance is one of the key problems in embedded systems for high-resolution face detection applications. To improve the computing performance of embedded high-resolution face detection systems, a novel parallel implementation of embedded face detection system was established based on a low power CPU-Accelerator heterogeneous many-core architecture. First, a basic CPU version of face detection prototype was implemented based on the cascade classifier and Local Binary Patterns operator. Second, the prototype was extended to a specified embedded parallel computing platform that is called Parallella and consists of Xilinx Zynq and Adapteva Epiphany. Third, the face detection algorithm was optimized to adapt to the Parallella architecture to improve the detection speed and the utilization of computing resources. Finally, a face detection experiment was conducted to evaluate the computing performance of the proposal in this paper. The experimental results show that the proposed implementation obtained a very consistent accuracy as that of the dual-core ARM, and achieved 7.8 times speedup than that of the dual-core ARM. Experiment results prove that the proposed implementation has significant advantages on computing performance.

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