Relevant bibliographies by topics / Heterogeneous embedded system

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Heterogeneous embedded system'

Author: Grafiati
Published: 11 March 2023
Last updated: 14 March 2023

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Journal articles on the topic "Heterogeneous embedded system"

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Valente, Giacomo, Tiziana Fanni, Carlo Sau, Tania Di Mascio, Luigi Pomante, and Francesca Palumbo. "A Composable Monitoring System for Heterogeneous Embedded Platforms." ACM Transactions on Embedded Computing Systems 20, no. 5 (July 2021): 1–34. http://dx.doi.org/10.1145/3461647.

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Advanced computations on embedded devices are nowadays a must in any application field. Often, to cope with such a need, embedded systems designers leverage on complex heterogeneous reconfigurable platforms that offer high performance, thanks to the possibility of specializing/customizing some computing elements on board, and are usually flexible enough to be optimized at runtime. In this context, monitoring the system has gained increasing interest. Ideally, monitoring systems should be non-intrusive, serve several purposes, and provide aggregated information about the behavior of the different system components. However, current literature is not close to such ideality: For example, existing monitoring systems lack in being applicable to modern heterogeneous platforms. This work presents a hardware monitoring system that is intended to be minimally invasive on system performance and resources, composable, and capable of providing to the user homogeneous observability and transparent access to the different components of a heterogeneous computing platform, so system metrics can be easily computed from the aggregation of the collected information. Building on a previous work, this article is primarily focused on the extension of an existing hardware monitoring system to cover also specialized coprocessing units, and the assessment is done on a Xilinx FPGA-based System on Programmable Chip. Different explorations are presented to explain the level of customizability of the proposed hardware monitoring system, the tradeoffs available to the user, and the benefits with respect to standard de facto monitoring support made available by the targeted FPGA vendor.
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Jammalamadaka, Sastry Kodanda Rama, Valluru Sai Kumar Reddy, and Smt J Sasi Bhanu. "Networking Heterogeneous Microcontroller based Systems through Universal Serial Bus." International Journal of Electrical and Computer Engineering (IJECE) 5, no. 5 (October 1, 2015): 992. http://dx.doi.org/10.11591/ijece.v5i5.pp992-1002.

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Networking heterogeneous embedded systems is a challenge. Every distributed embedded systems requires that the network is designed specifically considering the heterogeneity that exits among different Microcontroller based systems that are used in developing a distributed embedded system. Communication architecture, which considers the addressing of the individual systems, arbitration, synchronisation, error detection and control etc., needs to be designed considering a specific application. The issue of configuring the slaves has to be addressed. It is also important that the messages, flow of the messages across the individual ES systems must be designed. Every distributed embedded system is different and needs to be dealt with separately. This paper presents an approach that addresses various issues related to networking distributed embedded systems through use of universal serial bus communication protocol (USB). The approach has been applied to design a distributed embedded that monitors and controls temperatures within a Nuclear reactor system.
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Zhang, Huafeng, Hehua Zhang, Ming Gu, and Jiaguang Sun. "Modeling a Heterogeneous Embedded System in Coloured Petri Nets." Journal of Applied Mathematics 2014 (2014): 1–8. http://dx.doi.org/10.1155/2014/943094.

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Embedded devices are everywhere now and, unlike personal computers, their systems differ in implementation languages and behaviors. Interactions of different devices require programmers to master programming paradigms in all related languages. So, a defect may occur if differences in systems' behaviors are ignored. In this paper, a heterogeneous system which is composed of two subsystems is introduced and we point out a potential defect in this system caused by an interface mismatch. Then, a state based approach is applied to verify our analysis of the system.
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Syschikov, Alexey, Yuriy Sheynin, Boris Sedov, and Vera Ivanova. "Domain-Specific Programming Environment for Heterogeneous Multicore Embedded Systems." International Journal of Embedded and Real-Time Communication Systems 5, no. 4 (October 2014): 1–23. http://dx.doi.org/10.4018/ijertcs.2014100101.

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Nowadays embedded systems are used in a broad range of domains such as avionics, space, automotive, mobile, domestic appliances etc. Sophisticated software determines the quality of embedded systems and requires high-qualified experts for software development. Software becomes the main assert of embedded systems that is valuable to retain in changing computing platforms in embedded systems evolution. Computing platforms for embedded systems became multicore processors and SoC, they can change in the embedded system lifetime that could be long (dozen of years for an automobile and airplane). It requires software porting to new platforms as a regular process. Many tools and approaches allow developing of software for domain area experts, but mainly for general-purpose computing systems. In this paper the authors present the complex technology and tools that allows involving domain experts in software development for embedded systems. The proposed technology has various aspects and abilities that can be used to build verifiable and portable software for a wide range of embedded platforms.
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Wu, Dian Hong. "Task Optimization Scheduling Algorithm in Embedded System Based on Internet of Things." Applied Mechanics and Materials 513-517 (February 2014): 2398–402. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.2398.

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Embedded system has been widely used in the network, server, etc., and it has a good application prospect with the development of Internet of things. In the embedded heterogeneous computing system, task scheduling is the key to deciding the system performance. For multi-task scheduling, the current scheduling algorithm is mostly based on task duplication, without a full consideration of the correlation between the predecessor task and its subsequent tasks. Based on modeling the multi-frame task scheduling problem in the heterogeneous embedded system, this paper analyzes the availability of tasks through the design of genetic algorithm, so as to verify the algorithm's feasibility, which is of important guiding significance for the multi-task scheduling in the embedded heterogeneous computing system.
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Pervan, Branimir, Josip Knezović, and Emanuel Guberović. "Energy-efficient distributed password hash computation on heterogeneous embedded system." Automatika 63, no. 3 (February 28, 2022): 399–417. http://dx.doi.org/10.1080/00051144.2022.2042115.

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Rath, A. K., and S. N. Dehuri. "Non-dominated Sorting Genetic Algorithms for Heterogeneous Embedded System Design." Journal of Computer Science 2, no. 3 (March 1, 2006): 288–91. http://dx.doi.org/10.3844/jcssp.2006.288.291.

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E, Mounika. "A Hybridised Heterogeneous Embedded System Networking through Multi-Master Interface." International Journal of Emerging Trends in Engineering Research 8, no. 3 (March 15, 2020): 885–93. http://dx.doi.org/10.30534/ijeter/2020/45832020.

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Majumdar, Abhinandan, Srihari Cadambi, and Srimat T. Chakradhar. "An Energy-Efficient Heterogeneous System for Embedded Learning and Classification." IEEE Embedded Systems Letters 3, no. 1 (March 2011): 42–45. http://dx.doi.org/10.1109/les.2010.2100802.

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Campeanu, Gabriel, and Mehrdad Saadatmand. "A Two-Layer Component-Based Allocation for Embedded Systems with GPUs." Designs 3, no. 1 (January 19, 2019): 6. http://dx.doi.org/10.3390/designs3010006.

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Component-based development is a software engineering paradigm that can facilitate the construction of embedded systems and tackle its complexities. The modern embedded systems have more and more demanding requirements. One way to cope with such a versatile and growing set of requirements is to employ heterogeneous processing power, i.e., CPU–GPU architectures. The new CPU–GPU embedded boards deliver an increased performance but also introduce additional complexity and challenges. In this work, we address the component-to-hardware allocation for CPU–GPU embedded systems. The allocation for such systems is much complex due to the increased amount of GPU-related information. For example, while in traditional embedded systems the allocation mechanism may consider only the CPU memory usage of components to find an appropriate allocation scheme, in heterogeneous systems, the GPU memory usage needs also to be taken into account in the allocation process. This paper aims at decreasing the component-to-hardware allocation complexity by introducing a two-layer component-based architecture for heterogeneous embedded systems. The detailed CPU–GPU information of the system is abstracted at a high-layer by compacting connected components into single units that behave as regular components. The allocator, based on the compacted information received from the high-level layer, computes, with a decreased complexity, feasible allocation schemes. In the last part of the paper, the two-layer allocation method is evaluated using an existing embedded system demonstrator; namely, an underwater robot.
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Dissertations / Theses on the topic "Heterogeneous embedded system"

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Fischaber, Scott Johan. "Memory-centric system level design of heterogeneous embedded DSP systems." Thesis, Queen's University Belfast, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.491885.

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Modern embedded systems for DSP applications are increasingly being implemented on heterogeneous processing architectures, consisting of multiple processors and programmable hardware such as FPGAs. The layered memory structure of FPGAs provides an open platform for memory organisation which many algorithms can benefit from. To efficiently target these platforms, high level design tools are being developed to target these architectures; often for DSP applications, these tools have been based around process networks, and as such, their memory architectures typically closely match the simple FIFO buffering employed by these models. This is not always ideal in a hardware implementation, where off-chip memory accesses may be required, particularly when there is data reuse inherent to the algorithm. This thesis proposes a formalised methodology to synthesise efficient memory architectures for FPGA-based DSP systems from a high level dataflow model. This includes reducing the memory requirements of the system through transformations, model refinements and by including the hardware characteristics into the dataflow analysis: Standard dataflow transformations have been characterised so that their effects on the memory subsystem are apparent and these transformations have been placed appropriately in a memory-centric design flow. The memory generation techniques for hardware cores on these FPGA platforms are also analysed, providing extensions which can reduce memory requirements through automatic sub-scheduling using a range of MoCs. These techniques effectively target the distributed nature of FPGA memories to introduce memory hierarchies into the implementations, targeting any data reuse inherent to the application which can take advantage of the memory architecture. This layered memory approach is used to reduce the number of accesses reqUired to large memories, which in turn can increase performance and reduce power consumption. For a motion estimation algorithm the reqUired bandwidth for off-chip memory accesses can vary by a factor of a thousand between two DFGs. For a 2-D convolution algorithm, the total reqUired memory is reduced by half though refinement of the system level model. This methodology has been demonstrated in the design of a video encoder and template matching algorithm and used to efficiently implement the memory sub-systems.
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Peterson, Thomas. "Dynamic Allocation for Embedded Heterogeneous Memory : An Empirical Study." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-223904.

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Embedded systems are omnipresent and contribute to our lives in many ways by instantiating functionality in larger systems. To operate, embedded systems require well-functioning software, hardware as well as an interface in-between these. The hardware and software of these systems is under constant change as new technologies arise. An actual change these systems are undergoing are the experimenting with different memory management techniques for RAM as novel non-volatile RAM(NVRAM) technologies have been invented. These NVRAM technologies often come with asymmetrical read and write latencies and thus motivate designing memory consisting of multiple NVRAMs. As a consequence of these properties and memory designs there is a need for memory management that minimizes latencies.This thesis addresses the problem of memory allocation on heterogeneous memory by conducting an empirical study. The first part of the study examines free list, bitmap and buddy system based allocation techniques. The free list allocation technique is then concluded to be superior. Thereafter, multi-bank memory architectures are designed and memory bank selection strategies are established. These strategies are based on size thresholds as well as memory bank occupancies. The evaluation of these strategies did not result in any major conclusions but showed that some strategies were more appropriate for someapplication behaviors.
Inbyggda system existerar allestädes och bidrar till våran livsstandard på flertalet avseenden genom att skapa funktionalitet i större system. För att vara verksamma kräver inbyggda system en välfungerande hård- och mjukvara samt gränssnitt mellan dessa. Dessa tre måste ständigt omarbetas i takt med utvecklingen av nya användbara teknologier för inbyggda system. En förändring dessa system genomgår i nuläget är experimentering med nya minneshanteringstekniker för RAM-minnen då nya icke-flyktiga RAM-minnen utvecklats. Dessa minnen uppvisar ofta asymmetriska läs och skriv fördröjningar vilket motiverar en minnesdesign baserad på flera olika icke-flyktiga RAM. Som en konsekvens av dessa egenskaper och minnesdesigner finns ett behov av att hitta minnesallokeringstekniker som minimerar de fördröjningar som skapas. Detta dokument adresserar problemet med minnesallokering på heterogena minnen genom en empirisk studie. I den första delen av studien studerades allokeringstekniker baserade på en länkad lista, bitmapp och ett kompissystem. Med detta som grund drogs slutsatsen att den länkade listan var överlägsen alternativen. Därefter utarbetades minnesarkitekturer med flera minnesbanker samtidigt som framtagandet av flera strategier för val av minnesbank utfördes. Dessa strategier baserades på storleksbaserade tröskelvärden och nyttjandegrad hos olika minnesbanker. Utvärderingen av dessa strategier resulterade ej i några större slutsatser men visade att olika strategier var olika lämpade för olika beteenden hos applikationer.
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Pop, Traian. "Analysis and Optimisation of Distributed Embedded Systems with Heterogeneous Scheduling Policies." Doctoral thesis, Linköping : Department of Computer and Information Science, Linköpings universitet, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8934.

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Hegde, Sridhar. "FUNCTIONAL ENHANCEMENT AND APPLICATIONS DEVELOPMENT FOR A HYBRID, HETEROGENEOUS SINGLE-CHIP MULTIPROCESSOR ARCHITECTURE." UKnowledge, 2004. http://uknowledge.uky.edu/gradschool_theses/252.

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Reconfigurable and dynamic computer architecture is an exciting area of research that is rapidly expanding to meet the requirements of compute intense real and non-real time applications in key areas such as cryptography, signal/radar processing and other areas. To meet the demands of such applications, a parallel single-chip heterogeneous Hybrid Data/Command Architecture (HDCA) has been proposed. This single-chip multiprocessor architecture system is reconfigurable at three levels: application, node and processor level. It is currently being developed and experimentally verified via a three phase prototyping process. A first phase prototype with very limited functionality has been developed. This initial prototype was used as a base to make further enhancements to improve functionality and performance resulting in a second phase virtual prototype, which is the subject of this thesis. In the work reported here, major contributions are in further enhancing the functionality of the system by adding additional processors, by making the system reconfigurable at the node level, by enhancing the ability of the system to fork to more than two processes and by designing some more complex real/non-real time applications which make use of and can be used to test and evaluate enhanced and new functionality added to the architecture. A working proof of concept of the architecture is achieved by Hardware Description Language (HDL) based development and use of a Virtual Prototype of the architecture. The Virtual Prototype was used to evaluate the architecture functionality and performance in executing several newly developed example applications. Recommendations are made to further improve the system functionality.
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Souza, Jeckson Dellagostin. "A reconfigurable heterogeneous multicore system with homogeneous ISA." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/140321.

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Dada a grande diversidade de aplicações embarcadas presentes nos atuais dispositivos portáveis, ambos os paralelismos em nível de threads e de instruções devem ser explorados para obter ganhos de desempenho e energia. Enquanto MPSoCs (sistemas em chip de múltiplos núcleos) são amplamente usados para esse propósito, estes falham quando consideramos produtividade de software, já que eles são compostos de chips com diferentes arquiteturas que precisam ser programados separadamente. Por outro lado, processadores multi núcleos de propósito geral implementam a mesma arquitetura, mas são compostos de núcleos homogêneos de processadores superescalares que consomem muita potência. Nesta dissertação, propõe-se um novo sistema, que tira proveito de circuitos reconfiguráveis para criar diferentes organizações que implementam a mesma arquitetura, capazes de apresentar alto desempenho com baixo custo energético. Para garantir a compatibilidade binária, usa-se um mecanismo de tradução binária que transforma o código a ser executado no circuito reconfigurável durante a execução. Usando aplicações representativas, mostra-se que uma versão do sistema heterogêneo pode ganhar da sua versão homogênea em média de 59% em desempenho e 10% em energia, com melhoras em EDP (Energy-Delay Product – Produto da energia pelo tempo de execução) em quase todos os cenários. Além disso, este trabalho também propõe e avalia seis escalonadores para este sistema heterogêneo: dois algoritmos estáticos, os quais alocam as threads no primeiro núcleo livre, onde elas permanecerão durante toda a execução; um escalonador direcionado por contagem de instruções, o qual realoca as threads durante pontos de sincronização de acordo com a sua contagem de instruções; um escalonador de Feedback, que usa dados de dentro da unidade reconfigurável para realocar threads; o PC-Feedback, que adiciona um mecanismo de reuso de dados ao último escalonador; e um escalonador Oráculo, que é capaz de decidir a melhor alocação de threads possível. Mostra-se que o algoritmo estático pode ter alto desempenho em aplicações com alto paralelismo, contudo para um desempenho mais uniforme em todas as aplicações os algoritmos de Feedback e PC-Feedback são mais indicados.
Given the large diversity of embedded applications one can find in current portable devices, for energy and performance reasons one must exploit both Thread- and Instruction Level Parallelism. While MPSoCs (Multiprocessor system-on-chip) are largely used for this purpose, they fail when one considers software productivity, since it comprises different ISAs (Instruction Set Architecture) that must be programmed separately. On the other hand, general purpose multicores implement the same ISA, but are composed of a homogeneous set of very power consuming superscalar processors. In this dissertation, we show how one can effectively use a reconfigurable unit to provide a number of different possible heterogeneous configurations while still sustaining the same ISA, capable of reaching high performance with low energy cost. To ensure ISA compatibility, we use a binary translation mechanism that transforms code to be executed on the fabric at run-time. Using representative benchmarks, we show that one version of the heterogeneous system can outperform its homogenous counterpart in average by 59% in performance and 10% in energy, with EDP (Energy-Delay Product) improvements in almost every scenario. Furthermore, this work also proposes and evaluates six schedulers for the heterogeneous system: two static algorithms, which allocate the threads on the first free core, where they will run during the entire execution; an Instruction Count (IC) Driven scheduler, which reallocates threads during synchronization points accordingly to their instruction count; a Feedback scheduler, which uses data from inside the reconfigurable unit to reallocate threads; the PCFeedback scheduler, that adds a reuse mechanism to the last one; and an Oracle scheduler, which is capable of deciding the best thread allocation possible. We show that the static algorithm can reach high performance in applications with high parallelism, however for uniform performance in all applications, the Feedback and PC-Feedback algorithms are better designated.
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Patel, Hiren Dhanji. "HEMLOCK: HEterogeneous ModeL Of Computation Kernel for SystemC." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/9632.

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As SystemC gains popularity as a System Level Design Language (SLDL) for System-On-Chip (SOC) designs, heterogeneous modelling and efficient simulation become increasingly important. The key in making an SLDL heterogeneous is the facility to express different Models Of Computation (MOC). Currently, all SystemC models employ a Discrete-Event simulation kernel making it difficult to express most MOCs without specific designer guidelines. This often makes it unnatural to express different MOCs in SystemC. For the simulation framework, this sometimes results in unnecessary delta cycles for models away from the Discrete-Event MOC, hindering the simulation performance of the model. Our goal is to extend SystemC's simulation framework to allow for better modelling expressiveness and efficiency for the Synchronous Data Flow (SDF) MOC. The SDF MOC follows a paradigm where the production and consumption rates of data by a function block are known a priori. These systems are common in Digital Signal Processing applications where relative sample rates are specified for every component. Knowledge of these rates enables the use of static scheduling. When compared to dynamic scheduling of SDF models, we experience a noticeable improvement in simulation efficiency. We implement an extension to the SystemC kernel that exploits such static scheduling for SDF models and propose designer style guidelines for modelers to use this extension. The modelling paradigm becomes more natural to SDF which results to better simulation efficiency. We will distribute our implementation to the SystemC community to demonstrate that SystemC can be a heterogeneous SLDL.
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Bergenhem, Carl, and Magnus Jonsson. "Two Protocols with Heterogeneous Real-Time Services for High-Performance Embedded Networks." Högskolan i Halmstad, Centrum för forskning om inbyggda system (CERES), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-21296.

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High-performance embedded networks are found in computer systems that perform applications such as radar signal processing and multimedia rendering. The system can be composed of multiple computer nodes that are interconnected with the network. Properties of the network such as latency and speed affect the performance of the entire system. A node´s access to the network is controlled by a medium access protocol. This protocol decides e.g. real-time properties and services that the network will offer its users, i.e. the nodes. Two such network protocols with heterogeneous real-time services are presented. The protocols offer different communication services and services for parallel and distributed real-time processing. The latter services include barrier synchronisation, global reduction and short message service. A network topology of a unidirectional pipelined optical fibre-ribbon ring is assumed for both presented protocols. In such a network several simultaneous transmissions in non-overlapping segments are possible. Both protocols are aimed for applications that require a high-performance embedded network such as radar signal processing and multimedia. In these applications the system can be organised as multiple interconnected computation nodes that co-operate in parallel to achieve higher performance. The computing performance of the whole system is greatly affected by the choice of network. Computing nodes in a system for radar signal processing should be tightly coupled, i.e., communications cost, such as latency, between nodes should be small. This is possible if a suitable network with an efficient protocol is used. The target applications have heterogeneous real-time requirements for communication in that different classes of data-traffic exist. The traffic can be classified according to its requirements. The proposed protocols partition data-traffic into three classes with distinctly different qualities. These classes are: traffic with hard real-time demands, such as mission critical commands; traffic with soft real-time demands, such as application data (a deadline miss here only leads to decreased performance); and traffic with no real-time constraints at all. The protocols are analysed and performance is tested through simulation with different data-traffic patterns.
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Swegert, Eric B. "RTOS Tutorials for a Heterogeneous Class of Senior and Beginning Graduate Students." University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1367934958.

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Gantel, Laurent. "Hardware and software architecture facilitating the operation by the industry of dynamically adaptable heterogeneous embedded systems." Phd thesis, Université de Cergy Pontoise, 2014. http://tel.archives-ouvertes.fr/tel-01019909.

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This thesis aims to define software and hardware mechanisms helping in the management the Heterogeneous and dynamically Reconfigurable Systems-on-Chip (HRSoC). The heterogeneity is due to the presence of general processing units and reconfigurable IPs. Our objective is to provide to an application developer an abstracted view of this heterogeneity, regarding the task mapping on the available processing elements. First, we homogenize the user interface defining a hardware thread model. Then, we pursue with the homogenization of the hardware threads management. We implemented OS services permitting to save and restore a hardware thread context. Conception tools have also been developed in order to overcome the relocation issue. The last step consisted in extending the access to the distributed OS services to every thread running on the platform. This access is provided independently from the thread location and is is realized implementing the MRAPI API. With these three steps, we build a solid basis to, in future work, provide to the developer, a conception flow dedicated to HRSoC allowing to perform precise architectural space explorations. Finally, to validate these mechanisms, we realize a demonstration platform on a Virtex 5 FPGA running a dynamic tracking application.
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Robino, Francesco. "A model-based design approach for heterogeneous NoC-based MPSoCs on FPGA." Licentiate thesis, KTH, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-145521.

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Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. System-level design (SLD) is considered to be the next frontier in electronic design automation (EDA). It enables the description of embedded systems in terms of abstract functions and interconnected blocks. A promising complementary approach to SLD is the use of models of computation (MoCs) to formally describe the execution semantics of functions and blocks through a set of rules. However, also when this formalization is used, there is no clear way to synthesize system-level models into software (SW) and hardware (HW) towards a NoC-based MPSoC implementation, i.e., there is a lack of system design automation (SDA) techniques to rapidly synthesize and prototype system-level models onto heterogeneous NoC-based MPSoCs. In addition, many of the proposed solutions require large overhead in terms of SW components and memory requirements, resulting in complex and customized multi-processor platforms. In order to tackle the problem, a novel model-based SDA flow has been developed as part of the thesis. It starts from a system-level specification, where functions execute according to the synchronous MoC, and then it can rapidly prototype the system onto an FPGA configured as an heterogeneous NoC-based MPSoC. In the first part of the thesis the HeartBeat model is proposed as a model-based technique which fills the abstraction gap between the abstract system-level representation and its implementation on the multiprocessor prototype. Then details are provided to describe how this technique is automated to rapidly prototype the modeled system on a flexible platform, permitting to adjust the system specification until the designer is satisfied with the results. Finally, the proposed SDA technique is improved defining a methodology to automatically explore possible design alternatives for the modeled system to be implemented on a heterogeneous NoC-based MPSoC. The goal of the exploration is to find an implementation satisfying the designer's requirements, which can be integrated in the proposed SDA flow. Through the proposed SDA flow, the designer is relieved from implementation details and the design time of systems targeting heterogeneous NoC-based MPSoCs on FPGA is significantly reduced. In addition, it reduces possible design errors proposing a completely automated technique for fast prototyping. Compared to other SDA flows, the proposed technique targets a bare-metal solution, avoiding the use of an operating system (OS). This reduces the memory requirements on the FPGA platform comparing to related work targeting MPSoC on FPGA. At the same time, the performance (throughput) of the modeled applications can be increased when the number of processors of the target platform is increased. This is shown through a wide set of case studies implemented on FPGA.

QC 20140609

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Books on the topic "Heterogeneous embedded system"

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Pop, Traian. Analysis and optimisation of distributed embedded systems with heterogeneous scheduling policies. Linköping: Department of Computer and Information Science, Linköpings universitet, 2007.

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United States. National Aeronautics and Space Administration, ed. Database interfaces on NASA's heterogeneous distributed database system: Semi-annual report. Houston, Tex: University of Houston, Dept. of Computer Science, 1987.

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United States. National Aeronautics and Space Administration., ed. Database interfaces on NASA's heterogeneous distributed database system: Semi-annual report. Houston, Tex: Univeristy of Houston, Dept. of Computer Science, 1987.

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Peón Quirós, Miguel, Francky Catthoor, and José Manuel Mendías Cuadros. Heterogeneous Memory Organizations in Embedded Systems. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-37432-7.

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Nicolescu, Gabriela, Ian O'Connor, and Christian Piguet, eds. Design Technology for Heterogeneous Embedded Systems. Dordrecht: Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-94-007-1125-9.

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Ian, O'Connor, Piguet Christian, and SpringerLink (Online service), eds. Design Technology for Heterogeneous Embedded Systems. Dordrecht: Springer Science+Business Media B.V., 2012.

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Uchiyama, Kunio, Fumio Arakawa, Hironori Kasahara, Tohru Nojiri, Hideyuki Noda, Yasuhiro Tawara, Akio Idehara, Kenichi Iwata, and Hiroaki Shikano. Heterogeneous Multicore Processor Technologies for Embedded Systems. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-0284-8.

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Uchiyama, Kunio. Heterogeneous Multicore Processor Technologies for Embedded Systems. New York, NY: Springer New York, 2012.

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Neill, Richard W. Heterogeneous Cloud Systems Based on Broadband Embedded Computing. [New York, N.Y.?]: [publisher not identified], 2013.

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Pop, Traian. Scheduling and optimisation of heterogeneous time/event-triggered distributed embedded systems. Linko ping: Univ., 2003.

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Book chapters on the topic "Heterogeneous embedded system"

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Pulini, Gabriele, and David Hulance. "Flexeos Embedded FPGA Solution." In Dynamic System Reconfiguration in Heterogeneous Platforms, 39–47. Dordrecht: Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-90-481-2427-5_4.

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Kriebel, Florian, Faiq Khalid, Bharath Srinivas Prabakaran, Semeen Rehman, and Muhammad Shafique. "Fault-Tolerant Computing with Heterogeneous Hardening Modes." In Dependable Embedded Systems, 161–80. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_7.

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AbstractFault-tolerance using (full-scale) redundancy-based techniques has been employed to detect and correct reliability errors (i.e., soft errors), but they pose significant area and power overhead. On the other hand, due to the masking and the error tolerance properties at different system layers and of different applications, respectively, reliable heterogeneous architectures have been emerged as an attractive design choice for power-efficient dependable computing platforms. This chapter discusses the building blocks of such computing systems, based on both embedded and superscalar processors, with different reliability (fault-tolerant) modes at the architecture layer to memories like caches, for heterogeneous in-order and out-of-order processors. We provide a comprehensive reliability, i.e., soft error, vulnerability analysis of different components in in-order and out-of-order processors, e.g., caches. We also discuss different methodologies to improve the performance and power of such a system by analyzing these vulnerabilities. Moreover, we show how such heterogeneous hardware-level hardening modes can further be complemented by software-level techniques that can be realized using a reliability-driven compiler (as introduced in Chapter “Dependable Software Generation and Execution on Embedded Systems”).
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Elespuru, Peter R., Sagun Shakya, and Shivakant Mishra. "MapReduce System over Heterogeneous Mobile Devices." In Software Technologies for Embedded and Ubiquitous Systems, 168–79. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-10265-3_16.

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Wu, Qiang, Jinian Bian, and Hongxi Xue. "A Distributed Architecture Model for Heterogeneous Multiprocessor System-on-Chip Design." In Embedded Software and Systems, 150–57. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11535409_21.

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Cheng, Xu. "Heterogeneous Multi-processor SoC: An Emerging Paradigm of Embedded System Design and Its Challenges." In Embedded Software and Systems, 3. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11599555_3.

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Duranton, Marc, Jan Hoogerbrugge, Ghiath Al-kadi, Surendra Guntur, and Andrei Terechko. "Rapid Technology-Aware Design Space Exploration for Embedded Heterogeneous Multiprocessors." In Processor and System-on-Chip Simulation, 259–75. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6175-4_16.

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Gheorghe, L., F. Bouchhima, G. Nicolescu, and M. Abid. "Anatomy of a Continuous/Discrete System Execution Model for Timed Execution of Heterogeneous Systems." In Global Specification and Validation of Embedded Systems, 75–108. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-6153-0_6.

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Pomante, Luigi. "System-Level Partitioning." In Electronic System-Level HW/SW Co-Design of Heterogeneous Multi-Processor Embedded Systems, 123–38. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338079-8.

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Pomante, Luigi. "System-Level Design Space Exploration for Dedicated Heterogeneous Multi-Processor Systems." In Electronic System-Level HW/SW Co-Design of Heterogeneous Multi-Processor Embedded Systems, 175–98. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338079-13.

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Pomante, Luigi. "System-Level Co-Simulation." In Electronic System-Level HW/SW Co-Design of Heterogeneous Multi-Processor Embedded Systems, 139–58. New York: River Publishers, 2022. http://dx.doi.org/10.1201/9781003338079-9.

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Conference papers on the topic "Heterogeneous embedded system"

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Mitra, Tulika. "Mobile heterogeneous computing." In ESWEEK'17: THIRTEENTH EMBEDDED SYSTEM WEEK. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3139315.3151619.

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Meyer, Brett. "Session details: Optimizing heterogeneous multicore systems." In ESWEEK'12: Eighth Embedded System Week. New York, NY, USA: ACM, 2012. http://dx.doi.org/10.1145/3250260.

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Plumbridge, Gary, and Neil Audsley. "Extending Java for heterogeneous embedded system description." In 2011 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). IEEE, 2011. http://dx.doi.org/10.1109/recosoc.2011.5981527.

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Neshatpour, Katayoun, Avesta Sasan, and Houman Homayoun. "Big data analytics on heterogeneous accelerator architectures." In ESWEEK'16: TWELFTH EMBEDDED SYSTEM WEEK. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2968456.2976765.

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Kurth, Andreas, Andreas Tretter, Pascal A. Hager, Sergio Sanabria, Orçun Göksel, Lothar Thiele, and Luca Benini. "Mobile Ultrasound Imaging on Heterogeneous Multi-Core Platforms." In ESWEEK'16: TWELFTH EMBEDDED SYSTEM WEEK. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2993452.2993565.

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Pham, Thinh H., Shanker Shreejith, Sebastian Steinhorst, Suhaib A. Fahmy, and Samarjit Chakraborty. "Heterogeneous Communication Virtualization for Distributed Embedded Applications." In 2021 24th Euromicro Conference on Digital System Design (DSD). IEEE, 2021. http://dx.doi.org/10.1109/dsd53832.2021.00047.

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Teich, Juigen. "Session details: Perfomance analysis and optimization for heterogeneous multiprocesses system." In ESWeek '09: Fifth Embedded Systems Week. New York, NY, USA: ACM, 2009. http://dx.doi.org/10.1145/3257649.

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Naghashi, M., S. H. Mozafari, and S. Hessabi. "Heterogeneous redundancy to address performance and cost in multi-core SIMT." In ESWEEK'17: THIRTEENTH EMBEDDED SYSTEM WEEK. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3125502.3125547.

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Maghazeh, Arian, Unmesh D. Bordoloi, Adrian Horga, Petru Eles, and Zebo Peng. "Saving energy without defying deadlines on mobile GPU-based heterogeneous systems." In ESWEEK'14: TENTH EMBEDDED SYSTEM WEEK. New York, NY, USA: ACM, 2014. http://dx.doi.org/10.1145/2656075.2656097.

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Chandramohan, Kiran, and Michael F. P. O'Boyle. "A compiler framework for automatically mapping data parallel programs to heterogeneous MPSoCs." In ESWEEK'14: TENTH EMBEDDED SYSTEM WEEK. New York, NY, USA: ACM, 2014. http://dx.doi.org/10.1145/2656106.2656107.

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Reports on the topic "Heterogeneous embedded system"

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Dafflon, Baptiste, S. Wielandt, S. Uhlemann, Haruko Wainwright, K. Bennett, Jitendra Kumar, Sebastien Biraud, Susan Hubbard, and Stan Wullschleger. Revolutionizing observations and predictability of Arctic system dynamics through next-generation dense, heterogeneous and intelligent wireless sensor networks with embedded AI. Office of Scientific and Technical Information (OSTI), April 2021. http://dx.doi.org/10.2172/1769774.

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Russo, David, Daniel M. Tartakovsky, and Shlomo P. Neuman. Development of Predictive Tools for Contaminant Transport through Variably-Saturated Heterogeneous Composite Porous Formations. United States Department of Agriculture, December 2012. http://dx.doi.org/10.32747/2012.7592658.bard.

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The vadose (unsaturated) zone forms a major hydrologic link between the ground surface and underlying aquifers. To understand properly its role in protecting groundwater from near surface sources of contamination, one must be able to analyze quantitatively water flow and contaminant transport in variably saturated subsurface environments that are highly heterogeneous, often consisting of multiple geologic units and/or high and/or low permeability inclusions. The specific objectives of this research were: (i) to develop efficient and accurate tools for probabilistic delineation of dominant geologic features comprising the vadose zone; (ii) to develop a complementary set of data analysis tools for discerning the fractal properties of hydraulic and transport parameters of highly heterogeneous vadose zone; (iii) to develop and test the associated computational methods for probabilistic analysis of flow and transport in highly heterogeneous subsurface environments; and (iv) to apply the computational framework to design an “optimal” observation network for monitoring and forecasting the fate and migration of contaminant plumes originating from agricultural activities. During the course of the project, we modified the third objective to include additional computational method, based on the notion that the heterogeneous formation can be considered as a mixture of populations of differing spatial structures. Regarding uncertainly analysis, going beyond approaches based on mean and variance of system states, we succeeded to develop probability density function (PDF) solutions enabling one to evaluate probabilities of rare events, required for probabilistic risk assessment. In addition, we developed reduced complexity models for the probabilistic forecasting of infiltration rates in heterogeneous soils during surface runoff and/or flooding events Regarding flow and transport in variably saturated, spatially heterogeneous formations associated with fine- and coarse-textured embedded soils (FTES- and CTES-formations, respectively).We succeeded to develop first-order and numerical frameworks for flow and transport in three-dimensional (3-D), variably saturated, bimodal, heterogeneous formations, with single and dual porosity, respectively. Regarding the sampling problem defined as, how many sampling points are needed, and where to locate them spatially in the horizontal x₂x₃ plane of the field. Based on our computational framework, we succeeded to develop and demonstrate a methdology that might improve considerably our ability to describe quntitaively the response of complicated 3-D flow systems. The results of the project are of theoretical and practical importance; they provided a rigorous framework to modeling water flow and solute transport in a realistic, highly heterogeneous, composite flow system with uncertain properties under-specified by data. Specifically, they: (i) enhanced fundamental understanding of the basic mechanisms of field-scale flow and transport in near-surface geological formations under realistic flow scenarios, (ii) provided a means to assess the ability of existing flow and transport models to handle realistic flow conditions, and (iii) provided a means to assess quantitatively the threats posed to groundwater by contamination from agricultural sources.
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Venkataramana, Raju D. Adaptive Framework for Automated Mapping and Architecture Trades for Embedded Heterogeneous Systems. Fort Belvoir, VA: Defense Technical Information Center, May 2003. http://dx.doi.org/10.21236/ada419986.

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de Kemp, E. A., H. A. J. Russell, B. Brodaric, D. B. Snyder, M. J. Hillier, M. St-Onge, C. Harrison, et al. Initiating transformative geoscience practice at the Geological Survey of Canada: Canada in 3D. Natural Resources Canada/CMSS/Information Management, 2022. http://dx.doi.org/10.4095/331097.

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Application of 3D technologies to the wide range of Geosciences knowledge domains is well underway. These have been operationalized in workflows of the hydrocarbon sector for a half-century, and now in mining for over two decades. In Geosciences, algorithms, structured workflows and data integration strategies can support compelling Earth models, however challenges remain to meet the standards of geological plausibility required for most geoscientific studies. There is also missing links in the institutional information infrastructure supporting operational multi-scale 3D data and model development. Canada in 3D (C3D) is a vision and road map for transforming the Geological Survey of Canada's (GSC) work practice by leveraging emerging 3D technologies. Primarily the transformation from 2D geological mapping, to a well-structured 3D modelling practice that is both data-driven and knowledge-driven. It is tempting to imagine that advanced 3D computational methods, coupled with Artificial Intelligence and Big Data tools will automate the bulk of this process. To effectively apply these methods there is a need, however, for data to be in a well-organized, classified, georeferenced (3D) format embedded with key information, such as spatial-temporal relations, and earth process knowledge. Another key challenge for C3D is the relative infancy of 3D geoscience technologies for geological inference and 3D modelling using sparse and heterogeneous regional geoscience information, while preserving the insights and expertise of geoscientists maintaining scientific integrity of digital products. In most geological surveys, there remains considerable educational and operational challenges to achieve this balance of digital automation and expert knowledge. Emerging from the last two decades of research are more efficient workflows, transitioning from cumbersome, explicit (manual) to reproducible implicit semi-automated methods. They are characterized by integrated and iterative, forward and reverse geophysical modelling, coupled with stratigraphic and structural approaches. The full impact of research and development with these 3D tools, geophysical-geological integration and simulation approaches is perhaps unpredictable, but the expectation is that they will produce predictive, instructive models of Canada's geology that will be used to educate, prioritize and influence sustainable policy for stewarding our natural resources. On the horizon are 3D geological modelling methods spanning the gulf between local and frontier or green-fields, as well as deep crustal characterization. These are key components of mineral systems understanding, integrated and coupled hydrological modelling and energy transition applications, e.g. carbon sequestration, in-situ hydrogen mining, and geothermal exploration. Presented are some case study examples at a range of scales from our efforts in C3D.
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