Relevant bibliographies by topics / Heterogeneous ASIPs

Academic literature on the topic 'Heterogeneous ASIPs'

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Published: 4 June 2021
Last updated: 1 February 2022

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Journal articles on the topic "Heterogeneous ASIPs"

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Diken, Erkan, Roel Jordans, Rosilde Corvino, Lech Jóźwiak, Henk Corporaal, and Felipe Augusto Chies. "Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths." Microprocessors and Microsystems 38, no. 8 (November 2014): 947–59. http://dx.doi.org/10.1016/j.micpro.2014.05.004.

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Radhakrishnan, S., H. Guo, S. Parameswaran, and A. Ignjatovic. "HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors." IET Computers & Digital Techniques 3, no. 1 (2009): 94. http://dx.doi.org/10.1049/iet-cdt:20080005.

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Meloni, Paolo, Claudio Rubattu, Giuseppe Tuveri, Danilo Pani, Luigi Raffo, and Francesca Palumbo. "Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs." Journal of Systems Architecture 76 (May 2017): 89–101. http://dx.doi.org/10.1016/j.sysarc.2016.11.005.

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Li, Tao, Shuibing He, Ping Chen, Siling Yang, Yanlong Yin, and Cheng Xu. "Application and Storage-Aware Data Placement and Job Scheduling for Hadoop Clusters." Journal of Circuits, Systems and Computers 29, no. 16 (December 21, 2020): 2050254. http://dx.doi.org/10.1142/s0218126620502540.

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As one of the most popular frameworks for large-scale analytics processing, Hadoop is facing two challenges: both applications and storage devices become heterogeneous. However, existing data placement and job scheduling schemes pay little attention to such heterogeneity of either application I/O requirements or I/O device capability, thus can greatly degrade system efficiencies. In this paper, we propose ASPS, an Application and Storage-aware data Placement and job Scheduling approach for Hadoop clusters. The idea is to place application data and schedule application tasks considering both application I/O requirements and storage device characteristics. Specifically, ASPS first introduces novel metrics to quantify I/O requirements of applications. Then, based on the quantification, ASPS places data of different applications to the preferred storage devices. Finally, ASPS tries to launch jobs with high I/O requirements on the nodes with the same type of faster devices to improve system efficiency. We have implemented ASPS in Hadoop framework. Experimental results show that ASPS can reduce the completion time of a single application by up to 36% and the average completion time of six concurrent applications by 27%, compared to existing data placement policies and job scheduling approaches.
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Pasha, Muhammad Adeel, Umer Farooq, and Bilal Siddiqui. "A framework for high-level simulation and optimization of fine-grained reconfigurable architectures." SIMULATION 95, no. 8 (September 10, 2018): 737–51. http://dx.doi.org/10.1177/0037549718796272.

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Field Programmable Gate Arrays (FPGAs), due to their programmability, have become a popular design choice for control and processing blocks of modern-day digital design. However, this flexibility makes them larger, slower, and less power-efficient when compared to Application Specific Integrated Circuits (ASICs). On the other hand, ASICs have their own drawbacks, such as lack of programmability and inflexibility. One potential solution is specialized fine-grained reconfigurable architectures that have improved flexibility over ASICs and better resource utilization than FPGAs. However, designing a fine-grained reconfigurable architecture is a daunting task in itself due to lack of high-level design-flow support. This article proposes an automated design-flow for the system-level simulation, optimization, and resource estimation of generic as well as custom fine-grained reconfigurable architectures. The proposed framework is generic in nature as it can be used for both control-oriented and compute-intensive applications and then generates a homogeneous or heterogeneous reconfigurable architecture for them. Four sets of homogeneous and heterogeneous benchmarks are used in this work to show the efficacy of our proposed design-flow, and simulation results reveal that our framework can generate both generic and custom fine-grained reconfigurable architectures. Moreover, the area and power estimations show that auto-generated domain-specific reconfigurable architectures are 76% and 73% more area and power-efficient, respectively, than generic FPGA-based implementations. These results are consistent with the savings reported for manual designs in the literature.
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Wei, Zhenqi, Peilin Liu, Rongdi Sun, Jun Dai, Zunquan Zhou, Xiangming Geng, and Rendong Ying. "HAVA: Heterogeneous Multicore ASIP for Multichannel Low-Bit-Rate Vocoder Applications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, no. 7 (July 2016): 2593–97. http://dx.doi.org/10.1109/tvlsi.2015.2509459.

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Isaac, Allan Punzalan, Johan Mathew, Anjali Nerlekar, Paul Schalow, and Tamara Sears. "Further thoughts on Asian Studies “inside-out”." International Journal of Asian Studies 18, no. 2 (June 10, 2021): 217–24. http://dx.doi.org/10.1017/s1479591421000152.

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AbstractIn response to Sato and Sonoda's “Asian Studies ‘inside out’: research agenda for the development of Global Asian Studies,” members of the Global Asias Collaborative at Rutgers University – comprised of a diverse group of scholars of Asia and the Asian diaspora located in history, literature, art history, geography, among other disciplines – offer responses to this generative prompt to remap the place and field of “Asia” in its heterogeneous and interwoven temporalities and topologies.
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Dersch, Rick, Ludger Tebartz van Elst, Benedikt Hochstuhl, Bernd L. Fiebich, Oliver Stich, Tilman Robinson, Miriam Matysik, et al. "Anti-Thyroid Peroxidase and Anti-Thyroglobulin Autoantibodies in the Cerebrospinal Fluid of Patients with Unipolar Depression." Journal of Clinical Medicine 9, no. 8 (July 27, 2020): 2391. http://dx.doi.org/10.3390/jcm9082391.

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Introduction: The risk of developing depression is increased in patients with autoimmune thyroiditis. Autoimmune Hashimoto thyroiditis is diagnosed using the serum markers anti-thyroid peroxidase (TPO) and anti-thyroglobulin (TG) antibodies. In rare cases, patients with autoimmune thyroiditis can also suffer from the heterogeneous and ill-defined syndrome of Hashimoto encephalopathy. Biomarkers for Hashimoto encephalopathy or for any brain involvement of autoimmune thyroiditis are currently lacking. The aim of the present descriptive study was therefore to determine whether a subgroup of seropositive patients shows intrathecal anti-thyroid antibody synthesis in the cerebrospinal fluid (CSF). Participants and methods: Paired serum and CSF samples from 100 patients with unipolar depression were examined for anti-TPO and anti-TG antibodies using enzyme-linked immunosorbent assays. Antibody-specific indices (ASIs) were calculated for seropositive samples. These ASIs allow the differentiation between the brain-derived fraction of antibodies and antibodies which are passively diffused from the serum. ASIs >1.4 were assessed as positive for brain-derived antibodies. Additionally, for explorative evaluations, a stricter ASI limit of >2 was applied. Results: Anti-TPO antibodies were increased in the serum of 16 patients (16%); increased anti-TPO ASIs (>1.4) were detected in 11 of these patients (69%). Anti-TG antibodies in the serum were detected in three patients (3%), with two of them (67%) showing increased ASIs (>1.4). Overall, the authors found increased anti-thyroid antibodies in 17 of 100 patients (17%), with 13 out of 17 patients showing increased ASIs (76%; range 1.4–4.1). Choosing ASI levels of >2 led to positive findings in six out of 16 patients (38%) with anti-TPO antibodies in their serum but no increase in ASIs in three patients (0%) who were seropositive for anti-TG antibodies. The patients with elevated ASIs (N = 13) were younger than the ASI-negative patients (N = 87; p = 0.009); no differences were noted in the frequency of CSF, electroencephalography, and/or magnetic resonance imaging alterations. Discussion: A subgroup of seropositive patients showed intrathecal synthesis of anti-TPO and, more rarely, of anti-TG antibodies, which might be an indication of central autoimmunity in a subgroup of patients with unipolar depression. The confirmation of elevated ASIs as a biomarker for Hashimoto encephalopathy must await further studies. The relevance of the findings is limited by the study’s retrospective and uncontrolled design.
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Jafri, Atif Raza, Amer Baghdadi, M. Najam-ul-Islam, and Michel Jezequel. "Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD." IEEE Transactions on Circuits and Systems II: Express Briefs 64, no. 3 (March 2017): 259–63. http://dx.doi.org/10.1109/tcsii.2016.2555018.

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Vishnyakova, A. Yu, A. B. Berdalin, D. A. Golovin, S. E. Lelyuk, and V. G. Lelyuk. "Similarities and differences in ultrasound of extracranial brachiocephalic atherosclerotic lesions in patients with ischemic anterior and posterior circulation stroke." Cardiovascular Therapy and Prevention 20, no. 1 (February 19, 2021): 2437. http://dx.doi.org/10.15829/1728-8800-2021-2437.

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Aim. To establish similarities and differences in ultrasound of extracranial brachiocephalic atherosclerotic lesions in patients with ischemic anterior and posterior circulation stroke.Material and methods. The study involved 668 patients (men, 370; women, 298) with carotid territory IS aged 63±11 and 69±9 years, respectively, and 235 patients (men, 129; women, 106) with vertebrobasilar (VB) territory IS aged 59±12 and 63±10 years, respectively, who underwent duplex ultrasound.Results. Atherosclerotic plaques (ASP) in the internal carotid arteries (ICA) were diagnosed significantly more often (p<0,05) (right ICA (ICAr) — 44,0% of cases; left ICA (ICAl) — 48,4%) and the degree of stenosis of ICA mouths was significantly higher (p<0,05) (ICAr —53±23%, ICAl — 54±24%) in carotid territory IS than in VB territory IS (ICAr — 34,0% of cases; average degree of stenosis — 47±18%; ICAl — 33,6%, average degree of stenosis — 46±18%. There were no significant differences in the prevalence of ASP in vertebral arteries and related stenosis in IS in both territories. Also, there were no significant intergroup differences in the prevalence of homogeneous anechoic or hypoechoic and heterogeneous with hypoechoic predominance ASPs in the ICA mouths: in carotid territory IS, such ASPs were detected in each ICA in 33,5% of cases; in VB territory IS, in 29,6% of cases.Conclusion. In patients with carotid and VB territory IS, risky ASPs were recorded with the same frequency, while the overall prevalence of ASPs and the stenosis degree of ICA mouths was significantly higher in carotid IS.
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Dissertations / Theses on the topic "Heterogeneous ASIPs"

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Radhakrishnan, Swarnalatha Computer Science &amp Engineering Faculty of Engineering UNSW. "Heterogeneous multi-pipeline application specific instruction-set processor design and implementation." Awarded by:University of New South Wales. Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/29161.

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Embedded systems are becoming ubiquitous, primarily due to the fast evolution of digital electronic devices. The design of modern embedded systems requires systems to exhibit, high performance and reliability, yet have short design time and low cost. Application Specific Instruction set processors (ASIPs) are widely used in embedded system since they are economical to use, flexible, and reusable (thus saves design time). During the last decade research work on ASIPs have been carried out in mainly for single pipelined processors. Improving performance in processors is possible by exploring the available parallelism in the program. Designing of multiple parallel execution paths for parallel execution of the processor naturally incurs additional cost. The methodology presented in this dissertation has addressed the problem of improving performance in ASIPs, at minimal additional cost. The devised methodology explores the available parallelism of an application to generate a multi-pipeline heterogeneous ASIP. The processor design is application specific. No pre-defined IPs are used in the design. The generated processor contains multiple standalone pipelined data paths, which are not necessarily identical, and are connected by the necessary bypass paths and control signals. Control unit are separate for each pipeline (though with the same clock) resulting in a simple and cost effective design. By using separate instruction and data memories (Harvard architecture) and by allowing memory access by two separate pipes, the complexity of the controller and buses are reduced. The impact of higher memory latencies is nullified by utilizing parallel pipes during memory access. Efficient bypass network selection and encoding techniques provide a better implementation. The initial design approach with only two pipelines without bypass paths show speed improvements of up to 36% and switching activity reductions of up to 11%. The additional area costs around 16%. An improved design with different number of pipelines (more than two) based on applications show on average of 77% performance improvement with overheads of: 49% on area; 51% on leakage power; 17% on switching activity; and 69% on code size. The design was further trimmed, with bypass path selection and encoding techniques, which show a saving of up to 32% of area and 34% of leakage power with 6% performance improvement and 69% of code size reduction compared to the design approach without these techniques in the multi pipeline design.
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Book chapters on the topic "Heterogeneous ASIPs"

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Zhang, Diandian, Jeronimo Castrillon, Stefan Schürmans, Gerd Ascheid, Rainer Leupers, and Bart Vanthournout. "System-Level Analysis of MPSoCs with a Hardware Scheduler." In Advances in Systems Analysis, Software Engineering, and High Performance Computing, 335–67. IGI Global, 2014. http://dx.doi.org/10.4018/978-1-4666-6034-2.ch014.

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Efficient runtime resource management in heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) for achieving high performance and energy efficiency is one key challenge for system designers. In the past years, several IP blocks have been proposed that implement system-wide runtime task and resource management. As the processor count continues to increase, it is important to analyze the scalability of runtime managers at the system-level for different communication architectures. In this chapter, the authors analyze the scalability of an Application-Specific Instruction-Set Processor (ASIP) for runtime management called OSIP on two platform paradigms: shared and distributed memory. For the former, a generic bus is used as interconnect. For distributed memory, a Network-on-Chip (NoC) is used. The effects of OSIP and the communication architecture are jointly investigated from the system point of view, based on a broad case study with real applications (an H.264 video decoder and a digital receiver for wireless communications) and a synthetic benchmark application.
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Conference papers on the topic "Heterogeneous ASIPs"

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Jozwiak, Lech, and Menno Lindwer. "Issues and Challenges in Development of Massively-Parallel Heterogeneous MPSoCs Based on Adaptable ASIPs." In 2011 19th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP). IEEE, 2011. http://dx.doi.org/10.1109/pdp.2011.55.

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Radhakrishnan, Swarnalatha, Hui Guo, and Sri Parameswaran. "Dual-pipeline heterogeneous ASIP design." In the 2nd IEEE/ACM/IFIP international conference. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/1016720.1016727.

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"Session details: Session 7A: Accelerators: GPUs, ASICs, and Heterogeneous Systems." In the Twenty-Second International Conference, Chair Lingjia Tang. New York, New York, USA: ACM Press, 2017. http://dx.doi.org/10.1145/3037697.3248626.

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Tang, Lingjia. "Session details: Session 7A: Accelerators: GPUs, ASICs, and Heterogeneous Systems." In ASPLOS '17: Architectural Support for Programming Languages and Operating Systems. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3248626.

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Xiong Bing, Wang Yanlin, and Li Dong. "Multi-port embedded debugger agent for heterogeneous multi-core ASIP debug." In 2015 12th IEEE International Conference on Electronic Measurement & Instruments (ICEMI). IEEE, 2015. http://dx.doi.org/10.1109/icemi.2015.7494306.

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Grossman, J. P., Cliff Young, Joseph A. Bank, Kenneth Mackenzie, Douglas J. Ierardi, John K. Salmon, Ron O. Dror, and David E. Shaw. "Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs." In the 6th IEEE/ACM/IFIP international conference. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1450135.1450165.

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Li, Tuo, Muhammad Shafique, Semeen Rehman, Jude Angelo Ambrose, Jorg Henkel, and Sri Parameswaran. "DHASER: Dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems." In 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2013. http://dx.doi.org/10.1109/iccad.2013.6691184.

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