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Journal articles on the topic 'Heterogeneous Architecture Design'

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Published: 22 June 2023

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1

LIU, SHAOSHAN, WON W. RO, CHEN LIU, ALFREDO CRISTOBAL-SALAS, CHRISTOPHE CÉRIN, JIAN-JUN HAN, and JEAN-LUC GAUDIOT. "INTRODUCING THE EXTREMELY HETEROGENEOUS ARCHITECTURE." Journal of Interconnection Networks 13, no. 03n04 (September 2012): 1250010. http://dx.doi.org/10.1142/s0219265912500107.

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The computer industry is moving towards two extremes: extremely high-performance high-throughput cloud computing, and low-power mobile computing. Cloud computing, while providing high performance, is very costly. Google and Microsoft Bing spend billions of dollars each year to maintain their server farms, mainly due to the high power bills. On the other hand, mobile computing is under a very tight energy budget, but yet the end users demand ever increasing performance on these devices. This trend indicates that conventional architectures are not able to deliver high-performance and low power consumption at the same time, and we need a new architecture model to address the needs of both extremes. In this paper, we thus introduce our Extremely Heterogeneous Architecture (EHA) project: EHA is a novel architecture that incorporates both general-purpose and specialized cores on the same chip. The general-purpose cores take care of generic control and computation. On the other hand, the specialized cores, including GPU, hard accelerators (ASIC accelerators), and soft accelerators (FPGAs), are designed for accelerating frequently used or heavy weight applications. When acceleration is not needed, the specialized cores are turned off to reduce power consumption. We demonstrate that EHA is able to improve performance through acceleration, and at the same time reduce power consumption. Since EHA is a heterogeneous architecture, it is suitable for accelerating heterogeneous workloads on the same chip. For example, data centers and clouds provide many services, including media streaming, searching, indexing, scientific computations. The ultimate goal of the EHA project is two-fold: first, to design a chip that is able to run different cloud services on it, and through this design, we would be able to greatly reduce the cost, both recurring and non-recurring, of data centers\clouds; second, to design a light-weight EHA that runs on mobile devices, providing end users with improved experience even under tight battery budget constraints.
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Ahsan, AMM, Ruinan Xie, and Bashir Khoda. "Heterogeneous topology design and voxel-based bio-printing." Rapid Prototyping Journal 24, no. 7 (October 8, 2018): 1142–54. http://dx.doi.org/10.1108/rpj-05-2017-0076.

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Purpose The purpose of this paper is to present a topology-based tissue scaffold design methodology to accurately represent the heterogeneous internal architecture of tissues/organs. Design/methodology/approach An image analysis technique is used that digitizes the topology information contained in medical images of tissues/organs. A weighted topology reconstruction algorithm is implemented to represent the heterogeneity with parametric functions. The parametric functions are then used to map the spatial material distribution following voxelization. The generated chronological information yields hierarchical tool-path points which are directly transferred to the three-dimensional (3D) bio-printer through a proposed generic platform called Application Program Interface (API). This seamless data corridor between design (virtual) and fabrication (physical) ensures the manufacturability of personalized heterogeneous porous scaffold structure without any CAD/STL file. Findings The proposed methodology is implemented to verify the effectiveness of the approach and the designed example structures are bio-fabricated with a deposition-based bio-additive manufacturing system. The designed and fabricated heterogeneous structures are evaluated which shows conforming porosity distribution compared to uniform method. Originality/value In bio-fabrication process, the generated bio-models with boundary representation (B-rep) or surface tessellation (mesh) do not capture the internal architectural information. This paper provides a design methodology for scaffold structure mimicking the native tissue/organ architecture and direct fabricating the structure without reconstructing the CAD model. Therefore, designing and direct bio-printing the heterogeneous topology of tissue scaffolds from medical images minimize the disparity between the internal architecture of target tissue and its scaffold.
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Sek Meng Chai, T. M. Taha, D. S. Wills, and J. D. Meindl. "Heterogeneous architecture models for interconnect-motivated system design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8, no. 6 (December 2000): 660–70. http://dx.doi.org/10.1109/92.902260.

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Yang, Chungang, Jiandong Li, and Alagan Anpalagan. "Energy Efficiency Architecture Design for Heterogeneous Cellular Networks." Wireless Communications and Mobile Computing 16, no. 12 (September 15, 2015): 1588–602. http://dx.doi.org/10.1002/wcm.2635.

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Kovalyov, S. P. "Design of Heterogeneous Cyber-Physical Systems Employing Category Theory." Mekhatronika, Avtomatizatsiya, Upravlenie 23, no. 2 (February 6, 2022): 59–67. http://dx.doi.org/10.17587/mau.23.59-67.

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Heterogeneous cyber-physical control systems based on digital twins are in demand by Industry 4.0. In accordance with the contemporary systems engineering methodology, such systems are designed at the level of digital models. The paper proposes approaches to formalization and subsequent automation of solving direct and inverse problems of their design. To unify descriptions of heterogeneous components, we follow a viewpoint-based approach to architecture design recommended by the international standard ISO/IEC/IEEE 42010. Following recent trends, we employ category theory as a mathematical framework for the formal description and solution of design problems. Indeed, category theory is a branch of higher algebra specifically aimed at a unified representation of objects of different nature and relationships between them. The design space of a heterogeneous cyber-physical system is constructed as a subcategory of the multicomma category, the objects of which describe possible system architectures with a fixed structural hierarchy represented from a certain viewpoint as diagrams, and morphisms denote actions associated with the parts selection and replacement during the system design. Direct design problems consist in evaluating the properties of the system as a whole by its architecture and are solved using a universal category-theoretic construction of the colimit of the diagram. The solution of inverse problems that require finding variants of the system architecture, which are (sub-, Pareto-) optimal according to the consumer quality criteria, consists in reconstructing diagrams by their colimit edges. For such reconstruction, optimization algorithms of gradient descent type are reasonable to employ, which navigate along the system design space morphisms calculating the path by means of computer algebra. Typical techniques of assembling cyber-physical systems, such as modular composition and aspect weaving, are described in the language of category theory and illustrated. As an example, we outline the design of energy-efficient robotic production lines represented from the behavior viewpoint as discrete-event simulation models.
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AGYEMAN, MICHAEL O., ALI AHMADINIA, and ALIREZA SHAHRABI. "HETEROGENEOUS 3D NETWORK-ON-CHIP ARCHITECTURES: AREA AND POWER AWARE DESIGN TECHNIQUES." Journal of Circuits, Systems and Computers 22, no. 04 (April 2013): 1350016. http://dx.doi.org/10.1142/s0218126613500163.

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Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip floorplan compared to a 2D router. Hence, more efficient architectures should be designed. In this paper, we propose area efficient and low power 3D heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D NoC architectures. Experimental results show a negligible penalty (less than 5%) in average packet latency of the proposed heterogeneous 3D NoC architectures compared to typical homogeneous 3D NoCs, while the heterogeneity provides power and area efficiency of up to 61% and 19.7%, respectively.
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Pasha, Muhammad Adeel, Umer Farooq, and Bilal Siddiqui. "A framework for high-level simulation and optimization of fine-grained reconfigurable architectures." SIMULATION 95, no. 8 (September 10, 2018): 737–51. http://dx.doi.org/10.1177/0037549718796272.

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Field Programmable Gate Arrays (FPGAs), due to their programmability, have become a popular design choice for control and processing blocks of modern-day digital design. However, this flexibility makes them larger, slower, and less power-efficient when compared to Application Specific Integrated Circuits (ASICs). On the other hand, ASICs have their own drawbacks, such as lack of programmability and inflexibility. One potential solution is specialized fine-grained reconfigurable architectures that have improved flexibility over ASICs and better resource utilization than FPGAs. However, designing a fine-grained reconfigurable architecture is a daunting task in itself due to lack of high-level design-flow support. This article proposes an automated design-flow for the system-level simulation, optimization, and resource estimation of generic as well as custom fine-grained reconfigurable architectures. The proposed framework is generic in nature as it can be used for both control-oriented and compute-intensive applications and then generates a homogeneous or heterogeneous reconfigurable architecture for them. Four sets of homogeneous and heterogeneous benchmarks are used in this work to show the efficacy of our proposed design-flow, and simulation results reveal that our framework can generate both generic and custom fine-grained reconfigurable architectures. Moreover, the area and power estimations show that auto-generated domain-specific reconfigurable architectures are 76% and 73% more area and power-efficient, respectively, than generic FPGA-based implementations. These results are consistent with the savings reported for manual designs in the literature.
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Son, Hyun-Seung, Woo-Yeol Kim, and R. Young-Chul Kim. "MDA(Model Driven Architecture) based Design for Multitasking of Heterogeneous Embedded System." KIPS Transactions:PartD 15D, no. 3 (June 30, 2008): 355–60. http://dx.doi.org/10.3745/kipstd.2008.15-d.3.355.

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He, Tao, Hua Zhong Li, Tang Ren Dan, De Fen Zhang, Jun Qiang Liu, and Guo Rong Qin. "Design and Analysis of Test Model under Heterogeneous and Internet-Ware." Applied Mechanics and Materials 687-691 (November 2014): 2635–39. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.2635.

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Studying a method based on UML model software architecture performance prediction: this method chosen software architecture design in UML, use case diagram, activity diagram and component diagram, and pull stereotypes and tagged values in it, and enlarge them to be UML SPT model, and then turn UML SPT model into queuing network model through conversion algorithm, this algorithm can deal with UML model activity diagram which included branch node and confluent nodes. Finally, using frequency domain analysis theory to get queuing network model, to know performance parameters and performance bottlenecks and also introduce the design plan of UML software architecture performance automation tools, and give a example of performance prediction software architecture.
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Fang, Wei. "Design of Heterogeneous Data Exchange Technology for Teaching Resources Based on ICMPv6." International Journal of Emerging Technologies in Learning (iJET) 13, no. 11 (November 9, 2018): 78. http://dx.doi.org/10.3991/ijet.v13i11.9600.

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To promote the innovation of teaching resources and heterogeneous data exchange platform technologies and theories, heterogeneous data exchange platforms based on ICMPv6 teaching resources were studied. First, based on ICMPv6, the middle-tier architecture of the heterogeneous data exchange platform for teaching resources was studied. Second, the application layer architecture in the heterogeneous data exchange platform system of educational resources was studied. The middle layer and application layer were designed and implemented. Finally, the system was applied to the education platform to reflect its performance. The results showed that the ICMPv6 system could solve data exchange and data sharing systems between schools and homes. Contributions were made in solving interactive education between home and school. To sum up, it is feasible to use ICMPv6 on heterogeneous educational resources exchange platform.
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Fleischer, J., R. Häner, S. Herrnkind, A. Kloth, U. Kriegel, H. Schwarting, and J. Wächter. "An integration platform for heterogeneous sensor systems in GITEWS – Tsunami Service Bus." Natural Hazards and Earth System Sciences 10, no. 6 (June 17, 2010): 1239–52. http://dx.doi.org/10.5194/nhess-10-1239-2010.

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Abstract. The German Indonesian Tsunami Early Warning System (GITEWS) is built upon a complex sensor data infrastructure. To best fulfill the demand for a long living system, the underlying software and hardware architecture of GITEWS must be prepared for future modifications both of single sensors and entire sensors systems. The foundation for a flexible integration and for stable interfaces is a result of following the paradigm of a Service Oriented Architecture (SOA). The Tsunami Service Bus (TSB) – our integration platform in GITEWS – realizes this SOA approach by implementing the Sensor Web Enablement (SWE) standards and services. This paper focuses on architectural and implementation aspects of the TSB. Initially, the general architectural approach in GITEWS by SOA and SWE is presented. Based on this conception, the concrete system architecture of GITEWS is introduced. The sensor integration platform TSB is then discussed in detail, following by its primary responsibilities and components. Special emphasis is laid on architectural transparency, comprehensible design decisions, and references to the applied technology.
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Vítku, Jaroslav, and Pavel Nahodil. "TOWARDS EVOLUTIONARY DESIGN OF COMPLEX SYSTEMS INSPIRED BY NATURE." Acta Polytechnica 54, no. 5 (October 31, 2014): 367–77. http://dx.doi.org/10.14311/ap.2014.54.0367.

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This paper presents first steps towards evolutionary design of complex autonomous systems. The approach is inspired in modularity of human brain and principles of evolution. Rather than evolving neural networks or neural-based systems, the approach focuses on evolving hybrid networks composed of heterogeneous sub-systems implementing various algorithms/behaviors. Currently, the evolutionary techniques are used to optimize weights between predefined blocks (so called Neural Modules) in order to find an agent architecture appropriate for given task. The framework, together with the simulator of such systems is presented. Then, examples of agent architectures represented as hybrid networks are presented. One architecture is hand-designed and one is automatically optimized by means of evolutionary algorithm. Even on such a simple experiment, it can be observed how the evolution is able to pick-up unexpected attributes of the task and exploit them when designing new architecture.
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Payvar, Saman, Maxime Pelcat, and Timo D. Hämäläinen. "A model of architecture for estimating GPU processing performance and power." Design Automation for Embedded Systems 25, no. 1 (January 16, 2021): 43–63. http://dx.doi.org/10.1007/s10617-020-09244-4.

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AbstractEfficient usage of heterogeneous computing architectures requires distribution of the workload on available processing elements. Traditionally, the mapping is based on information acquired from application profiling and utilized in architecture exploration. To reduce the amount of manual work required, statistical application modeling and architecture modeling can be combined with exploration heuristics. While the application modeling side of the problem has been studied extensively, architecture modeling has received less attention. Linear System Level Architecture (LSLA) is a Model of Architecture that aims at separating the architectural concerns from algorithmic ones when predicting performance. This work builds on the LSLA model and introduces non-linear semantics, specifically to support GPU performance and power modeling, by modeling also the degree of parallelism. The model is evaluated with three signal processing applications with various workload distributions on a desktop GPU and mobile GPU. The measured average fidelity of the new model is 93% for performance, and 84% for power, which can fit design space exploration purposes.
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Mahmood, Adnan, Wei Zhang, and Quan Sheng. "Software-Defined Heterogeneous Vehicular Networking: The Architectural Design and Open Challenges." Future Internet 11, no. 3 (March 11, 2019): 70. http://dx.doi.org/10.3390/fi11030070.

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The promising advancements in the telecommunications and automotive sectors over the years have empowered drivers with highly innovative communication and sensing capabilities, in turn paving the way for the next-generation connected and autonomous vehicles. Today, vehicles communicate wirelessly with other vehicles and vulnerable pedestrians in their immediate vicinity to share timely safety-critical information primarily for collision mitigation. Furthermore, vehicles connect with the traffic management entities via their supporting network infrastructure to become more aware of any potential hazards on the roads and for guidance pertinent to their current and anticipated speeds and travelling course to ensure more efficient traffic flows. Therefore, a secure and low-latency communication is highly indispensable in order to meet the stringent performance requirements of such safety-critical vehicular applications. However, the heterogeneity of diverse radio access technologies and inflexibility in their deployment results in network fragmentation and inefficient resource utilization, and these, therefore, act as bottlenecks in realizing the aims for a highly efficient vehicular networking architecture. In order to overcome such sorts of bottlenecks, this article brings forth the current state-of-the-art in the context of intelligent transportation systems (ITS) and subsequently proposes a software-defined heterogeneous vehicular networking (SDHVNet) architecture for ensuring a highly agile networking infrastructure to ensure rapid network innovation on-demand. Finally, a number of potential architectural challenges and their probable solutions are discussed.
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Garg, Siddharth, Shreyas Sundaram, and Hiren D. Patel. "Robust heterogeneous data center design." ACM SIGMETRICS Performance Evaluation Review 39, no. 3 (December 21, 2011): 28–30. http://dx.doi.org/10.1145/2160803.2160850.

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Liu, Li Cheng, Lu Guo Hao, and Rui Hu. "The Design of the Signal Processing Architecture of a Wireless Relay in Heterogeneous Wireless Networks." Advanced Materials Research 403-408 (November 2011): 1728–31. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1728.

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Focusing on the wireless relay in heterogeneous wireless networks, a new signal processing architecture of a wireless relay has been proposed. And with an example of the heterogeneous wireless network consisted of GSM and CDMA systems, the detailed design is illustrated. The instance of the wireless relay demonstrates the feasibility of the proposed signal processing architecture.
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Roorda, Esther, Seyedramin Rasoulinezhad, Philip H. W. Leong, and Steven J. E. Wilton. "FPGA Architecture Exploration for DNN Acceleration." ACM Transactions on Reconfigurable Technology and Systems 15, no. 3 (September 30, 2022): 1–37. http://dx.doi.org/10.1145/3503465.

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Recent years have seen an explosion of machine learning applications implemented on Field-Programmable Gate Arrays (FPGAs) . FPGA vendors and researchers have responded by updating their fabrics to more efficiently implement machine learning accelerators, including innovations such as enhanced Digital Signal Processing (DSP) blocks and hardened systolic arrays. Evaluating architectural proposals is difficult, however, due to the lack of publicly available benchmark circuits. This paper addresses this problem by presenting an open-source benchmark circuit generator that creates realistic DNN-oriented circuits for use in FPGA architecture studies. Unlike previous generators, which create circuits that are agnostic of the underlying FPGA, our circuits explicitly instantiate embedded blocks, allowing for meaningful comparison of recent architectural proposals without the need for a complete inference computer-aided design (CAD) flow. Our circuits are compatible with the VTR CAD suite, allowing for architecture studies that investigate routing congestion and other low-level architectural implications. In addition to addressing the lack of machine learning benchmark circuits, the architecture exploration flow that we propose allows for a more comprehensive evaluation of FPGA architectures than traditional static benchmark suites. We demonstrate this through three case studies which illustrate how realistic benchmark circuits can be generated to target different heterogeneous FPGAs.
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de Paulo, Vitor, and Cristinel Ababei. "3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans." International Journal of Reconfigurable Computing 2010 (2010): 1–12. http://dx.doi.org/10.1155/2010/603059.

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We propose new 3D 2-layer and 3-layer NoC architectures that utilizehomogeneousregular mesh networks on a separate layer and one or twoheterogeneousfloorplanning layers. These architectures combine the benefits of compact heterogeneous floorplans and of regular mesh networks. To demonstrate these benefits, a design methodology that integrates floorplanning, routers assignment, and cycle-accurate NoC simulation is proposed. The implementation of the NoC on a separate layer offers an additional area that may be utilized to improve the network performance by increasing the number of virtual channels, buffers size, or mesh size. Experimental results show that increasing the number of virtual channels rather than the buffers size has a higher impact on network performance. Increasing the mesh size can significantly improve the network performance under the assumption that the clock frequency is given by the length of the physical links. In addition, the 3-layer architecture can offer significantly better network performance compared to the 2-layer architecture.
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Sun, Yao. "Construction of Artistic Design Patterns Based on Improved Distributed Data Parallel Computing of Heterogeneous Tasks." Mathematical Problems in Engineering 2022 (March 31, 2022): 1–11. http://dx.doi.org/10.1155/2022/3890255.

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With the continuous upgrading of hardware in the terminal equipment, how to provide high-performance computing for low-tech threshold users has become a current research hotspot. In the era of green high-performance computing, the heterogeneous computing system can provide good versatility, performance, and efficiency and has broad development prospects. This article provides an in-depth analysis and research on the construction and application of improved models using the artistic design pattern of heterogeneous tasks and parallel computing. Based on the hardware resources in the existing desktop system, this article optimizes the original heterogeneous parallel technology from the aspects of task division and data transmission to reduce the complexity of data allocation and processing for users. Based on the analysis and study of the multicore CPU and GPU architectures in the desktop system, as well as the original CPU-GPU heterogeneous parallel technology, this article optimizes the solution of heterogeneous parallel computing, designs a heterogeneous parallel computing architecture, and deploys a heterogeneous parallel computing architecture. The nodes of the desktop system constitute the parallel computing system. In terms of task allocation, the computing system divides tasks according to the parallelism of tasks. According to the computing resources and bandwidth conditions of each heterogeneous node, starting from the parallel execution time, the task scheduling algorithm is optimized, and the load balancing scheduling scheme is designed to achieve the optimal allocation of resources. In terms of storage resources, the computing system adopts distributed storage as a whole. The CPU-GPU heterogeneous parallel in the desktop system adopts virtual unified storage. Global distributed storage and local shared storage are used to balance overall performance and programming complexity. This article introduces the design and implementation of JTangSync, a distributed heterogeneous data synchronization system. The system adopts a distributed architecture, and each node is organized by a data source module, a data transmission module, a processor module, etc. The data source module is responsible for extracting data, the data transmission module is mainly responsible for efficient data transmission, and the processor module is responsible for data processing. More importantly, each module is designed as a replaceable plug-in, which is convenient for secondary expansion. Each node relies on ZooKeeper to form a cluster, which realizes distributed functions such as centralized management of distributed resources, failover, and resumed transmission. Compared with the mainstream scheduling algorithms HEFT, CPOP, PEFT, and HSIP on heterogeneous systems participating in the experimental evaluation, the scheduling length ratio of DONF series algorithms is reduced by 36.3%–67.5% and the parallelism is increased by 17%–125% in terms of efficiency. Compared with the existing database synchronization system, the JTangSync system has built-in multiple heterogeneous database data sources and supports the synchronization of complex heterogeneous databases. The system supports users to develop and customize their own data sources and data processing programs, to promote secondary development. By adopting the custom compressed data exchange format and network optimization methods such as packet merging, caching, and adaptive compression algorithm, the system has high performance.
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Feldkaemper, H. T., H. Blume, and T. G. Noll. "Study of heterogeneous and reconfigurable architectures in the communication domain." Advances in Radio Science 1 (May 5, 2003): 165–69. http://dx.doi.org/10.5194/ars-1-165-2003.

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Abstract. One of the most challenging design issues for next generations of (mobile) communication systems is fulfilling the computational demands while finding an appropriate trade-off between flexibility and implementation aspects, especially power consumption. Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. Typical target architectures for future communication systems include embedded FPGAs, dedicated macros as well as programmable digital signal and control oriented processor cores as each of these has its specific advantages. These will be integrated as a System-on-Chip (SoC). For such a heterogeneous architecture a design space exploration and an appropriate partitioning plays a crucial role. On the exemplary vehicle of a Viterbi decoder as frequently used in communication systems we show which costs in terms of ATE complexity arise implementing typical components on different types of architecture blocks. A factor of about seven orders of magnitude spans between a physically optimised implementation and an implementation on a programmable DSP kernel. An implementation on an embedded FPGA kernel is in between these two representing an attractive compromise with high flexibility and low power consumption. Extending this comparison to further components, it is shown quantitatively that the cost ratio between different implementation alternatives is closely related to the operation to be performed. This information is essential for the appropriate partitioning of heterogeneous systems.
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Chromiak, Michal, and Marcin Grabowiecki. "Heterogeneous Data Integration Architecture-Challenging Integration Issues." Annales Universitatis Mariae Curie-Sklodowska, sectio AI – Informatica 15, no. 1 (January 1, 2015): 7. http://dx.doi.org/10.17951/ai.2015.15.1.7-11.

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As of today, most of the data processing systems have to deal with a large amount of data originated from numerous sources. Data sources almost always differ regarding its purpose of existence. Thus model, data processing engine and technology differ intensely. Due to current trend for systems fusion there is a growing demand for data to be present in a common way regardless of its legacy. Many systems have been devised as a response to such integration needs. However, the present data integration systems mostly are dedicated solutions that bring constraints and issues when considered in general. In this paper we will focus on the present solutions for data integration, their flaws originating from their architecture or design concepts and present an abstract and general approach that could be introduced as an response to existing issues. The system integration is considered out of scope for this paper, we will focus particularly on efficient data integration.
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Popovici, Katalin, Xavier Guerin, Frederic Rousseau, Pier Stanislao Paolucci, and Ahmed Amine Jerraya. "Platform-based software design flow for heterogeneous MPSoC." ACM Transactions on Embedded Computing Systems 7, no. 4 (July 2008): 1–23. http://dx.doi.org/10.1145/1376804.1376807.

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Saponara, Sergio, and Luca Fanucci. "Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing." VLSI Design 2012 (August 14, 2012): 1–17. http://dx.doi.org/10.1155/2012/450302.

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Two multiprocessor system-on-chip (MPSoC) architectures are proposed and compared in the paper with reference to audio and video processing applications. One architecture exploits a homogeneous topology; it consists of 8 identical tiles, each made of a 32-bit RISC core enhanced by a 64-bit DSP coprocessor with local memory. The other MPSoC architecture exploits a heterogeneous-tile topology with on-chip distributed memory resources; the tiles act as application specific processors supporting a different class of algorithms. In both architectures, the multiple tiles are interconnected by a network-on-chip (NoC) infrastructure, through network interfaces and routers, which allows parallel operations of the multiple tiles. The functional performances and the implementation complexity of the NoC-based MPSoC architectures are assessed by synthesis results in submicron CMOS technology. Among the large set of supported algorithms, two case studies are considered: the real-time implementation of an H.264/MPEG AVC video codec and of a low-distortion digital audio amplifier. The heterogeneous architecture ensures a higher power efficiency and a smaller area occupation and is more suited for low-power multimedia processing, such as in mobile devices. The homogeneous scheme allows for a higher flexibility and easier system scalability and is more suited for general-purpose DSP tasks in power-supplied devices.
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Oxman, Neri. "Structuring Materiality: Design Fabrication of Heterogeneous Materials." Architectural Design 80, no. 4 (July 8, 2010): 78–85. http://dx.doi.org/10.1002/ad.1110.

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KWAK, SANGHOON, JEONG-GUN LEE, EUN-GU JUNG, DONGSOO HAR, MILOS D. ERCEGOVAC, and JEONG-A. LEE. "EXPLORATION OF POWER-DELAY TRADE-OFFS WITH HETEROGENEOUS ADDERS BY INTEGER LINEAR PROGRAMMING." Journal of Circuits, Systems and Computers 18, no. 04 (June 2009): 787–800. http://dx.doi.org/10.1142/s0218126609005368.

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The performance of arithmetic adders varies widely in their power consumption, delay, and area requirements. To acquire more fine-grained trade-offs in the power-delay trade-off curve of a binary adder, the heterogeneous adder architecture is adopted. In heterogeneous adder architecture, a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and bit-widths. Thus the method allows us to expand the original design space of a specific type of adder into the more fine-grained design space by mixing that of each sub-adder. In this paper, a design for heterogeneous adder through power optimization under delay constraints or delay optimization under power constraints was presented by determining the bit-width of each sub-adder. Also the effectiveness of the proposed method was demonstrated by showing the ratio of the power consumption of heterogeneous adder to that of conventional adder.
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Van Craeynest, Kenzo, and Lieven Eeckhout. "Understanding fundamental design choices in single-ISA heterogeneous multicore architectures." ACM Transactions on Architecture and Code Optimization 9, no. 4 (January 2013): 1–23. http://dx.doi.org/10.1145/2400682.2400691.

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Lu, Yu, Jin Ying Wu, Hong Min Chen, Yong Pin Zheng, and Yun Ping Wu. "A Kind of Heterogeneous Data Synchronous Design for the Internet of Things." Advanced Materials Research 476-478 (February 2012): 1392–98. http://dx.doi.org/10.4028/www.scientific.net/amr.476-478.1392.

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The way of heterogeneous data synchronization based on WEB service mode used in the Internet of things is analyzed, the problem of synchronization mechanism of heterogeneous data based on internet web port is solved. Combined with the characteristics of SOA architecture, this paper proposes synchronization model WLDSS (Web-level Data Synchronization System) of distributed heterogeneous data, and gives the design principles and the key strategies of the model. Through the application of distributed solar water heating system of control system data synchronization, it verifies the stability of the WLDSS model.
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Bouyamh, Charoenporn, and Chanankorn Jandaeng. "THE MIDDLEWARE ARCHITECTURE DESIGN FOR GATHERING THE HETEROGENEOUS DATA IN BIG DATA." Indian Journal of Computer Science and Engineering 12, no. 3 (June 25, 2021): 701–8. http://dx.doi.org/10.21817/indjcse/2021/v12i3/211203172.

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JIANG, Jian-chun, Su-hua ZENG, and Ming CEN. "Architecture design of embedded operating system based on heterogeneous dual-core processor." Journal of Computer Applications 28, no. 10 (September 30, 2009): 2686–89. http://dx.doi.org/10.3724/sp.j.1087.2008.02686.

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Shuai, Wen Ming, and Xiu Fen Fu. "A Method of Heterogeneous Data Integration Based on SOA." Applied Mechanics and Materials 536-537 (April 2014): 494–98. http://dx.doi.org/10.4028/www.scientific.net/amm.536-537.494.

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With the rapid development of information technology, the growth of heterogeneous Web data and the requirements of access to the Web of data also is growing. In view of this, a method of heterogeneous data integration based on SOA(Service-Oriented Architecture) is proposed. This method combines the technology of middleware and SOA design, using XML and Web services technologies, presents a framework of heterogeneous data integration based on SOA, and introduces the architecture of SOA data integration middleware. Experimental results show that this method reduces the coupling of heterogeneous data integration system effectively, and improves the scalability of the system.
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Verkest, D., K. Van Rompaey, I. Bolsens, and H. De Man. "CoWare—A design environment for heterogeneous hardware/software systems." Design Automation for Embedded Systems 1, no. 4 (October 1996): 357–86. http://dx.doi.org/10.1007/bf00209910.

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Gongora, Andres, Javier Monroy, and Javier Gonzalez-Jimenez. "An Electronic Architecture for Multipurpose Artificial Noses." Journal of Sensors 2018 (2018): 1–9. http://dx.doi.org/10.1155/2018/5427693.

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This paper deals with the design of an electronic device aimed at the detection and characterization of volatile chemical substances, that is, an electronic nose (e-nose). We pursue the development of a versatile, multipurpose e-nose that can be employed for a wide variety of applications, can integrate heterogeneous sensing technologies, and can offer a mechanism to be customized for different requirements. To that end, we contribute with a fully configurable and decentralized e-nose architecture based on self-contained and intelligent sensor boards (i.e., modules). This design allows for the integration not only of heterogeneous gas sensor technologies, like MOX and AEC sensors, but also of other components, such as GPS or Bluetooth, for a total of up to 127 individual modules. We describe an implementation of a fully operative prototype as an illustrative example of its potential for sensor networks, mobile robotics, and wearable technologies, each using different combinations of sensors.
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Wu, Rongteng, and Xiaohong Xie. "A Heterogeneous Parallel LU Factorization Algorithm Based on a Basic Column Block Uniform Allocation Strategy." Mathematical Problems in Engineering 2019 (February 25, 2019): 1–12. http://dx.doi.org/10.1155/2019/3720450.

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Most supercomputers are shipped with both a CPU and a GPU. With the powerful parallel computing capability of GPUs, heterogeneous computing architecture produces new challenges for system software development and application design. Because of the significantly different architectures and programming models of CPUs and GPUs, conventional optimization techniques for CPUs may not work well in a heterogeneous multi-CPU and multi-GPU system. We present a heterogeneous parallel LU factorization algorithm for heterogeneous architectures. According to the different performances of the processors in the system, any given matrix is partitioned into different sizes of basic column blocks. Then, a static task allocation strategy is used to distribute the basic column blocks to corresponding processors uniformly. The idle time is minimized by optimized sizes and the number of basic column blocks. Right-looking ahead technology is also used in systems configured with one CPU core to one GPU to decrease the wait time. Experiments are conducted to test the performance of synchronization and load balancing, communication cost, and scalability of the heterogeneous parallel LU factorization in different systems and compare it with the related matrix algebra algorithm on a heterogeneous system configured with multiple GPUs and CPUs.
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Dongarra, Jack, Mark Gates, Azzam Haidar, Yulu Jia, Khairul Kabir, Piotr Luszczek, and Stanimire Tomov. "HPC Programming on Intel Many-Integrated-Core Hardware with MAGMA Port to Xeon Phi." Scientific Programming 2015 (2015): 1–11. http://dx.doi.org/10.1155/2015/502593.

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This paper presents the design and implementation of several fundamental dense linear algebra (DLA) algorithms for multicore with Intel Xeon Phi coprocessors. In particular, we consider algorithms for solving linear systems. Further, we give an overview of the MAGMA MIC library, an open source, high performance library, that incorporates the developments presented here and, more broadly, provides the DLA functionality equivalent to that of the popular LAPACK library while targeting heterogeneous architectures that feature a mix of multicore CPUs and coprocessors. The LAPACK-compliance simplifies the use of the MAGMA MIC library in applications, while providing them with portably performant DLA. High performance is obtained through the use of the high-performance BLAS, hardware-specific tuning, and a hybridization methodology whereby we split the algorithm into computational tasks of various granularities. Execution of those tasks is properly scheduled over the heterogeneous hardware by minimizing data movements and mapping algorithmic requirements to the architectural strengths of the various heterogeneous hardware components. Our methodology and programming techniques are incorporated into the MAGMA MIC API, which abstracts the application developer from the specifics of the Xeon Phi architecture and is therefore applicable to algorithms beyond the scope of DLA.
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Wan, Neng, Ke Du, Rong Mo, and Gongnan Xie. "A “Model to Model” Collaborative Perception Methodology for Distributed Design." Advances in Mechanical Engineering 6 (January 1, 2014): 520672. http://dx.doi.org/10.1155/2014/520672.

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To solve the problem of collaborative engineering changes of models distributed in heterogeneous design platforms, a “model to model” perception methodology is proposed in this paper. A self-management collaborative architecture is presented by peer to peer architecture and multiagent system. The network addresses correlation between heterogeneous platforms is built up by the perception router ontology. In the same way, the correlation between design models is described by the feature relation ontology. The design changes are encapsulated by the model modification ontology. Along with the ontology above, the design change search method is devised to catch the geometric changes; the influence search method is proposed to discover the influenced design feature and the design change adapting method is used to preserve the correlation coherence after perception. Through the work, the conventional design perception mode among designers has transformed into direct perception among models instead.
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Hartono, Ludy, and Imam Faisal Pane. "PENELUSURAN ARSITEKTUR INDIS PADA STASIUN KERETA API BINJAI." Jurnal Koridor 8, no. 1 (January 11, 2017): 37–45. http://dx.doi.org/10.32734/koridor.v8i1.1321.

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The colonial’s architecture was spread in cities in Indonesia. It was influenced by the modern architecture that was emerging in Europe. For the time being, acculturation happened between the Dutch and the heterogeneous Indonesian. Its design adapted with the local condition and climate. Mostly, it is called by Indis Architecture. It was the result of the culture and lifestyle which was begun since the Dutch colony. As for example, Binjai Railway Station, which was established in 1887. This adapted two different culture, the Dutch and the Malays. This research describes Indis architecture in Binjai Railway Station by qualitative methods and descriptive approach. Data will be taken by observing form and architectural element of the building. As of it, Binjai Railway Staion adapted two different cultures which resulted in a new culture, Indis architecture.
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Sherazi, Hafiz Husnain Raza, Zuhaib Ashfaq Khan, Razi Iqbal, Shahzad Rizwan, Muhammad Ali Imran, and Khalid Awan. "A Heterogeneous IoV Architecture for Data Forwarding in Vehicle to Infrastructure Communication." Mobile Information Systems 2019 (February 3, 2019): 1–12. http://dx.doi.org/10.1155/2019/3101276.

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The Internet of vehicles (IoV) is a newly emerged wave that converges Internet of things (IoT) into vehicular networks to benefit from ubiquitous Internet connectivity. Despite various research efforts, vehicular networks are still striving to achieve higher data rate, seamless connectivity, scalability, security, and improved quality of service, which are the key enablers for IoV. It becomes even more critical to investigate novel design architectures to accomplish efficient and reliable data forwarding when it comes to handling the emergency communication infrastructure in the presence of natural epidemics. The article proposes a heterogeneous network architecture incorporating multiple wireless interfaces (e.g., wireless access in vehicular environment (WAVE), long-range wireless fidelity (WiFi), and fourth generation/long-term evolution (4G/LTE)) installed on the on-board units, exploiting the radio over fiber approach to establish a context-aware network connectivity. This heterogeneous network architecture attempts to meet the requirements of pervasive connectivity for vehicular ad hoc networks (VANETs) to make them scalable and adaptable for IoV supporting a range of emergency services. The architecture employs the Best Interface Selection (BIS) algorithm to always ensure reliable communication through the best available wireless interface to support seamless connectivity required for efficient data forwarding in vehicle to infrastructure (V2I) communication successfully avoiding the single point of failure. Moreover, the simulation results clearly argue about the suitability of the proposed architecture in IoV environment coping with different types of applications against individual wireless technologies.
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Manzano, Wallace, Valdemar Vicente Graciano Neto, and Elisa Yumi Nakagawa. "Dynamic-SoS: An Approach for the Simulation of Systems-of-Systems Dynamic Architectures." Computer Journal 63, no. 5 (April 12, 2019): 709–31. http://dx.doi.org/10.1093/comjnl/bxz028.

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Abstract Systems-of-Systems (SoS) combine heterogeneous, independent systems to offer complex functionalities for highly dynamic smart applications. Besides their dynamic architecture with continuous changes at runtime, SoS should be reliable and work without interrupting their operation and with no failures that could cause accidents or losses. SoS architectural design should facilitate the prediction of the impact of architectural changes and potential failures due to SoS behavior. However, existing approaches do not support such evaluation. Hence, these systems have been usually built without a proper evaluation of their architecture. This article presents Dynamic-SoS, an approach to predict/anticipate at design time the SoS architectural behavior at runtime to evaluate whether the SoS can sustain their operation. The main contributions of this approach comprise: (i) characterization of the dynamic architecture changes via a set of well-defined operators; (ii) a strategy to automatically include a reconfiguration controller for SoS simulation; and (iii) a means to evaluate architectural configurations that an SoS could assume at runtime, assessing their impact on the viability of the SoS operation. Results of our case study reveal Dynamic-SoS is a promising approach that could contribute to the quality of SoS by enabling prior assessment of its dynamic architecture.
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Arka, Aqeeb Iqbal, Biresh Kumar Joardar, Ryan Gary Kim, Dae Hyun Kim, Janardhan Rao Doppa, and Partha Pratim Pande. "HeM3D." ACM Transactions on Design Automation of Electronic Systems 26, no. 2 (February 2021): 1–21. http://dx.doi.org/10.1145/3424239.

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Heterogeneous manycore architectures are the key to efficiently execute compute- and data-intensive applications. Through-silicon-via (TSV)-based 3D manycore system is a promising solution in this direction as it enables the integration of disparate computing cores on a single system. Recent industry trends show the viability of 3D integration in real products (e.g., Intel Lakefield SoC Architecture, the AMD Radeon R9 Fury X graphics card, and Xilinx Virtex-7 2000T/H580T, etc.). However, the achievable performance of conventional TSV-based 3D systems is ultimately bottlenecked by the horizontal wires (wires in each planar die). Moreover, current TSV 3D architectures suffer from thermal limitations. Hence, TSV-based architectures do not realize the full potential of 3D integration. Monolithic 3D (M3D) integration, a breakthrough technology to achieve “More Moore and More Than Moore,” opens up the possibility of designing cores and associated network routers using multiple layers by utilizing monolithic inter-tier vias (MIVs) and hence, reducing the effective wire length. Compared to TSV-based 3D integrated circuits (ICs), M3D offers the “true” benefits of vertical dimension for system integration: the size of an MIV used in M3D is over 100 × smaller than a TSV. This dramatic reduction in via size and the resulting increase in density opens up numerous opportunities for design optimizations in 3D manycore systems: designers can use up to millions of MIVs for ultra-fine-grained 3D optimization, where individual cores and routers can be spread across multiple tiers for extreme power and performance optimization. In this work, we demonstrate how M3D-enabled vertical core and uncore elements offer significant performance and thermal improvements in manycore heterogeneous architectures compared to its TSV-based counterpart. To overcome the difficult optimization challenges due to the large design space and complex interactions among the heterogeneous components (CPU, GPU, Last Level Cache, etc.) in a M3D-based manycore chip, we leverage novel design-space exploration algorithms to trade off different objectives. The proposed M3D-enabled heterogeneous architecture, called HeM3D , outperforms its state-of-the-art TSV-equivalent counterpart by up to 18.3% in execution time while being up to 19°C cooler.
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Spagnolo, Fanny, Stefania Perri, Fabio Frustaci, and Pasquale Corsonello. "Energy-Efficient Architecture for CNNs Inference on Heterogeneous FPGA." Journal of Low Power Electronics and Applications 10, no. 1 (December 24, 2019): 1. http://dx.doi.org/10.3390/jlpea10010001.

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Due to the huge requirements in terms of both computational and memory capabilities, implementing energy-efficient and high-performance Convolutional Neural Networks (CNNs) by exploiting embedded systems still represents a major challenge for hardware designers. This paper presents the complete design of a heterogeneous embedded system realized by using a Field-Programmable Gate Array Systems-on-Chip (SoC) and suitable to accelerate the inference of Convolutional Neural Networks in power-constrained environments, such as those related to IoT applications. The proposed architecture is validated through its exploitation in large-scale CNNs on low-cost devices. The prototype realized on a Zynq XC7Z045 device achieves a power efficiency up to 135 Gops/W. When the VGG-16 model is inferred, a frame rate up to 11.8 fps is reached.
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Li, Qiang, Weijun Qin, Bing Han, Ruicong Wang, and Limin Sun. "A case study on REST-style architecture for cyber-physical systems: Restful smart gateway." Computer Science and Information Systems 8, no. 4 (2011): 1317–29. http://dx.doi.org/10.2298/csis110310062l.

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Due to several key factors, Cyber-physical systems (CPS) pose great challenges in software system design, which are dynamic composition, heterogeneous, adaptation and uncertain in environmental factors. In this paper we present our research on the development of REST-style architecture for CPS. We propose a path towards solving requirements of CPS architecture through Restful principles. By using this architectural style, we have built a prototyping system called the restful smart gateway, which seamlessly integrates conceptual and physical resources into the Web and scale better. Some experiments on the smart gateway are given to illustrate its performance.
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Hassan, Syed Rizwan, Ishtiaq Ahmad, Ateeq Ur Rehman, Seada Hussen, and Habib Hamam. "Design of Resource-Aware Load Allocation for Heterogeneous Fog Computing Environments." Wireless Communications and Mobile Computing 2022 (June 7, 2022): 1–11. http://dx.doi.org/10.1155/2022/3543640.

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The architecture employed by most of the researchers for the deployment of latency-sensitive Internet of Things (IoT) applications is fog computing. Fog computing architecture offers less delay as compared to the cloud computing paradigm by providing resource constraint fog devices close to the edge of the network. Fog nodes process the incoming data by utilizing available resources which reduces the volume of data to be sent to the cloud server. Fog devices having dissimilar processing capabilities are present in a system. The connection of suitable sensor nodes to the parent fog node plays an essential role in achieving the optimum performance of the system. In this paper, we have designed an algorithm that dynamically assigns appropriate sensor devices to fog nodes to achieve a reduction in network utilization and latency. The proposed algorithm estimates the volume of information detected by an edge device from the rate of sensing frequency of the sensor attached to the edge device. The proposed policy while connecting the network nodes takes into account the heterogeneity and processing capability of the devices. Several evaluations are performed on multiple scales for the evaluation of the proposed algorithm. The outcomes of the evaluations confirm the effectiveness of the proposed algorithm in achieving a reduction in network consumption and end-to-end delay.
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Bocciarelli, Paolo, and Andrea D’Ambrogio. "A TOSCA-Based Conceptual Architecture to Support the Federation of Heterogeneous MSaaS Infrastructure." Future Internet 15, no. 2 (January 26, 2023): 48. http://dx.doi.org/10.3390/fi15020048.

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Modeling and simulation (M&S) techniques are effectively used in many application domains to support various operational tasks ranging from system analyses to innovative training activities. Any (M&S) effort might strongly benefit from the adoption of service orientation and cloud computing to ease the development and provision of M&S applications. Such an emerging paradigm is commonly referred to as M&S-as-a-Service (MSaaS). The need for orchestrating M&S services provided by different partners in a heterogeneous cloud infrastructure introduces new challenges. In this respect, the adoption of an effective architectural approach might significantly help the design and development of MSaaS infrastructure implementations that cooperate in a federated environment. In this context, this work introduces a MSaaS reference architecture (RA) that aims to investigate innovative approaches to ease the building of inter-cloud MSaaS applications. Moreover, this work presents ArTIC-MS, a conceptual architecture that refines the proposed RA for introducing the TOSCA (topology and orchestration specification for cloud applications) standard. ArTIC-MS’s main objective is to enable effective portability and interoperability among M&S services provided by different partners in heterogeneous federations of cloud-based MSaaS infrastructure. To show the validity of the proposed architectural approach, the results of concrete experimentation are provided.
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Wang, Feng, Liang Hu, Jin Zhou, and Kuo Zhao. "A Data Processing Middleware Based on SOA for the Internet of Things." Journal of Sensors 2015 (2015): 1–8. http://dx.doi.org/10.1155/2015/827045.

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The Internet of Things (IoT) emphasizes on connecting every object around us by leveraging a variety of wireless communication technologies. Heterogeneous data fusion is widely considered to be a promising and urgent challenge in the data processing of the IoT. In this study, we first discuss the development of the concept of the IoT and give a detailed description of the architecture of the IoT. And then we design a middleware platform based on service-oriented architecture (SOA) for integration of multisource heterogeneous information. New research angle regarding flexible heterogeneous information fusion architecture for the IoT is the theme of this paper. Experiments using environmental monitoring sensor data derived from indoor environment are performed for system validation. Through the theoretical analysis and experimental verification, the data processing middleware architecture represents better adaptation to multisensor and multistream application scenarios in the IoT, which improves heterogeneous data utilization value. The data processing middleware based on SOA for the IoT establishes a solid foundation of integration and interaction for diverse networks data among heterogeneous systems in the future, which simplifies the complexity of integration process and improves reusability of components in the system.
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Absalom, Ezugwu E., Buhari M. Seyed, Obiniyi A. Afolayan, and Junaidu B. Sahalu. "A Generic Reference Architecture for Collaboratory Scientific Virtual Laboratory." International Journal of Grid and High Performance Computing 5, no. 1 (January 2013): 37–52. http://dx.doi.org/10.4018/jghpc.2013010103.

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The paper presents a generic reference architecture framework for collaboratory experiment virtual laboratory. The model presented is open source driven, flexible and based on modern tools and technologies. This in effect will allow geographically remote scientists with limited internal laboratory resources, access to wealth of experimental datasets, computing facilities, and distributed hard-to-duplicate laboratory devices. The key issues discussed are architectural design and choice of technology used for creating virtual laboratory. This architecture offers great levels of flexibility, simplicity, and interoperability that are needed to allow integration between heterogeneous distributed grid resources and its clients and executors. The framework, besides theoretical modelling, will provide a road map for future research and open questions.
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Hossain, Md Sanwar, Khondoker Ziaul Islam, Abdullah G. Alharbi, Md Shafiullah, Md Rabiul Islam, and Afef Fekih. "Optimal Design of a Hybrid Solar PV/BG-Powered Heterogeneous Network." Sustainability 14, no. 4 (February 15, 2022): 2201. http://dx.doi.org/10.3390/su14042201.

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The increased penetration of renewable energy sources (RESs) along with the rise in demand for wireless communication had led to the need to deploy cellular base stations powered by locally accessible RESs. Moreover, networks powered by renewable energy sources have the ability to reduce the costs of generating electricity, as well as greenhouse gas emissions, thus maintaining the quality of service (QoS). This paper examines the techno-economic feasibility of developing grid-tied solar photovoltaic (PV)/biomass generator (BG)-powered heterogeneous networks in Bangladesh, taking into account the dynamic characteristics of RESs and traffic. To guarantee QoS, each macro and micro-base station is supplied through a hybrid solar PV/BG coupled with enough energy storage devices. In contrast, pico and femto BSs are powered through standalone solar PV units due to their smaller power rating. A hybrid optimization model for electric renewables (HOMER)-based optimization algorithm is considered to determine the optimum system architecture, economic and environmental analysis. MATLAB-based Monte-Carlo simulations are used to assess the system’s throughput and energy efficiency. A new weighted proportional-fair resource method is presented by trading power consumption and communication latency in non-real-time applications. Performance analysis of the proposed architecture confirmed its energy efficiency, economic soundness, reliability, and environmental friendliness. Additionally, the suggested method was shown to increase the battery life of the end devices.
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N, Thenmozhi, and Padmaloshani P. "Design of a Real-Time Face Detection Architecture for Heterogeneous Systems-on-Chips." ESP Journal of Engineering & Technology Advancements 2, no. 3 (July 29, 2022): 24–27. http://dx.doi.org/10.56472/25832646/esp-v2i3p106.

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Spagnolo, Fanny, Stefania Perri, and Pasquale Corsonello. "Design of a real-time face detection architecture for heterogeneous systems-on-chips." Integration 74 (September 2020): 1–10. http://dx.doi.org/10.1016/j.vlsi.2020.04.008.

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Verma, Sandeep, Neetu Sood, and Ajay Kumar Sharma. "Design of a novel routing architecture for harsh environment monitoring in heterogeneous WSN." IET Wireless Sensor Systems 8, no. 6 (December 1, 2018): 284–94. http://dx.doi.org/10.1049/iet-wss.2018.5025.

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Perri, Stefania, Cristian Sestito, Fanny Spagnolo, and Pasquale Corsonello. "Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip." Journal of Imaging 6, no. 9 (August 25, 2020): 85. http://dx.doi.org/10.3390/jimaging6090085.

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Today, convolutional and deconvolutional neural network models are exceptionally popular thanks to the impressive accuracies they have been proven in several computer-vision applications. To speed up the overall tasks of these neural networks, purpose-designed accelerators are highly desirable. Unfortunately, the high computational complexity and the huge memory demand make the design of efficient hardware architectures, as well as their deployment in resource- and power-constrained embedded systems, still quite challenging. This paper presents a novel purpose-designed hardware accelerator to perform 2D deconvolutions. The proposed structure applies a hardware-oriented computational approach that overcomes the issues of traditional deconvolution methods, and it is suitable for being implemented within any virtually system-on-chip based on field-programmable gate array devices. In fact, the novel accelerator is simply scalable to comply with resources available within both high- and low-end devices by adequately scaling the adopted parallelism. As an example, when exploited to accelerate the Deep Convolutional Generative Adversarial Network model, the novel accelerator, running as a standalone unit implemented within the Xilinx Zynq XC7Z020 System-on-Chip (SoC) device, performs up to 72 GOPs. Moreover, it dissipates less than 500mW@200MHz and occupies 5.6%, 4.1%, 17%, and 96%, respectively, of the look-up tables, flip-flops, random access memory, and digital signal processors available on-chip. When accommodated within the same device, the whole embedded system equipped with the novel accelerator performs up to 54 GOPs and dissipates less than 1.8W@150MHz. Thanks to the increased parallelism exploitable, more than 900 GOPs can be executed when the high-end Virtex-7 XC7VX690T device is used as the implementation platform. Moreover, in comparison with state-of-the-art competitors implemented within the Zynq XC7Z045 device, the system proposed here reaches a computational capability up to 20% higher, and saves more than 60% and 80% of power consumption and logic resources requirement, respectively, using 5.7× fewer on-chip memory resources.
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