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Journal articles on the topic 'Heterogeneous Architecture Design'

Author: Grafiati

Published: 22 June 2023

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1

LIU, SHAOSHAN, WON W. RO, CHEN LIU, et al. "INTRODUCING THE EXTREMELY HETEROGENEOUS ARCHITECTURE." Journal of Interconnection Networks 13, no. 03n04 (2012): 1250010. http://dx.doi.org/10.1142/s0219265912500107.

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The computer industry is moving towards two extremes: extremely high-performance high-throughput cloud computing, and low-power mobile computing. Cloud computing, while providing high performance, is very costly. Google and Microsoft Bing spend billions of dollars each year to maintain their server farms, mainly due to the high power bills. On the other hand, mobile computing is under a very tight energy budget, but yet the end users demand ever increasing performance on these devices. This trend indicates that conventional architectures are not able to deliver high-performance and low power c

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Ahsan, AMM, Ruinan Xie, and Bashir Khoda. "Heterogeneous topology design and voxel-based bio-printing." Rapid Prototyping Journal 24, no. 7 (2018): 1142–54. http://dx.doi.org/10.1108/rpj-05-2017-0076.

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Purpose The purpose of this paper is to present a topology-based tissue scaffold design methodology to accurately represent the heterogeneous internal architecture of tissues/organs. Design/methodology/approach An image analysis technique is used that digitizes the topology information contained in medical images of tissues/organs. A weighted topology reconstruction algorithm is implemented to represent the heterogeneity with parametric functions. The parametric functions are then used to map the spatial material distribution following voxelization. The generated chronological information yiel

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Sek Meng Chai, T. M. Taha, D. S. Wills, and J. D. Meindl. "Heterogeneous architecture models for interconnect-motivated system design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8, no. 6 (2000): 660–70. http://dx.doi.org/10.1109/92.902260.

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Yang, Chungang, Jiandong Li, and Alagan Anpalagan. "Energy Efficiency Architecture Design for Heterogeneous Cellular Networks." Wireless Communications and Mobile Computing 16, no. 12 (2015): 1588–602. http://dx.doi.org/10.1002/wcm.2635.

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Kovalyov, S. P. "Design of Heterogeneous Cyber-Physical Systems Employing Category Theory." Mekhatronika, Avtomatizatsiya, Upravlenie 23, no. 2 (2022): 59–67. http://dx.doi.org/10.17587/mau.23.59-67.

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Heterogeneous cyber-physical control systems based on digital twins are in demand by Industry 4.0. In accordance with the contemporary systems engineering methodology, such systems are designed at the level of digital models. The paper proposes approaches to formalization and subsequent automation of solving direct and inverse problems of their design. To unify descriptions of heterogeneous components, we follow a viewpoint-based approach to architecture design recommended by the international standard ISO/IEC/IEEE 42010. Following recent trends, we employ category theory as a mathematical fra

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AGYEMAN, MICHAEL O., ALI AHMADINIA, and ALIREZA SHAHRABI. "HETEROGENEOUS 3D NETWORK-ON-CHIP ARCHITECTURES: AREA AND POWER AWARE DESIGN TECHNIQUES." Journal of Circuits, Systems and Computers 22, no. 04 (2013): 1350016. http://dx.doi.org/10.1142/s0218126613500163.

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Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip floorplan compared to a 2D router. Hence, more efficient architectures should be designed. In this paper, we propose area efficient and low power 3D heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers

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Pasha, Muhammad Adeel, Umer Farooq, and Bilal Siddiqui. "A framework for high-level simulation and optimization of fine-grained reconfigurable architectures." SIMULATION 95, no. 8 (2018): 737–51. http://dx.doi.org/10.1177/0037549718796272.

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Field Programmable Gate Arrays (FPGAs), due to their programmability, have become a popular design choice for control and processing blocks of modern-day digital design. However, this flexibility makes them larger, slower, and less power-efficient when compared to Application Specific Integrated Circuits (ASICs). On the other hand, ASICs have their own drawbacks, such as lack of programmability and inflexibility. One potential solution is specialized fine-grained reconfigurable architectures that have improved flexibility over ASICs and better resource utilization than FPGAs. However, designin

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Son, Hyun-Seung, Woo-Yeol Kim, and R. Young-Chul Kim. "MDA(Model Driven Architecture) based Design for Multitasking of Heterogeneous Embedded System." KIPS Transactions:PartD 15D, no. 3 (2008): 355–60. http://dx.doi.org/10.3745/kipstd.2008.15-d.3.355.

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He, Tao, Hua Zhong Li, Tang Ren Dan, De Fen Zhang, Jun Qiang Liu, and Guo Rong Qin. "Design and Analysis of Test Model under Heterogeneous and Internet-Ware." Applied Mechanics and Materials 687-691 (November 2014): 2635–39. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.2635.

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Studying a method based on UML model software architecture performance prediction: this method chosen software architecture design in UML, use case diagram, activity diagram and component diagram, and pull stereotypes and tagged values in it, and enlarge them to be UML SPT model, and then turn UML SPT model into queuing network model through conversion algorithm, this algorithm can deal with UML model activity diagram which included branch node and confluent nodes. Finally, using frequency domain analysis theory to get queuing network model, to know performance parameters and performance bottl

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Fang, Wei. "Design of Heterogeneous Data Exchange Technology for Teaching Resources Based on ICMPv6." International Journal of Emerging Technologies in Learning (iJET) 13, no. 11 (2018): 78. http://dx.doi.org/10.3991/ijet.v13i11.9600.

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To promote the innovation of teaching resources and heterogeneous data exchange platform technologies and theories, heterogeneous data exchange platforms based on ICMPv6 teaching resources were studied. First, based on ICMPv6, the middle-tier architecture of the heterogeneous data exchange platform for teaching resources was studied. Second, the application layer architecture in the heterogeneous data exchange platform system of educational resources was studied. The middle layer and application layer were designed and implemented. Finally, the system was applied to the education platform to r

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Fleischer, J., R. Häner, S. Herrnkind, et al. "An integration platform for heterogeneous sensor systems in GITEWS – Tsunami Service Bus." Natural Hazards and Earth System Sciences 10, no. 6 (2010): 1239–52. http://dx.doi.org/10.5194/nhess-10-1239-2010.

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Abstract. The German Indonesian Tsunami Early Warning System (GITEWS) is built upon a complex sensor data infrastructure. To best fulfill the demand for a long living system, the underlying software and hardware architecture of GITEWS must be prepared for future modifications both of single sensors and entire sensors systems. The foundation for a flexible integration and for stable interfaces is a result of following the paradigm of a Service Oriented Architecture (SOA). The Tsunami Service Bus (TSB) – our integration platform in GITEWS – realizes this SOA approach by implementing the Sensor W

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Vítku, Jaroslav, and Pavel Nahodil. "TOWARDS EVOLUTIONARY DESIGN OF COMPLEX SYSTEMS INSPIRED BY NATURE." Acta Polytechnica 54, no. 5 (2014): 367–77. http://dx.doi.org/10.14311/ap.2014.54.0367.

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This paper presents first steps towards evolutionary design of complex autonomous systems. The approach is inspired in modularity of human brain and principles of evolution. Rather than evolving neural networks or neural-based systems, the approach focuses on evolving hybrid networks composed of heterogeneous sub-systems implementing various algorithms/behaviors. Currently, the evolutionary techniques are used to optimize weights between predefined blocks (so called Neural Modules) in order to find an agent architecture appropriate for given task. The framework, together with the simulator of

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Payvar, Saman, Maxime Pelcat, and Timo D. Hämäläinen. "A model of architecture for estimating GPU processing performance and power." Design Automation for Embedded Systems 25, no. 1 (2021): 43–63. http://dx.doi.org/10.1007/s10617-020-09244-4.

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AbstractEfficient usage of heterogeneous computing architectures requires distribution of the workload on available processing elements. Traditionally, the mapping is based on information acquired from application profiling and utilized in architecture exploration. To reduce the amount of manual work required, statistical application modeling and architecture modeling can be combined with exploration heuristics. While the application modeling side of the problem has been studied extensively, architecture modeling has received less attention. Linear System Level Architecture (LSLA) is a Model o

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Mahmood, Adnan, Wei Zhang, and Quan Sheng. "Software-Defined Heterogeneous Vehicular Networking: The Architectural Design and Open Challenges." Future Internet 11, no. 3 (2019): 70. http://dx.doi.org/10.3390/fi11030070.

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The promising advancements in the telecommunications and automotive sectors over the years have empowered drivers with highly innovative communication and sensing capabilities, in turn paving the way for the next-generation connected and autonomous vehicles. Today, vehicles communicate wirelessly with other vehicles and vulnerable pedestrians in their immediate vicinity to share timely safety-critical information primarily for collision mitigation. Furthermore, vehicles connect with the traffic management entities via their supporting network infrastructure to become more aware of any potentia

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Garg, Siddharth, Shreyas Sundaram, and Hiren D. Patel. "Robust heterogeneous data center design." ACM SIGMETRICS Performance Evaluation Review 39, no. 3 (2011): 28–30. http://dx.doi.org/10.1145/2160803.2160850.

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Liu, Li Cheng, Lu Guo Hao, and Rui Hu. "The Design of the Signal Processing Architecture of a Wireless Relay in Heterogeneous Wireless Networks." Advanced Materials Research 403-408 (November 2011): 1728–31. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1728.

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Focusing on the wireless relay in heterogeneous wireless networks, a new signal processing architecture of a wireless relay has been proposed. And with an example of the heterogeneous wireless network consisted of GSM and CDMA systems, the detailed design is illustrated. The instance of the wireless relay demonstrates the feasibility of the proposed signal processing architecture.

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Roorda, Esther, Seyedramin Rasoulinezhad, Philip H. W. Leong, and Steven J. E. Wilton. "FPGA Architecture Exploration for DNN Acceleration." ACM Transactions on Reconfigurable Technology and Systems 15, no. 3 (2022): 1–37. http://dx.doi.org/10.1145/3503465.

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Recent years have seen an explosion of machine learning applications implemented on Field-Programmable Gate Arrays (FPGAs) . FPGA vendors and researchers have responded by updating their fabrics to more efficiently implement machine learning accelerators, including innovations such as enhanced Digital Signal Processing (DSP) blocks and hardened systolic arrays. Evaluating architectural proposals is difficult, however, due to the lack of publicly available benchmark circuits. This paper addresses this problem by presenting an open-source benchmark circuit generator that creates realistic DNN-or

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de Paulo, Vitor, and Cristinel Ababei. "3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans." International Journal of Reconfigurable Computing 2010 (2010): 1–12. http://dx.doi.org/10.1155/2010/603059.

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We propose new 3D 2-layer and 3-layer NoC architectures that utilizehomogeneousregular mesh networks on a separate layer and one or twoheterogeneousfloorplanning layers. These architectures combine the benefits of compact heterogeneous floorplans and of regular mesh networks. To demonstrate these benefits, a design methodology that integrates floorplanning, routers assignment, and cycle-accurate NoC simulation is proposed. The implementation of the NoC on a separate layer offers an additional area that may be utilized to improve the network performance by increasing the number of virtual chann

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Sun, Yao. "Construction of Artistic Design Patterns Based on Improved Distributed Data Parallel Computing of Heterogeneous Tasks." Mathematical Problems in Engineering 2022 (March 31, 2022): 1–11. http://dx.doi.org/10.1155/2022/3890255.

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With the continuous upgrading of hardware in the terminal equipment, how to provide high-performance computing for low-tech threshold users has become a current research hotspot. In the era of green high-performance computing, the heterogeneous computing system can provide good versatility, performance, and efficiency and has broad development prospects. This article provides an in-depth analysis and research on the construction and application of improved models using the artistic design pattern of heterogeneous tasks and parallel computing. Based on the hardware resources in the existing des

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Feldkaemper, H. T., H. Blume, and T. G. Noll. "Study of heterogeneous and reconfigurable architectures in the communication domain." Advances in Radio Science 1 (May 5, 2003): 165–69. http://dx.doi.org/10.5194/ars-1-165-2003.

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Abstract. One of the most challenging design issues for next generations of (mobile) communication systems is fulfilling the computational demands while finding an appropriate trade-off between flexibility and implementation aspects, especially power consumption. Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. Typical target architectures for future communication systems include embedded FPGAs, dedicated macros as well as programmable digital signal and control oriented processor cores as each of th

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Chromiak, Michal, and Marcin Grabowiecki. "Heterogeneous Data Integration Architecture-Challenging Integration Issues." Annales Universitatis Mariae Curie-Sklodowska, sectio AI – Informatica 15, no. 1 (2015): 7. http://dx.doi.org/10.17951/ai.2015.15.1.7-11.

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As of today, most of the data processing systems have to deal with a large amount of data originated from numerous sources. Data sources almost always differ regarding its purpose of existence. Thus model, data processing engine and technology differ intensely. Due to current trend for systems fusion there is a growing demand for data to be present in a common way regardless of its legacy. Many systems have been devised as a response to such integration needs. However, the present data integration systems mostly are dedicated solutions that bring constraints and issues when considered in gener

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Popovici, Katalin, Xavier Guerin, Frederic Rousseau, Pier Stanislao Paolucci, and Ahmed Amine Jerraya. "Platform-based software design flow for heterogeneous MPSoC." ACM Transactions on Embedded Computing Systems 7, no. 4 (2008): 1–23. http://dx.doi.org/10.1145/1376804.1376807.

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Saponara, Sergio, and Luca Fanucci. "Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing." VLSI Design 2012 (August 14, 2012): 1–17. http://dx.doi.org/10.1155/2012/450302.

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Two multiprocessor system-on-chip (MPSoC) architectures are proposed and compared in the paper with reference to audio and video processing applications. One architecture exploits a homogeneous topology; it consists of 8 identical tiles, each made of a 32-bit RISC core enhanced by a 64-bit DSP coprocessor with local memory. The other MPSoC architecture exploits a heterogeneous-tile topology with on-chip distributed memory resources; the tiles act as application specific processors supporting a different class of algorithms. In both architectures, the multiple tiles are interconnected by a netw

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Oxman, Neri. "Structuring Materiality: Design Fabrication of Heterogeneous Materials." Architectural Design 80, no. 4 (2010): 78–85. http://dx.doi.org/10.1002/ad.1110.

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KWAK, SANGHOON, JEONG-GUN LEE, EUN-GU JUNG, DONGSOO HAR, MILOS D. ERCEGOVAC, and JEONG-A. LEE. "EXPLORATION OF POWER-DELAY TRADE-OFFS WITH HETEROGENEOUS ADDERS BY INTEGER LINEAR PROGRAMMING." Journal of Circuits, Systems and Computers 18, no. 04 (2009): 787–800. http://dx.doi.org/10.1142/s0218126609005368.

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The performance of arithmetic adders varies widely in their power consumption, delay, and area requirements. To acquire more fine-grained trade-offs in the power-delay trade-off curve of a binary adder, the heterogeneous adder architecture is adopted. In heterogeneous adder architecture, a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and bit-widths. Thus the method allows us to expand the original design space of a specific type of adder into the more fine-grained design space by mixing that of each sub-adder. In this paper, a design for heterogeneo

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Van Craeynest, Kenzo, and Lieven Eeckhout. "Understanding fundamental design choices in single-ISA heterogeneous multicore architectures." ACM Transactions on Architecture and Code Optimization 9, no. 4 (2013): 1–23. http://dx.doi.org/10.1145/2400682.2400691.

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Lu, Yu, Jin Ying Wu, Hong Min Chen, Yong Pin Zheng, and Yun Ping Wu. "A Kind of Heterogeneous Data Synchronous Design for the Internet of Things." Advanced Materials Research 476-478 (February 2012): 1392–98. http://dx.doi.org/10.4028/www.scientific.net/amr.476-478.1392.

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The way of heterogeneous data synchronization based on WEB service mode used in the Internet of things is analyzed, the problem of synchronization mechanism of heterogeneous data based on internet web port is solved. Combined with the characteristics of SOA architecture, this paper proposes synchronization model WLDSS (Web-level Data Synchronization System) of distributed heterogeneous data, and gives the design principles and the key strategies of the model. Through the application of distributed solar water heating system of control system data synchronization, it verifies the stability of t

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Bouyamh, Charoenporn, and Chanankorn Jandaeng. "THE MIDDLEWARE ARCHITECTURE DESIGN FOR GATHERING THE HETEROGENEOUS DATA IN BIG DATA." Indian Journal of Computer Science and Engineering 12, no. 3 (2021): 701–8. http://dx.doi.org/10.21817/indjcse/2021/v12i3/211203172.

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JIANG, Jian-chun, Su-hua ZENG, and Ming CEN. "Architecture design of embedded operating system based on heterogeneous dual-core processor." Journal of Computer Applications 28, no. 10 (2009): 2686–89. http://dx.doi.org/10.3724/sp.j.1087.2008.02686.

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Shuai, Wen Ming, and Xiu Fen Fu. "A Method of Heterogeneous Data Integration Based on SOA." Applied Mechanics and Materials 536-537 (April 2014): 494–98. http://dx.doi.org/10.4028/www.scientific.net/amm.536-537.494.

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With the rapid development of information technology, the growth of heterogeneous Web data and the requirements of access to the Web of data also is growing. In view of this, a method of heterogeneous data integration based on SOA(Service-Oriented Architecture) is proposed. This method combines the technology of middleware and SOA design, using XML and Web services technologies, presents a framework of heterogeneous data integration based on SOA, and introduces the architecture of SOA data integration middleware. Experimental results show that this method reduces the coupling of heterogeneous

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Verkest, D., K. Van Rompaey, I. Bolsens, and H. De Man. "CoWare—A design environment for heterogeneous hardware/software systems." Design Automation for Embedded Systems 1, no. 4 (1996): 357–86. http://dx.doi.org/10.1007/bf00209910.

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Gongora, Andres, Javier Monroy, and Javier Gonzalez-Jimenez. "An Electronic Architecture for Multipurpose Artificial Noses." Journal of Sensors 2018 (2018): 1–9. http://dx.doi.org/10.1155/2018/5427693.

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This paper deals with the design of an electronic device aimed at the detection and characterization of volatile chemical substances, that is, an electronic nose (e-nose). We pursue the development of a versatile, multipurpose e-nose that can be employed for a wide variety of applications, can integrate heterogeneous sensing technologies, and can offer a mechanism to be customized for different requirements. To that end, we contribute with a fully configurable and decentralized e-nose architecture based on self-contained and intelligent sensor boards (i.e., modules). This design allows for the

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Wu, Rongteng, and Xiaohong Xie. "A Heterogeneous Parallel LU Factorization Algorithm Based on a Basic Column Block Uniform Allocation Strategy." Mathematical Problems in Engineering 2019 (February 25, 2019): 1–12. http://dx.doi.org/10.1155/2019/3720450.

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Most supercomputers are shipped with both a CPU and a GPU. With the powerful parallel computing capability of GPUs, heterogeneous computing architecture produces new challenges for system software development and application design. Because of the significantly different architectures and programming models of CPUs and GPUs, conventional optimization techniques for CPUs may not work well in a heterogeneous multi-CPU and multi-GPU system. We present a heterogeneous parallel LU factorization algorithm for heterogeneous architectures. According to the different performances of the processors in t

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Dongarra, Jack, Mark Gates, Azzam Haidar, et al. "HPC Programming on Intel Many-Integrated-Core Hardware with MAGMA Port to Xeon Phi." Scientific Programming 2015 (2015): 1–11. http://dx.doi.org/10.1155/2015/502593.

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This paper presents the design and implementation of several fundamental dense linear algebra (DLA) algorithms for multicore with Intel Xeon Phi coprocessors. In particular, we consider algorithms for solving linear systems. Further, we give an overview of the MAGMA MIC library, an open source, high performance library, that incorporates the developments presented here and, more broadly, provides the DLA functionality equivalent to that of the popular LAPACK library while targeting heterogeneous architectures that feature a mix of multicore CPUs and coprocessors. The LAPACK-compliance simplifi

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Wan, Neng, Ke Du, Rong Mo, and Gongnan Xie. "A “Model to Model” Collaborative Perception Methodology for Distributed Design." Advances in Mechanical Engineering 6 (January 1, 2014): 520672. http://dx.doi.org/10.1155/2014/520672.

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To solve the problem of collaborative engineering changes of models distributed in heterogeneous design platforms, a “model to model” perception methodology is proposed in this paper. A self-management collaborative architecture is presented by peer to peer architecture and multiagent system. The network addresses correlation between heterogeneous platforms is built up by the perception router ontology. In the same way, the correlation between design models is described by the feature relation ontology. The design changes are encapsulated by the model modification ontology. Along with the onto

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Hartono, Ludy, and Imam Faisal Pane. "PENELUSURAN ARSITEKTUR INDIS PADA STASIUN KERETA API BINJAI." Jurnal Koridor 8, no. 1 (2017): 37–45. http://dx.doi.org/10.32734/koridor.v8i1.1321.

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The colonial’s architecture was spread in cities in Indonesia. It was influenced by the modern architecture that was emerging in Europe. For the time being, acculturation happened between the Dutch and the heterogeneous Indonesian. Its design adapted with the local condition and climate. Mostly, it is called by Indis Architecture. It was the result of the culture and lifestyle which was begun since the Dutch colony. As for example, Binjai Railway Station, which was established in 1887. This adapted two different culture, the Dutch and the Malays. This research describes Indis architecture in B

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Sherazi, Hafiz Husnain Raza, Zuhaib Ashfaq Khan, Razi Iqbal, Shahzad Rizwan, Muhammad Ali Imran, and Khalid Awan. "A Heterogeneous IoV Architecture for Data Forwarding in Vehicle to Infrastructure Communication." Mobile Information Systems 2019 (February 3, 2019): 1–12. http://dx.doi.org/10.1155/2019/3101276.

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The Internet of vehicles (IoV) is a newly emerged wave that converges Internet of things (IoT) into vehicular networks to benefit from ubiquitous Internet connectivity. Despite various research efforts, vehicular networks are still striving to achieve higher data rate, seamless connectivity, scalability, security, and improved quality of service, which are the key enablers for IoV. It becomes even more critical to investigate novel design architectures to accomplish efficient and reliable data forwarding when it comes to handling the emergency communication infrastructure in the presence of na

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Manzano, Wallace, Valdemar Vicente Graciano Neto, and Elisa Yumi Nakagawa. "Dynamic-SoS: An Approach for the Simulation of Systems-of-Systems Dynamic Architectures." Computer Journal 63, no. 5 (2019): 709–31. http://dx.doi.org/10.1093/comjnl/bxz028.

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Abstract Systems-of-Systems (SoS) combine heterogeneous, independent systems to offer complex functionalities for highly dynamic smart applications. Besides their dynamic architecture with continuous changes at runtime, SoS should be reliable and work without interrupting their operation and with no failures that could cause accidents or losses. SoS architectural design should facilitate the prediction of the impact of architectural changes and potential failures due to SoS behavior. However, existing approaches do not support such evaluation. Hence, these systems have been usually built witho

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Arka, Aqeeb Iqbal, Biresh Kumar Joardar, Ryan Gary Kim, Dae Hyun Kim, Janardhan Rao Doppa, and Partha Pratim Pande. "HeM3D." ACM Transactions on Design Automation of Electronic Systems 26, no. 2 (2021): 1–21. http://dx.doi.org/10.1145/3424239.

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Heterogeneous manycore architectures are the key to efficiently execute compute- and data-intensive applications. Through-silicon-via (TSV)-based 3D manycore system is a promising solution in this direction as it enables the integration of disparate computing cores on a single system. Recent industry trends show the viability of 3D integration in real products (e.g., Intel Lakefield SoC Architecture, the AMD Radeon R9 Fury X graphics card, and Xilinx Virtex-7 2000T/H580T, etc.). However, the achievable performance of conventional TSV-based 3D systems is ultimately bottlenecked by the horizonta

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Spagnolo, Fanny, Stefania Perri, Fabio Frustaci, and Pasquale Corsonello. "Energy-Efficient Architecture for CNNs Inference on Heterogeneous FPGA." Journal of Low Power Electronics and Applications 10, no. 1 (2019): 1. http://dx.doi.org/10.3390/jlpea10010001.

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Due to the huge requirements in terms of both computational and memory capabilities, implementing energy-efficient and high-performance Convolutional Neural Networks (CNNs) by exploiting embedded systems still represents a major challenge for hardware designers. This paper presents the complete design of a heterogeneous embedded system realized by using a Field-Programmable Gate Array Systems-on-Chip (SoC) and suitable to accelerate the inference of Convolutional Neural Networks in power-constrained environments, such as those related to IoT applications. The proposed architecture is validated

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Li, Qiang, Weijun Qin, Bing Han, Ruicong Wang, and Limin Sun. "A case study on REST-style architecture for cyber-physical systems: Restful smart gateway." Computer Science and Information Systems 8, no. 4 (2011): 1317–29. http://dx.doi.org/10.2298/csis110310062l.

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Due to several key factors, Cyber-physical systems (CPS) pose great challenges in software system design, which are dynamic composition, heterogeneous, adaptation and uncertain in environmental factors. In this paper we present our research on the development of REST-style architecture for CPS. We propose a path towards solving requirements of CPS architecture through Restful principles. By using this architectural style, we have built a prototyping system called the restful smart gateway, which seamlessly integrates conceptual and physical resources into the Web and scale better. Some experim

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Hassan, Syed Rizwan, Ishtiaq Ahmad, Ateeq Ur Rehman, Seada Hussen, and Habib Hamam. "Design of Resource-Aware Load Allocation for Heterogeneous Fog Computing Environments." Wireless Communications and Mobile Computing 2022 (June 7, 2022): 1–11. http://dx.doi.org/10.1155/2022/3543640.

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The architecture employed by most of the researchers for the deployment of latency-sensitive Internet of Things (IoT) applications is fog computing. Fog computing architecture offers less delay as compared to the cloud computing paradigm by providing resource constraint fog devices close to the edge of the network. Fog nodes process the incoming data by utilizing available resources which reduces the volume of data to be sent to the cloud server. Fog devices having dissimilar processing capabilities are present in a system. The connection of suitable sensor nodes to the parent fog node plays a

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Bocciarelli, Paolo, and Andrea D’Ambrogio. "A TOSCA-Based Conceptual Architecture to Support the Federation of Heterogeneous MSaaS Infrastructure." Future Internet 15, no. 2 (2023): 48. http://dx.doi.org/10.3390/fi15020048.

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Modeling and simulation (M&S) techniques are effectively used in many application domains to support various operational tasks ranging from system analyses to innovative training activities. Any (M&S) effort might strongly benefit from the adoption of service orientation and cloud computing to ease the development and provision of M&S applications. Such an emerging paradigm is commonly referred to as M&S-as-a-Service (MSaaS). The need for orchestrating M&S services provided by different partners in a heterogeneous cloud infrastructure introduces new challenges. In this resp

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Wang, Feng, Liang Hu, Jin Zhou, and Kuo Zhao. "A Data Processing Middleware Based on SOA for the Internet of Things." Journal of Sensors 2015 (2015): 1–8. http://dx.doi.org/10.1155/2015/827045.

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The Internet of Things (IoT) emphasizes on connecting every object around us by leveraging a variety of wireless communication technologies. Heterogeneous data fusion is widely considered to be a promising and urgent challenge in the data processing of the IoT. In this study, we first discuss the development of the concept of the IoT and give a detailed description of the architecture of the IoT. And then we design a middleware platform based on service-oriented architecture (SOA) for integration of multisource heterogeneous information. New research angle regarding flexible heterogeneous info

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Absalom, Ezugwu E., Buhari M. Seyed, Obiniyi A. Afolayan, and Junaidu B. Sahalu. "A Generic Reference Architecture for Collaboratory Scientific Virtual Laboratory." International Journal of Grid and High Performance Computing 5, no. 1 (2013): 37–52. http://dx.doi.org/10.4018/jghpc.2013010103.

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The paper presents a generic reference architecture framework for collaboratory experiment virtual laboratory. The model presented is open source driven, flexible and based on modern tools and technologies. This in effect will allow geographically remote scientists with limited internal laboratory resources, access to wealth of experimental datasets, computing facilities, and distributed hard-to-duplicate laboratory devices. The key issues discussed are architectural design and choice of technology used for creating virtual laboratory. This architecture offers great levels of flexibility, simp

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Hossain, Md Sanwar, Khondoker Ziaul Islam, Abdullah G. Alharbi, Md Shafiullah, Md Rabiul Islam, and Afef Fekih. "Optimal Design of a Hybrid Solar PV/BG-Powered Heterogeneous Network." Sustainability 14, no. 4 (2022): 2201. http://dx.doi.org/10.3390/su14042201.

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The increased penetration of renewable energy sources (RESs) along with the rise in demand for wireless communication had led to the need to deploy cellular base stations powered by locally accessible RESs. Moreover, networks powered by renewable energy sources have the ability to reduce the costs of generating electricity, as well as greenhouse gas emissions, thus maintaining the quality of service (QoS). This paper examines the techno-economic feasibility of developing grid-tied solar photovoltaic (PV)/biomass generator (BG)-powered heterogeneous networks in Bangladesh, taking into account t

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N, Thenmozhi, and Padmaloshani P. "Design of a Real-Time Face Detection Architecture for Heterogeneous Systems-on-Chips." ESP Journal of Engineering & Technology Advancements 2, no. 3 (2022): 24–27. http://dx.doi.org/10.56472/25832646/esp-v2i3p106.

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Spagnolo, Fanny, Stefania Perri, and Pasquale Corsonello. "Design of a real-time face detection architecture for heterogeneous systems-on-chips." Integration 74 (September 2020): 1–10. http://dx.doi.org/10.1016/j.vlsi.2020.04.008.

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Verma, Sandeep, Neetu Sood, and Ajay Kumar Sharma. "Design of a novel routing architecture for harsh environment monitoring in heterogeneous WSN." IET Wireless Sensor Systems 8, no. 6 (2018): 284–94. http://dx.doi.org/10.1049/iet-wss.2018.5025.

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Perri, Stefania, Cristian Sestito, Fanny Spagnolo, and Pasquale Corsonello. "Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip." Journal of Imaging 6, no. 9 (2020): 85. http://dx.doi.org/10.3390/jimaging6090085.

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Today, convolutional and deconvolutional neural network models are exceptionally popular thanks to the impressive accuracies they have been proven in several computer-vision applications. To speed up the overall tasks of these neural networks, purpose-designed accelerators are highly desirable. Unfortunately, the high computational complexity and the huge memory demand make the design of efficient hardware architectures, as well as their deployment in resource- and power-constrained embedded systems, still quite challenging. This paper presents a novel purpose-designed hardware accelerator to

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