Dissertations / Theses on the topic 'Hardware'
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1
Chilingirian, Berj Krikor. "Hashing hardware : identifying hardware during boot-time system verification." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/112837.
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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 85-90).
Modern systems measure the software loaded at boot-time to ensure the machine starts in a trusted state. Such measurements, however, do not include any information about the underlying hardware of the machine. Recent DRAM-based attacks and the growing complexity of the supply chain attest to the importance of measuring hardware at boot. In this thesis, we propose a technique for designing measurement schemes for hardware components. We then apply this technique to designing and implementing a hardware measurement scheme for DRAM on a real system without hardware modifications. Finally, we evaluate our DRAM hardware measurement scheme and demonstrate that it achieves 89% accuracy in mapping a DRAM measurement to the manufacturing process from which that DRAM was produced.
by Berj Krikor Chilingirian.
M. Eng.
2
Figueiredo, Boneti Carlos Santieri de. "Exploring coordinated software and hardware support for hardware resource allocation." Doctoral thesis, Universitat Politècnica de Catalunya, 2009. http://hdl.handle.net/10803/6018.
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Multithreaded processors are now common in the industry as they offer high performance at a low cost. Traditionally, in such processors, the assignation of hardware resources between the multiple threads is done implicitly, by the hardware policies. However, a new class of multithreaded hardware allows the explicit allocation of resources to be controlled or biased by the software. Currently, there is little or no coordination between the allocation of resources done by the hardware and the prioritization of tasks done by the software.This thesis targets to narrow the gap between the software and the hardware, with respect to the hardware resource allocation, by proposing a new explicit resource allocation hardware mechanism and novel schedulers that use the currently available hardware resource allocation mechanisms.
It approaches the problem in two different types of computing systems: on the high performance computing domain, we characterize the first processor to present a mechanism that allows the software to bias the allocation hardware resources, the IBM POWER5. In addition, we propose the use of hardware resource allocation as a way to balance high performance computing applications. Finally, we propose two new scheduling mechanisms that are able to transparently and successfully balance applications in real systems using the hardware resource allocation. On the soft real-time domain, we propose a hardware extension to the existing explicit resource allocation hardware and, in addition, two software schedulers that use the explicit allocation hardware to improve the schedulability of tasks in a soft real-time system.
In this thesis, we demonstrate that system performance improves by making the software aware of the mechanisms to control the amount of resources given to each running thread. In particular, for the high performance computing domain, we show that it is possible to decrease the execution time of MPI applications biasing the hardware resource assignation between threads. In addition, we show that it is possible to decrease the number of missed deadlines when scheduling tasks in a soft real-time SMT system.
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Desai, Avinash R. "Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation." Thesis, Virginia Tech, 2013. http://hdl.handle.net/10919/23756.
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Tampering and Reverse Engineering of a chip to extract the hardware Intellectual Property
(IP) core or to inject malicious alterations is a major concern. First, offshore chip manufac-
turing allows the design secrets of the IP cores to be transparent to the foundry and other
entities along the production chain. Second, small malicious modifications to the design
may not be detectable after fabrication without anti-tamper mechanisms. Counterfeit Inte-
grated Circuits (ICs) also have become an important security issue in recent years, in which
counterfeit ICs that perform incorrectly or sub-par to the expected can lead to catastrophic
consequences in safety and/or mission-critical applications, in addition to the tremendous
economic toll they incur to the semiconductor industry. Some techniques have been devel-
oped in the past to improve the defense against such attacks but they tend to fall prey to
the increasing power of the attacker. We present a new way to protect against tampering
by a clever obfuscation of the design, which can be unlocked with a specific, dynamic path
traversal. Hence, the functional mode of the controller is hidden with the help of obfuscated
states, and the functional mode is made operational only on the formation of a specific
interlocked Code-Word during state transition. A novel time-stamp is proposed that can
provide the date at which the IC was manufactured for counterfeit detection. Furthermore,
we propose a second layer of tamper resistance to the time-stamp circuit to make it even
more difficult to modify. Results show that methods proposed offer higher levels of security
with small area overhead. A side benefit is that any small alteration will be magnified via
the obfuscated design proposed in these methods.Master of Science
4
Acosta, Roberto S. M. Massachusetts Institute of Technology. "Open source hardware." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/55201.
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Thesis (S.M.)--Massachusetts Institute of Technology, System Design and Management Program, 2009.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 82-83).
Open source software development models have created some of the most innovative tools and companies in the industry today modifying the way value is created and businesses developed. The purpose of this thesis is to analyze open source hardware in its current state and its potential impact at several stages of the value chain. Existing examples of open source hardware at different stages of the value chain are analyzed in terms of their innovation and potential impact to existing players in the value chain. An Ethernet framer is develop through the use of traditional development and benchmarked against a design developed based on open source hardware cores. The research concludes with an examination of business models established around open source hardware.
by Roberto Acosta.
S.M.
5
Lamy, M. F., and D. H. Ellis. "CAIS AIRBORNE HARDWARE." International Foundation for Telemetering, 1992. http://hdl.handle.net/10150/608890.
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International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, CaliforniaThe Common Airborne Instrumentation System (CAIS) is designed as a general purpose system for flight test applications into the next century. The system has an open architecture which readily permits the addition of new equipment as the need arises. This paper describes the current complement of airborne hardware as well as the approach to the design of the open architecture. This paper is presented as a companion to the CAIS overview prepared for this conference.
6
Martínez, Miguel, and Berral Miguel Gámez. "OPEN HARDWARE AGV." Thesis, Högskolan i Skövde, Institutionen för ingenjörsvetenskap, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:his:diva-20010.
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The versatility of open source technologies could grant them an intriguing place in the industry. Moreparticularly, an open source hardware automated guided vehicle (AGV) might show up as an idealsolution for low-scale logistic process, as well as a useful development and didactic tool. What is more,a modular vehicle with interchangeable components would comply even better with this philosophy.Hereafter, besides from a literature review including research related to the many subjects that thisproject attempts to orchestrate, an open source hardware methodology has been followed, acomparison analysis of each component and structure performed and configurations of possible AGVsselected, in order to shed light on the viability of conducting this sort of project in reality. Plus, a modularframe has been designed and tested with computer-aided and simulation tools. The conclusions showthat constructing an open source-based industrial vehicle is to a high extent feasible, although theprecise economic outcomes are not clear and building a real model is a future requisite to give evidence.There are other digital material (eg. film, imgage or audio files) or models/artifacts that belongs to the thesis and need to be archived.
7
Vlach, Jiří. "Zabezpečovací ústředna - hardware." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218368.
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This work deals with the design and realization of a modular security central unit's hardware positioned in familial houses. As an operating component of the central unit is used Module Rabbit 3365 with an integrated Ethernet interface. Based on user's requirements and general requirements for electronic security system, circuit diagrams of the central unit's motherboard and power supply with a function of backup power supply are designed. The work also includes layout of a keyboard and LCD display. Printed circuit boards are designed, produced and assembled. The device is set to work. The last part concerns programming of the module Rabbit 3365 in Dynamic C. Gradually, set of operating functions for individual components of the security central unit are implemented.
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Lee, Justin Alexander. "Morphogenetic evolvable hardware." Thesis, Queensland University of Technology, 2006. https://eprints.qut.edu.au/16231/1/Justin_Lee_Thesis.pdf.
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Evolvable hardware (EHW) uses simulated evolution to generate an electronic circuit with specific characteristics, and is generally implemented on Field Programmable Gate Arrays (FPGAs). EHW has proven to be successful at producing small novel circuits for applications such as robot control and image processing, however, traditional approaches, in which the FPGA configuration is directly encoded on the chromosome, have not scaled well with increases in problem and FPGA architecture complexity. One of the methods proposed to overcome this is the incorporation of a growth process, known as morphogenesis, into the evolutionary process. However, existing approaches have tended to abstract away the underlying architectural details, either to present a simpler virtual FPGA architecture, or a biochemical model that hides the relationship between the cellular state and the underlying hardware. By abstracting away the underlying architectural details, EHW has moved away from one of its key strengths, that being to allow evolution to discover novel solutions free of designer bias. Also, by separating the biological model from the target FPGA architecture, too many assumptions and arbitrary decisions need to be made, which are liable to lead to the growth process failing to produce the desired results. In this thesis a new approach to applying morphogenesis to gate-level FPGA- based EHW is presented, whereby circuit growth is closely tied to the underlying gate-level architecture, with circuit growth being driven largely by the state of gate-level resources of the FPGA. An investigation into the applicability of biological processes, structures and mechanisms to morphogenetic EHW (MGEHW) is conducted, and the resulting design elaborated. The developed MGEHW system is applied to solving a signal routing problem with irregular and severe constraints on routing resources. It is shown that the morphogenetic approach outperforms a traditional EHW approach using a direct encoding, and importantly, is able to scale to larger, more complex, signal routing problems without any significant increase in the number of generations required to find an optimal solution. With the success of the MGEHW system in solving primarily structural prob- lems, it is then applied to solving a combinatorial function problem, specifically a one-bit full adder, with a more complete set of FPGA resources. The results of these experiments, together with the previous experiments, has provided valuable information that when analysed has enabled the identification of the critical factors that determine the likelihood of an EHW problem being solvable. In particular this has highlighted the importance of effective fitness feedback for guiding evolution towards its desired goal. Results indicate that the gate-level morphogenetic approach is promising. The research presented here is far from complete; many avenues for future research have opened. The MGEHW system that has been developed allows further research in this area to be explored experimentally. Some of the most fruitful directions for future research are described.
9
Lee, Justin Alexander. "Morphogenetic evolvable hardware." Queensland University of Technology, 2006. http://eprints.qut.edu.au/16231/.
Full textAbstract:
Evolvable hardware (EHW) uses simulated evolution to generate an electronic circuit with specific characteristics, and is generally implemented on Field Programmable Gate Arrays (FPGAs). EHW has proven to be successful at producing small novel circuits for applications such as robot control and image processing, however, traditional approaches, in which the FPGA configuration is directly encoded on the chromosome, have not scaled well with increases in problem and FPGA architecture complexity. One of the methods proposed to overcome this is the incorporation of a growth process, known as morphogenesis, into the evolutionary process. However, existing approaches have tended to abstract away the underlying architectural details, either to present a simpler virtual FPGA architecture, or a biochemical model that hides the relationship between the cellular state and the underlying hardware. By abstracting away the underlying architectural details, EHW has moved away from one of its key strengths, that being to allow evolution to discover novel solutions free of designer bias. Also, by separating the biological model from the target FPGA architecture, too many assumptions and arbitrary decisions need to be made, which are liable to lead to the growth process failing to produce the desired results. In this thesis a new approach to applying morphogenesis to gate-level FPGA- based EHW is presented, whereby circuit growth is closely tied to the underlying gate-level architecture, with circuit growth being driven largely by the state of gate-level resources of the FPGA. An investigation into the applicability of biological processes, structures and mechanisms to morphogenetic EHW (MGEHW) is conducted, and the resulting design elaborated. The developed MGEHW system is applied to solving a signal routing problem with irregular and severe constraints on routing resources. It is shown that the morphogenetic approach outperforms a traditional EHW approach using a direct encoding, and importantly, is able to scale to larger, more complex, signal routing problems without any significant increase in the number of generations required to find an optimal solution. With the success of the MGEHW system in solving primarily structural prob- lems, it is then applied to solving a combinatorial function problem, specifically a one-bit full adder, with a more complete set of FPGA resources. The results of these experiments, together with the previous experiments, has provided valuable information that when analysed has enabled the identification of the critical factors that determine the likelihood of an EHW problem being solvable. In particular this has highlighted the importance of effective fitness feedback for guiding evolution towards its desired goal. Results indicate that the gate-level morphogenetic approach is promising. The research presented here is far from complete; many avenues for future research have opened. The MGEHW system that has been developed allows further research in this area to be explored experimentally. Some of the most fruitful directions for future research are described.
10
Nagaonkar, Yajuvendra. "FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1294.pdf.
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Lüthi, Martin. "Electronic Commerce im IT-Hardware-Markt : ausgeführt anhand zweier Fallbeispiele aus dem Computer-Hardware- und dem Data-Communication-Hardware-Markt /." [S.l.] : [s.n.], 1999. http://www.ub.unibe.ch/content/bibliotheken_sammlungen/sondersammlungen/dissen_bestellformular/index_ger.html.
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Heik, Andreas. "Open Hardware - AVR Mikrocontroller." Universitätsbibliothek Chemnitz, 2008. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-200800266.
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Mikrocontroller erfreuen sich großer Beliebtheit in
Elektronik-Bastelprojekte. Unzählige Anschlüsse und
Features wie Timer, Counter, AD-Wandler, ...
erlauben die Umsetzung komplexer Projekte.
Doch wie erfolgt die Programmierung?
Der Vortrag gibt einen einführenden Überblick zu
AVR Mikrokontrollern, Programmierwerkzeugen und deren
Anwendung anhand von Beispielen.
13
Kuvaiskii, Dmitrii. "Hardware-Assisted Dependable Systems." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2018. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-234205.
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Unpredictable hardware faults and software bugs lead to application crashes, incorrect computations, unavailability of internet services, data losses, malfunctioning components, and consequently financial losses or even death of people. In particular, faults in microprocessors (CPUs) and memory corruption bugs are among the major unresolved issues of today. CPU faults may result in benign crashes and, more problematically, in silent data corruptions that can lead to catastrophic consequences, silently propagating from component to component and finally shutting down the whole system. Similarly, memory corruption bugs (memory-safety vulnerabilities) may result in a benign application crash but may also be exploited by a malicious hacker to gain control over the system or leak confidential data.
Both these classes of errors are notoriously hard to detect and tolerate. Usual mitigation strategy is to apply ad-hoc local patches: checksums to protect specific computations against hardware faults and bug fixes to protect programs against known vulnerabilities. This strategy is unsatisfactory since it is prone to errors, requires significant manual effort, and protects only against anticipated faults. On the other extreme, Byzantine Fault Tolerance solutions defend against all kinds of hardware and software errors, but are inadequately expensive in terms of resources and performance overhead.
In this thesis, we examine and propose five techniques to protect against hardware CPU faults and software memory-corruption bugs. All these techniques are hardware-assisted: they use recent advancements in CPU designs and modern CPU extensions. Three of these techniques target hardware CPU faults and rely on specific CPU features: ∆-encoding efficiently utilizes instruction-level parallelism of modern CPUs, Elzar re-purposes Intel AVX extensions, and HAFT builds on Intel TSX instructions. The rest two target software bugs: SGXBounds detects vulnerabilities inside Intel SGX enclaves, and “MPX Explained” analyzes the recent Intel MPX extension to protect against buffer overflow bugs.
Our techniques achieve three goals: transparency, practicality, and efficiency. All our systems are implemented as compiler passes which transparently harden unmodified applications against hardware faults and software bugs. They are practical since they rely on commodity CPUs and require no specialized hardware or operating system support. Finally, they are efficient because they use hardware assistance in the form of CPU extensions to lower performance overhead.
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Gupta, Amit Kumar Electrical Engineering & Telecommunications Faculty of Engineering UNSW. "Hardware optimization of JPEG2000." Awarded by:University of New South Wales. School of Electrical Engineering and Telecommunications, 2006. http://handle.unsw.edu.au/1959.4/30581.
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The Key algorithms of JPEG2000, the new image compression standard, have high computational complexity and thus present challenges for efficient implementation. This has led to research on the hardware optimization of JPEG2000 for its efficient realization. Luckily, in the last century the growth in Microelectronics allows us to realize dedicated ASIC solutions as well as hardware/software FPGA based solutions for complex algorithms such as JPEG2000. But an efficient implementation within hard constraints of area and throughput, demands investigations of key dependencies within the JPEG2000 system. This work presents algorithms and VLSI architectures to realize a high performance JPEG2000 compression system. The embedded block coding algorithm which lies at the heart of a JPEG2000 compression system is a main contributor to enhanced JPEG2000 complexity. This work first concentrates on algorithms to realize low-cost high throughput Block Coder (BC) system. For this purpose concurrent symbol processing capable Bit Plane Coder architecture is presented. Further optimal 2 sub-bank memory and an efficient buffer architectures are designed to keep the hardware cost low. The proposed overall BC system presents the highest Figure Of Merit (FOM) in terms of throughput versus hardware cost in comparison to existing BC solutions. Further, this work also investigates the challenges involved in the efficient integration of the BC with the overall JPEG2000 system. A novel low-cost distortion estimation approach with near-optimal performance is proposed which is necessary for accurate rate-control performance of JPEG2000. Additionally low bandwidth data storage and transfer techniques are proposed for efficient transfer of subband samples to the BC. Simulation results show that the proposed techniques have approximately 4 times less bandwidth than existing architectures. In addition, an efficient high throughput block decoder architecture based on the proposed selective sample-skipping algorithm is presented. The proposed architectures are designed and analyzed on both ASIC and FPGA platforms. Thus, the proposed algorithms, architectures and efficient BC integration strategies are useful for realizing a dedicated ASIC JPEG2000 system as well as a hardware/software FPGA based JPEG2000 solution. Overall this work presents algorithms and architectures to realize a high performance JPEG2000 system without imposing any restrictions in terms of coding modes or block size for the BC system.
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Daubert, Katja. "Hardware-supported cloth rendering." München Verl. Dr. Hut, 2004. http://deposit.d-nb.de/cgi-bin/dokserv?idn=972319344.
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Beeckler, John Sachs. "FPGA particle graphics hardware." Thesis, McGill University, 2006. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=98944.
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Particle graphics simulations are well suited for modeling phenomena such as water, cloth, explosions, fire, smoke, and clouds. They are normally realized in software, as part of an interactive graphics application. Their use in such applications is limited by the computational burden and resource competition they create. This thesis presents the design and implementation of a reconfigurable hardware particle graphics system for accelerating real-time particle graphics effects: The Particle Pipe. We explore the design process, implementation issues, limitations, challenges, and new possibilities of using FPGAs for the acceleration of real-time particle graphics. The Particle Pipe has been synthesized to an operating frequency of 130 MHz and has the potential for an increase in performance of two orders of magnitude over software methods and one order of magnitude over GPU methods.
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Sharp, Richard William. "Higher-level hardware synthesis." Thesis, University of Cambridge, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.619747.
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Singh, Satnam. "Analysis of hardware descriptions." Thesis, University of Glasgow, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.390451.
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Waller, Marcus D. "3D rasterisarion hardware techniques." Thesis, University of Sussex, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.388702.
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Martin, Peter N. "Genetic programming in hardware." Thesis, University of Essex, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.272585.
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Chau, Man Ping Grace. "Goal-oriented hardware design." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/45853.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 145-146).
This thesis presents Fide, a hardware design system that uses Goal-oriented programming. Goal-oriented programming is a programming framework to specify open-ended decision logic. This approach relies on two fundamental concepts-Goals and Techniques. Goals encode decision points and Techniques are scripts that describe how to satisfy Goals. In Fide, Goals represent the functional requirements (e.g., addition of two 32-bit binary integers) of the target circuit. Techniques represent hardware implementation alternatives that fulfill the functions. Techniques may declare their own subgoals, allowing a hierarchical decomposition of the functions. A Planner selects among Techniques based on the Goals declared to generate an implementation of the target circuit automatically. Users' preferences can be added to generate circuits for different scenarios: for different hardware environments, under different circuit constraints, or different implementation criteria etc. A Beta processor is implemented using Fide. The quality of the implementation is comparable to those optimized manually.
by Man Ping Grace Chau.
S.M.
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Guadiana, Juan M. "Look Ma, No Hardware!" International Foundation for Telemetering, 2009. http://hdl.handle.net/10150/606015.
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ITC/USA 2009 Conference Proceedings / The Forty-Fifth Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2009 / Riviera Hotel & Convention Center, Las Vegas, NevadaGoogle Soft Decom and the number of hits will be tenfold over the same search last year. The migration of hardware functionality toward software is relentless. On the telemetry front, Data Bridges that take Pulse Code Modulated (PCM) signals and transform them to ubiquitous network packets make it all too easy. The need for expensive hardware such as the Decommutator (Decom), Frame Synchronizer, Digital Recorder, and Oscillograph Recorder (StripChart) will diminish sharply. Software Decom packages will feel the squeeze too, from homegrown Soft Decom software that is easier to maintain and has no licensing issues. This paper airs the dirty laundry associated with this hardware and software. Latencies and ugly temporal aberration that really plague an analyst. Also discussed is how a few packet/file formats eliminate the need for most of the hardware in a traditional telemetry data processing facility.
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Silva, Alexandre Rodrigues da. "Hardware de ventilador pulmonar." Universidade de São Paulo, 2011. http://www.teses.usp.br/teses/disponiveis/3/3139/tde-03052012-121527/.
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Este trabalho visou mostrar o desenvolvimento de um ventilador pulmonar mecânico, focando principalmente na parte de hardware necessária para que este equipamento pudesse funcionar. Ventilação mecânica é a modalidade da medicina mais importante no cuidado a pacientes criticamente enfermos. O ventilador é um equipamento utilizado principalmente em unidades de terapia intensiva, que basicamente coloca uma mistura de ar e oxigênio para dentro do pulmão de um paciente incapacitado de fazer isto naturalmente, quer seja por força de uma doença que o impossibilita de fazê-lo, ou por uma cirurgia, a qual impossibilitou o movimento do músculo do diafragma para que o ar entrasse no pulmão naturalmente. Este projeto cobriu uma descrição abrangente sobre este ventilador, sua transformação de ar comprimido e oxigênio provenientes de um cilindro em uma mistura controlada de fluxos que entra no pulmão para a inspiração de um volume, ou para atingir uma pressão determinada, e a saída desta mistura, mantendo no pulmão uma pressão também controlada. Foi desenvolvido um protótipo de hardware e firmware para este aparelho, e o intuito foi mostrar o processo de transformação da ideia inicial e as necessidades de projeto em um aparelho testado e certificado para uso no mercado.This work aimed to present the development of a pulmonary mechanical ventilator, mainly focusing on the hardware part needed in order for this device to work. Mechanical ventilation is the most important medical mode concerning the care of patients that are critically ill. The ventilator is a device very much used in intensive care units (ICUs), and it basically delivers an air and oxygen mixture to the patients lungs that is normally unable to do so naturally, either because the patient is seriously ill that prevents him/her to do so, or due to surgery, in this case prevented the movement of the diaphragm muscle so the air could be naturally delivered to the lung. This work covered a comprehensive description about this ventilator, its transformation of compressed air and oxygen coming from a cylinder in a controlled mixture of flows that enters the lung for the inspiration of a volume, or to achieve a determined pressure, and the output of this mixture, maintaining a controlled pressure in the lung too. A hardware and firmware prototype was developed for this device. The aim was to show the transformation process from the main idea and the need for a project of a tested and certified device to be used in the market.
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Santa, Marek. "Zpětnovazební funkční verifikace hardware." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2011. http://www.nusl.cz/ntk/nusl-237045.
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In the development process of digital circuits, it is often not possible to avoid introducing errors into systems that are being developed. Early detection of such errors saves money and time. This project deals with automation of feedback in functional verification of various data processing components. The goal of automatic feedback is not only to shorten the time needed to verify the functionality of a system, but mainly to improve verification coverage of corner cases and thus increase the confidence in the verified system. General functional and formal verification principles and practices are discussed, coverage metrics are presented, limitations of both techniques are mentioned and room for improvement of current status is identified. Design of feedback verification environment using a genetic algorithm is described in detial. The verification results are summarized and evaluated.
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Li, Zhuoxuan. "Open source hardware entrepreneurship." Thesis, Massachusetts Institute of Technology, 2020. https://hdl.handle.net/1721.1/127724.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Mechanical Engineering, 2020Cataloged from PDF of thesis.
Includes bibliographical references (pages 136-145).
Having overturned the traditional producer-led, in-house production model of software, open source entered the physical world and started to change physical products' development and commercialization process. Will open source diversify the hardware world as it did in software 20 years ago? Since mid-2000, engineer entrepreneurs were observed to have purposefully chosen to abandon the intellectual properties of their products and licensed the design under open source licenses. As a consequence, public are allowed to participate to the product design processes from an early phase and interact with firms in an open, transparent way. It is reasonable to consider this extreme openness as a high risk move for hardware startup-level firms, who are normally resource-scarce, capital-intense and loosely organized. Then, the research questions come as how open source hardware firms generate profit and manage risks? Can open source model be a sustainable hardware development model in an entrepreneurial setting? Using data collected from 66 open source hardware firms over 4 years across 21 countries, the research questions were answered with a series of four research projects. In brief, the success of open source model in entrepreneurial activities is a result of dynamic design of organizational openness and community governance mechanism according to firm's business model and community's social needs, so that firms are able to exploit community value brought by being open and mitigate risks associated. Open source hardware entrepreneurship can serve as an extreme application of open innovation and user innovation theories in hardware venture creation, and we hope to use this work as a pilot study for the emerging socio-technological phenomenon.
by Zhuoxuan Li.
Ph. D.
Ph.D. Massachusetts Institute of Technology, Department of Mechanical Engineering
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Nayak, Ankita Manjunath. "Precision Tunable Hardware Design." University of Cincinnati / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1479814631903673.
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Woidt, Hendrik. "Hardware Synthesis in ForSyDe." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-197307.
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There have been numerous e orts in the development of functional hardware description languages over the past years. In this thesis project the design space for embedded domain specic languages for hardware synthesis in Haskell is explored by comparing the approaches of two di erent language implementations. This report contains an introduction to the fundamental concepts for modeling hardware in a functional style and the core concepts of implementing deep embedded languages. Based on this, the architectures of ForSyDe.Deep and Cash are examined in order to nd their strengths and weaknesses. The results are applied to the implementation of translation of data-parallel higher order functions in ForSyDe.Deep. The implementation of higher order functions has shown that the lack of type information available for the translation of process functions in the current implementation of ForSyDe.Deep is the limiting factor for achieving a higher level of abstraction within process functions through polymorphism or higher order functions. This does not diminish the approach of ForSyDe though as the real power lies in the abstraction provided by the process network.
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Richards, Dominic Anthony. "Hardware languages and proof." Thesis, University of Manchester, 2011. https://www.research.manchester.ac.uk/portal/en/theses/hardware-languages-and-proof(94392511-3019-4c56-863f-c93ea58da06c).html.
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Formal methods play a significant and increasing role in hardware verification, but their effectiveness can be impaired by the ac hoc nature of mainstream hardware languages such as VHDL, Verilog and SystemC, which have convoluted semantics that often necessitate contrived proof techniques. This dissertation investigates the application of formal reasoning to hardware architectures expressed in an alternative class of semantically elegant languages, which support efficient design, whilst also having been developed with proof techniques in mind. A network-on-chip architecture belonging to the SpiNNaker many-core processor is specified in Concurrent Haskell, and a hand proof is presented which verifies a novel routing mechanism by mathematical induction. A subset of Bluespec SystemVerilog (BSV) is embedded in the higher order logic of the PVS theorem prover. Owing to the clean semantics of BSV, application of monadic techniques leads to a surprisingly elegant embedding, in which hardware designs are translated into logic almost verbatim, preserving types and language constructs. Proof strategies are written in the PVS strategy language; these automatically verify temporal logic theorems concerning the resulting monadic expressions, by employing a combination of model checking and deductive reasoning. The subset of BSV which is embedded includes module definition and instantiation, methods, implicit conditions, scheduling attributes, and rule composition using methods from instantiated modules. The aforementioned subset of BSV is also embedded in the specification language of the SAL model checker, and a verification strategy is presented which combines the specialised model checking capabilities of SAL with the diverse proof strategies of PVS.
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Cheung, Chak-Chung Ray. "Customisable arithmetic hardware designs." Thesis, Imperial College London, 2007. http://hdl.handle.net/10044/1/11976.
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Miller, Christopher Michael. "Hardware accelerated volume texturing." Thesis, Swansea University, 2006. https://cronfa.swan.ac.uk/Record/cronfa42524.
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The emergence of volume graphics, a sub field in computer graphics, has been evident for the last 15 years. Growing from scientific visualization problems, volume graphics has established itself as an important field in general computer graphics. However, the general graphics fraternity still favour the established surface graphics techniques. This is due to well founded and established techniques and a complete pipeline through software onto display hardware. This enables real-time applications to be constructed with ease and used by a wide range of end users due to the readily available graphics hardware adopted by many computer manufacturers. Volume graphics has traditionally been restricted to high-end systems due to the complexity involved with rendering volume datasets. Either specialised graphics hardware or powerful computers were required to generate images, many of these not in real-time. Although there have been specialised hardware solutions to the volume rendering problem, the adoption of the volume dataset as a primitive relies on end-users with commodity hardware being able to display images at interactive rates. The recent emergence of programmable consumer level graphics hardware is now allowing these platforms to compute volume rendering at interactive rates. Most of the work in this field is directed towards scientific visualisation. The work in this thesis addresses the issues in providing real-time volume graphics techniques to the general graphics community using commodity graphics hardware. Real-time texturing of volumetric data is explored as an important set of techniques in delivering volume datasets as a general graphics primitive. The main contributions of this work are; The introduction of efficient acceleration techniques; Interactive display of amorphous phenomena modelled outside an object defined in a volume dataset; Interactive procedural texture synthesis for volume data; 2D texturing techniques and extensions for volume data in real-time; A flexible surface detail mapping algorithm that removes many previous restrictions Parts of this work have been presented at the 4th International Workshop on Volume Graphics and also published in Volume Graphics 2005.
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Weng, Darrin Kalung. "Accurate Hardware RAID Simulator." DigitalCommons@CalPoly, 2013. https://digitalcommons.calpoly.edu/theses/1005.
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Computer data storage is growing at an astonishing rate. With cloud computing and the growth of the Internet enterprise storage has been predicted to grow at rates as high as 300\% per year. To fulfill this need technologies such as Redundant Array of Independent Disks or RAID are being used in industry today. Not only does RAID increase I/O performance but also provides redundancy measures to protect against hardware failure. Even though RAID has existed for some time now and is well understood, proprietary optimizations such as command scheduling and cache strategies that are employed by current RAID controllers are not well known. This thesis presents a model for RAID 5 that incorporates these features and describes the overall function of hardware RAID controllers. Also a python implementation of this model, Accurate Hardware RAID Simulator (AHRS) is presented and validated against a current hardware RAID controller. It is shown that AHRS can reproduce the behavior of a hardware RAID system with an accuracy of 97.92\% on average compared to a LSI hardware RAID controller.
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Pavlidis, Antonios. "Analog Hardware Fault Diagnosis." Electronic Thesis or Diss., Sorbonne université, 2021. http://www.theses.fr/2021SORUS452.
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Le nombre de circuits intégrés (CIs) utilisés dans les applications liées à des missions critiques et à la sûreté augmente sans cesse. Ces applications imposent aux CIs de présenter des propriétés de sûreté fonctionnelle. Cette thèse introduit un auto-test intégré (BIST) pour les CIs analogiques et à signaux mixtes, appelé autotest à symétrie (SymBIST) pour répondre à l’objectif de sûreté fonctionnelle. SymBIST repose sur le principe du BIST et sur l'existence de signaux invariants en fonctionnement nominal et variant en cas de fonctionnement erroné. Les invariants sont mesurés à l'aide de dispositifs intégrés spécifiques. SymBIST répond à trois objectifs de sûreté fonctionnelle : le test les défauts du CI, le test en ligne, et le diagnostic les défauts. SymBIST est démontré sur un convertisseur analogique-numérique à approximations successives (CAN SAR). Les résultats montent que la couverture de test et la précision de diagnostic sont plus élevées que l’état de l’artThe number of integrated circuits (ICs) used in safety- and mission-critical applications is ever increasing. These applications demand that ICs carry functional safety properties. In this thesis, we develop a Built-In Self Test (BIST) approach for Analog and Mixed-Signal (A/M-S) ICs, called Symmetry-Based Built-In Self Test (SymBIST), which achieves several objectives towards the functional safety goal. SymBIST is a generic BIST paradigm based on identifying inherent invariances that should hold true only in error-free operation, while their violation points to abnormal operation. The invariances are being checked using dedicated on-die checkers. SymBIST meets three functional safety objectives: post-manufacturing defect-oriented test, on-line testing, and fault diagnosis. SymBIST is demonstrated on a successive approximation analog-to-digital converter (SAR ADC). The results show that the test coverage and diagnostic accuracy are promising compared to the state of the art
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Johansson, Hanna. "Interdisciplinary Requirement Engineering for Hardware and Software Development : from a Hardware Development Perspective." Thesis, Linköpings universitet, Industriell miljöteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-139097.
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Complexity in products is increasing, and still there is lack of a shared design language ininterdisciplinary development projects. The research questions of the thesis concern differencesand similarities in requirement handling, and integration, current and future. Futureintegration is given more focus with a pair of research questions highlighting obstacles andenablers for increased integration. Interviews were performed at four different companieswith complex development environments whose products originated from different fields;hardware, software, and service. Main conclusions of the thesis are: Time-frames in different development processes are very different and hard to unite. Internal standards exist for overall processes, documentation, and modification handling. Traceability is poorly covered in theory whilst being a big issue in companies. Companies understand that balancing and compromising of requirements is critical fora successful final product. The view on future increased interdisciplinary development is that there are more obstaclesto overcome than enablers supporting it. Dependency is seen as an obstacle inthis regard and certain companies strive to decrease it.The thesis has resulted in general conclusions and further studies is suggested into morespecific areas such as requirement handling tools, requirement types, and traceability.
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Thompson, Adrian. "Hardware evolution : automatic design of electronic circuits in reconfigurable hardware by artificial evolution." Thesis, University of Sussex, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.360588.
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Chen, Zhe. "Hardware Accelerator of Matrix Multiplication on FPGAs : Hardware Accelerator of Matrix Multiplication on FPGAs." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-366815.
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To solve the computational complexity and time-consuming problem of large matrix multiplication, this thesis design a hardware accelerator using parallel computation structure based on FPGA. After function simulation in ModelSim, matrix multiplication functional modules as a custom component used as a coprocessor in co-operation with Nios II CPU by Avalon bus interface. To analyze computation performance of the hardware accelerator, two software systems are designed for comparison. The results show that the hardware accelerator can improve the computational performance of matrix multiplication significantly.
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TAKALOO, HADIS. "Design and Implementation of Two Hardware Silicon Prototypes for Cryptography and Hardware Security Applications." Doctoral thesis, Università di Siena, 2020. http://hdl.handle.net/11365/1107236.
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This thesis reports the main research results that I achieved during my PhD program at the Department of Information Engineering and Mathematics of the University of Siena, Italy.
The purpose of my research was to study and design lightweight crypto-hardware silicon Integrated Circuits (ICs) based on non-linear dynamical systems for hardware security and cryptographic applications. The objectives of this work were ambitious, since the goal was facing the design of silicon True Random Bit Generators (TRBGs) and Physically Unclonable Functions (PUFs) with new methods and multidisciplinary approaches, linking together Measure Theory, Neural Networks, Complex Systems, Nonlinear Dynamics, Integrated Circuit design and technology, as well as Cryptography.
This thesis is divided in two parts. The first part presents the study and the design of an IC implementing a chaos-based TRBG with statistical self-tuning capabilities. As a result of my research, an integrated circuit was designed and taped-out during my PhD program. The IC is a full custom mixed-signal circuit implementing a TRBG based on a discrete-time piecewise linear 1D chaotic map. The TRBG exploits self-tuning capabilities to achieve the maximum entropy, which is obtained monitoring and adjusting the chaotic map parameters to compensate possible perturbing deviances due to, e.g., technological process variability and temperature variations. To this aim, the IC is equipped with a digital core analyzing the statistical characteristics of the generated sequences, to
achieve the estimation of the chaotic system parameters and to perform a digitized control and correction of the analog circuit implementing the map. The chip has been fabricated after being selected and ranked among the 10 best project proposals in the very first user category, in the second EUROPRACTICE First User Stimulation action. The IC has been fabricated at the end of April, 2018, and tested in June/July 2018. To house and power the IC a PCB has been designed and fabricated, providing the necessary physical analog and digital interfaces for the chip testing. Furthermore, the testing environment has been developed in the LABVIEW environment exploring to a development board equipped with a Xilinx FPGA, and providing the software and hardware tools to perform the tests.
The second part of this thesis presents the study and the design of an IC implementing a novel PUF circuit derived from Cellular Neural Networks (CNNs).
The fundamental idea in this research is to exploit the rich dynamical versatility of CNNs to derive a novel class of low-complexity mixed-signal silicon PUFs, taking advantages from a wide set of mathematical models that can be analyzed by means of well-established theoretical tools. Also for this research activity, as a result of my research, an integrated circuit was designed and taped-out during my PhD program. The design of the hardware silicon prototype aimed to study the feasibility of the proposal, referring to standard mixedsignal CMOS technologies, and exploring different architectures and circuit topologies.
The chip database for the tape-out was delivered at the end of August 2019, and at the time of writing this thesis the chip was currently under fabrication.
In both of the research activities the results were achieved through circuit simulations, including the effects of temperature variations and technological process variability to verify and refine the proposed theoretical models. The activities presented in this thesis covered the design of the proposed circuits both at the electrical and physical levels, including post-layout validation and the writing of the design documentation.
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Chakraborty, Rajat Subhra. "Hardware Security through Design Obfuscation." Cleveland, Ohio : Case Western Reserve University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=case1270133481.
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Thesis (Doctor of Philosophy)--Case Western Reserve University, 2010Department of EECS - Computer Engineering Title from PDF (viewed on 2010-05-25) Includes abstract Includes bibliographical references and appendices Available online via the OhioLINK ETD Center
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Krutz, David. "Ein Betriebssystem für konfigurierbare Hardware." [S.l.] : [s.n.], 2006. http://deposit.ddb.de/cgi-bin/dokserv?idn=983406014.
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Zabel, Martin, Thomas B. Preußer, Peter Reichel, and Rainer G. Spallek. "SHAP-Secure Hardware Agent Platform." Universitätsbibliothek Chemnitz, 2007. http://nbn-resolving.de/urn:nbn:de:swb:ch1-200701011.
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This paper presents a novel implementation
of an embedded Java microarchitecture for secure, realtime,
and multi-threaded applications. Together with the
support of modern features of object-oriented languages,
such as exception handling, automatic garbage collection
and interface types, a general-purpose platform is established
which also fits for the agent concept. Especially,
considering real-time issues, new techniques have been
implemented in our Java microarchitecture, such as an
integrated stack and thread management for fast context
switching, concurrent garbage collection for real-time
threads and autonomous control flows through preemptive
round-robin scheduling.
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Kizito, Jimmy Anthony Galiwango. "Pattern Classification using Reconfigurable Hardware." Thesis, University of Manchester, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.508603.
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Pasca, Isabela Mona. "Neural network digital hardware implementation." Thesis, University of Ottawa (Canada), 2007. http://hdl.handle.net/10393/27902.
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This thesis presents a digital hardware implementation of an artificial neuron with learning ability using the QuartusII 5.1sp1 web edition software on Altera's University Program Development Board (UP2). The learning method implemented is neither backpropagation nor conjugate gradient, but the weight simultaneous perturbation. By combining this method with a pulse density system and using a Field Programmable Gate Array, an interesting artificial neuron hardware architecture is obtained. Finally, two applications of the neuron implementation are presented: an analog function and a digital function.
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Gülerman, Ender. "Advanced Throttle Control Hardware Implementation." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-177299.
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Low cost, reliable and durable solutions are required in all industries. In automotive industry, BLDC (Brushless Direct Current) motors are widely used due to its advantages over brushed DC motors, which also brings more complex commutation schemes and increased development cost. Despite the fact, BLDC motors require low maintenance and provide reliable results in compare with brushed DC motors, the cost of development of control stage and required hardware topology has been a competence area. The requirements of the application tailor the required hardware topology and control strategy. In this thesis, BLDC motor commutation control hardware topologies to implement a BLDC motor based air throttle control circuit, power dissipation and EMC considerations are addressed. BLDC motor control of a throttle were chosen as a test case due to Scania requirements. An air throttle adjusts the air intake going to a combustion engine, thus directly e ecting the performance. The better controlling the throttle means, providing reliable results with lower consumption of energy. The throttle chosen is an intelligent self positioning unit being bought from a sub-supplier and Scania steers the control by means of an angle position reference sent via CAN (Controller Area Network) bus. The sub-supplier solution results in lack of exibility in software and hardware implementation and lacking possible customization improvements. A customized hardware solution was implemented to question whether a custom hardware implementation and a control strategy planned by Scania can resolve in less power consumption. In addition, what is required to make the throttle unit better should be reected. For this purpose,a customized commutation control circuit was built and a benchmarking in compare with the original sub-supplier solution were done to enable comparison and discussion on possible improvements. One unit of sub-supplier and one unit of customized hardware were benchmarked with respect to heat dissipation, current consumption at the time angle is settled and EMI (Electromagnetic Interference). The results showed that the given Scania control strategy may yield in decreased current consumption, thus reduced heat dissipation. Despite the fact the results are prospective, from a scientic point of view, a comprehensive long term benchmarking should be done with multiple units. The outcomes of this project are a hardware platform which can be used as a development platform to further enable comparison and development, partially proven Scania control strategy to reduce dissipation and enabling cumulative future work in form of diagnostics.
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Cervin, Albert. "Adaptive Hardware-accelerated Terrain Tessellation." Thesis, Linköpings universitet, Medie- och Informationsteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91334.
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In this master thesis report, a scheme for adaptive hardware terrain tessellation is presented. The scheme uses an offline processing approach where a height map is analyzed in terms of curvature and the result is stored in a resource called density map. This density map is then bound as a resource to the hardware tessellation stage and used to bias the tessellation factor for a given edge. The scheme is implemented inside FrostbiteTM2 by EATM DICETM and produces good results while making the heightfield rendering more efficient. The performance gain can be used to increase the rendering detail, allowing for better visual appearance for the terrain mesh. The scheme is currently implemented for hardware tessellation but could also be used for software terrain mesh generation. The implementation works satisfactory and produces good results with a reasonable speed.I den här rapporten för examensarbete presenteras en algoritm för att utföra adaptiv hårdvarutessellation av terräng. Algoritmen använder sig av ett offline-steg där ett höjdfält analyseras med avseende på kurvatur och resultatet lagras i en densitets-karta. Den här densitets-kartan används sedan som en resurs i hårdvarutessellationen där den påverkar en tessellationsfaktor för en given triangel-kant. Algoritmen har implementerats i spelmotorn FrostbiteTM2 skapad av EATM DICETM och producerar goda resultat samtidigt som den gör rendering av terrängen effektivare. Detta medf¨or att detaljnivån för terrängrenderingen kanökas, vilket i sin tur leder till en visuell förbättring. Algoritmen är för närvarande endast implementerad för hårdvarutessellation men skulle också kunna användas för mjukvarugenerering av terrängens geometri. Algoritmen fungerar tillfredsställande och producerar goda resultat med en acceptabel hastighet.
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Dyer, Michael Ian Electrical Engineering & Telecommunications Faculty of Engineering UNSW. "Hardware Implementation Techniques for JPEG2000." Awarded by:University of New South Wales. Electrical Engineering and Telecommunications, 2007. http://handle.unsw.edu.au/1959.4/30510.
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JPEG2000 is a recently standardized image compression system that provides substantial improvements over the existing JPEG compression scheme. This improvement in performance comes with an associated cost in increased implementation complexity, such that a purely software implementation is inefficient. This work identifies the arithmetic coder as a bottleneck in efficient hardware implementations, and explores various design options to improve arithmetic coder speed and size. The designs produced improve the critical path of the existing arithmetic coder designs, and then extend the coder throughput to 2 or more symbols per clock cycle. Subsequent work examines more system level implementation issues. This work examines the communication between hardware blocks and utilizes certain modes of operation to add flexibility to buffering solutions. It becomes possible to significantly reduce the amount of intermediate buffering between blocks, whilst maintaining a loose synchronization. Full hardware implementations of the standard are necessarily limited in the amount of features that they can offer, in order to constrain complexity and cost. To circumvent this, a hardware / software codesign is produced using the Altera NIOS II softcore processor. By keeping the majority of the standard implemented in software and using hardware to accelerate those time consuming functions, generality of implementation can be retained, whilst implementation speed is improved. In addition to this, there is the opportunity to explore parallelism, by providing multiple identical hardware blocks to code multiple data units simultaneously.
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Trendall, Chris. "Ray tracing refraction in hardware." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape3/PQDD_0016/MQ49742.pdf.
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Steinhurst, Joshua Eli Lastra Anselmo. "Practical photon mapping in hardware." Chapel Hill, N.C. : University of North Carolina at Chapel Hill, 2007. http://dc.lib.unc.edu/u?/etd,741.
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Thesis (Ph. D.)--University of North Carolina at Chapel Hill, 2007.Title from electronic title page (viewed Dec. 18, 2007). "... in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the Department of Computer Science." Discipline: Computer Science; Department/School: Computer Science.
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Lyons, Michael John. "Toward a Hardware Accelerated Future." Thesis, Harvard University, 2014. http://pqdtopen.proquest.com/#viewpdf?dispub=3600206.
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Hardware accelerators provide a rare opportunity to achieve orders-of-magnitude performance and power improvements with customized circuit designs.
Many forms of hardware acceleration exist—attributes and trade-offs of each approach is discussed. Single-algorithm accelerators, which maximize efficiency gains through maximum specialization, are one such approach. By combining many of these into a many-accelerator system, high specialization is possible with fewer specialization limits.
The development of one such single-algorithm hardware accelerator for managing compressed Bloom filters in wireless sensor networks is presented. Results from the development of the accelerator highlight scalability deficiencies in the way accelerators are currently integrated into processors, and that the majority of accelerator area is consumed by generic SRAM memory rather than algorithm-specific logic.
These results motivate development of the accelerator store, a system architecture designed for the needs of many-accelerator systems. In particular, the accelerator store improves inter-accelerator communication and includes support for sharing accelerator SRAM memories. Using a security application as an example, the accelerator store architecture is able to reduce total processor area by 30% with less than 1% performance overhead.
Using the accelerator store as a base, the ShrinkFit framework allows accelerators to grow and shrink, to achieve accelerated performance within small FPGA budgets and efficiently expand for more performance when larger FPGA budgets are available. The ability to resize accelerators is particularly useful for hybrid systems combining GP-CPUs and FPGA resources, in which applications may deploy accelerators to a shared FPGA fabric. ShrinkFit performance overheads for small and large FPGA resources are found to be low using a robotic bee brain workload and FPGA prototype.
Finally, future directions are briefly discussed along with details about the production of the robotic bee helicopter brain prototype.
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Busch, Holger. "Hardware design by proven transformations." Thesis, Brunel University, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.293219.
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Milligan, Graeme Richard. "Reconfigurable hardware for control applications." Thesis, University of Glasgow, 2008. http://theses.gla.ac.uk/456/.
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This portfolio document is intended to present the work carried out in order to meet the requirements of the Engineering Doctorate (EngD) program undertaken at the Institute for System Level Integration (ISLI). This program was undertaken in partnership with the Universities of Glasgow, Edinburgh, Strathclyde and Heriott Watt and was funded by EPSRC and SLI Ltd. The use of control systems is becoming ubiquitous with even the simplest of systems now employing some kind of control logic. For this reason the project investigated the use and development of reconfigurable hardware for control applications. This first involved a detailed analysis of the current state of the art in the reconfigurable field as well as some selected applications where it is thought this technology may be of benefit. The main body of the project was separated into three distinct areas of research and is hence presented as a collection of three technical documents. The first of these areas was the use of reconfigurable hardware for the implementation of Finite State Machines (FSM) with particular reference to reducing the size of the hardware block required to implement these structures. From this a novel implementation method was developed based on the principle of Forward Transition Expressions which are capable of implementing FSMs on a reconfigurable device using run-time reconfiguration. The second area of research was the investigation of the characteristics of reconfigurable devices with a view to estimating the amount of hardware required within a device from high level parameters. The final area of research was the development of a custom reconfigurable device specifically tailored for the implementation of FSM.
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Hoggins, Carl Andrew. "Hardware acceleration of photon mapping." Thesis, University of Newcastle Upon Tyne, 2011. http://hdl.handle.net/10443/1242.
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The quest for realism in computer-generated graphics has yielded a range of algorithmic techniques, the most advanced of which are capable of rendering images at close to photorealistic quality. Due to the realism available, it is now commonplace that computer graphics are used in the creation of movie sequences, architectural renderings, medical imagery and product visualisations. This work concentrates on the photon mapping algorithm [1, 2], a physically based global illumination rendering algorithm. Photon mapping excels in producing highly realistic, physically accurate images. A drawback to photon mapping however is its rendering times, which can be significantly longer than other, albeit less realistic, algorithms. Not surprisingly, this increase in execution time is associated with a high computational cost. This computation is usually performed using the general purpose central processing unit (CPU) of a personal computer (PC), with the algorithm implemented as a software routine. Other options available for processing these algorithms include desktop PC graphics processing units (GPUs) and custom designed acceleration hardware devices. GPUs tend to be efficient when dealing with less realistic rendering solutions such as rasterisation, however with their recent drive towards increased programmability they can also be used to process more realistic algorithms. A drawback to the use of GPUs is that these algorithms often have to be reworked to make optimal use of the limited resources available. There are very few custom hardware devices available for acceleration of the photon mapping algorithm. Ray-tracing is the predecessor to photon mapping, and although not capable of producing the same physical accuracy and therefore realism, there are similarities between the algorithms. There have been several hardware prototypes, and at least one commercial offering, created with the goal of accelerating ray-trace rendering [3]. However, properties making many of these proposals suitable for the acceleration of ray-tracing are not shared by photon mapping. There are even fewer proposals for acceleration of the additional functions found only in photon mapping. All of these approaches to algorithm acceleration offer limited scalability. GPUs are inherently difficult to scale, while many of the custom hardware devices available thus far make use of large processing elements and complex acceleration data structures. In this work we make use of three novel approaches in the design of highly scalable specialised hardware structures for the acceleration of the photon mapping algorithm. Increased scalability is gained through: • The use of a brute-force approach in place of the commonly used smart approach, thus eliminating much data pre-processing, complex data structures and large processing units often required. • The use of Logarithmic Number System (LNS) arithmetic computation, which facilitates a reduction in processing area requirement. • A novel redesign of the photon inclusion test, used within the photon search method of the photon mapping algorithm. This allows an intelligent memory structure to be used for the search. The design uses two hardware structures, both of which accelerate one core rendering function. Renderings produced using field programmable gate array (FPGA) based prototypes are presented, along with details of 90nm synthesised versions of the designs which show that close to an orderof- magnitude speedup over a software implementation is possible. Due to the scalable nature of the design, it is likely that any advantage can be maintained in the face of improving processor speeds. Significantly, due to the brute-force approach adopted, it is possible to eliminate an often-used software acceleration method. This means that the device can interface almost directly to a frontend modelling package, minimising much of the pre-processing required by most other proposals.