Academic literature on the topic 'Hardware Under Test'
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Journal articles on the topic "Hardware Under Test"
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Pomeranz, Irith. "Test Compaction by Test Removal Under Transparent Scan." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, no. 2 (February 2019): 496–500. http://dx.doi.org/10.1109/tvlsi.2018.2878067.
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Yin, Jiao, Hu Liu, Jun Wang, and Ke Li. "Control System Design of Pneumatic Conveying in Sand/Dust Environment Simulation Test." Applied Mechanics and Materials 442 (October 2013): 424–29. http://dx.doi.org/10.4028/www.scientific.net/amm.442.424.
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This paper focuses on the design of pneumatic conveying control system, including the design of both hardware and software part. The hardware part is mainly about building a test bed. Under certain wind conditions, by controlling the rotary feed valve to achieve the control of sand/dust concentration. The software part is to make the use of LabVIEW to develop a screen display program, which can achieve real-time data acquisition and control. The paper consists of three parts, the pneumatic control system hardware design, the pneumatic conveying control system software design and then Origin is used to linear fit the wind speed parameters collected back.
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Wan Jamaludin, Wan Shahmisufi, Tan Wei Ren, Bakhtiar Affendi Rosdi, Dahaman Ishak, Noor Hafizi Hanafi, and Muhammad Nasiruddin Mahyuddin. "Adopting Hardware-In-the-Loop for Testing Vehicle Instrument Panel using Economical Approach." Indonesian Journal of Electrical Engineering and Computer Science 10, no. 1 (April 1, 2018): 50. http://dx.doi.org/10.11591/ijeecs.v10.i1.pp50-58.
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An economical approach for testing Vehicle Instrument Panel is proposed in this paper due to high expenditure of purchasing the available Commercial Off-The-Shelf Hardware-In-The-Loop. Vehicle Instrument Panel is designated as the Device-Under-Test in this paper. The Hardware-In-The-Loop, designated as the test equipment, will simulate the assigned input signals controllable via designed Graphical User Interface. The resulting display is shown on the Graphical User Interface and the Device-Under-Test. The speedometer gauge measurement showed the highest disparity of 4 km/h which is within the tolerance of the pre-determined specification of the Device-Under-Test.
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Zhang, Peng, Hou Jun Wang, Li Li, and Ping Wang. "Design and Implementation of Intermediate Frequency Generation and Analysis Module for Avionics Test." Advanced Materials Research 1049-1050 (October 2014): 1147–53. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.1147.
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To test airborne avionics device, it is necessary to provide signal stimulus for the device under test (DUT) to simulate the real work environment. This paper proposes a hardware module which used to signal generate and analyze. The hardware structure and diagram of logic design are described. The generated waveforms and measurement results are presented. This test module combined with other necessary modules can achieve the test of L band airborne avionics such as ATC, TCAS and TACAN.
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Tian, Zeng Hao. "MIMO Channel Research and Hardware Implementation." Applied Mechanics and Materials 543-547 (March 2014): 2581–84. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.2581.
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The MIMO technology, namely through many antenna clear signal transmission and the receive, in does not increase the extra band width under the premise, enhanced the channel capacity greatly. Understood the MIMO channel the characteristic, studies the channel modelling method, unified the FPGA parallel characteristic, the design has manufactured one kind based on XILINX FPGA the platform MIMO channel analog meter, through the massive test confirmation, and did with the theoretically simulation performance compares, has confirmed the accuracy.
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Larsson, E., and S. Edbom. "Test data truncation for test quality maximisation under ATE memory depth constraint." IET Computers & Digital Techniques 1, no. 1 (2007): 27. http://dx.doi.org/10.1049/iet-cdt:20050209.
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Shi, Zhendong, Haocheng Ma, Qizhi Zhang, Yanjiang Liu, Yiqiang Zhao, and Jiaji He. "Test Generation for Hardware Trojan Detection Using Correlation Analysis and Genetic Algorithm." ACM Transactions on Embedded Computing Systems 20, no. 4 (June 2021): 1–20. http://dx.doi.org/10.1145/3446837.
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Hardware Trojan (HT) is a major threat to the security of integrated circuits (ICs). Among various HT detection approaches, side channel analysis (SCA)-based methods have been extensively studied. SCA-based methods try to detect HTs by comparing side channel signatures from circuits under test with those from trusted golden references. The pre-condition for SCA-based HT detection to work is that the testers can collect extra signatures/anomalies introduced by activated HTs. Thus, activation of HTs and amplification of the differences between circuits under test and golden references are the keys to SCA-based HT detection methods. Test vectors are of great importance to the activation of HTs, but existing test generation methods have two major limitations. First, the number of test vectors required to trigger HTs is quite large. Second, the HT circuit’s activities are marginal compared with the whole circuit’s activities. In this article, we propose an optimized test generation methodology to assist SCA-based HT detection. Considering the HTs’ inherent surreptitious nature, inactive nodes with low transition probability are more likely to be selected as HT trigger nodes. Therefore, the correlations between circuit inputs and inactive nodes are first exploited to activate HTs. Then a test reordering process based on the genetic algorithm (GA) is implemented to increase the proportion of the HT circuit’s activities to the whole circuit’s activities. Experiments on 10 selected ISCAS benchmarks, wb_conmax benchmark, and b17 benchmark demonstrate that the number of test vectors required to trigger HTs reduces 28.8% on average compared with the result of MERO and MERS methods. After the test vector reordering process, the proportion of the HT circuit’s activities to the whole circuit’s activities is improved by 95% on average, compared with the result of MERS method.
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Han, Gu Jing, Meng Zou, and Wu Zhi Min. "Research on Deadbeat Control for Three-Phase Grid-Connected Inverter in Model Based Design." Applied Mechanics and Materials 241-244 (December 2012): 1159–63. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.1159.
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Using model based design(MBD) method, deadbeat control algorithm for three-phase grid-connected inverter was designed in optimization and realized in hardware. According to the advanced idea of MBD and its basic procedure, the software-in-loop(SIL) test, processor-in-loop(PIL) test and hardware-in-loop(HIL) test for deadbeat control algorithm were mainly researched under MATLAB/Simulink environment choosing TMS320F2812 as object hardware board. In such method, embedded codes could be produced automatically and the errors brought in through algorithm model could be tested and corrected earlier. Meanwhile, simply changing the PIL related modules, the self-defined deadbeat algorithm module could be flexibly applied in other hardware platforms. At last, the correctness and efficiency of deadbeat control algorithm were verified in three-phase grid-connected inverter experiment platform.
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Alymova, E. V., and O. V. Khachkinaev. "Automation of Software and Hardware Systems Acceptance Testing in the Paradigm of Behavior-Driven Development." Informacionnye Tehnologii 29, no. 4 (April 18, 2023): 186–96. http://dx.doi.org/10.17587/it.29.189-196.
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The paper is devoted to the problem of software and hardware systems acceptance testing according to the Agile Testing methodology. The Agile approach is widely used by software developers, however, developers of software and hardware solutions rarely use this approach, not believing in its effectiveness. The paper assumes that for software and hardware complexes, the practice of continuous integration should be applicable and, as a result, test interaction with hardware at the level ofphysical interfaces performs automatically. The article's authors presented Accepta, a system for automating acceptance testing of software and hardware complexes, explicitly designed for the Agile Testing methodology in the context of continuous integration. The main component of Accepta is an interface block based on the Nucleo-F767ZI debug board manufactured by ST. Test actions that run within the framework of Accepta supplement by expanding the command system of the interface block. The software part, which implements the functions of test describing and execution, is based on the Cucumber framework for automating software systems acceptance testing. The requirements for the object under test and the scenarios for checking the requirements are described in the Gherkin language, which is close to the natural description. The test script steps are described programmatically in the Ruby language. The actual execution of test actions is provided by sending commands through the COM port to the interface unit and analyzing the received responses. As the practice of using Accepta in working projects has shown, this approach allows us to successfully apply the Agile development methodology for software and hardware systems. Due to the automotive interaction with the device under the test interface, high intensity of testing in the development process, including regression, is ensured. The regular testing consequence is fast feedback: as soon as any functionality stops working correctly, developers find out about it fast. At the same time, due to the use of test automation tools, the reproducibility of test action sequences led to the detection of a defect is ensured.
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Wang, Zhi Shen, and Gang Yan Li. "Compensation Control Network and Test of Bus Air Brake System in Under-Pressure State." Applied Mechanics and Materials 711 (December 2014): 342–46. http://dx.doi.org/10.4028/www.scientific.net/amm.711.342.
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The paper aims at pressure compensation control of bus air brake system in under-pressure state, based on SAE J1939 protocol, using CAN bus technology, the nodes such as vehicle status data acquisition node, brake system pressure information collection node, brake pressure compensation controller node, brake actuator system node, test and diagnostic node were defined, hardware and software of communication interface were designed, under-pressure compensation control network of bus air brake system was built and test, the test results show reliability, stability, real-time of the network meet the requirements of brake control.
Dissertations / Theses on the topic "Hardware Under Test"
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Bard, Robin, and Simon Banasik. "En prestanda- och funktionsanalys av Hypervisors för molnbaserade datacenter." Thesis, Malmö högskola, Fakulteten för teknik och samhälle (TS), 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:mau:diva-20491.
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I dagens informationssamhälle pågår en växande trend av molnbaserade tjänster. Vid implementering av molnbaserade tjänster används metoden Virtualisering. Denna metod minskar behovet av antal fysiska datorsystem i ett datacenter. Vilket har en positiv miljöpåverkan eftersom energikonsumtionen minskar när hårdvaruresurser kan utnyttjas till sin fulla kapacitet. Molnbaserade tjänster skapar samhällsnytta då nya aktörer utan teknisk bakgrundskunskap snabbt kan komma igång med verksamhetsberoende tjänster. För tillämpning av Virtualisering används en så kallad Hypervisor vars uppgift är att distribuera molnbaserade tjänster. Efter utvärdering av vetenskapliga studier har vi funnit att det finns skillnader i prestanda och funktionalitet mellan olika Hypervisors. Därför väljer vi att göra en prestanda- samt funktionsanalys av Hypervisors som kommer från de största aktörerna på marknaden. Dessa är Microsoft Hyper-V Core Server 2012, Vmware ESXi 5.1.0 och Citrix XenServer 6.1.0 Free edition. Vår uppdragsgivare är försvarsmakten som bekräftade en stor efterfrågan av vår undersökning. Rapporten innefattar en teoretisk grund som beskriver tekniker bakom virtualisering och applicerbara användningsområden. Genomförandet består av två huvudsakliga metoder, en kvalitativ- respektive kvantitativ del. Grunden till den kvantitativa delen utgörs av ett standardsystem som fastställdes utifrån varje Hypervisors begränsningar. På detta standardsystem utfördes prestandatester i form av dataöverföringar med en serie automatiserade testverktyg. Syftet med testverktygen var att simulera datalaster som avsiktligt påverkade CPU och I/O för att avgöra vilka prestandaskillnader som förekommer mellan Hypervisors. Den kvalitativa undersökningen omfattade en utredning av funktionaliteter och begränsningar som varje Hypervisor tillämpar. Med tillämpning av empirisk analys av de kvantitativa mätresultaten kunde vi fastställa orsaken bakom varje Hypervisors prestanda. Resultaten visade att det fanns en korrelation mellan hur väl en Hypervisor presterat och vilken typ av dataöverföring som den utsätts för. Den Hypervisor som uppvisade goda prestandaresultat i samtliga dataöverföringar är ESXi. Resultaten av den kvalitativa undersökningen visade att den Hypervisor som offererade mest funktionalitet och minst begränsningar är Hyper-V. Slutsatsen blev att ett mindre datacenter som inte planerar en expansion bör lämpligtvis välja ESXi. Ett större datacenter som både har behov av funktioner som gynnar molnbaserade tjänster och mer hårdvaruresurser bör välja Hyper-V vid implementation av molntjänster.A growing trend of cloud-based services can be witnessed in todays information society. To implement cloud-based services a method called virtualization is used. This method reduces the need of physical computer systems in a datacenter and facilitates a sustainable environmental and economical development. Cloud-based services create societal benefits by allowing new operators to quickly launch business-dependent services. Virtualization is applied by a so-called Hypervisor whose task is to distribute cloud-based services. After evaluation of existing scientific studies, we have found that there exists a discernible difference in performance and functionality between different varieties of Hypervisors. We have chosen to perform a functional and performance analysis of Hypervisors from the manufacturers with the largest market share. These are Microsoft Hyper-V Core Server 2012, Vmware ESXi 5.1.0 and Citrix XenServer 6.1.0 Free edition. Our client, the Swedish armed forces, have expressed a great need of the research which we have conducted. The thesis consists of a theoretical base which describes techniques behind virtualization and its applicable fields. Implementation comprises of two main methods, a qualitative and a quantitative research. The basis of the quantitative investigation consists of a standard test system which has been defined by the limitations of each Hypervisor. The system was used for a series of performance tests, where data transfers were initiated and sampled by automated testing tools. The purpose of the testing tools was to simulate workloads which deliberately affected CPU and I/O to determine the performance differences between Hypervisors. The qualitative method comprised of an assessment of functionalities and limitations for each Hypervisor. By using empirical analysis of the quantitative measurements we were able to determine the cause of each Hypervisors performance. The results revealed that there was a correlation between Hypervisor performance and the specific data transfer it was exposed to. The Hypervisor which exhibited good performance results in all data transfers was ESXi. The findings in the qualitative research revealed that the Hypervisor which offered the most functionality and least amount of constraints was Hyper-V. The conclusion of the overall results uncovered that ESXi is most suitable for smaller datacenters which do not intend to expand their operations. However a larger datacenter which is in need of cloud service oriented functionalities and requires greater hardware resources should choose Hyper-V at implementation of cloud-based services.
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Mazumdar, Sushmit. "Hardware Emulation of a Long Transmission Line by High Frequency Power Electronic Converter for the study of Switching Transients." Thesis, 2019. https://etd.iisc.ac.in/handle/2005/5099.
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To ensure smooth functioning of the grid, the reliability and robustness of the power
system equipment needs to be precisely evaluated during their development process.
But direct on- eld tests of most of the equipment are not possible. This urges for
having an emulated environment which will operate in real-time thereby capturing all
the physical phenomenon of the Hardware Under Test (HUT). The control and pro-
tection equipments are generally tested by Hardware-In-The-Loop (HIL) technology,
where a Real-Time Simulator (RTS) implemented on a digital platform, interacts with
the HUT in real-time. Also high power rating devices can be tested by adopting a
di erent technology known as Power-Hardware-In-The-Loop (PHIL), where a Power
Amplifier (PA) acts as the interface between the RTS and HUT. The most expensive
component of the PHIL is the general purpose RTS like Opal-RT or RTDS. To reduce
the cost, RTS can be made application speci c. This Application Specific-Real-Time
Simulator (AS-RTS) and the PA collectively simulating the test environment for the
HUT is termed as the Hardware Emulator (HE) of that particular application. Being
the fundamental component of the power system, HE of transmission line is required
to bridge the gap between the source and load emulators. Hence a programmable
type of Transmission Line hardware Emulator (TLE) needs to be developed which
will have the
exibility of emulating transmission line with varying line parameters.
The general architecture of a TLE comprises of two major components, namely, Ob-
server and Power Ampli er, where the AS-RTS for the TLE is termed as the Observer.
With the line end voltages as the input, the Observer solves the emulated line model
in real-time and estimates the line end currents which are then tracked by the PA by
controlling its output currents. Utilizing the
exibility of controlling power electronic
converters, the PA is comprised of two back-to-back 3 Voltage Source Converters
(VSCs) operating under closed loop current control mode. Based on similar archi-
tecture, emulation for short lines during steady state and 3 short-circuit faults are
reported in literature, where the transmission line is modeled as a lumped resistor
in series with a lumped inductor. For analyzing the performance of the grid at the
transmission level, it becomes necessary to consider long lines. Emulation of a dis-
tributed parameter lossy transmission line during steady state and 3 faults using
Method of Characteristics (MOC) has also been performed. However with MOC, the
computational burden of the Observer signi cantly increases.
i
Hardware emulation of energization of a long transmission line is not addressed
in either of the previous work. Simultaneous switching of all the phases of one end
of the transmission line with a shunt reactor connected at the other end has been
studied in this work and the transients in the source end line currents during the
instant of switching has been emulated by the developed TLE. When an unenergized
transmission line is suddenly connected to a voltage source, high frequency transients
appear in the line currents due to the travelling wave phenomenon before the at-
tainment of steady state. After studying di erent line models for lossy long lines, a
travelling wave based numerical solution is identi ed which can be solved by the Ob-
server in real-time. The Observer is implemented on a Zynq System-On-Chip (SoC)
platform from Xilinx. As the transient current contains high frequency components,
the switching frequency of the VSC should be su ciently high in order to minimize
the phase loss of the current control loop of the PA. So a Silicon Carbide (SiC) based
power electronic converter has been designed and fabricated to implement the PA
of the TLE. A comprehensive analysis has been made to choose the switching fre-
quency of the power electronic converter and the sampling frequency of the Observer,
while adhering to the power and digital hardware constraints (maximum switching
frequency limit, clock speed, etc.). Further, the hardware topology for the imple-
mentation of the TLE as well as scaling of the actual transmission line to laboratory
level emulator without compromising on the system dynamics has been presented.
Finally the relevant simulation waveforms are matched with the experimental results
performed on the developed hardware prototype of the TLE, thus validating the TLE
test bench setup.
Books on the topic "Hardware Under Test"
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Hughes, Jim. Introduction to Intra-Operative and Surgical Radiography. Oxford University Press, 2018. http://dx.doi.org/10.1093/med/9780198813170.001.0001.
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This book is designed to be both a quick guide and a reference text for radiographers and other staff who perform imaging during surgical procedures. Over 40 of the most common procedures are covered in detail, from initial setup to sending final images, with sections on patient positioning, C-arm approach, anatomy, surgical hardware, and alternative techniques. These include cases related to orthopaedics, urology, paediatrics, neurology, and other branches of medicine. Each chapter covers both surgical and imaging techniques, to give the radiographer a better idea of what is required in terms of imaging and technique, along with comprehensive positioning graphics and accompanying high-quality radiograph images. The techniques and methods demonstrated are fully explained, and will allow staff to confidently perform imaging for procedures not covered in the text. Also included are sections on the practical skills required for working in theatres (such as team work and safe practice), infection control, radiation protection, exposures, and image quality, as well as discussions about the function, systems, and usage of intraoperative imaging equipment. This includes both image intensifier (II) systems and the newer flat-panel detector systems. Image artefacts and the effects of under- and overexposure are also covered, with examples of radiograph images and details on how to remedy them. Each chapter is separated by specialty and body region for quick reference and ease of navigation, while key points and imaging considerations are highlighted in each procedure for emphasis.
Book chapters on the topic "Hardware Under Test"
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Xiao, Shengping, Chengyu Zhang, Jianwen Li, and Geguang Pu. "FuzzBtor2: A Random Generator of Word-Level Model Checking Problems in Btor2 Format." In Tools and Algorithms for the Construction and Analysis of Systems, 36–43. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-30820-8_5.
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AbstractWe present , a fuzzer to generate random word-level model checking problems in Btor2 format. Btor2 is one of the mainstream input formats for word-level hardware model checking and was used in the most recent hardware model checking competition. Compared to bit-level one, word-level model checking is a more complex research field at an earlier stage of development. Therefore, it is necessary to develop a tool that can produce a large number of test cases in Btor2 format to test either existing or under-developed word-level model checkers. To evaluate the practicality of , we tested the state-of-the-art word-level model checkers and with the generated benchmarks. Experimental results show that both tools are buggy and not mature enough, which reflects the practical value of .
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Millitzer, Jonathan, Jan Hansmann, Giovanni Lapiccirella, Christoph Tamm, and Sven Herold. "Tuning and Emulation of Mechanical Characteristics – Tunable Mounts and a Mechanical Hardware-in-the-Loop Approach for More Efficient Research and Testing." In Lecture Notes in Mechanical Engineering, 129–44. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-77256-7_12.
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AbstractNumerical simulations offer a wide range of benefits, therefore they are widely used in research and development. One of the biggest benefits is the possibility of automated parameter variation. This allow testing different scenarios in a very short period of time. Nevertheless, physical experiments in the laboratory or on a test rig are still necessary and will still be necessary in the future. The physical experiments offer benefits e.g. for very complex and/or nonlinear systems and are needed for the validation of numerical models.Fraunhofer LBF has developed hardware solutions to bring the benefit of rapid and automated parameter variation to experimental environments. These solutions allow the tuning and emulation of the mechanical properties, like stiffness, damping and eigenfrequencies of structures.The work presents two approaches: First a stiffness tunable mount, which has been used in laboratory tests in the field of semi-active load path redistribution. It allowed the researcher to test the semi-active system under different mechanical boundary conditions in a short period of time. Second, a mechanical Hardware-in-the-loop (mHIL) approach for the NVH development of vehicles components is presented. Here a mHIL-system is used to emulate the mechanical characteristics of a vehicle’s body in white in a wide frequency range. This allows the experimental NVH optimization of vehicle components under realistic boundary conditions, without actually needing a (prototype) body in white.
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Simner, Ben, Alasdair Armstrong, Jean Pichon-Pharabod, Christopher Pulte, Richard Grisenthwaite, and Peter Sewell. "Relaxed virtual memory in Armv8-A." In Programming Languages and Systems, 143–73. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-99336-8_6.
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AbstractVirtual memory is an essential mechanism for enforcing security boundaries, but its relaxed-memory concurrency semantics has not previously been investigated in detail. The concurrent systems code managing virtual memory has been left on an entirely informal basis, and OS and hypervisor verification has had to make major simplifying assumptions.We explore the design space for relaxed virtual memory semantics in the Armv8-A architecture, to support future system-software verification. We identify many design questions, in discussion with Arm; develop a test suite, including use cases from the pKVM production hypervisor under development by Google; delimit the design space with axiomatic-style concurrency models; prove that under simple stable configurations our architectural model collapses to previous “user” models; develop tooling to compute allowed behaviours in the model integrated with the full Armv8-A ISA semantics; and develop a hardware test harness.This lays out some of the main issues in relaxed virtual memory bringing these security-critical systems phenomena into the domain of programming-language semantics and verification with foundational architecture semantics.
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Bruno, Giovanni di Dio. "Erwhi Hedgehog: A New Learning Platform for Mobile Robotics." In Makers at School, Educational Robotics and Innovative Learning Environments, 243–48. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-77040-2_32.
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AbstractErwhi Hedgehog is one of the smallest mobile robots. It enables mapping and vision analysis, and also displays machine learning features. Behaving like a small, curious animal, eager to explore the surroundings, the robot can be used to test navigation, mapping and localization algorithms, thus allowing the prototyping of new hardware and software for robotics. This application is particularly handy for educational robotics, at both high school and university level. On the one hand, the project is fully open source and open hardware under MIT license and available on Github, so everyone can build his/her own Erwhi Hedgehog robot with the aid of a step-by-step guide. On the other hand, students with more advanced knowledge can use it as a prototyping platform for developing new software programs and features. Erwhi uses Intel RealSense, AAEON UP Squared and Myriad X VPU technologies, with software based on the Robotic Operating System (ROS), and implements SLAM algorithms, such as RTAB-Map. The machine learning aspect is based on the OpenVINO framework and a dedicated ROS wrapper was used. The software package includes all the programs needed to create a Gazebo simulation. In terms of hardware, motor control is based on an STM32 microcontroller and the Arduino software, and the robot works on the differential drive unicycle model. Finally, Erwhi is compatible with AWS RoboMaker tools.
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Chen, Qian, Xing Zhang, Ying Wang, Zhijia Zhai, and Fen Yang. "Applying a Random Forest Approach to Imbalanced Dataset on Network Monitoring Analysis." In Communications in Computer and Information Science, 28–37. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-8285-9_2.
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AbstractSince the rapid growth of big data technology and the continuous development of information technology in recent years, the significance of network security monitoring is increasing consistently. As one of the major tools to secure the system environment, organizations use various monitoring devices to govern the utilities of networks, hardware and applications. Meanwhile, massive and redundant data are produced by these devices constantly, which make a huge problem for analysts and scientists who are willing to extract useful information from them, and even impact the accuracy and efficiency of the monitoring systems. In this paper, we employ random forest algorithm and propose an ensemble learning model under certain scenarios with fixed data features. We use a preprocessing method to balance positive and negative samples, and then use 6 different intrusion detection systems as weak classifiers, which satisfy the rules of “partial sampling” and “partial features selection” of ensemble learning. Finally, we test three combination strategies, including relative majority voting, weighted voting and stacking, to combine the predictions. Experiments show that stacking has a better performance than the other two, with a score of 98.25% in recall, and achieves a 47.91% precision.
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Karpowicz, Barbara, Rafał Masłyk, Kinga Skorupska, Daniel Jabłoński, Krzysztof Kalinowski, Paweł Kobyliński, Grzegorz Pochwatko, Monika Kornacka, and Wiesław Kopeć. "Intergenerational Interaction with Avatars in VR: An Exploratory Study Towards an XR Research Framework." In Digital Interaction and Machine Intelligence, 229–38. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-11432-8_23.
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AbstractThe dynamic development of solutions in the field of virtual and augmented reality poses challenges to designers. These challenges relate to both technical conditions, including hardware capabilities and software solutions, as well as psychophysical constructs conditioning the end users’ reception of the generated multimedia message. One of the key elements of the virtual and augmented reality experience is the interaction with the system through a virtual agent represented by an avatar, i.e. a reflection of the image of a participant in the virtual world, carrying on a conversation with the user. This paper presents a proposed software and hardware solution for conducting multifaceted research and comparative analysis of diverse interfaces and human-computer interaction in virtual and augmented reality. In the course of this research, statistically significant results were obtained indicating differences in perception between three types of virtual agents. Each of them represented by different avatars in a specially created research environment that allowed to conduct usability tests under reproducible conditions to study user interaction in virtual reality.
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Sowmika, Muthyala, Manchalla O. V. P. Kumar, Kiran Mannem, and K. Jamal. "BIST Application of DCM Based True Random Number Generator." In Advances in Transdisciplinary Engineering. IOS Press, 2023. http://dx.doi.org/10.3233/atde221311.
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A hardware random number generator is designed with the help of digital clock manager. The number is evenly distributed in a random manner. Each number in the series is individualistic. The generated random number is unpredictable. Therefore they are used in key generation. Such keys are used to secure the transferred information. Built-in self test is an application of TRNG. Built-in self testing enables the circuit to test for any faults. BIST is a procedure where a circuit is designed so that it tests itself and describes whether it is faulty or fault free. A true random number which is generated using DCM is put in the circuit which is under testing. The corresponding circuit is vedic multiplier. The faults in the circuit under test are detected using built-in self test process. The software tool used for programming part is Xilinx suite 14.3.
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Donnarumma, Silvia, Camilla Fruzzetti, Michele Martelli, Roberto Chiti, Andrea Pecoraro, and Luca Sebastiani. "Rapid Prototyping for Enhanced Dynamic Positioning Systems." In Progress in Marine Science and Technology. IOS Press, 2022. http://dx.doi.org/10.3233/pmst220075.
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The paper aims to show the design procedure for a Class-2 dynamic positioning system, from initial conceptualisation upon factory assessment test. The approach involves the use of simulation–based design combined with hardware–in–the–loop testing. This kind of approach involves a detailed knowledge of the investigated ship but gives significant well-known advantages. A custom simulation platform has been developed to have realistic feedbacks of the case-study ship. The dynamic positioning controller structure, including regulator, force and thrust allocation; have been conceptualised, and then, after the porting procedure, the dynamic positioning software has been downloaded in the real programmable logic controller. Several hardware–in–the–loop tests have been carried out to fine-tune the controller parameters. The results show, under different environmental conditions, the respect of the design criteria.
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Kosmatov, Nikolai. "Concolic Test Generation and the Cloud." In Cloud Technology, 302–22. IGI Global, 2015. http://dx.doi.org/10.4018/978-1-4666-6539-2.ch014.
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Software testing in the cloud can reduce the need for hardware and software resources and offer a flexible and efficient alternative to the traditional software testing process. A major obstacle to the wider use of testing in the cloud is related to security issues. This chapter focuses on test generation techniques that combine concrete and symbolic execution of the program under test. Their deployment in the cloud leads to complex technical and security issues that do not occur for other testing methods. This chapter describes recent online deployment of such a technique implemented by the PathCrawler test generation tool for C programs, where the author faced, studied, and solved many of these issues. Mixed concrete/symbolic testing techniques not only constitute a challenging target for deployment in the cloud, but they also provide a promising way to improve the reliability of cloud environments. The author argues that these techniques can be efficiently used to help to create trustworthy cloud environments.
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Ouadi, Abderrahmane, Abdelkader Zitouni, and Ahmed Maache. "Advanced Real-Time Tester for a Smart Power Grid." In Advances in Computer and Electrical Engineering, 309–21. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-4027-5.ch013.
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The testing approach is facing many difficulties regarding the actual implementations in the modern smart power grids. One of these challenges is the testing of hardware devices such as protective relays, PMUs, and smart meters before its final deployment to the power grid. One way to overcome this is the real-time simulation of power grid. The hardware-under-test (HuT) is plugged to a real-time simulator via signal conditioning circuit (SCC). SCC is an interface circuit involving power amplifier and measurement sub-circuit between the real-time power grid simulator and the HuT. In this chapter, some advanced developed techniques and approaches will be presented.
Conference papers on the topic "Hardware Under Test"
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Zahid, Ussama, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, and Kees Vissers. "FAT: Training Neural Networks for Reliable Inference Under Hardware Faults." In 2020 IEEE International Test Conference (ITC). IEEE, 2020. http://dx.doi.org/10.1109/itc44778.2020.9325249.
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Feng, Ying Jun, Lei Zeng, Yu Chen, Xiao Dong Liu, Tao Li, Qi Xie, and Xiao Yuan Chen. "Hardware Design and Test of a Cryogenic Boost Chopper Under 77K." In 2018 IEEE International Conference on Applied Superconductivity and Electromagnetic Devices (ASEMD). IEEE, 2018. http://dx.doi.org/10.1109/asemd.2018.8558962.
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Lee, Seogoo, Lizy K. John, and Andreas Gerstlauer. "High-level synthesis of approximate hardware under joint precision and voltage scaling." In 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2017. http://dx.doi.org/10.23919/date.2017.7926980.
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Millican, Spencer K., and Kewal K. Saluja. "Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints." In 2015 28th International Conference on VLSI Design (VLSID). IEEE, 2015. http://dx.doi.org/10.1109/vlsid.2015.88.
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PEREIRA FILHO, R. D., V. B. FURLONG, and J. A. V. COSTA. "ARDUINO OPEN HARDWARE TEST THROUGH CHEMICAL SYSTEM SIMULATION UNDER LUMPED MODEL DYNAMICS." In XX Congresso Brasileiro de Engenharia Química. São Paulo: Editora Edgard Blücher, 2015. http://dx.doi.org/10.5151/chemeng-cobeq2014-0331-25973-155876.
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Kadim, H. J. "Analytical Modelling of Power Attenuation under Parameter Fluctuations with Applications to Self-Test and Repair." In First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06). IEEE, 2006. http://dx.doi.org/10.1109/ahs.2006.24.
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Demarest, J., N. Arnold, K. Brew, V. Chan, A. Cote, T. Gordon, M. Iwatake, et al. "Failure Analysis Challenges of Phase Change Memory Test Structures with Two Case Studies." In ISTFA 2021. ASM International, 2021. http://dx.doi.org/10.31399/asm.cp.istfa2021p0034.
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Abstract There are several variants of artificial intelligence (AI) hardware structures that are under study by the semiconductor industry for potential use in complementary metal–oxide–semiconductor (CMOS) designs. This paper discusses some of the failure analysis challenges that have appeared in discrete test structures and test arrays developed as part of an exploratory phase-change memory (PCM) program at IBM's Albany AI Hardware Research Center.
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Sinha, K., M. Al-Bassyiouni, P. Hansen, A. Dasgupta, P. McCluskey, R. Beaupre, and J. Jacobsen. "Test Methodologies for Power Cycling Experiment." In ASME 2009 International Mechanical Engineering Congress and Exposition. ASMEDC, 2009. http://dx.doi.org/10.1115/imece2009-11074.
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When compared to temperature distributions in an actual application, thermal cycling is not a complete representation of the thermal gradients found in functional electronics under power-on condition. This discrepancy is particularly severe in power electronics and it distorts the thermo-mechanical stresses experienced at the joints and interfaces of power devices. Accelerated stress tests for power electronics are therefore better conducted with accelerated power cycling experiments rather than with accelerated thermal cycling, because the power cycles simulate more closely accelerated versions of an application cycle where the junction temperature of the die rises and falls as the power is turned off and on. However, developing a power cycling test setup can be comparatively more challenging than temperature cycling test setup, because of the complex triggering circuitry and logic needed for rapid power cycling, power circuitry needed to supply the large wattage safely to the devices under test, thermal cooling system to remove the high amount of heat generated, and software/hardware to control the test setup to maintain the right operational parameters. In this study, a test setup has been developed to power cycle IGBT and bipolar semiconductor devices for accelerated durability tests. The test setup is described and the role of each hardware and software component in the test setup is elaborated. Sample test results are presented, to illustrate the capabilities of the test setup. This work adds to the state of the art of power cycling experiments and improves our understanding of ways to develop stable power cycling test setups for various kinds of applications.
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Oravec, Heather A., Christopher C. Daniels, and Janice L. Mather. "Validation of Test Methods for Air Leak Rate Verification of Spaceflight Hardware." In ASME 2017 Fluids Engineering Division Summer Meeting. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/fedsm2017-69076.
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As deep space exploration continues to be the goal of NASA’s human spaceflight program, verification of the performance of spaceflight hardware becomes increasingly critical. Suitable test methods for verifying the leak rate of sealing systems are identified in program qualification testing requirements. One acceptable method for verifying the air leak rate of gas pressure seals is the tracer gas leak detector method. In this method, a tracer gas (commonly helium) leaks past the test seal and is transported to the leak detector where the leak rate is quantified. To predict the air leak rate, a conversion factor of helium-to-air is applied depending on the magnitude of the helium flow rate. The conversion factor is based on either the molecular mass ratio or the ratio of the dynamic viscosities. The current work was aimed at validating this approach for permeation-level leak rates using a series of tests with a silicone elastomer O-ring. An established pressure decay method with constant differential pressure was used to evaluate both the air and helium leak rates of the O-ring under similar temperature and pressure conditions. The results from the pressure decay tests showed, for the elastomer O-ring, that neither the molecular flow nor the viscous flow helium-to-air conversion factors were applicable. Leak rate tests were also performed using nitrogen and argon as the test gas. Molecular mass and viscosity based helium-to-test gas conversion factors were applied, but did not correctly predict the measured leak rates of either gas. To further this study, the effect of pressure boundary conditions was investigated. Often, pressure decay leak rate tests are performed at a differential pressure of 101.3 kPa with atmospheric pressure on the downstream side of the test seal. In space applications, the differential pressure is similar, but with vacuum as the downstream pressure. The same O-ring was tested at four unique differential pressures ranging from 34.5 to 137.9 kPa. Up to six combinations of upstream and downstream pressures for each differential pressure were compared. For a given differential pressure, the various combinations of upstream and downstream dry air pressures did not significantly affect the leak rate. As expected, the leak rate of the O-ring increased with increasing differential pressure. The results suggested that the current leak test pressure conditions, used to verify spacecraft sealing systems with elastomer seals, produce accurate values even though the boundary conditions do not model the space application.
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Viennet, Emmanuel, Nicolas Ramosaj, and Christian Fusco. "Development of a Hardware-in-the-Loop Test Bench for Validation of an ABS System on an e-Bike." In The Evolving Scholar - BMD 2023, 5th Edition. The Evolving Scholar - BMD 2023, 5th Edition, 2023. http://dx.doi.org/10.59490/649d9ceb4adb98a3b887079f.
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The availability of electric energy onboard e-bikes allows the emergence of active safety systems like antilock braking systems (ABS). This paper presents the development of a test-bench that can be leveraged to validate an e-bike ABS for multiple bicycle geometry, loading and test scenarios. The approach consists in reproducing the dynamics of an e-bike thanks to a simulation model and interfacing it with a physical brake and the ABS hardware under test. The results and useability of the obtained hardware-in-the-loop (HiL) test-bench are discussed.
Reports on the topic "Hardware Under Test"
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Wang, Shenlong, and David Forsyth. Safely Test Autonomous Vehicles with Augmented Reality. Illinois Center for Transportation, August 2022. http://dx.doi.org/10.36501/0197-9191/22-015.
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This work exploits augmented reality to safely train and validate autonomous vehicles’ performance in the real world under safety-critical scenarios. Toward this goal, we first develop algorithms that create virtual traffic participants with risky behaviors and seamlessly insert the virtual events into real images perceived from the physical world. The resulting composed images are photorealistic and physically grounded. The manipulated images are fed into the autonomous vehicle during testing, allowing the self-driving vehicle to react to such virtual events within either a photorealistic simulator or a real-world test track and real hardware systems. Our presented technique allows us to develop safe, hardware-in-the-loop, and cost-effective tests for self-driving cars to respond to immersive safety-critical traffic scenarios.
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Cao Romero, Julio A., Jorge Reyes-Avendaño, Julio Soriano, Leonardo Farfan-Cabrera, and Ali Erdemir. A Pin-on-Disc Study on the Electrified Sliding Wear of EVs Powertrain Gears. SAE International, March 2022. http://dx.doi.org/10.4271/2022-01-0320.
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In contrast to conventional powertrains from internal combustion engine vehicles (ICEV), the tribological performance of powertrains of electric vehicles (EVs) must be further evaluated by considering new critical operating conditions such as electrical environments. The operation of any type of electric motor produces shaft voltages and currents due to various hardware configurations and factors. Furthermore, the common application of inverters intensifies this problem. It has been reported that the induced shaft voltages and currents can cause premature failure problems in tribological components such as bearings and gears due to accelerated wear and/or fatigue. It is ascribed to effects of electric discharge machining (EDM), also named, sparking wear caused by shaft currents and poor or increasingly diminishing dielectric strength of lubricants. A great effort has been done to study this problem in bearings, but it has not yet been the case for gears. Considering that EVs powertrains can be configurated with an electric motor coupled to a single-speed or multi-speed transmission, it is expected that shaft currents can also affect gears to some extent. The pin-on-disc test has been widely used to study sliding wear of gear materials under comparable or realistic operating conditions. This accelerated test is effective for screening materials, lubricants and operating conditions allowing evaluations of their friction and wear properties. However, it has not been implemented for studying gear materials under electrified environments. Thus, this paper aims to explore the friction coefficient and wear of gear materials under non-electrified and electrified sliding in a pin-on-disc tester applying typical of EVs powertrain shaft currents during sliding. The tests were carried out at two different DC currents under comparable gear dry and lubricated sliding contact conditions. Friction coefficient, wear volumes and morphologies were evaluated and reported in this work.
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Tao, Yang, Amos Mizrach, Victor Alchanatis, Nachshon Shamir, and Tom Porter. Automated imaging broiler chicksexing for gender-specific and efficient production. United States Department of Agriculture, December 2014. http://dx.doi.org/10.32747/2014.7594391.bard.
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Extending the previous two years of research results (Mizarch, et al, 2012, Tao, 2011, 2012), the third year’s efforts in both Maryland and Israel were directed towards the engineering of the system. The activities included the robust chick handling and its conveyor system development, optical system improvement, online dynamic motion imaging of chicks, multi-image sequence optimal feather extraction and detection, and pattern recognition. Mechanical System Engineering The third model of the mechanical chick handling system with high-speed imaging system was built as shown in Fig. 1. This system has the improved chick holding cups and motion mechanisms that enable chicks to open wings through the view section. The mechanical system has achieved the speed of 4 chicks per second which exceeds the design specs of 3 chicks per second. In the center of the conveyor, a high-speed camera with UV sensitive optical system, shown in Fig.2, was installed that captures chick images at multiple frames (45 images and system selectable) when the chick passing through the view area. Through intensive discussions and efforts, the PIs of Maryland and ARO have created the protocol of joint hardware and software that uses sequential images of chick in its fall motion to capture opening wings and extract the optimal opening positions. This approached enables the reliable feather feature extraction in dynamic motion and pattern recognition. Improving of Chick Wing Deployment The mechanical system for chick conveying and especially the section that cause chicks to deploy their wings wide open under the fast video camera and the UV light was investigated along the third study year. As a natural behavior, chicks tend to deploy their wings as a mean of balancing their body when a sudden change in the vertical movement was applied. In the latest two years, this was achieved by causing the chicks to move in a free fall, in the earth gravity (g) along short vertical distance. The chicks have always tended to deploy their wing but not always in wide horizontal open situation. Such position is requested in order to get successful image under the video camera. Besides, the cells with checks bumped suddenly at the end of the free falling path. That caused the chicks legs to collapse inside the cells and the image of wing become bluer. For improving the movement and preventing the chick legs from collapsing, a slowing down mechanism was design and tested. This was done by installing of plastic block, that was printed in a predesign variable slope (Fig. 3) at the end of the path of falling cells (Fig.4). The cells are moving down in variable velocity according the block slope and achieve zero velocity at the end of the path. The slop was design in a way that the deacceleration become 0.8g instead the free fall gravity (g) without presence of the block. The tests showed better deployment and wider chick's wing opening as well as better balance along the movement. Design of additional sizes of block slops is under investigation. Slops that create accelerations of 0.7g, 0.9g, and variable accelerations are designed for improving movement path and images.