Journal articles: 'Hardware / Software Codesign'

1

Gupta, P. "Hardware-software codesign." IEEE Potentials 20, no. 5 (2002): 31–32. http://dx.doi.org/10.1109/45.983337.

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Jerraya, A. "Hardware-software codesign." IEEE Design and Test of Computers 17, no. 1 (January 2000): 92–99. http://dx.doi.org/10.1109/mdt.2000.825680.

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3

Maillet-Contoz, L. "Codesign [hardware/software partitioning]." IEEE Potentials 16, no. 4 (1997): 13–14. http://dx.doi.org/10.1109/45.624333.

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4

De Micheli, G. "Computer-aided hardware-software codesign." IEEE Micro 14, no. 4 (August 1994): 10–16. http://dx.doi.org/10.1109/40.296153.

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5

Färber, G. "Hardware-Software-Codesign eingebetteter Systeme." e & i Elektrotechnik und Informationstechnik 115, no. 3 (March 1998): 128–37. http://dx.doi.org/10.1007/bf03159563.

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6

Hsiung, Pao-Ann. "Embedded software verification in hardware–software codesign." Journal of Systems Architecture 46, no. 15 (December 2000): 1435–50. http://dx.doi.org/10.1016/s1383-7621(00)00034-5.

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7

Chiodo, M., P. Giusto, A. Jurecska, H. C. Hsieh, A. Sangiovanni-Vincentelli, and L. Lavagno. "Hardware-software codesign of embedded systems." IEEE Micro 14, no. 4 (August 1994): 26–36. http://dx.doi.org/10.1109/40.296155.

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8

Kuttner, C. "Hardware-software codesign using processor synthesis." IEEE Design & Test of Computers 13, no. 3 (1996): 43–53. http://dx.doi.org/10.1109/54.536095.

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9

Schrott, G., and T. Tempelmeier. "Putting Hardware-Software Codesign into Practice." IFAC Proceedings Volumes 30, no. 23 (September 1997): 15–22. http://dx.doi.org/10.1016/s1474-6670(17)41385-1.

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Schrott, G., and T. Tempelmeier. "Putting hardware–software codesign into practice." Control Engineering Practice 6, no. 3 (March 1998): 397–402. http://dx.doi.org/10.1016/s0967-0661(98)00019-7.

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11

Tempelmeier, T. "A note on hardware-software codesign." Annual Review in Automatic Programming 18 (January 1994): 121–26. http://dx.doi.org/10.1016/0066-4138(94)90021-3.

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12

Kumar, S., J. H. Aylor, B. W. Johnson, and W. A. Wulf. "A framework for hardware/software codesign." Computer 26, no. 12 (December 1993): 39–45. http://dx.doi.org/10.1109/2.247650.

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13

Plaks, ToomasP, MarcoD Santambrogio, and Donatella Sciuto. "Reconfigurable Computing and Hardware/Software Codesign." EURASIP Journal on Embedded Systems 2008, no. 1 (2008): 731830. http://dx.doi.org/10.1155/2008/731830.

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14

Wolf, W. "A decade of hardware/ software codesign." Computer 36, no. 4 (April 2003): 38–43. http://dx.doi.org/10.1109/mc.2003.1193227.

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15

Gong, Jie, Daniel D. Gajski, and Smita Bakshi. "Model refinement for hardware-software codesign." ACM Transactions on Design Automation of Electronic Systems 2, no. 1 (January 1997): 22–41. http://dx.doi.org/10.1145/250243.250247.

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16

Tempelmeier, T. "A Note on Hardware-Software Codesign." IFAC Proceedings Volumes 27, no. 6 (June 1994): 121–26. http://dx.doi.org/10.1016/s1474-6670(17)45977-5.

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17

Harrison, J. "Editorial: Hardware/software codesign for embedded systems." IEE Proceedings - Computers and Digital Techniques 145, no. 3 (1998): 153. http://dx.doi.org/10.1049/ip-cdt:19982052.

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18

Olivito, Javier, Javier Resano, and Jose Luis Briz. "Accelerating Board Games Through Hardware/Software Codesign." IEEE Transactions on Computational Intelligence and AI in Games 9, no. 4 (December 2017): 393–401. http://dx.doi.org/10.1109/tciaig.2016.2604923.

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19

Shalf, John, Dan Quinlan, and Curtis Janssen. "Rethinking Hardware-Software Codesign for Exascale Systems." Computer 44, no. 11 (November 2011): 22–30. http://dx.doi.org/10.1109/mc.2011.300.

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Hwang, Yin-Tsung, Jer-Sho Hwang, and Yuan-Hung Wang. "Hardware/software codesign for embedded signal processing." Computer Standards & Interfaces 20, no. 6-7 (March 1999): 440. http://dx.doi.org/10.1016/s0920-5489(99)90903-0.

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21

Jerraya, A. A., and W. Wolf. "Hardware/software interface codesign for embedded systems." Computer 38, no. 2 (February 2005): 63–69. http://dx.doi.org/10.1109/mc.2005.61.

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22

Martin, Grant. "Will hardware and software be codesigned? [review of "A Practical Introduction to Hardware/Software Codesign" (Schaumont, P.R.; 2010)]." IEEE Design & Test of Computers 28, no. 2 (March 2011): 70–73. http://dx.doi.org/10.1109/mdt.2011.41.

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23

Schaumont, Patrick. "A Senior-Level Course in Hardware–Software Codesign." IEEE Transactions on Education 51, no. 3 (August 2008): 306–11. http://dx.doi.org/10.1109/te.2007.910434.

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24

Knudsen, P. V., and J. Madsen. "Integrating communication protocol selection with hardware/software codesign." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18, no. 8 (1999): 1077–95. http://dx.doi.org/10.1109/43.775629.

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25

Thomas, D. E., J. K. Adams, and H. Schmit. "A model and methodology for hardware-software codesign." IEEE Design & Test of Computers 10, no. 3 (September 1993): 6–15. http://dx.doi.org/10.1109/54.232468.

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26

Kalavade, A., and E. A. Lee. "A hardware-software codesign methodology for DSP applications." IEEE Design & Test of Computers 10, no. 3 (September 1993): 16–28. http://dx.doi.org/10.1109/54.232469.

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27

Shannon, Lesley, and Paul Chow. "Leveraging reconfigurability in the hardware/software codesign process." ACM Transactions on Reconfigurable Technology and Systems 4, no. 3 (August 2011): 1–27. http://dx.doi.org/10.1145/2000832.2000840.

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28

Abdallah, A., E. M. Feron, G. Hellestrand, P. Koopman, and M. Wolf. "Hardware/Software Codesign of Aerospace and Automotive Systems." Proceedings of the IEEE 98, no. 4 (April 2010): 584–602. http://dx.doi.org/10.1109/jproc.2009.2036747.

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29

Ha, Soonhoi. "Prolog to the Section on Hardware/Software Codesign." Proceedings of the IEEE 100, Special Centennial Issue (May 2012): 1409–10. http://dx.doi.org/10.1109/jproc.2012.2187138.

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30

Tokuno, Koichi, and Shigeru Yamada. "Codesign-Oriented Performability Modeling for Hardware-Software Systems." IEEE Transactions on Reliability 60, no. 1 (March 2011): 171–79. http://dx.doi.org/10.1109/tr.2010.2103991.

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31

Cabrera, A., S. Sánchez-Solano, P. Brox, A. Barriga, and R. Senhadji. "Hardware/software codesign of configurable fuzzy control systems." Applied Soft Computing 4, no. 3 (August 2004): 271–85. http://dx.doi.org/10.1016/j.asoc.2004.03.006.

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32

Bertels, Koen, Vlad-Mihai Sima, Yana Yankova, Georgi Kuzmanov, Wayne Luk, Gabriel Coutinho, Fabrizio Ferrandi, et al. "HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms." IEEE Micro 30, no. 5 (September 2010): 88–97. http://dx.doi.org/10.1109/mm.2010.91.

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33

Guo, Kaiyuan, Song Han, Song Yao, Yu Wang, Yuan Xie, and Huazhong Yang. "Software-Hardware Codesign for Efficient Neural Network Acceleration." IEEE Micro 37, no. 2 (March 2017): 18–25. http://dx.doi.org/10.1109/mm.2017.39.

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34

Steger, C., C. Bachmann, A. Genser, R. Weiss, and J. Haid. "Power-aware hardware/software codesign of mobile devices." e & i Elektrotechnik und Informationstechnik 127, no. 11 (November 2010): 327–34. http://dx.doi.org/10.1007/s00502-010-0784-4.

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35

Wang, Chao, Xi Li, Xuehai Zhou, Nadia Nedjah, and Aili Wang. "Codem: software/hardware codesign for embedded multicore systems supporting hardware services." International Journal of Electronics 102, no. 1 (July 23, 2014): 32–47. http://dx.doi.org/10.1080/00207217.2014.938312.

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36

Lu, Xu Ming, Wei Jie Wen, and Hong Zhou Tan. "A Prototyping Environment for Hardware/Software Codesign of OFDM Systems." Applied Mechanics and Materials 380-384 (August 2013): 2803–6. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.2803.

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To make rapid implementation and verification for the systems becomes important in frontend Application Specific Integrated Circuits. Therefore, a field programmable gate array based hardware/software codesign prototyping environment is proposed to simulate the software implementation and verify the hardware implementation of a baseband OFDM system. The system is implemented by software and hardware partitions, respectively. The analog radio frequency front-end module helps take a full insight into the actual baseband system performance. User datagram protocol is used for data transmission between these two partitions, and hence makes a complete baseband system. With the proposed codesign environment, the software simulation is running over real wireless channels, and the hardware implemental results can be flexibly processed in real time and enhances the design efficiency.

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37

Iguider, Adil, Oussama Elissati, Abdeslam En-Nouaary, and Mouhcine Chami. "Shortest Path Method for Hardware/Software Partitioning Problems." International Journal of Information Systems and Social Change 12, no. 3 (July 2021): 40–57. http://dx.doi.org/10.4018/ijissc.2021070104.

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Smart systems are becoming more present in every aspect of our daily lives. The main component of such systems is an embedded system; this latter assures the collection, the treatment, and the transmission of the accurate information in the right time and for the right component. Modern embedded systems are facing several challenges; the objective is to design a system with high performance and to decrease the cost and the development time. Consequently, some robust methodologies like the Codesign were developed to fulfill those requirements. The most important step of the Codesign is the partitioning of the systems' functionalities between a hardware set and a software set. This article deals with this problem and uses a heuristic approach based on shortest path optimizations to solve the problem. The aim is to minimize the total hardware area and to respect a constraint on the overall execution time of the system. Experiments results demonstrate that the proposed method is very fast and gives better results compared to the genetic algorithm.

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38

Oliveira, Samuel M. D., and Douglas Densmore. "Hardware, Software, and Wetware Codesign Environment for Synthetic Biology." BioDesign Research 2022 (September 2, 2022): 1–15. http://dx.doi.org/10.34133/2022/9794510.

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Synthetic biology is the process of forward engineering living systems. These systems can be used to produce biobased materials, agriculture, medicine, and energy. One approach to designing these systems is to employ techniques from the design of embedded electronics. These techniques include abstraction, standards, modularity, automated design, and formal semantic models of computation. Together, these elements form the foundation of “biodesign automation,” where software, robotics, and microfluidic devices combine to create exciting biological systems of the future. This paper describes a “hardware, software, wetware” codesign vision where software tools can be made to act as “genetic compilers” that transform high-level specifications into engineered “genetic circuits” (wetware). This is followed by a process where automation equipment, well-defined experimental workflows, and microfluidic devices are explicitly designed to house, execute, and test these circuits (hardware). These systems can be used as either massively parallel experimental platforms or distributed bioremediation and biosensing devices. Next, scheduling and control algorithms (software) manage these systems’ actual execution and data analysis tasks. A distinguishing feature of this approach is how all three of these aspects (hardware, software, and wetware) may be derived from the same basic specification in parallel and generated to fulfill specific cost, performance, and structural requirements.

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39

Khusainov, Bulat, Eric C. Kerrigan, and George A. Constantinides. "Automatic Software and Computing Hardware Codesign for Predictive Control." IEEE Transactions on Control Systems Technology 27, no. 5 (September 2019): 2295–304. http://dx.doi.org/10.1109/tcst.2018.2855666.

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40

Ou, Jingzhao, and ViktorK Prasanna. "Rapid Energy Estimation for Hardware-Software Codesign Using FPGAs." EURASIP Journal on Embedded Systems 2006, no. 1 (2006): 098045. http://dx.doi.org/10.1186/1687-3963-2006-098045.

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41

Slomka, F., M. Dorfel, R. Munzenberger, and R. Hofmann. "Hardware/software codesign and rapid prototyping of embedded systems." IEEE Design & Test of Computers 17, no. 2 (2000): 28–38. http://dx.doi.org/10.1109/54.844331.

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42

Chen, Kui-Ting, Xiao Wu, Molin Jia, and Takaaki Baba. "A Flexible Hardware/Software Codesign for Particle Swarm Optimization." Journal of Signal Processing 17, no. 4 (2013): 107–10. http://dx.doi.org/10.2299/jsp.17.107.

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43

Metri, Grace, Manuj Sabharwal, Sundar Iyer, and Abhishek Agrawal. "Hardware/Software Codesign to Optimize SoC Device Battery Life." Computer 46, no. 10 (October 2013): 89–92. http://dx.doi.org/10.1109/mc.2013.353.

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44

Alonso, Alejandro, Luis Sánchez, Angel Groba, Simon Pickin, Natividad Martínez, and Juan A. de la Puente. "Development of computer control systems with hardware-software codesign." IFAC Proceedings Volumes 32, no. 2 (July 1999): 8722–27. http://dx.doi.org/10.1016/s1474-6670(17)57488-1.

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45

Moreau, Jean-Pierre, Philippe di Crescenzo, and Lloyd Pople. "Hardware software system codesign based on SDL/C specifications." Microelectronic Engineering 54, no. 1-2 (December 2000): 181–91. http://dx.doi.org/10.1016/s0167-9317(00)80069-6.

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46

Boujarwah, A., I. Ahmad, K. Saleh, and M. K. Dhodhi. "Hardware/software codesign in the Estelle and VHDL environments." Computer Standards & Interfaces 17, no. 3 (June 1995): 253–76. http://dx.doi.org/10.1016/0920-5489(95)00004-e.

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47

Bhattacharyya, S. S., J. Henkel, and Xiaobo Sharon Hu. "Hardware/software codesign for DSP (from the Guest Editor)." IEEE Signal Processing Magazine 22, no. 3 (May 2005): 11–12. http://dx.doi.org/10.1109/msp.2005.1425892.

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48

Ou, Jingzhao. "Rapid Energy Estimation for Hardware-Software Codesign Using FPGAs." EURASIP Journal on Embedded Systems 2006 (2006): 1–11. http://dx.doi.org/10.1155/es/2006/98045.

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49

Jaziri, Ibtihel, Lotfi Charaabi, and Khaled Jelassi. "Codesign Methodology based FPGA and Embedded Linux for Motor Control." Indonesian Journal of Electrical Engineering and Computer Science 9, no. 1 (January 1, 2018): 204. http://dx.doi.org/10.11591/ijeecs.v9.i1.pp204-211.

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<p>Recently, the complexity of the embedded electrical systems is increasing due to the growing of industrial necessities. To handle with this complexity, the use of reconfigurable hardware/software codesign methodology using digital platforms becomes necessary. Reconfigurable methodology can be seen as an essential feature in motor control systems as it offers many advantages such as increased flexibility, low energy consumption. In these kind of systems, both hardware and software designs can be reconfigurated depending upon the designer requirements. This paper presents hardware/software codesign methodology with flexible hardware devices and configurable graphical user interface: the hardware architecture is based on field-programmable gate array and the software architecture is based on embedded Linux operating system running on Beaglebone. The user interface is designed as a graphical user interface developed on an emebdded server; this enables the user to access to the system rapidly, parameterize and observe the behavior of the controller.</p>

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50

Allam, Atef, and Wael Deabes. "Model-Based Hardware-Software Codesign of ECT Digital Processing Unit." Modelling and Simulation in Engineering 2021 (March 30, 2021): 1–14. http://dx.doi.org/10.1155/2021/4757464.

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Image reconstruction algorithm and its controller constitute the main modules of the electrical capacitance tomography (ECT) system; in order to achieve the trade-off between the attainable performance and the flexibility of the image reconstruction and control design of the ECT system, hardware-software codesign of a digital processing unit (DPU) targeting FPGA system-on-chip (SoC) is presented. Design and implementation of software and hardware components of the ECT-DPU and their integration and verification based on the model-based design (MBD) paradigm are proposed. The inner-product of large vectors constitutes the core of the majority of these ECT image reconstruction algorithms. Full parallel implementation of large vector multiplication on FPGA consumes a huge number of resources and incurs long combinational path delay. The proposed MBD of the ECT-DPU tackles this problem by crafting a parametric segmented parallel inner-product architecture so as to work as the shared hardware core unit for the parallel matrix multiplication in the image reconstruction and control of the ECT system. This allowed the parameterized core unit to be configured at system-level to tackle large matrices with the segment length working as a design degree of freedom. It allows the trade-off between performance and resource usage and determines the level of computation parallelism. Using MBD with the proposed segmented architecture, the system design can be flexibly tailored to the designer specifications to fulfill the required performance while meeting the resources constraint. In the linear-back projection image reconstruction algorithm, the segmentation scheme has exhibited high resource saving of 43% and 71% for a small degradation in a frame rate of 3% and 14%, respectively.

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Journal articles on the topic 'Hardware / Software Codesign'

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