Dissertations / Theses on the topic 'Hardware / Software Codesign'
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Hilton, Adrian J. "High integrity hardware-software codesign." Thesis, Open University, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.402249.
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King, Myron Decker. "A methodology for hardware-software codesign." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84891.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 150-156).
Special purpose hardware is vital to embedded systems as it can simultaneously improve performance while reducing power consumption. The integration of special purpose hardware into applications running in software is difficult for a number of reasons. Some of the difficulty is due to the difference between the models used to program hardware and software, but great effort is also required to coordinate the simultaneous execution of the application running on the microprocessor with the accelerated kernel(s) running in hardware. To further compound the problem, current design methodologies for embedded applications require an early determination of the design partitioning which allows hardware and software to be developed simultaneously, each adhering to a rigid interface contract. This approach is problematic because often a good hardware-software decomposition is not known until deep into the design process. Fixed interfaces and the burden of reimplementation prevent the migration of functionality motivated by repartitioning. This thesis presents a two-part solution to the integration of special purpose hardware into applications running in software. The first part addresses the problem of generating infrastructure for hardware-accelerated applications. We present a methodology in which the application is represented as a dataflow graph and the computation at each node is specified for execution either in software or as specialized hardware using the programmer's language of choice. An interface compiler as been implemented which takes as input the FIFO edges of the graph and generates code to connect all the different parts of the program, including those which communicate across the hardware/software boundary. This methodology, which we demonstrate on an FPGA platform, enables programmers to effectively exploit hardware acceleration without ever leaving the application space. The second part of this thesis presents an implementation of the Bluespec Codesign Language (BCL) to address the difficulty of experimenting with hardware/software partitioning alternatives. Based on guarded atomic actions, BCL can be used to specify both hardware and low-level software. Based on Bluespec SystemVerilog (BSV) for which a hardware compiler by Bluespec Inc. is commercially available, BCL has been augmented with extensions to support more efficient software generation. In BCL, the programmer specifies the entire design, including the partitioning, allowing the compiler to synthesize efficient software and hardware, along with transactors for communication between the partitions. The benefit of using a single language to express the entire design is that a programmer can easily experiment with many different hardware/software decompositions without needing to re-write the application code. Used together, the BCL and interface compilers represent a comprehensive solution to the task of integrating specialized hardware into an application.
by Myron King.
Ph.D.
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Dave, Nirav Hemant 1982. "A unified model for hardware/software codesign." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/68171.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student submitted PDF version of thesis.
Includes bibliographical references (p. 179-188).
Embedded systems are almost always built with parts implemented in both hardware and software. Market forces encourage such systems to be developed with dierent hardware-software decompositions to meet dierent points on the price-performance-power curve. Current design methodologies make the exploration of dierent hardware-software decompositions difficult because such exploration is both expensive and introduces signicant delays in time-to-market. This thesis addresses this problem by introducing, Bluespec Codesign Language (BCL), a united language model based on guarded atomic actions for hardware-software codesign. The model provides an easy way of specifying which parts of the design should be implemented in hardware and which in software without obscuring important design decisions. In addition to describing BCL's operational semantics, we formalize the equivalence of BCL programs and use this to mechanically verify design refinements. We describe the partitioning of a BCL program via computational domains and the compilation of dierent computational domains into hardware and software, respectively.
by Nirav Dave.
Ph.D.
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Bales, Jason M. "Multi-channel hardware/software codesign on a software radio platform." Fairfax, VA : George Mason University, 2008. http://hdl.handle.net/1920/3400.
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Thesis (M.S.)--George Mason University, 2008.Vita: p. 89. Thesis director: David D. Hwang. Submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering. Title from PDF t.p. (viewed Mar. 9, 2009). Includes bibliographical references (p. 85-88). Also issued in print.
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Nagaonkar, Yajuvendra. "FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1294.pdf.
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Mendoza, Jose Antonio. "Hardware and Software Codesign of a JPEG2000 Watermarking Encoder." Thesis, University of North Texas, 2008. https://digital.library.unt.edu/ark:/67531/metadc9752/.
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Analog technology has been around for a long time. The use of analog technology is necessary since we live in an analog world. However, the transmission and storage of analog technology is more complicated and in many cases less efficient than digital technology. Digital technology, on the other hand, provides fast means to be transmitted and stored. Digital technology continues to grow and it is more widely used than ever before. However, with the advent of new technology that can reproduce digital documents or images with unprecedented accuracy, it poses a risk to the intellectual rights of many artists and also on personal security. One way to protect intellectual rights of digital works is by embedding watermarks in them. The watermarks can be visible or invisible depending on the application and the final objective of the intellectual work. This thesis deals with watermarking images in the discrete wavelet transform domain. The watermarking process was done using the JPEG2000 compression standard as a platform. The hardware implementation was achieved using the ALTERA DSP Builder and SIMULINK software to program the DE2 ALTERA FPGA board. The JPEG2000 color transform and the wavelet transformation blocks were implemented using the hardware-in-the-loop (HIL) configuration.
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Motiwala, Quaeed. "Optimizations for acyclic dataflow graphs for hardware-software codesign." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-06302009-040504/.
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Mendoza, Jose Antonio Kougianos Elias. "Hardware & software codesign of a JPEG200 watermarking encoder." [Denton, Tex.] : University of North Texas, 2008. http://digital.library.unt.edu/permalink/meta-dc-9752.
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Junior, Carlos Alberto Oliveira de Souza. "A hardware/software codesign for the chemical reactivity of BRAMS." Universidade de São Paulo, 2017. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-21092017-170006/.
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Several critical human activities depend on the weather forecasting. Some of them are transportation, health, work, safety, and agriculture. Such activities require computational solutions for weather forecasting through numerical models. These numerical models must be accurate and allow the computers to process them quickly. In this project, we aim at migrating a small part of the software of the weather forecasting model of Brazil, BRAMS Brazilian developments on the Regional Atmospheric Modelling System to a heterogeneous system composed of Xeon (Intel) processors coupled to a reprogrammable circuit (FPGA) via PCIe bus. According to the studies in the literature, the chemical equation from the mass continuity equation is the most computationally demanding part. This term calculates several linear systems Ax = b. Thus, we implemented such equations in hardware and provided a portable and highly parallel design in OpenCL language. The OpenCL framework also allowed us to couple our circuit to BRAMS legacy code in Fortran90. Although the development tools present several problems, the designed solution has shown to be viable with the exploration of parallel techniques. However, the performance was below of what we expected.Várias atividades humanas dependem da previsão do tempo. Algumas delas são transporte, saúde, trabalho, segurança e agricultura. Tais atividades exigem solucões computacionais para previsão do tempo através de modelos numéricos. Estes modelos numéricos devem ser precisos e ágeis para serem processados no computador.Este projeto visa portar uma pequena parte do software do modelo de previsão de tempo do Brasil, o BRAMSBrazilian developments on the Regional Atmospheric Modelling Systempara uma arquitetura heterogênea composta por processadores Xeon (Intel) acoplados a um circuito reprogramável em FPGA via barramento PCIe. De acordo com os estudos, o termo da química da equação de continuidade da massa é o termo mais caro computacionalmente. Este termo calcula várias equações lineares do tipo Ax = b. Deste modo, este trabalho implementou estas equações em hardware, provendo um ´codigo portável e paralelo na linguagem OpenCL. O framework OpenCL também nos permitiu acoplar o código legado do BRAMS em Fortran90 junto com o hardware desenvolvido. Embora as ferramentas de desenvolvimento tenham apresentado vários problemas, a solução implementada mostrou-se viável com a exploração de técnicas de paralelismo. Entretando sua perfomance ficou muito aquém do desejado.
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Oudghiri, Houria. "A hardware/software partitioning framework for the codesign of digital systems." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0020/NQ55368.pdf.
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Lifa, Adrian Alin. "Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms." Doctoral thesis, Linköpings universitet, Programvara och system, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-117637.
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Modern applications running on today's embedded systems have very high requirements. Most often, these requirements have many dimensions: the applications need high performance as well as exibility, energy-eciency as well as real-time properties, fault tolerance as well as low cost. In order to meet these demands, the industry is adopting architectures that are more and more heterogeneous and that have reconguration capabilities. Unfortunately, this adds to the complexity of designing streamlined applications that can leverage the advantages of such architectures. In this context, it is very important to have appropriate tools and design methodologies for the optimization of such systems. This thesis addresses the topic of hardware/software codesign and optimization of adaptive real-time systems implemented on recongurable and heterogeneous platforms. We focus on performance enhancement for dynamically recongurable FPGA-based systems, energy minimization in multi-mode real-time systems implemented on heterogeneous platforms, and codesign techniques for fault-tolerant systems. The solutions proposed in this thesis have been validated by extensive experiments, ranging from computer simulations to proof of concept implementations on real-life platforms. The results have conrmed the importance of the addressed aspects and the applicability of our techniques for design optimization of modern embedded systems.
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McRitchie, I. "Multilanguage generative programming techniques for the codesign of hardware/software subsystems." Thesis, Queen's University Belfast, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.419447.
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Sredojević, Ranko Radovin. "Template-based hardware-software codesign for high-performance embedded numerical accelerators." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84895.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 129-132).
Sophisticated algorithms for control, state estimation and equalization have tremendous potential to improve performance and create new capabilities in embedded and mobile systems. Traditional implementation approaches are not well suited for porting these algorithmic solutions into practical implementations within embedded system constraints. Most of the technical challenges arise from design approach that manipulates only one level in the design stack, thus being forced to conform to constraints imposed by other levels without question. In tightly constrained environments, like embedded and mobile systems, such approaches have a hard time efficiently delivering and delivering efficiency. In this work we offer a solution that cuts through all the design stack layers. We build flexible structures at the hardware, software and algorithm level, and approach the solution through design space exploration. To do this efficiently we use a template-based hardware-software development flow. The main incentive for template use is, as in software development, to relax the generality vs. efficiency/performance type tradeoffs that appear in solutions striving to achieve run-time flexibility. As a form of static polymorphism, templates typically incur very little performance overhead once the design is instantiated, thus offering the possibility to defer many design decisions until later stages when more is known about the overall system design. However, simply including templates into design flow is not sufficient to result in benefits greater than some level of code reuse. In our work we propose using templates as flexible interfaces between various levels in the design stack. As such, template parameters become the common language that designers at different levels of design hierarchy can use to succinctly express their assumptions and ideas. Thus, it is of great benefit if template parameters map directly and intuitively into models at every level. To showcase the approach we implement a numerical accelerator for embedded Model Predictive Control (MPC) algorithm. While most of this work and design flow are quite general, their full power is realized in search for good solutions to a specific problem. This is best understood in direct comparison with recent works on embedded and high-speed MPC implementations. The controllers we generate outperform published works by a handsome margin in both speed and power consumption, while taking very little time to generate.
by Ranko Radovin Sredojević.
Ph.D.
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Dudebout, Nicolas. "Multigigabit multimedia processor for 60GHz WPAN a hardware software codesign implementation /." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26677.
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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Member: Chang, Gee-Kung; Committee Member: Hasler, Paul; Committee Member: Laskar, Joy. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Wang, Jian. "An FPGA Based Software/Hardware Codesign for Real Time Video Processing : A Video Interface Software and Contrast Enhancement Hardware Codesign Implementation using Xilinx Virtex II Pro FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6173.
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Xilinx Virtex II Pro FPGA with integrated PowerPC core offers an opportunity to implementing a software and hardware codesign. The software application executes on the PowerPC processor while the FPGA implementation of hardware cores coprocess with PowerPC to achieve the goals of acceleration. Another benefit of coprocessing with the hardware acceleration core is the release of processor load. This thesis demonstrates such an FPGA based software and hardware codesign by implementing a real time video processing project on Xilinx ML310 development platform which is featured with a Xilinx Virtex II Pro FPGA. The software part in this project performs video and memory interface task which includes image capture from camera, the store of image into on-board memory, and the display of image on a screen. The hardware coprocessing core does a contrast enhancement function on the input image. To ease the software development and make this project flexible for future extension, an Embedded Operating System MontaVista Linux is installed on the ML310 platform. Thus the software video interface application is developed using Linux programming method, for example the use of Video4Linux API. The last but not the least implementation topic is the software and hardware interface, which is the Linux device driver for the hardware core. This thesis report presents all the above topics of Operating System installation, video interface software development, contrast enhancement hardware implementation, and hardware core’s Linux device driver programming. After this, a measurement result is presented to show the performance of hardware acceleration and processor load reduction, by comparing to the results from a software implementation of the same contrast enhancement function. This is followed by a discussion chapter, including the performance analysis, current design’s limitations and proposals for improvements. This report is ended with an outlook from this master thesis.
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Egolf, Thomas W. "Virtual prototyping of embedded digital systems : hardware/software codesign, integration, and test." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/15679.
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Chang, Daniel Y. "A systematic software, firmware, and hardware codesign methodology for digital signal processing." Thesis, Monterey, California: Naval Postgraduate School, 2014. http://hdl.handle.net/10945/41358.
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Approved for public release; distribution is unlimited.Creating an embedded system that meets its functional, performance, cost, and schedule goals is a software-and-hardware codesign problem, since the design of the software and hardware components influence each other. The traditional design methodology is sequential, with hardware designed first and then software. The lack of a unified and unbiased approach can lead to suboptimal design and incompatibilities across the software and hardware boundary. To solve these problems, we propose a new software/firmware/hardware codesign methodology to systematically build correct designs efficiently. This codesign methodology includes requirements development, architecture forming, software/ firmware/hardware partitioning, design-pattern mapping, new-design pattern synthesis, integration, and testing. We tested our methods on three application areas. One was a digitizer-filter architecture for ultra-high frequency signals for which we synthesized design patterns in firmware to meet high-frequency requirements. Another was a digitizer-filter architecture for low-frequency signals. A third was a hidden Markov model using dynamic programming. We implemented and tested the first application on a Tektronix/Synopsys embedded system and the second on a Pentek embedded system based on the requirements provided by the stakeholders
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Figueiredo, Boneti Carlos Santieri de. "Exploring coordinated software and hardware support for hardware resource allocation." Doctoral thesis, Universitat Politècnica de Catalunya, 2009. http://hdl.handle.net/10803/6018.
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Multithreaded processors are now common in the industry as they offer high performance at a low cost. Traditionally, in such processors, the assignation of hardware resources between the multiple threads is done implicitly, by the hardware policies. However, a new class of multithreaded hardware allows the explicit allocation of resources to be controlled or biased by the software. Currently, there is little or no coordination between the allocation of resources done by the hardware and the prioritization of tasks done by the software.This thesis targets to narrow the gap between the software and the hardware, with respect to the hardware resource allocation, by proposing a new explicit resource allocation hardware mechanism and novel schedulers that use the currently available hardware resource allocation mechanisms.
It approaches the problem in two different types of computing systems: on the high performance computing domain, we characterize the first processor to present a mechanism that allows the software to bias the allocation hardware resources, the IBM POWER5. In addition, we propose the use of hardware resource allocation as a way to balance high performance computing applications. Finally, we propose two new scheduling mechanisms that are able to transparently and successfully balance applications in real systems using the hardware resource allocation. On the soft real-time domain, we propose a hardware extension to the existing explicit resource allocation hardware and, in addition, two software schedulers that use the explicit allocation hardware to improve the schedulability of tasks in a soft real-time system.
In this thesis, we demonstrate that system performance improves by making the software aware of the mechanisms to control the amount of resources given to each running thread. In particular, for the high performance computing domain, we show that it is possible to decrease the execution time of MPI applications biasing the hardware resource assignation between threads. In addition, we show that it is possible to decrease the number of missed deadlines when scheduling tasks in a soft real-time SMT system.
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Hauff, Martin Anthony, and marty@extendabilities com au. "Compiler Directed Codesign for FPGA-based Embedded Systems." RMIT University. Electrical and Computer Engineering, 2008. http://adt.lib.rmit.edu.au/adt/public/adt-VIT20081202.141333.
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As embedded systems designers increasingly turn to programmable logic technologies in place of off-the-shelf microprocessors, there is a growing interest in the development of optimised custom processing cores that can be designed on a per-application basis. FPGAs blur the traditional distinction between hardware and software and offer the promise of application specific hardware acceleration. But realizing this in a general sense requires a significant departure from traditional embedded systems development flows. Whereas off-the-shelf processors have a fixed architecture, the same cannot be said of purpose-built FPGA-based processors. With this freedom comes the challenge of empirically determining the optimal boundary point between hardware and software. The fluidity of the hardware/software partition also poses an interesting challenge for compiler developers. This thesis presents a tool and methodology that addresses these codesign challenges in a new way. Described as 'compiler-directed codesign', it makes use of a suitably modified compiler to help direct the development of a custom processor core on a per-application basis. By exposing the compiler's internal representation of a compiled target program, visibility into those instructions, and hardware resources, that are most sought after by the compiler can be gained. This information is then used to inform further processor development and to determine the optimal partition between hardware and software. At each design iteration, the machine model is updated to reflect the available hardware resources, the compiler is rebuilt, and the target application is compiled once again. By including the compiler 'in-the-loop' of custom processor design, developers can accurately quantify the impact on performance caused by the addition or removal of specific hardware resources and iteratively converge on an optimal solution. Compiler Directed Codesign has advantages over existing codesign methodologies because it offers both a concrete point from which to begin the partitioning process as well as providing quantifiable and rapid feedback of the merits of different partitioning choices. When applied to an Adaptive PCM Encoder/Decoder case study, the Compiler Directed Codesign technique yielded a custom processor core that was between 36% and 73% smaller, consumed between 11% to 19% less memory, and performed up to 10X faster than comparable general-purpose FPGA-based processor cores. The conclusion of this work is that a suitably modified compiler can serve a valuable role in directing hardware/software partitioning on a per-application basis.
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Subramanian, Sriram. "Software Performance Estimation Techniques in a Co-Design Environment." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1061553201.
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Rößler, Marko. "Parallel Hardware- and Software Threads in a Dynamically Reconfigurable System on a Programmable Chip." Universitätsbibliothek Chemnitz, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-129626.
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Today’s embedded systems depend on the availability of hybrid platforms, that contain heterogeneous computing resources such as programmable processors units (CPU’s or DSP’s) and highly specialized hardware cores. These platforms have been scaled down to integrated embedded system-on-chip. Modern platform FPGAs enhance such systems by the flexibility of runtime configurable silicon. One of the major advantages that arises is the ability to use hardware (HW) and software (SW) resources in a time-shared manner. Though the ability to dynamically assign computing resources based on decisions taken at runtime is given.
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Ruan, Zhuo. "Interface Design and Synthesis for Structural Hybrid Microarchitectural Simulators." BYU ScholarsArchive, 2013. https://scholarsarchive.byu.edu/etd/4369.
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Computer architects have discovered the potential of using FPGAs to accelerate software microarchitectural simulators. One type of FPGA-accelerated microarchitectural simulator, namedthe hybrid structural microarchitectural simulator, is very promising. This is because a hybrid structural microarchitectural simulator combines structural software and hardware, and this particular organization provides both modeling flexibility and fast simulation speed. The performance of a hybrid simulator is significantly affected by how the interface between software and hardware is constructed. The work of this thesis creates an infrastructure, named Simulator Partitioning Research Infrastructure (SPRI), to implement the synthesis of hybrid structural microarchitectural simulators which includes simulator partitioning, simulator-to-hardware synthesis, interface synthesis. With the support of SPRI, this thesis characterizes the design space of interfaces for synthesized hybrid structural microarchitectural simulators and provides the implementations for several such interfaces. The evaluation of this thesis thoroughly studies the important design tradeoffs and performance factors (e.g. hardware capacity, design scalability, and interface latency) involved in choosing an efficient interface. The work of this thesis is essential to the research community of computer architecture. It not only contributes a complete synthesis infrastructure, but also provides guidelines to architects on how to organize software microarchitectural models and choose a proper software/hardware interface so the hybrid microarchitectural simulators synthesized from these software models can achieve desirable speedup
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Fons, Lluís Mariano. "Hardware accelerators for embedded fingerprint-based personal recognition systems." Doctoral thesis, Universitat Rovira i Virgili, 2012. http://hdl.handle.net/10803/83493.
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The development of automatic biometrics-based personal recognition systems is a reality in the current technological age. Not only those operations demanding stringent security levels but also many daily use consumer applications request the existence of computational platforms in charge of recognizing the identity of one individual based on the analysis of his/her physiological and/or behavioural characteristics. The state of the art points out two main open problems in the implementation of such applications: on the one hand, the needed reliability improvement in terms of recognition accuracy, overall security and real-time performances; and on the other hand, the cost reduction of those physical platforms in charge of the processing. This work aims at finding the proper system architecture able to address those limitations of current personal recognition applications. Embedded system solutions based on hardware-software co-design techniques and programmable (and run-time reconfigurable) logic devices under FPGAs or SOPCs is proven to be an efficient alternative to those existing multiprocessor systems based on HPCs, GPUs or PC platforms in the development of that kind of high-performance applications at low costEl desenvolupament de sistemes automàtics de reconeixement personal basats en tècniques biomètriques esdevé una realitat en l’era tecnològica actual. No només aquelles operacions que exigeixen un elevat nivell de seguretat sinó també moltes aplicacions quotidianes demanen l’existència de plataformes computacionals encarregades de reconèixer la identitat d’un individu a partir de l’anàlisi de les seves característiques fisiològiques i/o comportamentals. L’estat de l’art de la tècnica identifica dues limitacions importants en la implementació d’aquest tipus d’aplicacions: per una banda, és necessària la millora de la fiabilitat d’aquests sistemes en termes de precisió en el procés de reconeixement personal, seguretat i execució en temps real; i per altra banda, és necessari reduir notablement el cost dels sistemes electrònics encarregats del processat biomètric. Aquest treball té per objectiu la cerca de l’arquitectura adequada a nivell de sistema que permeti fer front a les limitacions de les aplicacions de reconeixement personal actuals. Es demostra que la proposta de sistemes empotrats basats en tècniques de codisseny hardware-software i dispositius lògics programables (i reconfigurables en temps d’execució) sobre FPGAs o SOPCs resulta ser una alternativa eficient en front d’aquells sistemes multiprocessadors existents basats en HPCs, GPUs o plataformes PC per al desenvolupament d’aquests tipus d’aplicacions que requereixen un alt nivell de prestacions a baix cost.
El desarrollo de sistemas automáticos de reconocimiento personal basados en técnicas biométricas se ha convertido en una realidad en la era tecnológica actual. No tan solo aquellas operaciones que requieren un alto nivel de seguridad sino también muchas otras aplicaciones cotidianas exigen la existencia de plataformas computacionales encargadas de verificar la identidad de un individuo a partir del análisis de sus características fisiológicas y/o comportamentales. El estado del arte de la técnica identifica dos limitaciones importantes en la implementación de este tipo de aplicaciones: por un lado, es necesario mejorar la fiabilidad que presentan estos sistemas en términos de precisión en el proceso de reconocimiento personal, seguridad y ejecución en tiempo real; y por otro lado, es necesario reducir notablemente el coste de los sistemas electrónicos encargados de dicho procesado biométrico. Este trabajo tiene por objetivo la búsqueda de aquella arquitectura adecuada a nivel de sistema que permita hacer frente a las limitaciones de los sistemas de reconocimiento personal actuales. Se demuestra que la propuesta basada en sistemas embebidos implementados mediante técnicas de codiseño hardware-software y dispositivos lógicos programables (y reconfigurables en tiempo de ejecución) sobre FPGAs o SOPCs resulta ser una alternativa eficiente frente a aquellos sistemas multiprocesador actuales basados en HPCs, GPUs o plataformas PC en el ámbito del desarrollo de aplicaciones que demandan un alto nivel de prestaciones a bajo coste
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Holanda, Jose Arnaldo Mascagni de. "Arquitetura multi-core reconfigurável para detecção de pedestres baseada em visão." Universidade de São Paulo, 2017. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-25092017-085556/.
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Dentre as diversas tecnologias de Assistência Avançada ao Condutor (ADAS) que têm sido adicionadas aos automóveis modernos estão os sistemas de detecção de pedestres. Tais sistemas utilizam sensores, como radares, lasers e câmeras de vídeo para captar informações do ambiente e evitar a colisão com pessoas no contexto do trânsito. Câmeras de vídeo têm se apresentado como um ótima opção para esses sistemas, devido ao relativo baixo custo e à riqueza de informações que capturam do ambiente. Muitas técnicas para detecção de pedestres baseadas em visão têm surgido nos últimos anos, tendo como característica a necessidade de um grande poder computacional para que se possa realizar o processamento das imagens em tempo real, de forma robusta, confiável e com baixa taxa de erros. Além disso, é necessário que sistemas que implementem essas técnicas tenham baixo consumo de energia, para que possam funcionar em um ambiente embarcado, como os automóveis. Uma tendência desses sistemas é o processamento de imagens de múltiplas câmeras presentes no veículo, de forma que o sistema consiga perceber potenciais perigos de colisão ao redor do veículo. Neste contexto, este trabalho aborda o coprojeto de hardware e software de uma arquitetura para detecção de pedestres, considerando a presença de quatro câmeras em um veículo (uma frontal, uma traseira e duas laterais). Com este propósito, utiliza-se a flexibilidade dos dispositivos FPGA para a exploração do espaço de projeto e a construção de uma arquitetura que forneça o desempenho necessário, o consumo de energia em níveis adequados e que também permita a adaptação a novos cenários e a evolução das técnicas de detecção de pedestres por meio da programabilidade. O desenvolvimento da arquitetura baseouse em dois algoritmos amplamente utilizados para detecção de pedestres, que são o Histogram of Oriented Gradients (HOG) e o Integral Channel Features (ICF). Ambos introduzem técnicas que servem como base para os algoritmos de detecção modernos. A arquitetura implementada permitiu a exploração de diferentes tipos de paralelismo das aplicações por meio do uso de múltiplos processadores softcore, bem como a aceleração de funções críticas por meio de implementações em hardware. Também foi demonstrada sua viabilidade no atendimento a um sistema contendo quatro câmeras de vídeo.Among the several Advanced Driver Assistance (ADAS) technologies that have been added to modern vehicles are pedestrian detection systems. Those systems use sensors, such as radars, lasers, and video cameras to capture information from the environment and avoid collision with people in the context of traffic. Video cameras have become as a great option for such systems because of the relatively low cost and all of information they are able to capture from the environment. Many techniques for vison-based pedestrian detection have appeared in the last years, having as characteristic the necessity of a great computational power so that image can be processed in real time, in a robust and reliable way, and with low error rate. In addition, systems that implement these techniques require low power consumption, so they can operate in an embedded environment such as automobiles. A trend of these systems is the processing of images from multiple cameras mounted in vehicles, so that the system can detect potential collision hazards around the vehicle. In this context, this work addresses the hardware and software codesign of an architecture for pedestrian detection, considering the presence of four cameras in a vehicle (one in the front, one in the rear and two in the sides). For this purpose, the flexibility of FPGA devices is used for design space exploration and the construction of an architecture that provides the necessary performance, energy consumption at appropriate levels and also allows adaptation to new scenarios and evolution of pedestrian detection techniques through programmability. The development of the architecture was based on two algorithms widely used for pedestrian detection, which are Histogram of Oriented Gradients (HOG) and Integral Channel Features (ICF). Both introduce techniques that serve as the basis for modern detection algorithms. The implemented architecture allowed the exploration of different types of parallelism through the use of multiple softcore processors, as well as the acceleration of critical functions through implementations in hardware. It has also been demonstrated its feasibility in attending to a system containing four video cameras.
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Kiehn, Luiz Henrique. "Técnicas de profiling para o co-projeto de hardware e software baseado em computação reconfigurável aplicadas ao processador softcore Nios II da Altera." Universidade de São Paulo, 2012. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-24012013-104256/.
Full textAbstract:
Como avanço dos paradigmas de desenvolvimento de sistemas eletrônicos, novos conceitos, modelos e técnicas resultaram dessa evolução, gerando ferramentas mais eficientes e objetivas. Entre estas, as de automação de projetos eletrônicos (EDA - Electronic Design Automation) em nível de sistema (ESL - Electronic System Level) trouxeram um incremento considerável de produtividade à confecção de sistemas eletrônicos, inclusive de sistemas embarcados. Já no que se refere ao desempenho do sistema elaborado, monitorar sua execução e determinar seu perfil de funcionamento são tarefas essenciais para avaliar, a partir do seu comportamento, quais os pontos que representam gargalos ou pontos críticos, afetando sua eficiência geral. Dessa forma, faz-se necessário pesquisar princípios de verificação e otimização dos sistemas elaborados que estejam mais bem adaptados aos novos paradigmas de desenvolvimento de projetos. O presente trabalho tem por objetivo implementar um módulo de coleta e processamento de dados para análise de perfil de programas escritos na linguagem C e que sejam executados em processadores soft core, como o NiosII, da Altera. Entretanto, diferentemente das estatísticas oferecidas pela ferramenta GProf (GNU Profiling) com relação à análise de desempenho, em que cada amostra obtida implica no incremento de um contador para a função flagrada, o presente trabalho volta seu interesse à análise do perfil de uso de memória heap, que encontra-se mormente no volume alocado constatado em cada amostragem. Dessa forma, para diferentes amostragens de uma mesma função interessa saber qual a maior quantidade de memória utilizada pela função entre todas as amostras coletadas. Isso significa que, ao invés de incremento por amostragem, adotar-se-á o princípio do registro do maior valor, em número de bytes, de uso de memória constatado em cada função. Os principais recursos do módulo proposto são: a) o armazenamento das informações de uso de memória heap obtidas no processo de Profiling em formato apropriado para uso posterior por aplicações de co-projeto de hardware e software; e b) a geração de relatórios de Profiling que apresentem o volume de memória dinâmica alocada durante o processamento dos programas analisados para que se possa identificar os locais onde esse uso é mais crítico, permitindo ao projetista tomar decisões quanto à reformulação do código fonte, ou quanto ao incremento no tamanho da memória a ser instalada no sistema, ou quanto à reformulação da arquitetura de um modo geralDue to the advancement of the paradigms of development of electronic systems, new concepts, models and techniques resulted from this evolution, generating more eficient and objective tools. Among them, the system-level (ESL) electronic design automation (EDA) ones has brought a considerable increase to the productivity of electronic systems manufacturing, especially including the embedded systems. In what refers to elaborated systems, monitoring its execution and determining its operating profile are the essential tasks to assess, from its behavior, which points in this system represent bottlenecks or hot spots, affecting its overall efficiency. Thus, it is necessary to study the principles of verification and optimization of the elaborated systems that are better adapted to the new paradigms of projects development. The present work has as its aim implementing a processing module for data collection and analysis of C language writen programs profile, wich will run in soft core processors, like Alteras NiosII. However, unlike the statistics offered by the tool GProf (GNU Profiling) tool with respect to performance analysis, in which each sample obtained implies the increment of a counter to the function caught, this paper turns his interest to the analysis of memory usage profiling, which is especially found in volume allocated in each sample. Thus, for different samples of the same function, the matter is to know the most amount of memory used by the function among all samples collected. This means that instead of increasing sample we will adopt the principle of registration of the highest number of bytes of memory usage observed in each function. So, this tools main features are: a) storing the information of memory use in the heap memory obtained in the process of Profiling in an appropriate format for later use by hardware and software codesign applications; and b) the reporting of Profiling that shows the dynamic memory volume allocated during analyzed programs processing so one can identify where such use is more critical, allowing the designer to make decisions regarding the reformulation of source code, or as to the increase in memory size to be installed int the system, or as to the architecture redesign
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Khuat, Quang Hai. "Definition and evaluation of spatio-temporal scheduling strategies for 3D multi-core heterogeneous architectures." Thesis, Rennes 1, 2015. http://www.theses.fr/2015REN1S007/document.
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Empilant une couche multiprocesseur (MPSoC) et une couche de FPGA pour former un système sur puce reconfigurable en trois dimension (3DRSoC), est une solution prometteuse donnant un niveau de flexibilité élevé en adaptant l'architecture aux applications visées. Pour une application exécutée sur ce système, l'un des principaux défis vient de la gestion de haut niveau des tâches. Cette gestion est effectuée par le service d'ordonnancement du système d'exploitation et elle doit être en mesure de déterminer, lors de l'exécution de l'application, quelle tâche est exécutée logiciellement et/ou matériellement, quand (dimension temporelle) et sur quelles ressources (dimension spatiale, c'est à dire sur quel processeur ou quelle région du FPGA) pour atteindre la haute performance du système. Dans cette thèse, nous proposons des stratégies d'ordonnancement spatio-temporel pour les architectures 3DRSoCs. La première stratégie décide la nécessité de placer une tâche matérielle et une tâche logicielle en face-à-face afin que le coût de la communication entre tâches soit minimisé. La deuxième stratégie vise à minimiser le temps d'exécution globale de l'application. Cette stratégie exploits la présence de processeurs de la couche MPSoC afin d'anticiper, en temps-réel, l'exécution d'une tâche logicielle quand sa version matérielle ne peut pas être allouée sur le FPGA. Ensuite, un outil de simulation graphique a été développé pour vérifier le bon fonctionnement des stratégies développées et aussi nous permettre de produire des résultatsStacking a multiprocessor (MPSoC) layer and a FPGA layer to form a 3D Reconfigurable System-on- Chip (3DRSoC) is a promising solution giving a high flexibility level in adapting the architecture to the targeted application. For an application defined as a graph of parallel tasks running on the 3DRSoC system, one of the main challenges comes from the high-level management of tasks. This management is done by the scheduling service of the Operating System and it must be able to determine, on the fly, what task should be run in software and/or hardware, when (temporal dimension) and where (spatial dimension, i.e. on what processor or what area of the FPGA) in order to achieve high performance of the system. In this thesis, we propose online spatio-temporal scheduling strategies for 3DRSoCs. The first strategy decides, during the task scheduling, the need for a SW task and a HW task to communicate in face-to-face so that the communication cost between tasks is minimized. The second strategy aims at minimizing the overall execution time of the application. It exploits the presence of processors in the MPSoC layer in order to anticipate, at run-time, the SW execution of a task when its HW version cannot be allocated to the FPGA. Then, a graphical simulation tool has been developed to verify the proper functioning of the developed strategies and also enable us to produce results
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Minařík, Miloš. "Souběžný evoluční návrh hardwaru a softwaru." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2018. http://www.nusl.cz/ntk/nusl-412594.
Full textAbstract:
Genetické programování (GP) je v určitém rozsahu schopno automaticky generovat požadované programy, aniž by uživatel musel určit, jakým způsobem má program postupovat. GP bylo s úspěchem použito k řešení široké škály praktických problémů z různých oblastí, přičemž výsledky byly často srovnatelné s řešeními vytvořenými člověkem. Doposud však nebyla zodpovězena otázka, zda GP dokáže generovat vysoce optimalizovaný výpočetní model (platformu) spolu s programem spustitelným na této platformě, který by řešil daný problém při dodržení všech omezení (například na plochu na čipu a zpoždění). V případě scénářů, kdy je optimalizováno více kritérií, by uživatelským výstupem měla být množina nedominovaných řešení s různými kombinacemi úrovně využití zdrojů (plocha, příkon) a výkonu (rychlosti provádění). Tento problém může být chápán jako souběžný návrh hardwaru a softwaru, zkráceně HW/SW codesign. Tato práce zkoumá způsoby, jakými lze souběžně evolučně vyvíjet platformu a programy v případě, že je problém zadán množinou vektorů vstupů a jim odpovídajících výstupů. Nejprve byl vytvořen model architektury a evoluční platforma zajišťující zpracování a evoluční vývoj těchto architektur. Kandidátní mikroprogramové architektury byly evolvovány spolu s programy pomocí lineárního genetického programování. Následně byla provedena série jednodušších experimentů. Navržená platforma dosahovala výsledků srovnatelných s nejnovějšími metodami. Na základě slabých míst objevených během počátečních experimentů byla platforma rozšířena. Rozšířená platforma byla poté ověřena na několika složitějších experimentech. Jeden z nich byla zaměřen na efektivní implementaci aproximace sigmoidální funkce. Platforma v tomto případě našla řadu různých řešení implementujících aproximaci sigmoidy, z nichž některá byla sekvenční a jiná čistě kombinační. V rámci experimentu byly evolučně nalezeny i známé algoritmy, přičemž některé z nich byly evolucí dokonce optimalizovány pro podmnožinu definičního oboru zvolenou pro daný experiment. Poslední sada experimentů byla zaměřena na evoluční návrh obrazových filtrů pro redukci šumu typu sůl a pepř. Platforma v tomto případě znovuobjevila koncept přepínaných filtrů a naezla variantu přepínaného mediánového filtru, která byla z hlediska výsledků filtrace srovnatelná s běžně používanými metodami. Tato práce prokázala, že pomocí genetického programování lze navrhovat a optimalizovat malé HW/SW systémy. Automatizovaný evoluční návrh složitějších HW/SW systémů zůstává otevřeným problémem vhodným k dalšímu výzkumu.
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Rößler, Marko. "Dynamische Anwendungspartitionierung für heterogene adaptive Computersysteme." Doctoral thesis, Universitätsbibliothek Chemnitz, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-151837.
Full textAbstract:
Die Dissertationsschrift stellt eine Methodik und die Infrastruktur zur Entwicklung von dynamisch verteilbaren Anwendungen für heterogene Computersysteme vor. Diese Computersysteme besitzen vielfältige Rechenwerke, die Berechnungen in den Domänen Software und Hardware realisieren. Als erster Schritt wird ein übergreifendes und integriertes Vorgehen für den Anwendungsentwurf auf Basis eines abstrakten “Single-Source” Ansatzes entwickelt. Durch die Virtualisierung der Rechenwerke wird die preemptive Verteilung der Anwendungen auch über die Domänengrenzen möglich. Die Anwendungsentwicklung für diese Computersysteme bedarf einer durchgehend automatisierten Entwurfsunterstützung. In der Arbeit wird der dazu vorgeschlagene Ansatz formalisiert und eine neuartige Unterbrechungspunktsynthese entwickelt, die ein hinsichtlich Zeit und Fläche optimiertes, präemptives Verhalten für beliebige Anwendungsbeschreibungen generiert. Das Verfahren wird beispielhaft implementiert und mittels einer FPGA- Prototypenplattform mit Linux-basierter Laufzeitumgebung anhand dreier Fallbeispiele unterschiedlicher Komplexität validiert und evaluiertThis thesis introduces a methodology and infrastructure for the development of dynamically distributable applications on heterogeneous computing systems. Such systems execute computations using resources from both the hardware and the software domain. An integrated approach based on an abstract single-source design entry is developed that allows preemptive partitioning through virtualization of computing resources across the boundaries of differing computational domains. Application design for heterogeneous computing systems is a complex task that demands aid by electronic design automation tools. This work provides a novel synthesis approach for breakpoints that generates preemptive behaviour for arbitrary applications. The breakpoint scheme is computed for a minimal additional resource utilization and given timing constraints. The approach is implemented on an FPGA prototyping platform driven by a Linux based runtime environment. Evaluation and validation of the approach have been carried out using three different application examples
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Oliveira, Wagner Luiz Alves de. "Uma abordagem para a modelagem de sistemas digitais." [s.n.], 2003. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260289.
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Orientadores: Norian MarranghelloTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-04T00:21:09Z (GMT). No. of bitstreams: 1 Oliveira_WagnerLuizAlvesde_D.pdf: 11239313 bytes, checksum: 6656f5270142e68410f7ed92ce02dc2d (MD5) Previous issue date: 2004
Resumo: O projeto de sistemas digitais alcançou um elevado grau de complexidade, inviabilizando sua consecução sem o uso de ferramentas de CAD. O ponto de partida de tais ferramentas consiste numa visão conceitual do sistema pretendido (dada por um ou mais modelos conceituais), a qual é capturada para tratamento computacional por uma ou mais linguagens de especificação. Várias dessas linguagens foram desenvolvidas visando capturar tantas características de hardware e de software quanto possível, de acordo com diferentes metodologias de projeto. Rede de Petri é uma classe de modelos conceituais utilizada na modelagem de diversos tipos de sistemas computacionais paralelos. Algumas extensões de rede de Petri foram propostas visando à descrição, de forma tão acurada quanto possível, de características de sistemas digitais. Entretanto, somente duas destas extensões possuem um número maior de características necessárias à descrição integral de tais sistemas. O presente trabalho apresenta uma extensão de rede de Petri desenvolvida para superar as limitações das demais extensões na representação de sistemas digitais. O trabalho apresenta, também, uma metodologia de coprojeto hardware/software na qual a extensão proposta pode ser usada como linguagem de modelagem interna. Tal plataforma visa a descrição, simulação, análise, validação e síntese em alto nível de sistemas digitais embutidos
Abstract: Digital system design has reached a high degree of complexity that prevents its realization without CAD tools. The starting point of such tools consists on a conceptual view of the intended system (given by one or more conceptual models), which is captured for computational handling by one or more specification languages. Several of such languages were developed aiming to capture as many hardware and software characteristics as possible, according to different design methodologies. Petri net is a class of conceptual models for parallel system modeling. Some Petri net extensions have been proposed aiming at describing digital systems characteristics as accurately as possible. However, only two of them have nearly all features needed to describe such systems in full. This work presents a Petri net extension developed to overcome the restrictions for digital system modeling through Petri net extensions. A hardware/software codesign methodology in which the proposed extension can be used as the internal modeling language is presented as well. Such a framework aims embedded digital system description, simulation, analysis, validation, and high-level synthesis
Doutorado
Eletrônica, Microeletrônica e Optoeletrônica
Doutor em Engenharia Elétrica
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Mühlbauer, Felix. "Entwurf, Methoden und Werkzeuge für komplexe Bildverarbeitungssysteme auf Rekonfigurierbaren System-on-Chip-Architekturen." Phd thesis, Universität Potsdam, 2011. http://opus.kobv.de/ubp/volltexte/2012/5992/.
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Bildverarbeitungsanwendungen stellen besondere Ansprüche an das ausführende Rechensystem.
Einerseits ist eine hohe Rechenleistung erforderlich.
Andererseits ist eine hohe Flexibilität von Vorteil, da die Entwicklung tendentiell ein experimenteller und interaktiver Prozess ist.
Für neue Anwendungen tendieren Entwickler dazu, eine Rechenarchitektur zu wählen, die sie gut kennen, anstatt eine Architektur einzusetzen, die am besten zur Anwendung passt.
Bildverarbeitungsalgorithmen sind inhärent parallel, doch herkömmliche bildverarbeitende eingebettete Systeme basieren meist auf sequentiell arbeitenden Prozessoren.
Im Gegensatz zu dieser "Unstimmigkeit" können hocheffiziente Systeme aus einer gezielten Synergie aus Software- und Hardwarekomponenten aufgebaut werden.
Die Konstruktion solcher System ist jedoch komplex und viele Lösungen, wie zum Beispiel grobgranulare Architekturen oder anwendungsspezifische Programmiersprachen, sind oft zu akademisch für einen Einsatz in der Wirtschaft.
Die vorliegende Arbeit soll ein Beitrag dazu leisten, die Komplexität von Hardware-Software-Systemen zu reduzieren und damit die Entwicklung hochperformanter on-Chip-Systeme im Bereich Bildverarbeitung zu vereinfachen und wirtschaftlicher zu machen.
Dabei wurde Wert darauf gelegt, den Aufwand für Einarbeitung, Entwicklung als auch Erweiterungen gering zu halten.
Es wurde ein Entwurfsfluss konzipiert und umgesetzt, welcher es dem Softwareentwickler ermöglicht, Berechnungen durch Hardwarekomponenten zu beschleunigen und das zu Grunde liegende eingebettete System komplett zu prototypisieren.
Hierbei werden komplexe Bildverarbeitungsanwendungen betrachtet, welche ein Betriebssystem erfordern, wie zum Beispiel verteilte Kamerasensornetzwerke.
Die eingesetzte Software basiert auf Linux und der Bildverarbeitungsbibliothek OpenCV.
Die Verteilung der Berechnungen auf Software- und Hardwarekomponenten und die daraus resultierende Ablaufplanung und Generierung der Rechenarchitektur erfolgt automatisch.
Mittels einer auf der Antwortmengenprogrammierung basierten Entwurfsraumexploration ergeben sich Vorteile bei der Modellierung und Erweiterung.
Die Systemsoftware wird mit OpenEmbedded/Bitbake synthetisiert und die erzeugten on-Chip-Architekturen auf FPGAs realisiert.Image processing applications have special requirements to the executing computational system. On the one hand a high computational power is necessary. On the other hand a high flexibility is an advantage because the development tends to be an experimental and interactive process. For new applications the developer tend to choose a computational architecture which they know well instead of using that one which fits best to the application. Image processing algorithms are inherently parallel while common image processing systems are mostly based on sequentially operating processors. In contrast to this "mismatch", highly efficient systems can be setup of a directed synergy of software and hardware components. However, the construction of such systems is complex and lots of solutions, like gross-grained architectures or application specific programming languages, are often too academic for the usage in commerce. The present work should contribute to reduce the complexity of hardware-software-systems and thus increase the economy of and simplify the development of high-performance on-chip systems in the domain of image processing. In doing so, a value was set on keeping the effort low on making familiar to the topic, on development and also extensions. A design flow was developed and implemented which allows the software developer to accelerate calculations with hardware components and to prototype the whole embedded system. Here complex image processing systems, like distributed camera sensor networks, are examined which need an operating system. The used software is based upon Linux and the image processing library OpenCV. The distribution of the calculations to software and hardware components and the resulting scheduling and generation of architectures is done automatically. The design space exploration is based on answer set programming which involves advantages for modelling in terms of simplicity and extensions. The software is synthesized with the help of OpenEmbedded/Bitbake and the generated on-chip architectures are implemented on FPGAs.
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Markert, Erik, Hailu Wang, Göran Herrmann, and Ulrich Heinkel. "Kostenmodellierung mit SystemC/System-AMS." Universitätsbibliothek Chemnitz, 2007. http://nbn-resolving.de/urn:nbn:de:swb:ch1-200700902.
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In diesem Beitrag wird eine Methode zur Beschreibung von Kostenfaktoren und deren Verknüpfung
über Hierarchiegrenzen hinweg dargestellt. Sie eignet sich sowohl für rein digitale Systeme mit Softwareanteilen
als auch für gemischt analog/digitale Systeme. Damit ist sie im Hardware-Software Codesign
und im Analog-Digital Codesign zum Vergleich verschiedener Systemkompositionen anwendbar.
Die Implementierung mit C++ ermöglicht neben einer Nutzung mit digitalem SystemC auch den Einsatz
mit der analogen SystemC-Erweiterung SystemC-AMS und vereinfacht die Nutzung gegenüber
einer vorhandenen VHDL-Implementierung. Als Anwendungsbeispiel fungieren Komponenten eines
Systems zur Inertialnavigation.
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Trhoň, Adam. "Vícekamerový snímač biometrických vlastností lidského prstu." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2015. http://www.nusl.cz/ntk/nusl-234920.
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This thesis describes a conceptual design of touchless fingerprint sensor and design, implementation and testing of its firmware, which is a composition of hardware implemented in VHDL and a program implemented in C. Result of this thesis can be used as the first step of building an industrial solution.
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Ilčík, Ondřej. "Nástroj pro grafické prototypování vestavěných systémů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2011. http://www.nusl.cz/ntk/nusl-412844.
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This study is focused on grafical modeling of embedded systems using dialects of UML. It provides a brief description of existing profiles. Furthemore it deals with modeling frameworks for the Eclipse platform and describes an implementation of such modeling tool as a part of project Lissom.
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Rößler, Marko. "Dynamische Anwendungspartitionierung für heterogene adaptive Computersysteme: Dynamische Anwendungspartitionierung für heterogene adaptiveComputersysteme." Doctoral thesis, Universitätsverlag der Technischen Universität Chemnitz, 2013. https://monarch.qucosa.de/id/qucosa%3A20106.
Full textAbstract:
Die Dissertationsschrift stellt eine Methodik und die Infrastruktur zur Entwicklung von dynamisch verteilbaren Anwendungen für heterogene Computersysteme vor. Diese Computersysteme besitzen vielfältige Rechenwerke, die Berechnungen in den Domänen Software und Hardware realisieren. Als erster Schritt wird ein übergreifendes und integriertes Vorgehen für den Anwendungsentwurf auf Basis eines abstrakten “Single-Source” Ansatzes entwickelt. Durch die Virtualisierung der Rechenwerke wird die preemptive Verteilung der Anwendungen auch über die Domänengrenzen möglich.
Die Anwendungsentwicklung für diese Computersysteme bedarf einer durchgehend automatisierten Entwurfsunterstützung. In der Arbeit wird der dazu vorgeschlagene Ansatz formalisiert und eine neuartige Unterbrechungspunktsynthese entwickelt, die ein hinsichtlich Zeit und Fläche optimiertes, präemptives Verhalten für beliebige Anwendungsbeschreibungen generiert. Das Verfahren wird beispielhaft implementiert und mittels einer FPGA- Prototypenplattform mit Linux-basierter Laufzeitumgebung anhand dreier Fallbeispiele unterschiedlicher Komplexität validiert und evaluiert.This thesis introduces a methodology and infrastructure for the development of dynamically distributable applications on heterogeneous computing systems. Such systems execute computations using resources from both the hardware and the software domain. An integrated approach based on an abstract single-source design entry is developed that allows preemptive partitioning through virtualization of computing resources across the boundaries of differing computational domains. Application design for heterogeneous computing systems is a complex task that demands aid by electronic design automation tools. This work provides a novel synthesis approach for breakpoints that generates preemptive behaviour for arbitrary applications. The breakpoint scheme is computed for a minimal additional resource utilization and given timing constraints. The approach is implemented on an FPGA prototyping platform driven by a Linux based runtime environment. Evaluation and validation of the approach have been carried out using three different application examples.
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Vlach, Jan. "Algoritmy souběžného technického a programového návrhu." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2007. http://www.nusl.cz/ntk/nusl-412761.
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This master's thesis deals with a parallel design of the program and a technical equipment of embedded systems. It involves both a general description of the whole process and an illustration of the design, a simulation and implementation of the FIR filter. It also includes a description of the proposed program Polis and the simulation system Ptolemy. The conclusion of the project is devoted to a generation of simulation models in VHDL language incl. a subsequent synthesis.
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Valderrama, Carlos. "Prototype virtuel pour la génération des architectures mixtes logicielles-matérielles." Grenoble INPG, 1998. http://www.theses.fr/1998INPG0121.
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L'objectif de ce travail de thèse est le développement d'une méthodologie pour la génération rapide d'architectures flexibles et modulaires pour les systèmes distribués. Cette approche, appelé aussi "prototypage virtuel", est une étape essentielle dans le processus de conception conjointe des systèmes mixtes logiciel/matériel. Les approches de recherche dans ce domaine sont motivées par le besoin urgent de prototypes pour valider la spécification, par la disponibilité des outils et des environnements de synthèse pour les parties logicielles et matérielles. Le prototypage virtuel permet à la fois la manipulation du domaine logiciel ainsi que du domaine matériel. Il prend en entrée une architecture hétérogène composée d'un ensemble de modules distribués issu du découpage matériel/logiciel et génère des descriptions exécutables pour des éléments matériels et logiciels. Ce travail décrit une stratégie de prototypage virtuel pour la cosynthèse (génération des modules matériels et logiciels sur une plateforme architecturale) et la cosimulation (c'estàdire la simulation conjointe de ces deux composants) dans un environnement unifié. Ces travaux définissent également le développement d'un environnement de cosimulation distribué et flexible permettant l'utilisation de différents outils de simulation, de langages, la génération de modèles matériels et logiciels synthésisables et l'ordonnancement des modèles multiprocesseurs sur une architecture monoprocesseur. Cette approche, présentée dans la conférence ED&TC, a obtenu le prix de l'année 1995. Des outils ont été mis en pratique dans l'environnement de conception conjointe Cosmos. Ce travail a aussi fait l'objet d'un transfert de technologie au profit de SGSThomson Microelectronics. Les outils développés au cours de cette thèse ont été utilisés pour les projets Européens COMITY (particulièrement utilisé par l'Aérospatiale Missiles à Toulouse et Intracom en Grèce) et CODAC, et par d'autres groupes comme le FZI de l'université de Tübingen et PSA à ParisThe objective of this work is to develop a methodology for the generation of flexible and modular architectures for distributed systems. This approach (also called " virtual prototyping ") is an essential stage in the process of joint design (codesign) of mixed software/hardware systems. Virtual prototyping takes as input a heterogeneous architecture made up of a whole of distributed modules resulting from software/hardware partitioning. It generates executable descriptions for software and hardware elements. Research approaches in this field are justified by the evolution of technology, the urgent need for prototypes to validate the specification, and by the availability of tools and synthesis environments for the design of software and hardware parts. One of the major difficulties of virtual prototyping is that it allows at the same time to handle both, software and hardware. This work describes a strategy of virtual prototyping for the cosynthesis (generation of the modules material and software on an architectural platform) and cosimulation (i. E. The joint simulation of these two kind of components) in a unified environment, the development of a distributed and flexible cosimulation environment allowing the use of several simulation tools and languages, the generation of hardware/software synthesizable models and mono-processor architecture software generation for a set of communicating processes. This approach, presented in the ED&TC conference, got the best paper award in 1995. The tools developed during this thesis were put into practice in the Cosmos codesign environment. One of them was transferred to SGS-Thomson Microelectronics. The tools were also used for the Europeans projects COMITY (particularly used by Aerospace the Missiles in Toulouse and Intracom in Greece) and CODAC, and by other groups like the FZI of the university of Tübingen and PSA in Paris
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Orsák, Michal. "Analýzy síťového provozu na procesoru NXP a FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2018. http://www.nusl.cz/ntk/nusl-385911.
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The primary goal of this thesis is to exploit possibilites of aa entirely new hardware based on NXP LS2088 and FPGA. The secondary goal is to create firmware for this processor working out-of-box and perform optimisations of existing software for L7 analysis. This software was deeply bound to a previous hardware platform. The network processor NXP LS2088 contains many hardware accellerators and a virtual reconfigurable network. This thesis exploits all hardware parts of on this platform. Many tweaks and optimizations were performed based on this analysis to achieve maximum efficieny of software for L7 analysis. There were many intensive optimisations like rewriting for the DPDK library and new hardware or hardware synchronization of worker threads of this application. The main result of this thesis is working platform with efficient L7 analysis software which actively uses accelerators in FPGA and NXP network processor. SDK for new platform is also prepared.
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Dolíhal, Luděk. "Testování generovaných překladačů jazyka c pro procesory ve vestavěných systémech." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-412583.
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Vestavěné systémy se staly nepostradatelnými pro náš každodenní život. Jsou to obvykle úzce zaměřená, vysoce optimalizovaná, jednoúčelová zařízení. Jádro vestavěných zařízení obvykle tvoří jeden nebo více aplikačně specifických instrukčních procesorů. Tato disertační práce se zaměřuje na problematiku testování nástrojú pro návrh aplikačně specifických procesorů a následně i samotných aplikačne specifických procesorů. Snahou bylo vytvořit systém, ve kterém bude možné otestovat jednotlivé nástroje, jako například překladač, assembler, disassembler, debugger. Nicméně vyvstává také potřeba provádět složitější testy, například integrační, které zaručí, že mezi jednotlivými nástroji nevzniká nekompatibilita. Autor vytvořil s podporou přůběžně integračního serveru prostředí, které napomáhá odhalování a odstraňování chyb při návrhu aplikačně specifických procesorů a které je navíc do značné míry automatizované.
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Pockrandt, Marcel [Verfasser], Sabine [Akademischer Betreuer] Glesner, Ben [Akademischer Betreuer] Juurlink, and Rolf [Akademischer Betreuer] Drechsler. "Model checking memory-related properties of hardware/software codesigns / Marcel Pockrandt. Gutachter: Sabine Glesner ; Ben Juurlink ; Rolf Drechsler. Betreuer: Sabine Glesner." Berlin : Technische Universität Berlin, 2014. http://d-nb.info/1067388087/34.
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Yeh, Jinn-Wang, and 葉進旺. "The Study on Hardware/Software CoDesign." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/02143895370729762762.
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碩士國立交通大學
電子工程系
88
This thesis investigates an effective approach to the system-level design of multimedia signal processing applications. To design these systems, we use the hardware/software codesign approach, which allows the hardware and software designs to be tightly coupled throughout the design process. Given a specification of system functionality and constraints, we propose a model to describe the system. After the model has been analyzed, partitioning is used to determine the parts of the system functionality that are delegated to application-specific hardware and the software that runs on the processor. Based on the result of hardware/software partitioning, we determine the optimal implementation of a system. We also explore issues concerning system synchronization and the implementation of hardware/software interface to accommodate communications between various parts of the system. This hardware and software codesign approach proposed makes it possible to build a time-constrained signal processing system on a chip using programmable parts and application-specific units. We use a media processor design as an example. The verification method and simulation results are also given in this thesis.
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Lu, Yu-Yin, and 盧昱穎. "Partitioning Strategies of Hardware Software Codesign." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/42449968580705942666.
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碩士大同大學
資訊工程研究所碩士在職專班
91
We exploit to design a partitioning tool at hardware software partitioning technology. The thesis describes the partitioning progress and method. There are used the Java programs partitioning tool to specify the partitioning technology and progress. We profile the Java programs to get the program profile information. Then we can use the partitioning tool to partition the program for hardware software co-design. The goal is to enhance the performance of design system. This partitioning tool identifies the critical section in the java programs. It proposed three strategies, execution time, invocation count and saving time cost-effective, and many configurations to setup the tool. It can base the design constrain to partitioning the java program. This can help developer evaluate the partitioning result, and then user can modify the partitioning objects of hardware or software parts to optimization system. The design steps of hardware software partitioning include four steps. First of all, we get the Java programs and define the system requirement. Then create the java bytecode. Second, profiling the program, we specify a tool to get the profile information. This progress needs testing data to realizable to run the program. Third, we specify the method and architecture of partitioning tool. And there are compare the advance and defect by each partitioning strategies. Finally, we specify the conclusion and feature work on hardware software partition.
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Chan, Wu-Hsiung, and 詹武雄. "HRMS：A Distributed Hardware/Software Codesign Environment." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/14816048968348389747.
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碩士逢甲大學
資訊工程學系
89
The three steps of designing program of the traditional Hardware/Software Codesign system are: Profiling Phase, Partitioning Phase, and Cosynthesis Phase. The system also needs a powerful cosynthesis compiler to compile a codesign program. There are advantages for traditional codesign system. There are more options to do the system optimization. The whole design procedure is variable, because of hardware environment could be modified immediately. And it would not impact the total design time. But there are also disadvantages for this system. The design procedure is too complex. Designer should have enough professional knowledge to the design job. This paper describes a simplified Hardware/Software Codesign procedure that designer could easily design a codesign program. It could reduce the difficulty and complexity in designing. And it reserves the basic performance of a codesign system. The Hardware Resources Management System (HRMS) is designed as the bridge between applications and the hardware device. On environment of the simplified codesign system of this paper, a program could employ the pre-user defined function to download and execute the circuits. By the HRMS, the working environment could be the stand-alone or the client-server architecture. The relational system components are designed with Visual Basic 6. The cooperating hardware device is a Reusable PCI Interface (RePCI) with a FPGA chip. It hopes that the design time and compiling time could be reduced with the system performance begin reserved in this simplified codesign system. And it also hopes to support more programming language could work in the codesign environment.
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Yeh, Ta-li, and 葉大立. "Design of the Software/Hardware Codesign Platform-IRES." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/pe59mg.
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碩士國立中山大學
電機工程學系研究所
96
High-performance reconfigurable computing has demonstrated its potential to accelerate demanding computational applications. Thus, the current trend is towards combining the microprocessor with the power of reconfigurable hardware in embedded system research area. However, integrating hardware and software that is the interface of communication is challenging. In this thesis, we present a methodology flow to improve the cohesion between hardware and software for reconfigurable embedded system design through IRES (I-link for Reconfigurable Embedded System), Hardware-Software integration platform. In IRES, we set up the platform and produce the Executor through I-link (Hardware-Software Integration Link). The Executor consists of tasks and hardware bitstreams which are provided by user design, bootloader and operation system which are provided by system, and PSPs (Program Segment Prefix) which are from the files given above. We initial the system through bootloader which will scan the PSPs of Executor to construct Task Control Block (TCB), Hardware Control Block (HCB) and Netlist IP Information Block (NIB) data structure. User can get the hardware information from those data structures, and communicate with hardware by using simple functions like “read()” and “write()”. Then, the system transmits the data to and from multi-hardware through Hardware Management Unit (HMU) which also has data buffering ability. Finally, we successfully accomplish IRES Hardware-Software integration platform in HSCP, which is developed in our laboratory, and verify the feasibility of communication between hardware and software.
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Luke, Yan-Xun Lee. "Hardware/Software Interface Synthesis for a Codesign Framework." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-3101200513520200.
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Lin, Yu-Tian, and 林玉田. "An Implementation of Hardware/Software Codesign Flow Environme." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/09695786373815491695.
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碩士逢甲大學
資訊工程學系
86
A reconfigurable computing (RC) system combines the traditional computing system with programmable hardware devices. The RC system explores hardware/software solutions for specific application needs. The programmable hardware devices is modified at runtime (or compile time) to meet the needs of an application. Thus system could gain the benefits of both flexibility of software and efficiency of hardware. In this thesis, we develop a design flow environment for designing program which transfers original prog In our design flow environment, we adopt the C language program as input source. In profiling phase, we insert "profiling tags" to collect program behavior data. Those behavior data contains the running time of basic blocks, the corresponding circuit complexity of basic blocks and the data transfer time between the basic blocks. In partitioning phase, we choose the "hardware candidates" by analyzing the program behavior data under certain criterions. In regard to the selection hardware candidates, the sys
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Lee, Luke Yan-Xun, and 李彥勳. "Hardware/Software Interface Synthesis for a Codesign Framework." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/57043734168500566328.
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碩士國立臺灣大學
資訊工程學研究所
93
Embedded system device driver developing has been identified as one of the most critical tasks in a System-on-Chip (SoC) design cycle. New tools and methodologies are required to improve the quality and development time of device drivers. We proposed a novel technique called “Expert Template” to meet this requirement. We also developed a methodology to co-simulate C/C++ software modules with SystemC derived hardware modules based on open-source tools and codes. Device driver source codes that are written by human experts are decomposed into extensible markup language (XML) structures. These parameterized structures are later reassembled back into source code form according to programmer specified parameters in XML tags. This tool enables automatic synthesis of device drivers from minimum descriptions. It allows developers to develop device driver from early design stages. Generic device drivers can be ported to various real-time operating systems (RTOS) easily. Our “Expert Template” also reduces the possible human errors in device driver development. The concept of expert template can be extended to reusable intellectual properties (IPs) as well. In this thesis, we first introduce the electronic system level (ESL) design trend and present our “Expert Template” approach. We then apply this new tool and our co-simulation methodology to realize a JPEG2000 codec design. The result shows that our “Expert Template” approach can improve the quality of source code and reduce the development time of device drivers.
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Lee, Trong-Yen, and 李宗演. "Hardware-Software Codesign Methodology for Distributed Embedded Systems." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/63390492826404501066.
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博士國立臺灣大學
電機工程學研究所
89
With the burgeoning widespread use of distributed embedded systems in almost all aspects of the human daily life, such as home appliance, work environments, public facilities, and high-assurance systems, the need of systematic design methodologies for such systems is becoming more and more impending. These distributed embedded systems have their own hardware and software parts, which must be designed concurrently. The codesign of a distributed system is more complex than that of a centralized one because each phase of codesign, including copartitioning, cosynthesis, cosimulation, and coverification, must consider the inherent physical restrictions imposed by the distributed characteristics of such a system. To reduce design complexity, design reuse techniques has to be applied because distributed systems often contain several parts that are similar in function. Hence, an object-oriented (OO) codesign approach, which considers physical restriction and object design reuse, is adopted in our newly purposed Distributed Embedded System Codesign (DESC) methodology. For different stages of system design, DESC methodology supports three types of models: Object Modeling Technique (OMT) models for system description and input, Linear Hybrid Automata (LHA) models for formal modeling and verification, and SES/workbench simulation models for performance evaluation. Moreover, a novel Multi-Level Partitioning (MLP) technique, that takes real-world constraints into consideration for hardware-software partitioning, is proposed. This MLP algorithm uses a gradient metric based on hardware-software cost and performance as the core metric for selection of optimal partitions and the structure of MLP consists of three nested levels. Comparisons between real-world examples partitioned using MLP and using other existing techniques demonstrate the contrasting strengths of MLP. Sharing, clustering, and hierarchical system model are some important features of MLP, which contribute towards producing more optimal partition results. After system partitioning in DESC, software is synthesized by task scheduling and hardware is synthesized by system-level and object-oriented techniques. Design alternatives for synthesized hardware-software systems are then checked for design feasibility through rapid prototyping using hardware-software emulators. Timing coverification is performed using corresponding LHA models. Through a case study on a Vehicle Parking Management System (VPMS), we illustrate each design phase of the DESC methodology and demonstrate the benefits of OO codesign, the efficiency of MLP algorithm, and the usefulness of formal timing coverification.
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Liao, Hsiao-Lun, and 廖孝倫. "Platform-based Hardware/Software CoDesign for MP3 Decoder." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/72261420777481107780.
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碩士國立成功大學
電機工程學系碩博士班
93
In recent years, digital audio coding is becoming increasingly popular and essential. MP3, the well-known compression format, is categorized as one of the MPEG standards for digital audio compression. Because of its high compression rate and high sound quality, MP3 has been applied extensively for internet transmissions and multimedia applications. In this thesis, we use a platform-based HW/SW co-design methodology to design a MP3 decoder on the ARM-based platform. According to the experimental results of the complexity analysis and overall efficiency estimation, we implement the computation-intensive and regular operation components (IMDCT and synthesis filterbank) in hardware, the other control-oriented and index decision making part in software. Furthermore, the MP3 decoder is verified through AMBA interface on ARM-based platform. The experimental results show that the MP3 decoder under HW/SW co-design improves 87% performance compared with the pure-software implementation, and achieves the real-time processing. Moreover, the sound quality also meets the ISO standard.
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Kuo, Su-Ming, and 郭書銘. "Design and Implementation of RTOS in Hardware Software Codesign." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/47582338524589224580.
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碩士大同大學
資訊工程學系(所)
95
There have some problems must be solve in electronics industry：Mobile devices must be small、light and low power consumption；The life cycle of Consumer-electronic products are getting shorter and shorter；For those requestments we implement a platform. The platform has two parts Java CPU and hardware OS. The Java CPU can commit across-platform requestment. Hardware OS (μC/OS-II) can speed-up system performance and reduce the CPU utility rate. Applation developer just use Java technologic to build Embedded System easily in this platform.
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Yu, Chia-Jun, and 余家潤. "Hardware/Software Codesign of Real-time Human Face Detection." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/91038786718960118348.
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碩士淡江大學
電機工程學系碩士班
98
In this thesis, a Hardware/Software (HW/SW) codesigned method based on a multiple master-slave system architecture is proposed to implement a real-time human face detection. In the design and implementation of real-time human face detection, a software and hardware codesign method which integrates C language and Hardware Description Language (HDL) based on a SOPC (System on a Programmable Chip) technique is applied to design five image processing modules: (1) Image Binary, (2) Image Enhancement, (3) Edge Detection, (4) Object Segmentation, and (5) Feature Comparison. In order to get real-time image processing, these modules which cost more computing time are implemented by using hardware accelerating circuits. Then, in the multiple master-slave system architecture, multiple master units are design to accelerate the process speed of image capture and display. Some experiment results illustrate that the image processing time is reduced effectively by the proposed method at the DE2-70 development board so that a real-time human face detection can be implemented.