Academic literature on the topic 'Hardware isolation'
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Journal articles on the topic "Hardware isolation"
Shang, Ming. "A New Hardware Isolation Architecture." Applied Mechanics and Materials 530-531 (February 2014): 631–36. http://dx.doi.org/10.4028/www.scientific.net/amm.530-531.631.
Full textHu, Nianhang, Mengmei Ye, and Sheng Wei. "Surviving Information Leakage Hardware Trojan Attacks Using Hardware Isolation." IEEE Transactions on Emerging Topics in Computing 7, no. 2 (April 1, 2019): 253–61. http://dx.doi.org/10.1109/tetc.2017.2648739.
Full textHooker, Sara. "The hardware lottery." Communications of the ACM 64, no. 12 (December 2021): 58–65. http://dx.doi.org/10.1145/3467017.
Full textKaplan, David. "Hardware VM Isolation in the Cloud." Queue 21, no. 4 (August 31, 2023): 49–67. http://dx.doi.org/10.1145/3623392.
Full textKaplan, David. "Hardware VM Isolation in the Cloud." Communications of the ACM 67, no. 1 (December 21, 2023): 54–59. http://dx.doi.org/10.1145/3624576.
Full textZeng, Qiang Hong, Shi Jian Zhu, Jing Jun Lou, and Shui Qing Xie. "Hardware Design for Active Vibration Isolation Controller." Advanced Materials Research 211-212 (February 2011): 1061–65. http://dx.doi.org/10.4028/www.scientific.net/amr.211-212.1061.
Full textChen, Sui, Lu Peng, and Samuel Irving. "Accelerating GPU Hardware Transactional Memory with Snapshot Isolation." ACM SIGARCH Computer Architecture News 45, no. 2 (September 14, 2017): 282–94. http://dx.doi.org/10.1145/3140659.3080204.
Full textOmar, Hamza, and Omer Khan. "PRISM." ACM Transactions on Architecture and Code Optimization 18, no. 3 (June 2021): 1–25. http://dx.doi.org/10.1145/3450523.
Full textCho, Yeongpil. "Fine-Grained Isolation to Protect Data against In-Process Attacks on AArch64." Electronics 9, no. 2 (February 1, 2020): 236. http://dx.doi.org/10.3390/electronics9020236.
Full textVerghese, Ben, Anoop Gupta, and Mendel Rosenblum. "Performance isolation." ACM SIGOPS Operating Systems Review 32, no. 5 (December 1998): 181–92. http://dx.doi.org/10.1145/384265.291044.
Full textDissertations / Theses on the topic "Hardware isolation"
Vilanova, García Lluís. "Code-Centric Domain Isolation : a hardware/software co-design for efficient program isolation." Doctoral thesis, Universitat Politècnica de Catalunya, 2016. http://hdl.handle.net/10803/385746.
Full textEls sistemes software d'avui en dia contenen una multitud de components software: des de simples llibreries fins a plugins o serveis complexos. La seguretat i fiabilitat d'aquests sistemes depèn de ser capaç d'aïllar cadascun d'aquests components en un domini a part. L'aïllament en els sistemes convencionals imposa grans costos tant en el rendiment com en la programabilitat del sistema. És més, tots els sistemes solen donar prioritat al rendiment sobre qualsevol altre consideració, degradant la seguretat i fiabilitat del sistema. Aquests costos en rendiment i programabilitat són deguts a la co-evolució de les arquitectures i Sistemes Operatius (SOs) convencionals, que exposen l'aïllament en termes d'un model de "CPUs virtuals". Els SOs encarnen aquest model a través dels processos que proprcionen. El SO s'aïlla del codi d'usuari a través d'un nivell de privilegi separat. Al mateix temps, els processos d'usuari estan aïllats els uns dels altres al utilitzar taules de pàgines separades. El nucli del SO multiplexa aquests processos entre els diferents recursos físics del sistema, proporcionant-los la il·lusió d'estar executant-se en una màquina per al seu ús exclusiu. Donat aquest model, els processos interactuen a través d'interfícies que han estat dissenyades per a sistemes distribuïts, empitjorant-ne la programabilitat i rendiment. Els elements de l'arquitectura que s'utilitzen per a construïr processos imposen costos en el rendiment que superen el 10x i 1000x en comparació amb una simple crida a funció (en el cas de nivells de privilegi i canvis de taula de pàgina, respectivament). És més, part d'aquests costos no vénen donats per l'arquitectura, sinó pels costos inherents al disseny dels SOs actuals. El nucli del SO actua com a mitjancer en la comunicació entre processos a través de primitives conegudes com a IPC. El IPC no és només costós en termes de rendiment, sinó que a més a més es desvia de les semàntiques tradicionals de crida síncrona de funcions. Tot "thread" està lligat al procés que el crea, i la invocació de funcionalitat entre processos requereix de la costosa mediació del SO i de la participació del programador a l'hora de sincronitzar "threads" i intercanviar informacio a través dels canals d'IPC. Aquesta tesi proposa un co-disseny del programari i del maquinari que elimina els costos de l'aïllament basat en processos, alhora que proporciona un camí per a l'adopció gradual d'optimitzacions més agressives. És a dir, permet que qualsevol procés faci una simple crida a una funció que està en un altre domini d'aïllament (com ara un altre procés) sense trencar la la semàntica de les crides síncrones a funció. Aquesta tesi proposa l'arquitectura de protecció CODOMs, que proporciona protecció de memòria i privilegis entre components de programari d'una forma que és, alhora, eficient i flexible. Aquest substrat del maquinari és aleshores utilitzat per proposar DomOS, un conjunt de canvis al SO al nivell del "runtime" i del nucli que permeten a qualsevol "thread" fer crides a funció de forma eficient i segura a codi que resideix en d'altres processos. És a dir, que el "thread" d'un procés pot cridar una funció d'un altre procés sense haver de passar pel SO en el seu camí crític. Això s'aconsegueix a través de mapejar tots els processos en un espai d'adreces compartit i d'eliminar tots els costos d'IPC a través d'una combinació de noves primitives en el maquinari i d'optimitzacions en temps de compilació i en temps d'execució. El IPC a DomOS és fins a 24x més ràpid que les pipes a Linux, i fins a 14x més ràpid que el IPC al SO L4 Fiasco.OC. Si s'aplica el sistema a un servidor web multi-capa, DomOS és fins a 2.18x més ràpid que un sistema Linux no modificat, i 1.32x més ràpid de mitjana. En totes les configuracions, DomOS proporciona més del 85% de la eficiència d'un sistema ideal.
Goonasekera, Nuwan Abhayawardena. "Program-level support for protecting an application from untrustworthy components." Thesis, Queensland University of Technology, 2012. https://eprints.qut.edu.au/60851/1/Nuwan_Goonasekera_Thesis.pdf.
Full textMaisuradze, Giorgi [Verfasser], and Christian [Akademischer Betreuer] Rossow. "Assessing the security of hardware-assisted isolation techniques / Giorgi Maisuradze ; Betreuer: Christian Rossow." Saarbrücken : Saarländische Universitäts- und Landesbibliothek, 2019. http://d-nb.info/120658873X/34.
Full textBehrens, Diogo. "Error isolation in distributed systems." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-203428.
Full textBehrens, Diogo, Marco Serafini, Sergei Arnautov, Flavio Junqueira, and Christof Fetzer. "Scalable error isolation for distributed systems: modeling, correctness proofs, and additional experiments." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-203622.
Full textBehrens, Diogo, Marco Serafini, Sergei Arnautov, Flavio Junqueira, and Christof Fetzer. "Scalable error isolation for distributed systems: modeling, correctness proofs, and additional experiments." Technische Universität Dresden, 2015. https://tud.qucosa.de/id/qucosa%3A29539.
Full textSensaoui, Abderrahmane. "Etude et implémentation de mécanismes de protection d'exécution d'applications embarquées." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALM002.
Full textLooking at the speed by which embedded systems technologies are advancing, there is no surprise the attacks' number is rising. Many applications are written quickly in a low-level language to keep up with industry pace, and they contain a variety of bugs. Bugs can be used to break into a device and to run malicious code. Reviewing code becomes more and more complex and costly due to its size. Another factor complicating code review is the use of on-the-shelf libraries. Even a detailed code review does not guarantee a bug-free application.This thesis presents an architecture to run securely untrusted applications on the same platform. We assume that the applications contain exploitable bugs, even the operating system can be exploited. We also assume that attackers can take control of In/Out hardware components (e.g., Direct Memory Access (DMA)). The device is trusted when the architecture guarantees that attackers cannot compromise the whole device and access sensitive code and data. Even when an application is compromised, our architecture guarantees a strong separation of multiple components: hardware and software. It ensures the authenticity and integrity of embedded applications and can verify their state before any sensitive operation. The architecture guarantees, for local and remote parties, that the device is running properly, and protect against software attacks.First, we study multiple attack vector and isolation and attestation architectures. We present multiple software attack vectors, and we define the security features and properties that these architectures need to ensure. We provide a detailed description of fifteen existing architectures in both academia and industry, and we compare their features. Then, we provide an in-depth study of five lightweight architectures where we give a comparison of performance, size, and how they behave against software-based attacks. From these studies, we draw our security objectives for lightweight devices: multi-layer isolation, attestation, upgradability, confidentiality, small size with a negligible run-time overhead and ease-of-use.Then, we design hybrid isolation and attestation architecture for lightweight devices. The so-called Toubkal offers multi-layered isolation; the system is composed of three layers of isolation. The first one is at the hardware level to separate In/Out components from each other. The second one is at the security monitor level; our study shows that there is a strong need to create a real separation between the security monitor and all the rest. Finally, the third layer is at the application level.However, isolation itself is not sufficient. Devices still need to ensure that the running application behaves as it was intended. For this reason, Toubkal provides attestation to be able to check the state of a device at any-time. It guarantees that a software component or data were not compromised.Finally, we prove the correctness of the security properties that Toubkal provides. We modeled Toubkal as a finite state machine and used computer-aided formal verification to prove the security properties. Then, we evaluated Toubkal's overhead. The results show that Toubkal overhead is small and fit for lightweight devices
Ducasse, Quentin. "Sécurisation matérielle de la compilation à la volée des machines virtuelles langage." Electronic Thesis or Diss., Brest, École nationale supérieure de techniques avancées Bretagne, 2024. http://www.theses.fr/2024ENTA0003.
Full textLanguage Virtual Machines (VMs) are the run-time environment of popular high level managed languages. They offer portability and memory handling for the developer and are deployed on most computing devices. Their widespread distribution, handling of untrusted user inputs, and low-level task execution make them interesting to attackers. Software-only solutions that isolate their different components often incur a high performance overhead incompatible with just-in-time (JIT) compilation. Hardware-accelerated run time protections are pushed in vendor processors as a solution to conciliate strong security guarantees with performance. To allow experimentation in the design and comparison of such solutions, this thesis is interested in the RISC-V instruction set and its extension capabilities. We present Gigue, a workload generator that outputs binaries similar to JIT code directly executable on RISC-V softcores. It provides an interface for custom instructions and guarantees their execution. We present an instruction-level domain isolation solution added to Gigue binaries and implemented in an application-class processor with processor modifications. The solution adds negligible performance overhead while enforcing strong properties on domains. As an effort to motivate deployment in real use cases, we extend the Pharo JIT compiler to the RISC-V instruction set along with its testing infrastructure
Wang, Shuo. "Control of a Uni-Axial Magnetorheological Vibration Isolator." University of Toledo / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1302200947.
Full textBenhani, El mehdi. "Sécurité des systèmes sur puce complexes hétérogènes." Thesis, Lyon, 2020. http://www.theses.fr/2020LYSES016.
Full textThe thesis studies the security of the ARM TrustZone technology in the context of complex heterogeneous SoCs. The thesis presents hardware attacks that affect elements of the SoCs architecture and it also presents countermeasure strategies
Books on the topic "Hardware isolation"
Patterson, Christopher B. Open World Empire. NYU Press, 2020. http://dx.doi.org/10.18574/nyu/9781479802043.001.0001.
Full textBook chapters on the topic "Hardware isolation"
Passaretti, Daniele, Felix Boehm, Martin Wilhelm, and Thilo Pionteck. "Hardware Isolation Support for Low-Cost SoC-FPGAs." In Architecture of Computing Systems, 148–63. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-21867-5_10.
Full textZhang, Kening, Ronald F. DeMara, and Carthik A. Sharma. "Consensus-Based Evaluation for Fault Isolation and On-line Evolutionary Regeneration." In Evolvable Systems: From Biology to Hardware, 12–24. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11549703_2.
Full textYe, Mengmei, Myra B. Cohen, Witawas Srisa-an, and Sheng Wei. "EvoIsolator: Evolving Program Slices for Hardware Isolation Based Security." In Search-Based Software Engineering, 377–82. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-99241-9_24.
Full textDowsley, Rafael, Jörn Müuller-Quade, and Tobias Nilges. "Weakening the Isolation Assumption of Tamper-Proof Hardware Tokens." In Lecture Notes in Computer Science, 197–213. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17470-9_12.
Full textDing, Baozeng, Fufeng Yao, Yanjun Wu, and Yeping He. "Improving Flask Implementation Using Hardware Assisted In-VM Isolation." In IFIP Advances in Information and Communication Technology, 115–25. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-30436-1_10.
Full textTople, Shruti, Soyeon Park, Min Suk Kang, and Prateek Saxena. "VeriCount: Verifiable Resource Accounting Using Hardware and Software Isolation." In Applied Cryptography and Network Security, 657–77. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-93387-0_34.
Full textShi, Bin, Lei Cui, Bo Li, Xudong Liu, Zhiyu Hao, and Haiying Shen. "ShadowMonitor: An Effective In-VM Monitoring Framework with Hardware-Enforced Isolation." In Research in Attacks, Intrusions, and Defenses, 670–90. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-00470-5_31.
Full textWang, Zhuoyue, Zhiqiang Wang, Jinyang Zhao, and Yaping Chi. "PCCP: A Private Container Cloud Platform Supporting Domestic Hardware and Software." In Proceeding of 2021 International Conference on Wireless Communications, Networking and Applications, 399–407. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2456-9_41.
Full textYuan, Shenghao, Frédéric Besson, Jean-Pierre Talpin, Samuel Hym, Koen Zandberg, and Emmanuel Baccelli. "End-to-End Mechanized Proof of an eBPF Virtual Machine for Micro-controllers." In Computer Aided Verification, 293–316. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-13188-2_15.
Full textMalipatlolla, Sunil. "A Novel Approach for a Hardware-Based Secure Process Isolation in an Embedded System." In Communications in Computer and Information Science, 1–9. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-40576-1_1.
Full textConference papers on the topic "Hardware isolation"
Ekberg, Jan-Erik. "Hardware Isolation for Trusted Execution." In CCS'16: 2016 ACM SIGSAC Conference on Computer and Communications Security. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2994459.2994460.
Full textSong, Chengyu, Hyungon Moon, Monjur Alam, Insu Yun, Byoungyoung Lee, Taesoo Kim, Wenke Lee, and Yunheung Paek. "HDFI: Hardware-Assisted Data-Flow Isolation." In 2016 IEEE Symposium on Security and Privacy (SP). IEEE, 2016. http://dx.doi.org/10.1109/sp.2016.9.
Full textYe, Mengmei, Nianhang Hu, and Sheng Wei. "Lightweight secure sensing using hardware isolation." In 2016 IEEE SENSORS. IEEE, 2016. http://dx.doi.org/10.1109/icsens.2016.7808904.
Full textAthalye, Anish, Frans Kaashoek, Nickolai Zeldovich, and Joseph Tassarotti. "The K2 Architecture for Trustworthy Hardware Security Modules." In KISV '23: 1st Workshop on Kernel Isolation, Safety and Verification. New York, NY, USA: ACM, 2023. http://dx.doi.org/10.1145/3625275.3625402.
Full textKumar Saha, Sujan, and Christophe Bobda. "FPGA Accelerated Embedded System Security Through Hardware Isolation." In 2020 Asian Hardware Oriented Security and Trust Symposium (AsianHOST). IEEE, 2020. http://dx.doi.org/10.1109/asianhost51057.2020.9358258.
Full textJang, Jinsoo, and Brent Byunghoon Kang. "In-process Memory Isolation Using Hardware Watchpoint." In DAC '19: The 56th Annual Design Automation Conference 2019. New York, NY, USA: ACM, 2019. http://dx.doi.org/10.1145/3316781.3317843.
Full textIbn Ziad, M. Tarek, Amr Alanwar, Yousra Alkabani, M. Watheq El-Kharashi, and Hassan Bedour. "Homomorphic Data Isolation for Hardware Trojan Protection." In 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2015. http://dx.doi.org/10.1109/isvlsi.2015.66.
Full textChen, Sui, Lu Peng, and Samuel Irving. "Accelerating GPU Hardware Transactional Memory with Snapshot Isolation." In ISCA '17: The 44th Annual International Symposium on Computer Architecture. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3079856.3080204.
Full textLeontie, Eugen, Gedare Bloom, Bhagirath Narahari, Rahul Simha, and Joseph Zambreno. "Hardware-enforced fine-grained isolation of untrusted code." In the first ACM workshop. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1655077.1655082.
Full textGarcia R., Ferreiro, Perez Castelo J., Pinon Pazos A., and Calvo Rolle J.L. "On Fault Isolation by Functional and Hardware Redundancy." In World Automation Congress (WAC) 2006. IEEE, 2006. http://dx.doi.org/10.1109/wac.2006.375955.
Full textReports on the topic "Hardware isolation"
Author, Not Given. Characteristics of spent fuel, high-level waste, and other radioactive wastes which may require long-term isolation: Appendix 2E, Physical descriptions of LWR nonfuel assembly hardware, Appendix 2F, User's guide to the LWR nonfuel assembly data base. Office of Scientific and Technical Information (OSTI), December 1987. http://dx.doi.org/10.2172/5294562.
Full textWu, Yingjie, Selim Gunay, and Khalid Mosalam. Hybrid Simulations for the Seismic Evaluation of Resilient Highway Bridge Systems. Pacific Earthquake Engineering Research Center, University of California, Berkeley, CA, November 2020. http://dx.doi.org/10.55461/ytgv8834.
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