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Journal articles on the topic 'Hardware extensions'

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Author: Grafiati

Published: 10 December 2022

Last updated: 28 January 2023

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1

Oliveira, Daniela, Nicholas Wetzel, Max Bucci, Jesus Navarro, Dean Sullivan, and Yier Jin. "Hardware-software collaboration for secure coexistence with kernel extensions." ACM SIGAPP Applied Computing Review 14, no. 3 (September 22, 2014): 22–35. http://dx.doi.org/10.1145/2670967.2670969.

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2

Nunez, J. L., and S. Jones. "Run-length coding extensions for high performance hardware data compression." IEE Proceedings - Computers and Digital Techniques 150, no. 6 (2003): 387. http://dx.doi.org/10.1049/ip-cdt:20030750.

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3

Craft, D. J. "A fast hardware data compression algorithm and some algorithmic extensions." IBM Journal of Research and Development 42, no. 6 (November 1998): 733–46. http://dx.doi.org/10.1147/rd.426.0733.

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4

Wang, Kailong, Yuxi Ling, Yanjun Zhang, Zhou Yu, Haoyu Wang, Guangdong Bai, Beng Chin Ooi, and Jin Song Dong. "Characterizing Cryptocurrency-themed Malicious Browser Extensions." Proceedings of the ACM on Measurement and Analysis of Computing Systems 6, no. 3 (December 2022): 1–31. http://dx.doi.org/10.1145/3570603.

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Due to the surging popularity of various cryptocurrencies in recent years, a large number of browser extensions have been developed as portals to access relevant services, such as cryptocurrency exchanges and wallets. This has stimulated a wild growth of cryptocurrency themed malicious extensions that cause heavy financial losses to the users and legitimate service providers. They have shown their capability of evading the stringent vetting processes of the extension stores, highlighting a lack of understanding of this emerging type of malware in our community. In this work, we conduct the first systematic study to identify and characterize cryptocurrency-themed malicious extensions. We monitor seven official and third-party extension distribution venues for 18 months (December 2020 to June 2022) and have collected around 3600 unique cryptocurrency-themed extensions. Leveraging a hybrid analysis, we have identified 186 malicious extensions that belong to five categories. We then characterize those extensions from various perspectives including their distribution channels, life cycles, developers, illicit behaviors, and illegal gains. Our work unveils the status quo of the cryptocurrency-themed malicious extensions and reveals their disguises and programmatic features on which detection techniques can be based. Our work serves as a warning to extension users, and an appeal to extension store operators to enact dedicated countermeasures. To facilitate future research in this area, we release our dataset of the identified malicious extensions and open-source our analyzer.

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5

Grübl, Andreas, Sebastian Billaudelle, Benjamin Cramer, Vitali Karasenko, and Johannes Schemmel. "Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System." Journal of Signal Processing Systems 92, no. 11 (July 9, 2020): 1277–92. http://dx.doi.org/10.1007/s11265-020-01558-7.

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Abstract This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Accelerated operation of neuromorphic circuits and highly-parallel digital data buses between the full-custom neuromorphic part and the PPU require custom methodologies to close the digital signal timing at the interfaces. Novel extensions to the standard digital physical implementation design flow are highlighted. We present early results from the first full-size BrainScaleS-2 ASIC containing 512 neurons and 130 K synapses, demonstrating the successful application of these methods. An application example illustrates the full functionality of the BrainScaleS-2 hybrid plasticity architecture.

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Stachour, Paul, and Bhavani Thuraisingham. "SQL extensions for security assertions." Computer Standards & Interfaces 11, no. 1 (January 1990): 5–14. http://dx.doi.org/10.1016/0920-5489(90)90067-p.

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7

Necula, George C., and Peter Lee. "Safe kernel extensions without run-time checking." ACM SIGOPS Operating Systems Review 30, SI (October 28, 1996): 229–43. http://dx.doi.org/10.1145/248155.238781.

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8

Guerra, Jorge, Luis Useche, Medha Bhadkamkar, Ricardo Koller, and Raju Rangaswami. "The case for active block layer extensions." ACM SIGOPS Operating Systems Review 42, no. 6 (October 2008): 3–9. http://dx.doi.org/10.1145/1453775.1453778.

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9

Jungeblut, T., C. Puttmann, R. Dreesen, M. Porrmann, M. Thies, U. Rückert, and U. Kastens. "Resource efficiency of hardware extensions of a 4-issue VLIW processor for elliptic curve cryptography." Advances in Radio Science 8 (December 22, 2010): 295–305. http://dx.doi.org/10.5194/ars-8-295-2010.

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Abstract. The secure transmission of data plays a significant role in today's information era. Especially in the area of public-key-cryptography methods, which are based on elliptic curves (ECC), gain more and more importance. Compared to asymmetric algorithms, like RSA, ECC can be used with shorter key lengths, while achieving an equal level of security. The performance of ECC-algorithms can be increased significantly by adding application specific hardware extensions. Due to their fine grained parallelism, VLIW-processors are well suited for the execution of ECC algorithms. In this work, we extended the fourfold parallel CoreVA-VLIW-architecture by several hardware accelerators to increase the resource efficiency of the overall system. For the design-space exploration we use a dual design flow, which is based on the automatic generation of a complete C-compiler based tool chain from a central processor specification. Using the hardware accelerators the performance of the scalar multiplication on binary fields can be increased by the factor of 29. The energy consumption can be reduced by up to 90%. The extended processor hardware was mapped on a current 65 nm low-power standard-cell-technology. The chip area of the CoreVA-VLIW-architecture is 0.24 mm2 at a power consumption of 29 mW/MHz. The performance gain is analyzed in respect to the increased hardware costs, as chip area or power consumption.

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10

Găitan, Vasile Gheorghiță, and Ionel Zagan. "Experimental Implementation and Performance Evaluation of an IoT Access Gateway for the Modbus Extension." Sensors 21, no. 1 (January 1, 2021): 246. http://dx.doi.org/10.3390/s21010246.

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This paper presents the relevant aspects regarding the experimental implementation and performance evaluation of an Internet of things (IoT) gateway for the Modbus extension. The proposed Modbus extension specifications are extended by defining the new optimized message format, and the structure of the acquisition cycle for obtaining a deterministic temporal behavior and solutions are presented for the description of devices at the MODBUS protocol level. Three different implementations are presented, and the Modbus extension’s performance is validated regarding the efficiency in the use of the acquisition cycle time. The software and hardware processing time and the importance and effect of the various components are analyzed and evaluated. They all support the implementation of an Internet of things gateway for Modbus extension. This paper introduces solutions for the structure of the acquisition cycle to include other valuable extensions, discusses the performance of a real implementation in the form of a gateway, adds new features to the Modbus extension specification, and strengthens some of the existing ones. In accordance with the novelty and contribution of this paper to the field of local industrial networks, the results obtained in the analysis, testing, and validation of the Modbus extension protocol refer to the extending of the Modbus functions for industrial process monitoring and control management.

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11

Wang, Yubo, Xiujia Zhao, Ting Chong, and Xianhua Liu. "Embedded Microprocessor Extension Design and Optimization for Real-Time Edge Computing." Wireless Communications and Mobile Computing 2022 (March 11, 2022): 1–15. http://dx.doi.org/10.1155/2022/5705184.

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With the development of 5G communication technology, more and more applications could be integrated into one system. Edge computing system and mixed-criticality system may integrate tasks of different criticality levels, which brings better balance in isolation and performance. Such advantages make it gradually become a research hotspot in edge computing and real-time systems with 5G. The important content of designing a mixed-criticality system is how to reduce interference between tasks and how to schedule tasks efficiently to ensure that tasks of different criticality levels can meet time constraints. Instruction extension and hardware software cooperative support may be an effective solution. Based on a fine-grained multithreaded RISC-V processor, this article gives some extensions for real-time operations and proposes a hardware software cooperative real-time scheduling mechanism. Experimental results show that, compared with FlexPRET hardware, the performance of thread scheduling is improved by 22.94% on average. Compared with software scheduling, the performance of scheduling same programs and multiple programs are improved by 15.46% and 26.00%, respectively.

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12

Kilaas, Roar, and Sidnei Paciornik. "The NCEM public domain software library of extensions to digital micrograph." Proceedings, annual meeting, Electron Microscopy Society of America 53 (August 13, 1995): 628–29. http://dx.doi.org/10.1017/s0424820100139512.

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The National Center for Electron Microscopy (NCEM) develops software for use in image processing and image interpretation as they are needed in ongoing research at the center. Some routines are esoteric and of little use to others, while some are more general and could be considered to be of interest to a large number of scientists. This represents the first announcement of the NCEM's dedication to making software developed at the center available to the general microscopy community.An unfortunate by-product of software development is the often necessary connection of the software to a hardware platform and/or another software platform. Most of the image processing carried out at the NCEM is done under Digital Micrograph running on the Macintosh, either through the built in functionality of the program or through extensions that are written at the center. Some of the functionality that we added were routines that were available under the SEMPER image processing software which was retired not because of limitations of the program, but because of the death of the hardware on which it was running.

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13

Dale, Sanda, C. R. Costea, and S. Zsolt. "Functionality Extension for A D.C. Motor Speed Control Didactic System with PID Controller." Scientific Bulletin of Electrical Engineering Faculty 18, no. 2 (October 1, 2018): 59–62. http://dx.doi.org/10.1515/sbeef-2017-0036.

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AbstractThe paper describes some functionality extensions for a D.C. motor speed control system with PID controller used as a didactic unit. The extensions are made in two directions: one at a physical-hardware level and the other one at software development of numerical algorithms and graphical interface. Both developments have the aim to extend and to get a more flexible paradigm for the control algorithms study on both continuous and discrete approach and to add the possibility to compare different control solutions.

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14

Ihsan, Ainan, Kashif Saghar, Tayyba Fatima, and Osman Hasan. "Formal comparison of LEACH and its extensions." Computer Standards & Interfaces 62 (February 2019): 119–27. http://dx.doi.org/10.1016/j.csi.2018.10.001.

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15

Appelt, W. "The ODA standard 1993 and future extensions." Computer Standards & Interfaces 15, no. 4 (September 1993): 343–51. http://dx.doi.org/10.1016/0920-5489(93)90034-o.

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16

Ashenden, Peter J., and Philip A. Wilsey. "Principles for Language Extensions to VHDL to Support High-Level Modeling." VLSI Design 10, no. 2 (January 1, 1999): 217–35. http://dx.doi.org/10.1155/1999/20186.

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This paper reviews proposals for extensions to VHDL to support high-level modeling and places them within a taxonomy that describes the modeling requirements they address. Many of the proposals focus on object-oriented extensions, whereas this paper argues that extension of VHDL to support high-level modeling requires a broader review. The paper presents a detailed discussion of issues to be considered in adding high-level modeling extensions to VHDL, including concurrency and communication, abstraction using entity interfaces, object-oriented data modeling, encapsulation, signal assignment semantics, shared variables, multiple inheritance, genericity and synthesis. Emphasis is placed on the importance of designing simple orthogonal semantic mechanisms that interact in well defined ways, and that integrate cleanly with existing language features.

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17

CADOLI, MARCO, and TONI MANCINI. "Combining relational algebra, SQL, constraint modelling, and local search." Theory and Practice of Logic Programming 7, no. 1-2 (January 2007): 37–65. http://dx.doi.org/10.1017/s1471068406002857.

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AbstractThe goal of this paper is to provide a strong integration between constraint modelling and relational DBMSs. To this end we propose extensions of standard query languages such as relational algebra and SQL, by adding constraint modelling capabilities to them. In particular, we propose non-deterministic extensions of both languages, which are specially suited for combinatorial problems. Non-determinism is introduced by means of a guessing operator, which declares a set of relations to have an arbitrary extension. This new operator results in languages with higher expressive power, able to express all problems in the complexity class NP. Some syntactical restrictions which make data complexity polynomial are shown. The effectiveness of both extensions is demonstrated by means of several examples. The current implementation, written in Java using local search techniques, is described.

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18

Nişancı, Görkem, Paul G. Flikkema, and Tolga Yalçın. "Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms." Cryptography 6, no. 3 (August 10, 2022): 41. http://dx.doi.org/10.3390/cryptography6030041.

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The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient implementation of common algorithms. While the algorithms can be implemented in software using base instruction sets, there is considerable potential to reduce memory cost and improve speed using specialized instructions and associated hardware. However, there is a need to assess the benefits and costs of software implementations and new instructions that implement key cryptographic algorithms in fewer cycles. The primary aim of this paper is to improve the understanding of the performance and cost of implementing cryptographic algorithms for the RISC-V instruction set architecture (ISA) in two cases: software implementations of the algorithms using the rv32i instruction set and using cryptographic instructions supported by dedicated hardware in additional functional units. For both cases, we describe a RISC-V processor with cryptography hardware extensions and hand-optimized RISC-V assembly language implementations of eleven cryptographic algorithms. Compared to implementations with only the rv32i instruction set, implementations with the cryptography set extension provide a 1.5× to 8.6× faster execution speed and 1.2× to 5.8× less program memory for five of the eleven algorithms. Based on our performance analyses, a new instruction is proposed to increase the implementation efficiency of the algorithms.

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19

Kraft, Donald H. "Research into fuzzy extensions of information retrieval." ACM SIGIR Forum 20, no. 1-4 (May 1986): 12–13. http://dx.doi.org/10.1145/15497.15499.

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20

Gonçalves, Enyo, João Araujo, and Jaelson Castro. "PRISE: A process to support iStar extensions." Journal of Systems and Software 168 (October 2020): 110649. http://dx.doi.org/10.1016/j.jss.2020.110649.

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21

Pires, Ivan Luiz Pedroso, Marco Antonio Zanata Alves, and Luiz Carlos Pessoa Albini. "Trace-driven and processing time extensions for Noxim simulator." Design Automation for Embedded Systems 23, no. 1-2 (January 5, 2019): 41–55. http://dx.doi.org/10.1007/s10617-018-09218-7.

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22

Benhadjyoussef, Noura, Wajih Elhadjyoussef, Mohsen Machhout, Rached Tourki, and Kholdoun Torki. "Enhancing a 32-Bit Processor Core with Efficient Cryptographic Instructions." Journal of Circuits, Systems and Computers 24, no. 10 (October 25, 2015): 1550158. http://dx.doi.org/10.1142/s0218126615501583.

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Embedded processor is often expected to achieve a higher security with good performance and economical use of resource. However, the choice regarding the best solution for how cryptographic algorithms are incorporated in processor core is one of the most challenging assignments a designer has to face. This paper presents an inexpensive instruction set extensions (ISE) of efficient cryptographic algorithms on 32-bit processors assuring various types of instruction (public/private key cryptography, random number generator (RNG) and secure hash function (SHF)). These extensions provide hardware instructions that implement a full algorithm in a single instruction. Our enhanced LEON2 SPARC V8 core with cryptographic ISE is implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40-nm technology. The total area of the resulting chip is about 1.93 mm2 and the estimated power consumption of the chip is 16.3 mW at 10 MHz. Hardware cost and power consumption evaluation are provided for different clock frequencies and the achieved results show that our circuit is able to be arranged in many security constrained devices.

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23

AMENDOLA, GIOVANNI, and FRANCESCO RICCA. "Paracoherent Answer Set Semantics meets Argumentation Frameworks." Theory and Practice of Logic Programming 19, no. 5-6 (September 2019): 688–704. http://dx.doi.org/10.1017/s1471068419000139.

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AbstractIn the last years, abstract argumentation has met with great success in AI, since it has served to capture several non-monotonic logics for AI. Relations between argumentation framework (AF) semantics and logic programming ones are investigating more and more. In particular, great attention has been given to the well-known stable extensions of an AF, that are closely related to the answer sets of a logic program. However, if a framework admits a small incoherent part, no stable extension can be provided. To overcome this shortcoming, two semantics generalizing stable extensions have been studied, namely semi-stable and stage. In this paper, we show that another perspective is possible on incoherent AFs, called paracoherent extensions, as they have a counterpart in paracoherent answer set semantics. We compare this perspective with semi-stable and stage semantics, by showing that computational costs remain unchanged, and moreover an interesting symmetric behaviour is maintained.

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KUTIL, RADE, and PETER EDER. "PARALLELIZATION OF WAVELET FILTERS USING SIMD EXTENSIONS." Parallel Processing Letters 16, no. 03 (September 2006): 335–49. http://dx.doi.org/10.1142/s012962640600268x.

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Much work has been done to optimize wavelet transforms for SIMD extensions of modern CPUs. However, these approaches are mostly restricted to the vertical part of 2-D transforms with line-wise organized memory layouts because this leads to a rather straight forward SIMD-implementation. This work shows for an example of a common wavelet filter new approaches to use SIMD operations on 1-D transforms that are able to produce reasonable speedups. As a result, the performance of algorithms that use wavelet transforms, such as JPEG2000, can be increased significantly. Various variants of parallelization are presented and compared. Their advantages and disadvantages for general filters are discussed.

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FERNANDES, RONALD, and ARKADY KANEVSKY. "ON RECURSIVE INTERCONNECTION NETWORKS AND THEIR EXTENSIONS." Parallel Processing Letters 06, no. 03 (September 1996): 377–88. http://dx.doi.org/10.1142/s0129626496000364.

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Properties of the WK-Recursive interconnection network are described and compared with other topologies. The effect of message locality is considered. The network is extended to two other topologies, the first of which extends the network to a third dimension, and the second defines a pyramid-like network structure.

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Cebrian, Juan M., Lasse Natvig, and Magnus Jahre. "Scalability analysis of AVX-512 extensions." Journal of Supercomputing 76, no. 3 (April 23, 2019): 2082–97. http://dx.doi.org/10.1007/s11227-019-02840-7.

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27

Smietanka, G., S. Brato, M. Freudenberg, and J. Götze. "Implementation and extension of a GNU-Radio RFID reader." Advances in Radio Science 11 (July 4, 2013): 107–11. http://dx.doi.org/10.5194/ars-11-107-2013.

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Abstract. The development of a flexible software defined RFID is discused. Commercial reader systems only allow a top level view on the communication and restrict the variation for many transmission parameters. Recently a software reader from the CGran project was proposed which uses the GNU Radio environment in combination with an USRP front end. Because most of the signal processing is done on a common host PC, this reader offers high flexibility, but also has several disadvantages. One of the main hardware limitations is the usage of only one separated antenna per transmit and receive path. Commercial readers usually use four antennas which are time multiplexed and can be used as transmitter and receiver. In this work a HF multiplexer for the USRP device is introduced. With this extension up to four transmit and receive antennas can be used in combination with the software reader. It is shown that the multiplexer achieves good read rates for a switching interval of 100 ms. Using this multiplexer the read range of the system decrease compared to the basic software reader, but distances over two meters can still be realized without additional hardware extensions.

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Cheded, L., and Ramadan A. Fan. "Controlling A Large Process with A Small Plc: A Senior Project Experience." International Journal of Electrical Engineering & Education 35, no. 4 (October 1998): 333–49. http://dx.doi.org/10.1177/002072099803500405.

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This paper describes the work of a senior project which investigated the possibility of controlling a large process with a small programmable logic controller (PLC). A new encoding strategy was successfully applied to overcome the low fan-out capability of the PLC. Both hardware and software aspects of this project are described and some extensions of this work are suggested.

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29

Egrot, Rob. "Order polarities." Journal of Logic and Computation 30, no. 3 (April 2020): 785–833. http://dx.doi.org/10.1093/logcom/exaa024.

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Abstract We define an order polarity to be a polarity $(X,Y,{\operatorname{R}})$ where $X$ and $Y$ are partially ordered, and we define an extension polarity to be a triple $(e_X,e_Y,{\operatorname{R}})$ such that $e_X:P\to X$ and $e_Y:P\to Y$ are poset extensions and $(X,Y,{\operatorname{R}})$ is an order polarity. We define a hierarchy of increasingly strong coherence conditions for extension polarities, each equivalent to the existence of a preorder structure on $X\cup Y$ such that the natural embeddings, $\iota _X$ and $\iota _Y$, of $X$ and $Y$, respectively, into $X\cup Y$ preserve the order structures of $X$ and $Y$ in increasingly strict ways. We define a Galois polarity to be an extension polarity satisfying the strongest of these coherence conditions and where $e_X$ and $e_Y$ are meet- and join-extensions, respectively. We show that for such polarities the corresponding preorder on $X\cup Y$ is unique. We define morphisms for polarities, providing the class of Galois polarities with the structure of a category, and we define an adjunction between this category and the category of $\varDelta _1$-completions and appropriate homomorphisms.

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30

Park, Seonghwan, Dongwook Kang, Jeonghwan Kang, and Donghyun Kwon. "Bratter: An Instruction Set Extension for Forward Control-Flow Integrity in RISC-V." Sensors 22, no. 4 (February 11, 2022): 1392. http://dx.doi.org/10.3390/s22041392.

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In recent decades, there has been an increasing number of studies on control flow integrity (CFI), particularly those implementing hardware-assisted CFI solutions that utilize a special instruction set extension. More recently, ARM and Intel, which are prominent processor architectures, also announced instruction set extensions for CFI called branch target identification (BTI) and control-flow enhancement technology (CET), respectively. However, according to our preliminary analysis, they do not support various CFI solutions in an efficient and scalable manner. In this study, we propose Bratter, a new instruction set extension for forward CFI solutions on RISC-V. At the center of Bratter, there are Branch Tag Registers and dedicated instructions for these registers. We implemented well-known CFI solutions (i.e., branch regulation and function signature check) using Bratter to evaluate its performance. Our experimental results show that, by using Bratter, even when these two solutions work together, they impose only 1.20% and 5.99% overhead for code size and execution time, respectively.

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Halevy, Alon Y., Inderpal Singh Mumick, Yehoshua Sagiv, and Oded Shmueli. "Static analysis in datalog extensions." Journal of the ACM 48, no. 5 (September 2001): 971–1012. http://dx.doi.org/10.1145/502102.502104.

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Dekleva, Janez, and Darko Menart. "Extensions of production flow analysis." Journal of Manufacturing Systems 6, no. 2 (January 1987): 93–105. http://dx.doi.org/10.1016/0278-6125(87)90033-1.

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Chiueh, Tzi-Cker, Ganesh Venkitachalam, and Prashant Pradhan. "Integrating segmentation and paging protection for safe, efficient and transparent software extensions." ACM SIGOPS Operating Systems Review 34, no. 2 (April 2000): 20. http://dx.doi.org/10.1145/346152.346187.

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Chiueh, Tzi-cker, Ganesh Venkitachalam, and Prashant Pradhan. "Integrating segmentation and paging protection for safe, efficient and transparent software extensions." ACM SIGOPS Operating Systems Review 33, no. 5 (December 12, 1999): 140–53. http://dx.doi.org/10.1145/319344.319161.

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35

Burger, Doug, Todd M. Austin, and Stephen W. Keckler. "Recent extensions to the SimpleScalar tool suite." ACM SIGMETRICS Performance Evaluation Review 31, no. 4 (March 2004): 4–7. http://dx.doi.org/10.1145/1054907.1054909.

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36

Dawson, Robert J., and Abdel Aziz Farrag. "Fault-tolerant extensions of star networks." Networks 21, no. 4 (July 1991): 373–85. http://dx.doi.org/10.1002/net.3230210402.

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NIEVES, JUAN CARLOS, ULISES CORTÉS, and MAURICIO OSORIO. "Preferred extensions as stable models." Theory and Practice of Logic Programming 8, no. 04 (May 8, 2008): 527–43. http://dx.doi.org/10.1017/s1471068408003359.

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AbstractGiven an argumentation frameworkAF, we introduce a mapping function that constructs a disjunctive logic programP, such that the preferred extensions ofAFcorrespond to the stable models ofP, after intersecting each stable model with the relevant atoms. The given mapping function is of polynomial size w.r.t.AF.In particular, we identify that there is a direct relationship between the minimal models of a propositional formula and the preferred extensions of an argumentation framework by working on representing the defeated arguments. Then we show how to infer the preferred extensions of an argumentation framework by using UNSAT algorithms and disjunctive stable model solvers. The relevance of this result is that we define a direct relationship between one of the most satisfactory argumentation semantics and one of the most successful approach of nonmonotonic reasoning i.e., logic programming with the stable model semantics.

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Ravi, Aadithya, Easwara E. A. Moorthy, D. Vidya, and G. Mahesh Kumar. "Hybrid Reconfigurable PC Add-on Card for Parallel Image Processing." Applied Mechanics and Materials 110-116 (October 2011): 5057–62. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.5057.

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Specific hardware solutions are always faster than programmable architectures. But dedicated architectures have the inherent disadvantage of inflexibility. Changes in the algorithm or extensions of the application are handled easily by programmable architectures. The approach discussed here involves a hardware-software co-design to optimize on performance and programmability. The architecture houses two SHARC processors to aid in parallelizing the image processing algorithms, and a reconfigurable FPGA which may be configured on the fly to execute any of the real-time algorithms as desired. The functional memory would consist of pre-designs (FPGA based) of certain objects, each of which could be used to configure an FPGA to perform a particular function.

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LEE, JOOHYUNG, and ZHUN YANG. "Translating LPOD and CR-Prolog2into standard answer set programs." Theory and Practice of Logic Programming 18, no. 3-4 (July 2018): 589–606. http://dx.doi.org/10.1017/s1471068418000315.

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AbstractLogic Programs with Ordered Disjunction (LPOD) is an extension of standard answer set programs to handle preference using the construct of ordered disjunction, and CR-Prolog2is an extension of standard answer set programs with consistency restoring rules and LPOD-like ordered disjunction. We present reductions of each of these languages into the standard ASP language, which gives us an alternative way to understand the extensions in terms of the standard ASP language.

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Bohnert, Thomas Michael, Jakub Jakubiak, Marcos Katz, Yevgeni Koucheryavy, Edmundo Monteiro, and Eugen Borcoci. "Network Simulation and Performance Evaluation of WiMAX Extensions for Isolated Research Data Networks." Journal of Communications Software and Systems 4, no. 1 (March 20, 2008): 62. http://dx.doi.org/10.24138/jcomss.v4i1.238.

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IEEE 802.16 is yet a very recent technology and released hardware does frequently only support standards partially. The same applies to public available simulation tools, in particular for NS-2. As the latter is the de-facto standard in science and as we use it for our research in the context of the WEIRD project, we evaluate the IEEE 802.16 support for NS-2. We present several general but also specific issues, which areimportant in order to carry out reliable research based on thesetools. In particular, we show in much detail where modulesdeviate significantly and even fail totally.

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Lessman, Roger E. "Changes and extensions in the C family of languages." ACM SIGCSE Bulletin 21, no. 2 (June 1989): 34–39. http://dx.doi.org/10.1145/65738.65744.

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Popovici, Cosmin-Andrei, and Andrei Stan. "Real-Time RISC-V-Based CAN-FD Bus Diagnosis Tool." Micromachines 14, no. 1 (January 12, 2023): 196. http://dx.doi.org/10.3390/mi14010196.

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Network Diagnosis Tools with industrial-grade quality are not widely available for common users such as researchers and students. This kind of tool enables users to develop Distributed Embedded Systems using low-cost and reliable setups. In the context of RISC-V Extensions and Domain-Specific Architecture, this paper proposes a Real-Time RISC-V-based CAN-FD Bus Diagnosis Tool, named RiscDiag CanFd, as an open-source alternative. The RISC-V Core extension is a CAN-FD Communication Unit controlled by a dedicated ISA Extension. Besides the extended RISC-V core, the proposed SoC provides UDP Communication via Ethernet for connecting the proposed solution to a PC. Additionally, a GUI application was developed for accessing and using the hardware solution deployed in an FPGA. The proposed solution is evaluated by measuring the lost frame rate, the precision of captured frames timestamps and the latency of preparing data for Ethernet communication. Measurements revealed a 0% frame loss rate, a timestamp error under 0.001% and an acquisition cycle jitter under 10 ns.

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Nieves, Juan Carlos, and Mauricio Osorio. "Ideal extensions as logical programming models." Journal of Logic and Computation 26, no. 5 (March 10, 2014): 1361–93. http://dx.doi.org/10.1093/logcom/exu014.

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Ciucu, Florin, and Felix Poloczek. "Two Extensions of Kingman's GI/G/1 Bound." ACM SIGMETRICS Performance Evaluation Review 47, no. 1 (December 17, 2019): 63–64. http://dx.doi.org/10.1145/3376930.3376971.

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Mamidi, Suman, Emily Blem, Michael J. Schulte, John Glossner, Daniel Iancu, Andrei Iancu, Mayan Moudgill, and Sanjay Jinturkar. "Instruction set extensions for software defined radio." Microprocessors and Microsystems 33, no. 4 (June 2009): 260–72. http://dx.doi.org/10.1016/j.micpro.2009.02.005.

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Kimms, A., and A. Drexl. "Proportional lot sizing and scheduling: Some extensions." Networks 32, no. 2 (September 1998): 85–101. http://dx.doi.org/10.1002/(sici)1097-0037(199809)32:2<85::aid-net2>3.0.co;2-e.

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Frost, G. P., T. J. Gordon, M. N. Howell, and Q. H. Wu. "Moderated Reinforcement Learning of Active and Semi-Active Vehicle Suspension Control Laws." Proceedings of the Institution of Mechanical Engineers, Part I: Journal of Systems and Control Engineering 210, no. 4 (November 1996): 249–57. http://dx.doi.org/10.1243/pime_proc_1996_210_464_02.

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This paper is concerned with the application of reinforcement learning to the dynamic ride control of an active vehicle suspension system. The study makes key extensions to earlier simulation work to enable on-line implementation of the learning automaton methodology using an actual vehicle. Extensions to the methodology allow safe and continuous learning to take place on the road, using a limited instrumentation set. An important new feature is the use of a moderator to set physical limits on the vehicle states. It is shown that the addition of the moderator has little direct effect on the system's ability to learn, and allows learning to take place continuously even when there are unstable controllers present. The study concludes with the results of an experimental trial using vehicle hardware, where the successful synthesis of a semi-active ride controller is demonstrated.

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Kunzman, David M., and Laxmikant V. Kalé. "Programming Heterogeneous Clusters with Accelerators Using Object-Based Programming." Scientific Programming 19, no. 1 (2011): 47–62. http://dx.doi.org/10.1155/2011/525717.

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Heterogeneous clusters that include accelerators have become more common in the realm of high performance computing because of the high GFlop/s rates such clusters are capable of achieving. However, heterogeneous clusters are typically considered hard to program as they usually require programmers to interleave architecture-specific code within application code. We have extended the Charm++ programming model and runtime system to support heterogeneous clusters (with host cores that differ in their architecture) that include accelerators. We are currently focusing on clusters that include commodity processors, Cell processors, and Larrabee devices. When our extensions are used to develop code, the resulting code is portable between various homogeneous and heterogeneous clusters that may or may not include accelerators. Using a simple example molecular dynamics (MD) code, we demonstrate our programming model extensions and runtime system modifications on a heterogeneous cluster comprised of Xeon and Cell processors. Even though there is no architecture-specific code in the example MD program, it is able to successfully make use of three core types, each with a different ISA (Xeon, PPE, SPE), three SIMD instruction extensions (SSE, AltiVec/VMX and the SPE's SIMD instructions), and two memory models (cache hierarchies and scratchpad memories) in a single execution. Our programming model extensions abstract away hardware complexities while our runtime system modifications automatically adjust application data to account for architectural differences between the various cores.

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Melnick, Corey, Patrick Sémon, Kwangmin Yu, Nicholas D'Imperio, André-Marie Tremblay, and Gabriel Kotliar. "Accelerated impurity solver for DMFT and its diagrammatic extensions." Computer Physics Communications 267 (October 2021): 108075. http://dx.doi.org/10.1016/j.cpc.2021.108075.

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Francês, Carlos Renato Lisboa, Edvar da Luz Oliveira, João Crisóstomo Weyl Albuquerque Costa, Marcos José Santana, Regina Helena Carlucci Santana, Sarita Mazzini Bruschi, Nandamudi Lankalapalli Vijaykumar, and Solon Venâncio de Carvalho. "Performance evaluation based on system modeling using Statecharts extensions." Simulation Modelling Practice and Theory 13, no. 7 (October 2005): 584–618. http://dx.doi.org/10.1016/j.simpat.2005.02.001.

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